Upload folder using huggingface_hub

.gitattributes

@@ -33,3 +33,6 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
 *.zip filter=lfs diff=lfs merge=lfs -text
 *.zst filter=lfs diff=lfs merge=lfs -text
 *tfevents* filter=lfs diff=lfs merge=lfs -text
+obj_dir/Vsim filter=lfs diff=lfs merge=lfs -text
+obj_dir/verilated.o filter=lfs diff=lfs merge=lfs -text
+obj_dir/verilated_vcd_c.o filter=lfs diff=lfs merge=lfs -text

Dockerfile

@@ -0,0 +1,110 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+# Multi-stage build using openenv-base
+# This Dockerfile is flexible and works for both:
+# - In-repo environments (with local OpenEnv sources)
+# - Standalone environments (with openenv from PyPI/Git)
+# The build script (openenv build) handles context detection and sets appropriate build args.
+
+ARG BASE_IMAGE=ghcr.io/meta-pytorch/openenv-base:latest
+FROM ${BASE_IMAGE} AS builder
+
+WORKDIR /app
+
+# OSS CAD Suite release to install into the image.
+ARG OSS_CAD_SUITE_VERSION=20260407
+ARG TARGETARCH
+
+# Ensure git and perl are available (required for installing dependencies from VCS and running Verilator)
+RUN apt-get update && \
+    apt-get install -y --no-install-recommends git perl perl-modules-5.40 && \
+    rm -rf /var/lib/apt/lists/*
+
+# Install OSS CAD Suite so tools like yosys are available in the container.
+RUN set -eux; \
+    case "${TARGETARCH}" in \
+        arm64) asset_arch=arm64 ;; \
+        amd64) asset_arch=x64 ;; \
+        *) echo "Unsupported target architecture: ${TARGETARCH}" && exit 1 ;; \
+    esac; \
+    archive="/tmp/oss-cad-suite.tgz"; \
+    curl -fsSL -o "${archive}" \
+      "https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2026-04-07/oss-cad-suite-linux-${asset_arch}-${OSS_CAD_SUITE_VERSION}.tgz"; \
+    top_level_dir="$(tar -tzf "${archive}" | head -n 1 | cut -d/ -f1)"; \
+    tar -xzf "${archive}" -C /opt; \
+    if [ "${top_level_dir}" != "oss-cad-suite" ]; then \
+        mv "/opt/${top_level_dir}" /opt/oss-cad-suite; \
+    fi; \
+    rm -f "${archive}"
+
+# Build argument to control whether we're building standalone or in-repo
+ARG BUILD_MODE=in-repo
+ARG ENV_NAME=chipforge
+
+# Copy environment code (always at root of build context)
+COPY . /app/env
+
+# For in-repo builds, openenv is already vendored in the build context
+# For standalone builds, openenv will be installed via pyproject.toml
+WORKDIR /app/env
+
+# Ensure uv is available (for local builds where base image lacks it)
+RUN if ! command -v uv >/dev/null 2>&1; then \
+        curl -LsSf https://astral.sh/uv/install.sh | sh && \
+        mv /root/.local/bin/uv /usr/local/bin/uv && \
+        mv /root/.local/bin/uvx /usr/local/bin/uvx; \
+    fi
+    
+# Install dependencies using uv sync
+# If uv.lock exists, use it; otherwise resolve on the fly
+RUN --mount=type=cache,target=/root/.cache/uv \
+    if [ -f uv.lock ]; then \
+        uv sync --frozen --no-install-project --no-editable; \
+    else \
+        uv sync --no-install-project --no-editable; \
+    fi
+
+RUN --mount=type=cache,target=/root/.cache/uv \
+    if [ -f uv.lock ]; then \
+        uv sync --frozen --no-editable; \
+    else \
+        uv sync --no-editable; \
+    fi
+
+# Final runtime stage
+FROM ${BASE_IMAGE}
+
+WORKDIR /app
+
+# Install runtime Perl support for Verilator's wrapper script.
+RUN apt-get update && \
+    apt-get install -y --no-install-recommends g++ make perl perl-modules-5.40 && \
+    rm -rf /var/lib/apt/lists/*
+
+# Copy OSS CAD Suite into the runtime image.
+COPY --from=builder /opt/oss-cad-suite /opt/oss-cad-suite
+
+# Copy the virtual environment from builder
+COPY --from=builder /app/env/.venv /app/.venv
+
+# Copy the environment code
+COPY --from=builder /app/env /app/env
+
+# Set PATH to use the virtual environment
+ENV PATH="/opt/oss-cad-suite/bin:/app/.venv/bin:$PATH"
+
+# Set PYTHONPATH so imports work correctly
+ENV PYTHONPATH="/app/env:$PYTHONPATH"
+
+# Health check
+HEALTHCHECK --interval=30s --timeout=3s --start-period=5s --retries=3 \
+    CMD curl -f http://localhost:8000/health || exit 1
+
+# Run the FastAPI server
+# Use the package-qualified module path so relative imports resolve correctly.
+ENV ENABLE_WEB_INTERFACE=true
+CMD ["sh", "-c", "cd /app/env && uvicorn chipforge.server.app:app --host 0.0.0.0 --port 8000"]

README.md

@@ -1,10 +1,167 @@
 ---
-title: Chiforge
-emoji: 🏃
-colorFrom: pink
-colorTo: yellow
-sdk: static
+title: ChipForge RTL Debugging Environment
+emoji: 🔧
+colorFrom: purple
+colorTo: green
+sdk: docker
 pinned: false
+app_port: 8000
+base_path: /web
+tags:
+  - openenv
+  - verilog
+  - rtl
+  - semiconductor
 ---
 
-Check out the configuration reference at https://huggingface.co/docs/hub/spaces-config-reference
+# ChipForge — RTL Debugging Environment
+
+An OpenEnv environment where an AI agent debugs buggy Verilog RTL code using real EDA tools (**Verilator** for simulation/lint, **Yosys** for synthesis).
+
+The agent receives buggy Verilog, inspects code, runs tools, reads error logs, edits lines to fix bugs, and submits the corrected design for grading.
+
+## Quick Start
+
+```python
+from chipforge import ChipforgeAction, ChipforgeEnv
+
+try:
+    env = ChipforgeEnv.from_docker_image("chipforge-env:latest")
+
+    # Start a new episode (loads a random buggy RTL task)
+    result = env.reset()
+    print(f"Task: {result.observation.task_description}")
+
+    # View the buggy RTL
+    result = env.step(ChipforgeAction(action_type="view_rtl"))
+    print(result.observation.rtl_code)
+
+    # Run simulation to see errors
+    result = env.step(ChipforgeAction(action_type="run_simulation"))
+    print(f"Status: {result.observation.sim_status}")
+    print(f"Error: {result.observation.error_summary}")
+
+    # Fix the bug
+    result = env.step(ChipforgeAction(
+        action_type="edit_line",
+        line_number=13,
+        new_content="assign sum = x1 ^ cin;"
+    ))
+
+    # Verify the fix
+    result = env.step(ChipforgeAction(action_type="run_simulation"))
+    print(f"Status: {result.observation.sim_status}")
+
+    # Submit solution
+    result = env.step(ChipforgeAction(action_type="submit"))
+    print(f"Reward: {result.observation.reward}")
+
+finally:
+    env.close()
+```
+
+## Action Space
+
+| Action | Parameters | Description |
+|--------|-----------|-------------|
+| `view_rtl` | — | View current RTL code with line numbers |
+| `view_testbench` | — | View the testbench code |
+| `view_logs` | `log_type`: sim/synth/lint | View output from last tool run |
+| `run_simulation` | — | Compile + simulate with Verilator |
+| `run_synthesis` | — | Synthesize with Yosys |
+| `run_lint` | — | Run Verilator lint checks |
+| `edit_line` | `line_number`, `new_content` | Replace a single line of RTL |
+| `submit` | — | Submit fix and get final reward |
+
+## Observation Space
+
+| Field | Type | Description |
+|-------|------|-------------|
+| `rtl_code` | str | Current RTL (populated by `view_rtl`) |
+| `testbench_code` | str | Testbench (populated by `view_testbench`) |
+| `log_output` | str | Tool output (populated by `view_logs`) |
+| `sim_status` | str | `not_run` / `pass` / `fail` / `error` |
+| `synth_status` | str | `not_run` / `pass` / `warning` / `error` |
+| `lint_status` | str | `not_run` / `clean` / `warning` / `error` |
+| `error_summary` | str | One-line error hint |
+| `task_description` | str | Description of the current task |
+| `step_count` | int | Steps taken so far |
+| `max_steps` | int | Maximum allowed steps (20) |
+
+## Reward
+
+| Component | Value | Condition |
+|-----------|-------|-----------|
+| Compiles | +0.2 | No syntax errors |
+| Simulation passes | +0.3 | Output matches expected truth table |
+| Synthesis clean | +0.3 | No warnings (e.g., no latches) |
+| Lint clean | +0.2 | No lint warnings |
+| Step penalty | -0.01/step | Encourages efficiency |
+
+Maximum reward: **1.0** (all checks pass, minimal steps).
+
+## Tasks
+
+| # | Name | Difficulty | Bug Type |
+|---|------|-----------|----------|
+| 1 | `task_easy_syntax` | Easy | Incomplete XOR expression |
+| 2 | `task_easy_missing_semicolon` | Easy | Missing semicolon on wire declaration |
+| 3 | `task_medium_logic_bug` | Medium | Wrong operator in sum computation |
+| 4 | `task_medium_wrong_operator` | Medium | XOR instead of AND in carry logic |
+| 5 | `task_hard_latch_inference` | Hard | Missing else branch → latch inferred |
+
+## Tools Used
+
+| Tool | Role | Installed via |
+|------|------|--------------|
+| **Verilator** | Simulation + Linting | OSS CAD Suite |
+| **Yosys** | Synthesis | OSS CAD Suite |
+
+Both tools are bundled in the Docker image via [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build).
+
+## Building & Running
+
+```bash
+# Build Docker image
+docker build -t chipforge-env:latest -f server/Dockerfile .
+
+# Run locally (for development)
+uvicorn chipforge.server.app:app --reload
+
+# Deploy to Hugging Face Spaces
+openenv push
+```
+
+## Project Structure
+
+```
+chipforge/
+├── __init__.py              # Module exports
+├── models.py                # Action + Observation models
+├── client.py                # ChipforgeEnv client
+├── openenv.yaml             # OpenEnv manifest
+├── pyproject.toml           # Dependencies
+└── server/
+    ├── app.py               # FastAPI application
+    ├── chipforge_environment.py  # Core environment logic
+    ├── Dockerfile           # Container with Verilator + Yosys
+    └── tasks/               # RTL debugging tasks
+        ├── task_easy_syntax/
+        ├── task_easy_missing_semicolon/
+        ├── task_medium_logic_bug/
+        ├── task_medium_wrong_operator/
+        └── task_hard_latch_inference/
+```
+
+## Example Agent Episode
+
+```
+reset()  →  Task: "Fix the syntax error in the full adder RTL"
+
+view_rtl  →  see buggy code with line numbers
+run_simulation  →  sim_status="error", error_summary="syntax error near '^'"
+edit_line(13, "assign sum = x1 ^ cin;")  →  "Line 13 updated"
+run_simulation  →  sim_status="pass"
+run_synthesis  →  synth_status="pass"
+submit  →  reward=0.93
+```

__init__.py

@@ -0,0 +1,16 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+"""Chipforge Environment."""
+
+from .client import ChipforgeEnv
+from .models import ChipforgeAction, ChipforgeObservation
+
+__all__ = [
+    "ChipforgeAction",
+    "ChipforgeObservation",
+    "ChipforgeEnv",
+]

client.py

@@ -0,0 +1,122 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+"""ChipForge Environment Client."""
+
+from typing import Dict
+
+from openenv.core import EnvClient
+from openenv.core.client_types import StepResult
+from openenv.core.env_server.types import State
+
+from .models import ChipforgeAction, ChipforgeObservation
+
+
+class ChipforgeEnv(
+    EnvClient[ChipforgeAction, ChipforgeObservation, State]
+):
+    """
+    Client for the ChipForge RTL Debugging Environment.
+
+    This client maintains a persistent WebSocket connection to the environment
+    server, enabling efficient multi-step interactions with lower latency.
+
+    Example:
+        >>> with ChipforgeEnv(base_url="http://localhost:8000") as client:
+        ...     result = client.reset()
+        ...     print(result.observation.rtl_code)  # RTL is always in observation
+        ...
+        ...     # View the testbench code
+        ...     result = client.step(ChipforgeAction(action_type="view_testbench"))
+        ...     print(result.observation.testbench_code)
+        ...
+        ...     # Run simulation and view the results
+        ...     result = client.step(ChipforgeAction(action_type="run_simulation"))
+        ...     result = client.step(ChipforgeAction(action_type="view_simulation_log"))
+        ...     print(result.observation.log_output)
+        ...
+        ...     # Edit a line
+        ...     result = client.step(ChipforgeAction(
+        ...         action_type="edit_line",
+        ...         line_number=13,
+        ...         new_content="assign sum = x1 ^ cin;"
+        ...     ))
+
+    Example with Docker:
+        >>> client = ChipforgeEnv.from_docker_image("chipforge-env:latest")
+        >>> try:
+        ...     result = client.reset()
+        ...     print(result.observation.rtl_code)  # RTL is always present
+        ...     result = client.step(ChipforgeAction(action_type="run_simulation"))
+        ... finally:
+        ...     client.close()
+    """
+
+    def _step_payload(self, action: ChipforgeAction) -> Dict:
+        """
+        Convert ChipforgeAction to JSON payload for step message.
+
+        Args:
+            action: ChipforgeAction instance
+
+        Returns:
+            Dictionary representation suitable for JSON encoding
+        """
+        payload = {"action_type": action.action_type}
+
+        if action.line_number is not None:
+            payload["line_number"] = action.line_number
+        if action.new_content is not None:
+            payload["new_content"] = action.new_content
+        return payload
+
+    def _parse_result(self, payload: Dict) -> StepResult[ChipforgeObservation]:
+        """
+        Parse server response into StepResult[ChipforgeObservation].
+
+        Args:
+            payload: JSON response data from server
+
+        Returns:
+            StepResult with ChipforgeObservation
+        """
+        obs_data = payload.get("observation", {})
+        observation = ChipforgeObservation(
+            rtl_code=obs_data.get("rtl_code", ""),
+            testbench_code=obs_data.get("testbench_code", ""),
+            log_output=obs_data.get("log_output", ""),
+            sim_status=obs_data.get("sim_status", "not_run"),
+            synth_status=obs_data.get("synth_status", "not_run"),
+            lint_status=obs_data.get("lint_status", "not_run"),
+            error_summary=obs_data.get("error_summary", ""),
+            task_description=obs_data.get("task_description", ""),
+            step_count=obs_data.get("step_count", 0),
+            max_steps=obs_data.get("max_steps", 20),
+            done=payload.get("done", False),
+            reward=payload.get("reward"),
+            metadata=obs_data.get("metadata", {}),
+        )
+
+        return StepResult(
+            observation=observation,
+            reward=payload.get("reward"),
+            done=payload.get("done", False),
+        )
+
+    def _parse_state(self, payload: Dict) -> State:
+        """
+        Parse server response into State object.
+
+        Args:
+            payload: JSON response from state request
+
+        Returns:
+            State object with episode_id and step_count
+        """
+        return State(
+            episode_id=payload.get("episode_id"),
+            step_count=payload.get("step_count", 0),
+        )

inference.py

@@ -0,0 +1,504 @@
+#!/usr/bin/env python3
+"""
+LLM inference runner for ChipForge RTL Debugging Environment.
+
+This script lets a chat model debug buggy Verilog RTL by choosing actions
+(view code, run simulation/synthesis, edit lines, submit) against the
+ChipForge HTTP server.
+
+Examples:
+  # HTTP mode against running server
+  python inference.py --mode http --env-url http://localhost:8000
+
+  # Local mode (requires Verilator + Yosys on PATH)
+  python inference.py --mode local --episodes 1
+"""
+from __future__ import annotations
+
+import argparse
+import json
+import os
+import re
+import urllib.error
+import urllib.request
+from typing import Any, Optional
+
+from dotenv import load_dotenv
+
+load_dotenv()
+
+# ---------------------------------------------------------------------------
+# Action definitions
+# ---------------------------------------------------------------------------
+
+VALID_ACTIONS = [
+    "view_testbench",
+    "view_synthesis_log",
+    "view_lint_log",
+    "view_simulation_log",
+    "run_simulation",
+    "run_synthesis",
+    "run_lint",
+    "edit_line",
+    "append_line",
+    "edit_testbench_line",
+    "append_testbench_line",
+    "submit",
+]
+
+DEFAULT_LLM_MODEL = os.environ.get("LLM_MODEL", "mistral-medium-2505")
+
+# ---------------------------------------------------------------------------
+# System prompt
+# ---------------------------------------------------------------------------
+
+SYSTEM_PROMPT = """You are an expert Verilog/RTL debugging agent controlling the ChipForge environment.
+Your goal is to fix buggy Verilog RTL code so it passes simulation, synthesis, and lint checks.
+
+Available actions (return exactly ONE JSON action per turn):
+
+1. view_testbench       — View the testbench code
+2. view_synthesis_log   — View synthesis tool logs from last run
+3. view_lint_log        — View lint tool logs from last run
+4. view_simulation_log  — View simulation tool logs from last run
+5. run_simulation       — Compile and simulate with Verilator
+6. run_synthesis        — Synthesize with Yosys
+7. run_lint             — Run Verilator lint checks
+8. edit_line            — Replace a single line. Requires line_number (1-indexed) and new_content
+9. append_line          — Append one RTL line. Requires new_content
+10. edit_testbench_line — Replace a single testbench line. Requires line_number and new_content
+11. append_testbench_line — Append one testbench line. Requires new_content
+12. submit              — Submit current RTL as final solution (triggers grading)
+
+Response format — return ONLY valid JSON:
+{"action_type": "...", "line_number": null, "new_content": null, "reasoning": "..."}
+
+Strategy:
+1. The observation always includes the current RTL code — you don't need to view it separately
+2. Run run_simulation to see compilation/output errors
+3. If there are errors, use view_simulation_log to read error details
+4. Use edit_line to fix the bug (one line at a time)
+5. Use append_line / append_testbench_line if a task starts with missing files
+6. Re-run simulation to verify the fix
+6. Run synthesis and lint to ensure clean results
+7. Use view_synthesis_log and view_lint_log to check for warnings/errors
+9. Submit when everything passes
+
+Rules:
+- Return valid JSON only, no markdown
+- Use null for fields that don't apply to the chosen action
+- Fix bugs methodically — read error logs before editing
+- Minimize steps for a higher reward (step penalty of -0.02/step)
+- Optimize cumulative_reward across the full episode, not only the immediate step reward
+"""
+
+
+# ---------------------------------------------------------------------------
+# LLM helpers
+# ---------------------------------------------------------------------------
+
+
+def build_prompt(observation: dict[str, Any]) -> str:
+    """Build user prompt from the current observation."""
+    parts = ["Fix the RTL bug."]
+
+    # Always show step information
+    parts.append(
+        f"Step: {observation.get('step_count', '?')}/{observation.get('max_steps', 20)}"
+    )
+
+    if observation.get("error_summary"):
+        parts.append(f"Error: {observation['error_summary']}")
+    if observation.get("last_action"):
+        parts.append(f"Last action: {observation['last_action']}")
+    if observation.get("action_result"):
+        parts.append(f"Action result: {observation['action_result']}")
+
+    status_line = (
+        f"Status: sim={observation.get('sim_status', 'not_run')}, "
+        f"synth={observation.get('synth_status', 'not_run')}, "
+        f"lint={observation.get('lint_status', 'not_run')}"
+    )
+    parts.append(status_line)
+
+    metadata = observation.get("metadata", {}) or {}
+    if "code_dirty" in metadata:
+        parts.append(f"Code dirty since last validation: {metadata.get('code_dirty')}")
+    tool_freshness = metadata.get("tool_freshness", {})
+    if tool_freshness:
+        parts.append(
+            "Tool freshness: "
+            f"sim={tool_freshness.get('simulation')}, "
+            f"synth={tool_freshness.get('synthesis')}, "
+            f"lint={tool_freshness.get('lint')}"
+        )
+
+    # Include content fields if populated
+    if observation.get("rtl_code"):
+        parts.append(f"\n--- RTL Code ---\n{observation['rtl_code']}")
+
+    if observation.get("testbench_code"):
+        parts.append(f"\n--- Testbench ---\n{observation['testbench_code']}")
+
+    if observation.get("log_output"):
+        # Truncate very long logs
+        log = observation["log_output"][:1500]
+        parts.append(f"\n--- Log Output ---\n{log}")
+
+    parts.append("\nReturn your next action as JSON:")
+    return "\n".join(parts)
+
+
+def parse_action(text: str) -> Optional[dict[str, Any]]:
+    """Try to extract a JSON action from the LLM response."""
+    text = text.strip()
+
+    # Direct JSON
+    try:
+        return json.loads(text)
+    except Exception:
+        pass
+
+    # Fenced code block
+    match = re.search(r"```(?:json)?\s*(\{.*?\})\s*```", text, re.DOTALL)
+    if match:
+        try:
+            return json.loads(match.group(1))
+        except Exception:
+            pass
+
+    # Any JSON object
+    match = re.search(r"\{.*\}", text, re.DOTALL)
+    if match:
+        try:
+            return json.loads(match.group(0))
+        except Exception:
+            pass
+
+    return None
+
+
+def validate_action(action: dict[str, Any]) -> dict[str, Any]:
+    """Validate and normalize the parsed action."""
+    action_type = action.get("action_type", "run_simulation")
+    if action_type not in VALID_ACTIONS:
+        action_type = "run_simulation"
+
+    payload: dict[str, Any] = {"action_type": action_type}
+
+    if action_type in ("edit_line", "edit_testbench_line"):
+        payload["line_number"] = action.get("line_number")
+        payload["new_content"] = action.get("new_content")
+    elif action_type in ("append_line", "append_testbench_line"):
+        payload["new_content"] = action.get("new_content")
+
+    return payload
+
+
+# ---------------------------------------------------------------------------
+# LLM client (Mistral)
+# ---------------------------------------------------------------------------
+
+
+def make_mistral_client(api_key: Optional[str] = None):
+    from mistralai.client import Mistral
+
+    return Mistral(
+        api_key=api_key or os.environ.get("MISTRAL_API_KEY"),
+        timeout_ms=120_000,  # 120s — magistral is a reasoning model
+    )
+
+
+def call_llm(client, model: str, prompt: str, temperature: float, max_retries: int = 3) -> str:
+    """Call the LLM with retry on timeout."""
+    import time as _time
+
+    for attempt in range(max_retries):
+        try:
+            response = client.chat.complete(
+                model=model,
+                messages=[
+                    {"role": "system", "content": SYSTEM_PROMPT},
+                    {"role": "user", "content": prompt},
+                ],
+                temperature=temperature,
+            )
+            content = response.choices[0].message.content
+            if not content:
+                raise RuntimeError("LLM response missing content")
+
+            # Some models (e.g. magistral) return content as a list of blocks
+            if isinstance(content, list):
+                parts = []
+                for block in content:
+                    if isinstance(block, str):
+                        parts.append(block)
+                    elif hasattr(block, "text"):
+                        parts.append(block.text)
+                    elif isinstance(block, dict) and "text" in block:
+                        parts.append(block["text"])
+                    else:
+                        parts.append(str(block))
+                content = "\n".join(parts)
+
+            return content
+
+        except Exception as e:
+            if attempt < max_retries - 1:
+                wait = 5 * (attempt + 1)
+                print(f"  ⚠️  LLM call failed ({e.__class__.__name__}), retrying in {wait}s...")
+                _time.sleep(wait)
+            else:
+                raise
+
+
+# ---------------------------------------------------------------------------
+# HTTP helpers
+# ---------------------------------------------------------------------------
+
+
+def request_json(
+    url: str,
+    method: str = "GET",
+    payload: Optional[dict[str, Any]] = None,
+) -> dict[str, Any]:
+    """Make an HTTP request and return parsed JSON."""
+    data = None
+    headers = {}
+    if payload is not None:
+        data = json.dumps(payload).encode("utf-8")
+        headers["Content-Type"] = "application/json"
+    req = urllib.request.Request(url, data=data, headers=headers, method=method)
+    with urllib.request.urlopen(req, timeout=120) as resp:
+        return json.loads(resp.read().decode("utf-8"))
+
+
+# ---------------------------------------------------------------------------
+# Episode runners
+# ---------------------------------------------------------------------------
+
+
+def run_http_episode(args: argparse.Namespace) -> float:
+    """Run one episode against the server using WebSocket (persistent session)."""
+    import time
+    import websocket  # pip install websocket-client
+
+    llm_client = make_mistral_client(args.api_key)
+
+    # Connect via WebSocket for persistent session state
+    ws_url = args.env_url.replace("http://", "ws://").replace("https://", "wss://") + "/ws"
+    ws = websocket.create_connection(ws_url, timeout=120)
+
+    def ws_send(msg_type: str, data: dict = None) -> dict:
+        """Send a WebSocket message and return the response."""
+        payload = {"type": msg_type}
+        if data is not None:
+            payload["data"] = data
+        ws.send(json.dumps(payload))
+        return json.loads(ws.recv())
+
+    # Reset
+    reset_payload: dict[str, Any] = {}
+    if args.seed is not None:
+        reset_payload["seed"] = args.seed
+    if args.task_name:
+        reset_payload["task_name"] = args.task_name
+    reset_resp = ws_send("reset", reset_payload if reset_payload else None)
+    obs = reset_resp.get("data", {})
+    total_reward = 0.0
+
+    print(f"  Starting episode...")
+    print()
+
+    for step in range(args.max_steps):
+        # Build prompt and query LLM
+        prompt = build_prompt(obs)
+        raw_response = call_llm(
+            client=llm_client,
+            model=args.model,
+            prompt=prompt,
+            temperature=args.temperature,
+        )
+
+        # Parse and validate
+        parsed = parse_action(raw_response)
+        if parsed is None:
+            parsed = {"action_type": "run_simulation", "reasoning": "Failed to parse LLM response"}
+
+        action_dict = validate_action(parsed)
+        
+        reasoning = parsed.get("reasoning", "")
+
+        # Step via WebSocket
+        step_resp = ws_send("step", action_dict)
+        obs = step_resp.get("data", {}).get("observation", step_resp.get("data", {}))
+        reward = float(step_resp.get("data", {}).get("reward", 0.0))
+        done = step_resp.get("data", {}).get("done", False)
+        total_reward += reward
+        obs_cumulative_reward = obs.get("cumulative_reward")
+
+        # Print step header
+        print(f"\n  {'─'*56}")
+        print(f"  STEP {step + 1}/{args.max_steps}")
+        print(f"  {'─'*56}")
+
+        # Print full action object
+        print(f"\n  ▶ ACTION:")
+        print(f"    {json.dumps(action_dict, indent=4)}")
+        if reasoning:
+            print(f"    reasoning: {reasoning}")
+
+        # Print observation
+        print(f"\n  ◀ OBSERVATION:")
+        print(f"    {json.dumps(obs, indent=4)}")
+
+        print(
+            f"\n  Reward: step={reward:+.3f}  episode_return={total_reward:+.3f}  "
+            f"obs_cumulative={obs_cumulative_reward}"
+        )
+
+        if done:
+            print(f"\n  🏁 EPISODE DONE — Episode return: {total_reward:+.3f}")
+            break
+
+        # 10 second delay between steps
+        print(f"\n  ⏳ Waiting 10 seconds...")
+        time.sleep(10)
+
+    ws.close()
+    print(f"\n  Final episode return: {total_reward:+.3f}")
+    return total_reward
+
+
+def run_local_episode(args: argparse.Namespace) -> float:
+    """Run one episode using the local environment (needs Verilator+Yosys)."""
+    import sys
+
+    sys.path.insert(0, os.path.dirname(__file__))
+
+    from models import ChipforgeAction
+    from server.chipforge_environment import ChipforgeEnvironment
+
+    client = make_mistral_client(args.api_key)
+    env = ChipforgeEnvironment()
+
+    reset_kwargs: dict[str, Any] = {}
+    if args.seed is not None:
+        reset_kwargs["seed"] = args.seed
+    if args.task_name:
+        reset_kwargs["task_name"] = args.task_name
+    obs = env.reset(**reset_kwargs)
+    total_reward = 0.0
+
+    print(f"  Starting episode...")
+    print()
+
+    for step in range(args.max_steps):
+        # Build observation dict for prompt
+        obs_dict = {
+            "rtl_code": obs.rtl_code,
+            "testbench_code": obs.testbench_code,
+            "log_output": obs.log_output,
+            "sim_status": obs.sim_status,
+            "synth_status": obs.synth_status,
+            "lint_status": obs.lint_status,
+            "last_action": obs.last_action,
+            "action_result": obs.action_result,
+            "error_summary": obs.error_summary,
+            "metadata": obs.metadata,
+            "step_count": obs.step_count,
+            "max_steps": obs.max_steps,
+        }
+
+        prompt = build_prompt(obs_dict)
+        raw_response = call_llm(
+            client=client,
+            model=args.model,
+            prompt=prompt,
+            temperature=args.temperature,
+        )
+
+        parsed = parse_action(raw_response)
+        if parsed is None:
+            parsed = {"action_type": "run_simulation", "reasoning": "Failed to parse"}
+
+        action_dict = validate_action(parsed)
+        reasoning = parsed.get("reasoning", "")
+
+        action = ChipforgeAction(**action_dict)
+        obs = env.step(action)
+        step_reward = float(obs.reward or 0.0)
+        total_reward += step_reward
+
+        action_str = action_dict["action_type"]
+        if action_dict["action_type"] == "edit_line":
+            action_str += f"({action_dict.get('line_number', '?')})"
+
+        print(
+            f"  step={step + 1:02d}  action={action_str:25s}  "
+            f"reward={step_reward:+.3f}  return={total_reward:+.3f}  done={obs.done}"
+        )
+        if reasoning:
+            print(f"          reasoning: {reasoning[:80]}")
+
+        if obs.done:
+            break
+
+    env.close()
+    print(f"\n  Final episode return: {total_reward:+.3f}")
+    return total_reward
+
+
+# ---------------------------------------------------------------------------
+# CLI
+# ---------------------------------------------------------------------------
+
+
+def build_arg_parser() -> argparse.ArgumentParser:
+    parser = argparse.ArgumentParser(
+        description="Run an LLM agent against ChipForge RTL Debugging Environment."
+    )
+    parser.add_argument("--mode", choices=["local", "http"], default="http")
+    parser.add_argument("--env-url", default="http://localhost:8000")
+    parser.add_argument("--model", default=DEFAULT_LLM_MODEL)
+    parser.add_argument("--api-key", default=os.environ.get("MISTRAL_API_KEY"))
+    parser.add_argument("--episodes", type=int, default=1)
+    parser.add_argument("--max-steps", type=int, default=20)
+    parser.add_argument("--seed", type=int, default=None)
+    parser.add_argument(
+        "--task-name",
+        default=None,
+        help="Optional task directory name under server/tasks (e.g. easy/03_write_testbench_from_prompt).",
+    )
+    parser.add_argument("--temperature", type=float, default=0.2)
+    return parser
+
+
+def main() -> int:
+    args = build_arg_parser().parse_args()
+
+    total_rewards = []
+    for episode in range(args.episodes):
+        print(f"\n{'='*60}")
+        print(f"  Episode {episode + 1}/{args.episodes}")
+        print(f"{'='*60}")
+
+        if args.mode == "local":
+            reward = run_local_episode(args)
+        else:
+            reward = run_http_episode(args)
+
+        total_rewards.append(reward)
+
+    # Summary
+    avg = sum(total_rewards) / len(total_rewards)
+    print(f"\n{'='*60}")
+    print(f"  Summary: {len(total_rewards)} episodes, avg reward: {avg:+.3f}")
+    print(f"  Rewards: {[f'{r:+.3f}' for r in total_rewards]}")
+    print(f"{'='*60}")
+
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())

models.py

@@ -0,0 +1,164 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+"""
+Data models for the ChipForge RTL Debugging Environment.
+
+Designed for RL training of LLMs:
+  - Observation is a self-contained Markov state (always includes RTL code)
+  - Reward uses potential-based shaping for dense per-step signal
+  - Action result feedback at every step
+"""
+
+from typing import Any, Dict, Literal, Optional
+
+from openenv.core.env_server.types import Action, Observation
+from pydantic import Field, model_validator
+
+ActionType = Literal[
+    "view_testbench",
+    "view_synthesis_log",
+    "view_lint_log",
+    "view_simulation_log",
+    "run_simulation",
+    "run_synthesis",
+    "run_lint",
+    "edit_line",
+    "append_line",
+    "edit_testbench_line",
+    "append_testbench_line",
+    "submit",
+]
+
+
+class ChipforgeAction(Action):
+    """Action for the ChipForge environment.
+
+    Supported action_types:
+        - view_testbench: View the testbench code
+        - view_synthesis_log: View synthesis log (only if run_synthesis was executed)
+        - view_lint_log: View lint log (only if run_lint was executed)
+        - view_simulation_log: View simulation log (only if run_simulation was executed)
+        - run_simulation: Compile and simulate with Verilator
+        - run_synthesis: Synthesize with Yosys
+        - run_lint: Run Verilator lint checks
+        - edit_line: Replace a single line (requires line_number + new_content)
+        - append_line: Append one new RTL line (requires new_content)
+        - edit_testbench_line: Replace a single testbench line (requires line_number + new_content)
+        - append_testbench_line: Append one new testbench line (requires new_content)
+        - submit: Submit current RTL as the final solution
+    """
+
+    action_type: ActionType = Field(..., description="Type of action to execute")
+    line_number: Optional[int] = Field(
+        default=None,
+        description="Line number to edit (1-indexed). Required for edit_line.",
+    )
+    new_content: Optional[str] = Field(
+        default=None,
+        description="New content for the line. Required for edit_line.",
+    )
+    log_type: Optional[str] = Field(
+        default=None,
+        description="Deprecated. Use view_synthesis_log, view_lint_log, or view_simulation_log instead.",
+    )
+
+    @model_validator(mode="after")
+    def validate_action_payload(self) -> "ChipforgeAction":
+        is_edit = self.action_type == "edit_line"
+        is_append = self.action_type == "append_line"
+        is_tb_edit = self.action_type == "edit_testbench_line"
+        is_tb_append = self.action_type == "append_testbench_line"
+        has_line = self.line_number is not None
+        has_content = self.new_content is not None
+
+        if is_edit and (not has_line or not has_content):
+            raise ValueError("edit_line requires both line_number and new_content")
+
+        if is_tb_edit and (not has_line or not has_content):
+            raise ValueError("edit_testbench_line requires both line_number and new_content")
+
+        if (is_append or is_tb_append) and (not has_content or has_line):
+            raise ValueError(
+                "append_line/append_testbench_line require new_content only"
+            )
+
+        if (not is_edit and not is_tb_edit and not is_append and not is_tb_append) and (
+            has_line or has_content
+        ):
+            raise ValueError(
+                "line_number/new_content are only valid for edit_line, append_line, "
+                "edit_testbench_line, append_testbench_line"
+            )
+        return self
+
+
+class ChipforgeObservation(Observation):
+    """Observation returned by the ChipForge environment.
+
+    Designed as a self-contained Markov state for RL training.
+    Always includes the current RTL code.
+    Tool logs are only populated when explicitly requested via:
+        - view_synthesis_log: Shows synthesis logs from last run
+        - view_lint_log: Shows lint logs from last run
+        - view_simulation_log: Shows simulation logs from last run
+    """
+
+    # ── Always populated (Markov state core) ─────────────────────────────
+    rtl_code: str = Field(
+        default="",
+        description="Current RTL design code with line numbers (always present)",
+    )
+    sim_status: Literal["not_run", "pass", "fail", "error"] = Field(
+        default="not_run",
+        description="Latest simulation status for current RTL snapshot",
+    )
+    synth_status: Literal["not_run", "pass", "warning", "error"] = Field(
+        default="not_run",
+        description="Latest synthesis status for current RTL snapshot",
+    )
+    lint_status: Literal["not_run", "clean", "warning", "error"] = Field(
+        default="not_run",
+        description="Latest lint status for current RTL snapshot",
+    )
+    error_summary: str = Field(
+        default="",
+        description="One-line summary of the most relevant diagnostic",
+    )
+    task_description: str = Field(
+        default="",
+        description="Natural language description of the loaded RTL debug task",
+    )
+
+    # Action feedback (what just happened)
+    last_action: str = Field(
+        default="reset", description="The action that produced this observation"
+    )
+    action_result: str = Field(
+        default="",
+        description="Human-readable result of the last action taken",
+    )
+
+    # ── Conditionally populated (verbose action-specific payload) ─────────
+    testbench_code: str = Field(
+        default="", description="Testbench code (populated by view_testbench)"
+    )
+    log_output: str = Field(
+        default="",
+        description="Tool output log, truncated to 2000 chars (populated by view_synthesis_log, view_lint_log, view_simulation_log, or tool runs)",
+    )
+    metadata: Dict[str, Any] = Field(
+        default_factory=dict,
+        description="Optional extra machine-readable fields for clients/prompts",
+    )
+
+    # ── RL signals ──────────────────────────────────────────────────────
+    step_count: int = Field(default=0, description="Steps taken so far")
+    max_steps: int = Field(default=20, description="Maximum allowed steps")
+    cumulative_reward: float = Field(
+        default=0.0,
+        description="Total quality score so far (0.0 to 1.0)",
+    )

obj_dir/Vsim

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:e178e8ea680df686c13f65b6251df05731d0476c78554ebd1cb0bd52f28d0ef4
+size 295160

obj_dir/Vsim.cpp

@@ -0,0 +1,137 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Model implementation (design independent parts)
+
+#include "Vsim__pch.h"
+#include "verilated_vcd_c.h"
+
+//============================================================
+// Constructors
+
+Vsim::Vsim(VerilatedContext* _vcontextp__, const char* _vcname__)
+    : VerilatedModel{*_vcontextp__}
+    , vlSymsp{new Vsim__Syms(contextp(), _vcname__, this)}
+    , rootp{&(vlSymsp->TOP)}
+{
+    // Register model with the context
+    contextp()->addModel(this);
+    contextp()->traceBaseModelCbAdd(
+        [this](VerilatedTraceBaseC* tfp, int levels, int options) { traceBaseModel(tfp, levels, options); });
+}
+
+Vsim::Vsim(const char* _vcname__)
+    : Vsim(Verilated::threadContextp(), _vcname__)
+{
+}
+
+//============================================================
+// Destructor
+
+Vsim::~Vsim() {
+    delete vlSymsp;
+}
+
+//============================================================
+// Evaluation function
+
+#ifdef VL_DEBUG
+void Vsim___024root___eval_debug_assertions(Vsim___024root* vlSelf);
+#endif  // VL_DEBUG
+void Vsim___024root___eval_static(Vsim___024root* vlSelf);
+void Vsim___024root___eval_initial(Vsim___024root* vlSelf);
+void Vsim___024root___eval_settle(Vsim___024root* vlSelf);
+void Vsim___024root___eval(Vsim___024root* vlSelf);
+
+void Vsim::eval_step() {
+    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vsim::eval_step\n"); );
+#ifdef VL_DEBUG
+    // Debug assertions
+    Vsim___024root___eval_debug_assertions(&(vlSymsp->TOP));
+#endif  // VL_DEBUG
+    vlSymsp->__Vm_activity = true;
+    vlSymsp->__Vm_deleter.deleteAll();
+    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
+        VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
+        Vsim___024root___eval_static(&(vlSymsp->TOP));
+        Vsim___024root___eval_initial(&(vlSymsp->TOP));
+        Vsim___024root___eval_settle(&(vlSymsp->TOP));
+        vlSymsp->__Vm_didInit = true;
+    }
+    VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
+    Vsim___024root___eval(&(vlSymsp->TOP));
+    // Evaluate cleanup
+    Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
+}
+
+//============================================================
+// Events and timing
+bool Vsim::eventsPending() { return !vlSymsp->TOP.__VdlySched.empty() && !contextp()->gotFinish(); }
+
+uint64_t Vsim::nextTimeSlot() { return vlSymsp->TOP.__VdlySched.nextTimeSlot(); }
+
+//============================================================
+// Utilities
+
+const char* Vsim::name() const {
+    return vlSymsp->name();
+}
+
+//============================================================
+// Invoke final blocks
+
+void Vsim___024root___eval_final(Vsim___024root* vlSelf);
+
+VL_ATTR_COLD void Vsim::final() {
+    contextp()->executingFinal(true);
+    Vsim___024root___eval_final(&(vlSymsp->TOP));
+    contextp()->executingFinal(false);
+}
+
+//============================================================
+// Implementations of abstract methods from VerilatedModel
+
+const char* Vsim::hierName() const { return vlSymsp->name(); }
+const char* Vsim::modelName() const { return "Vsim"; }
+unsigned Vsim::threads() const { return 1; }
+void Vsim::prepareClone() const { contextp()->prepareClone(); }
+void Vsim::atClone() const {
+    contextp()->threadPoolpOnClone();
+}
+std::unique_ptr<VerilatedTraceConfig> Vsim::traceConfig() const {
+    return std::unique_ptr<VerilatedTraceConfig>{new VerilatedTraceConfig{false, false, false}};
+};
+
+//============================================================
+// Trace configuration
+
+void Vsim___024root__trace_decl_types(VerilatedVcd* tracep);
+
+void Vsim___024root__trace_init_top(Vsim___024root* vlSelf, VerilatedVcd* tracep);
+
+VL_ATTR_COLD static void trace_init(void* voidSelf, VerilatedVcd* tracep, uint32_t code) {
+    // Callback from tracep->open()
+    Vsim___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Vsim___024root*>(voidSelf);
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) {
+        VL_FATAL_MT(__FILE__, __LINE__, __FILE__,
+            "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.");
+    }
+    vlSymsp->__Vm_baseCode = code;
+    tracep->pushPrefix(vlSymsp->name(), VerilatedTracePrefixType::SCOPE_MODULE);
+    Vsim___024root__trace_decl_types(tracep);
+    Vsim___024root__trace_init_top(vlSelf, tracep);
+    tracep->popPrefix();
+}
+
+VL_ATTR_COLD void Vsim___024root__trace_register(Vsim___024root* vlSelf, VerilatedVcd* tracep);
+
+VL_ATTR_COLD void Vsim::traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options) {
+    (void)levels; (void)options;
+    VerilatedVcdC* const stfp = dynamic_cast<VerilatedVcdC*>(tfp);
+    if (VL_UNLIKELY(!stfp)) {
+        vl_fatal(__FILE__, __LINE__, __FILE__,"'Vsim::trace()' called on non-VerilatedVcdC object;"
+            " use --trace-fst with VerilatedFst object, and --trace-vcd with VerilatedVcd object");
+    }
+    stfp->spTrace()->addModel(this);
+    stfp->spTrace()->addInitCb(&trace_init, &(vlSymsp->TOP), name(), false, 6);
+    Vsim___024root__trace_register(&(vlSymsp->TOP), stfp->spTrace());
+}

obj_dir/Vsim.h

@@ -0,0 +1,89 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Primary model header
+//
+// This header should be included by all source files instantiating the design.
+// The class here is then constructed to instantiate the design.
+// See the Verilator manual for examples.
+
+#ifndef VERILATED_VSIM_H_
+#define VERILATED_VSIM_H_  // guard
+
+#include "verilated.h"
+
+class Vsim__Syms;
+class Vsim___024root;
+class VerilatedVcdC;
+
+// This class is the main interface to the Verilated model
+class alignas(VL_CACHE_LINE_BYTES) Vsim VL_NOT_FINAL : public VerilatedModel {
+  private:
+    // Symbol table holding complete model state (owned by this class)
+    Vsim__Syms* const vlSymsp;
+
+  public:
+
+    // CONSTEXPR CAPABILITIES
+    // Verilated with --trace?
+    static constexpr bool traceCapable = true;
+
+    // PORTS
+    // The application code writes and reads these signals to
+    // propagate new values into/out from the Verilated model.
+
+    // CELLS
+    // Public to allow access to /* verilator public */ items.
+    // Otherwise the application code can consider these internals.
+
+    // Root instance pointer to allow access to model internals,
+    // including inlined /* verilator public_flat_* */ items.
+    Vsim___024root* const rootp;
+
+    // CONSTRUCTORS
+    /// Construct the model; called by application code
+    /// If contextp is null, then the model will use the default global context
+    /// If name is "", then makes a wrapper with a
+    /// single model invisible with respect to DPI scope names.
+    explicit Vsim(VerilatedContext* contextp, const char* name = "TOP");
+    explicit Vsim(const char* name = "TOP");
+    /// Destroy the model; called (often implicitly) by application code
+    virtual ~Vsim();
+  private:
+    VL_UNCOPYABLE(Vsim);  ///< Copying not allowed
+
+  public:
+    // API METHODS
+    /// Evaluate the model.  Application must call when inputs change.
+    void eval() { eval_step(); }
+    /// Evaluate when calling multiple units/models per time step.
+    void eval_step();
+    /// Evaluate at end of a timestep for tracing, when using eval_step().
+    /// Application must call after all eval() and before time changes.
+    void eval_end_step() {}
+    /// Simulation complete, run final blocks.  Application must call on completion.
+    void final();
+    /// Are there scheduled events to handle?
+    bool eventsPending();
+    /// Returns time at next time slot. Aborts if !eventsPending()
+    uint64_t nextTimeSlot();
+    /// Trace signals in the model; called by application code
+    void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0) { contextp()->trace(tfp, levels, options); }
+    /// Retrieve name of this model instance (as passed to constructor).
+    const char* name() const;
+
+    // Abstract methods from VerilatedModel
+    const char* hierName() const override final;
+    const char* modelName() const override final;
+    unsigned threads() const override final;
+    /// Prepare for cloning the model at the process level (e.g. fork in Linux)
+    /// Release necessary resources. Called before cloning.
+    void prepareClone() const;
+    /// Re-init after cloning the model at the process level (e.g. fork in Linux)
+    /// Re-allocate necessary resources. Called after cloning.
+    void atClone() const;
+    std::unique_ptr<VerilatedTraceConfig> traceConfig() const override final;
+  private:
+    // Internal functions - trace registration
+    void traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options);
+};
+
+#endif  // guard

obj_dir/Vsim.mk

@@ -0,0 +1,66 @@
+# Verilated -*- Makefile -*-
+# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
+#
+# Execute this makefile from the object directory:
+#    make -f Vsim.mk
+
+default: Vsim
+
+### Constants...
+# Perl executable (from $PERL, defaults to 'perl' if not set)
+PERL = perl
+# Python3 executable (from $PYTHON3, defaults to 'python3' if not set)
+PYTHON3 = python3
+# Path to Verilator kit (from $VERILATOR_ROOT)
+VERILATOR_ROOT = /opt/oss-cad-suite/share/verilator
+# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
+SYSTEMC_INCLUDE ?=
+# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
+SYSTEMC_LIBDIR ?=
+
+### Switches...
+# C++ code coverage  0/1 (from --prof-c)
+VM_PROFC = 0
+# SystemC output mode?  0/1 (from --sc)
+VM_SC = 0
+# Legacy or SystemC output mode?  0/1 (from --sc)
+VM_SP_OR_SC = $(VM_SC)
+# Deprecated
+VM_PCLI = 1
+# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
+VM_SC_TARGET_ARCH = linux
+
+### Vars...
+# Design prefix (from --prefix)
+VM_PREFIX = Vsim
+# Module prefix (from --prefix)
+VM_MODPREFIX = Vsim
+# User CFLAGS (from -CFLAGS on Verilator command line)
+VM_USER_CFLAGS = \
+  -DVL_TIME_CONTEXT \
+
+# User LDLIBS (from -LDFLAGS on Verilator command line)
+VM_USER_LDLIBS = \
+
+# User .cpp files (from .cpp's on Verilator command line)
+VM_USER_CLASSES = \
+
+# User .cpp directories (from .cpp's on Verilator command line)
+VM_USER_DIR = \
+  .. \
+
+### Default rules...
+# Include list of all generated classes
+include Vsim_classes.mk
+# Include global rules
+include $(VERILATOR_ROOT)/include/verilated.mk
+
+### Executable rules... (from --exe)
+VPATH += $(VM_USER_DIR)
+
+
+### Link rules... (from --exe)
+Vsim: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
+	$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
+
+# Verilated -*- Makefile -*-

obj_dir/Vsim__ALL.cpp

@@ -0,0 +1,11 @@
+// DESCRIPTION: Generated by verilator_includer via makefile
+#define VL_INCLUDE_OPT include
+#include "Vsim.cpp"
+#include "Vsim___024root__0.cpp"
+#include "Vsim__main.cpp"
+#include "Vsim__Trace__0.cpp"
+#include "Vsim___024root__Slow.cpp"
+#include "Vsim___024root__0__Slow.cpp"
+#include "Vsim__Syms__Slow.cpp"
+#include "Vsim__Trace__0__Slow.cpp"
+#include "Vsim__TraceDecls__0__Slow.cpp"

obj_dir/Vsim__ALL.d

@@ -0,0 +1,15 @@
+Vsim__ALL.o: Vsim__ALL.cpp Vsim.cpp Vsim__pch.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h \
+ Vsim__Syms.h Vsim.h Vsim___024root.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_timing.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_vcd_c.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_trace.h \
+ Vsim___024root__0.cpp Vsim__main.cpp Vsim__Trace__0.cpp \
+ Vsim___024root__Slow.cpp Vsim___024root__0__Slow.cpp \
+ Vsim__Syms__Slow.cpp Vsim__Trace__0__Slow.cpp \
+ Vsim__TraceDecls__0__Slow.cpp

obj_dir/Vsim__Syms.h

@@ -0,0 +1,40 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Symbol table internal header
+//
+// Internal details; most calling programs do not need this header,
+// unless using verilator public meta comments.
+
+#ifndef VERILATED_VSIM__SYMS_H_
+#define VERILATED_VSIM__SYMS_H_  // guard
+
+#include "verilated.h"
+
+// INCLUDE MODEL CLASS
+
+#include "Vsim.h"
+
+// INCLUDE MODULE CLASSES
+#include "Vsim___024root.h"
+
+// SYMS CLASS (contains all model state)
+class alignas(VL_CACHE_LINE_BYTES) Vsim__Syms final : public VerilatedSyms {
+  public:
+    // INTERNAL STATE
+    Vsim* const __Vm_modelp;
+    bool __Vm_activity = false;  ///< Used by trace routines to determine change occurred
+    uint32_t __Vm_baseCode = 0;  ///< Used by trace routines when tracing multiple models
+    VlDeleter __Vm_deleter;
+    bool __Vm_didInit = false;
+
+    // MODULE INSTANCE STATE
+    Vsim___024root                 TOP;
+
+    // CONSTRUCTORS
+    Vsim__Syms(VerilatedContext* contextp, const char* namep, Vsim* modelp);
+    ~Vsim__Syms();
+
+    // METHODS
+    const char* name() const { return TOP.vlNamep; }
+};
+
+#endif  // guard

obj_dir/Vsim__Syms__Slow.cpp

@@ -0,0 +1,28 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Symbol table implementation internals
+
+#include "Vsim__pch.h"
+
+Vsim__Syms::Vsim__Syms(VerilatedContext* contextp, const char* namep, Vsim* modelp)
+    : VerilatedSyms{contextp}
+    // Setup internal state of the Syms class
+    , __Vm_modelp{modelp}
+    // Setup top module instance
+    , TOP{this, namep}
+{
+    // Check resources
+    Verilated::stackCheck(256);
+    // Setup sub module instances
+    // Configure time unit / time precision
+    _vm_contextp__->timeunit(-9);
+    _vm_contextp__->timeprecision(-12);
+    // Setup each module's pointers to their submodules
+    // Setup each module's pointer back to symbol table (for public functions)
+    TOP.__Vconfigure(true);
+    // Setup scopes
+}
+
+Vsim__Syms::~Vsim__Syms() {
+    // Tear down scopes
+    // Tear down sub module instances
+}

obj_dir/Vsim__TraceDecls__0__Slow.cpp

@@ -0,0 +1,12 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Tracing declarations
+
+#include "verilated_vcd_c.h"
+
+
+void Vsim___024root__traceDeclTypesSub0(VerilatedVcd* tracep) {
+}
+
+void Vsim___024root__trace_decl_types(VerilatedVcd* tracep) {
+    Vsim___024root__traceDeclTypesSub0(tracep);
+}

obj_dir/Vsim__Trace__0.cpp

@@ -0,0 +1,52 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Tracing implementation internals
+
+#include "verilated_vcd_c.h"
+#include "Vsim__Syms.h"
+
+
+void Vsim___024root__trace_chg_0_sub_0(Vsim___024root* vlSelf, VerilatedVcd::Buffer* bufp);
+
+void Vsim___024root__trace_chg_0(void* voidSelf, VerilatedVcd::Buffer* bufp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_chg_0\n"); );
+    // Body
+    Vsim___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Vsim___024root*>(voidSelf);
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    if (VL_UNLIKELY(!vlSymsp->__Vm_activity)) return;
+    Vsim___024root__trace_chg_0_sub_0((&vlSymsp->TOP), bufp);
+}
+
+void Vsim___024root__trace_chg_0_sub_0(Vsim___024root* vlSelf, VerilatedVcd::Buffer* bufp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_chg_0_sub_0\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    uint32_t* const oldp VL_ATTR_UNUSED = bufp->oldp(vlSymsp->__Vm_baseCode + 0);
+    if (VL_UNLIKELY(((vlSelfRef.__Vm_traceActivity[1U] 
+                      | vlSelfRef.__Vm_traceActivity[2U])))) {
+        bufp->chgBit(oldp+0,(vlSelfRef.tb_full_adder__DOT__a));
+        bufp->chgBit(oldp+1,(vlSelfRef.tb_full_adder__DOT__b));
+        bufp->chgBit(oldp+2,(vlSelfRef.tb_full_adder__DOT__cin));
+        bufp->chgBit(oldp+3,(((IData)(vlSelfRef.tb_full_adder__DOT__cin) 
+                              ^ ((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                                 ^ (IData)(vlSelfRef.tb_full_adder__DOT__b)))));
+        bufp->chgBit(oldp+4,((((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                               & (IData)(vlSelfRef.tb_full_adder__DOT__b)) 
+                              | ((IData)(vlSelfRef.tb_full_adder__DOT__cin) 
+                                 & ((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                                    | (IData)(vlSelfRef.tb_full_adder__DOT__b))))));
+        bufp->chgBit(oldp+5,(((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                              ^ (IData)(vlSelfRef.tb_full_adder__DOT__b))));
+    }
+}
+
+void Vsim___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_cleanup\n"); );
+    // Body
+    Vsim___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Vsim___024root*>(voidSelf);
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    vlSymsp->__Vm_activity = false;
+    vlSymsp->TOP.__Vm_traceActivity[0U] = 0U;
+    vlSymsp->TOP.__Vm_traceActivity[1U] = 0U;
+    vlSymsp->TOP.__Vm_traceActivity[2U] = 0U;
+}

obj_dir/Vsim__Trace__0__Slow.cpp

@@ -0,0 +1,95 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Tracing implementation internals
+
+#include "verilated_vcd_c.h"
+#include "Vsim__Syms.h"
+
+
+VL_ATTR_COLD void Vsim___024root__trace_init_sub__TOP__0(Vsim___024root* vlSelf, VerilatedVcd* tracep) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_init_sub__TOP__0\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    const int c = vlSymsp->__Vm_baseCode;
+    VL_TRACE_PUSH_PREFIX(tracep, "tb_full_adder", VerilatedTracePrefixType::SCOPE_MODULE, 0, 0);
+    VL_TRACE_DECL_BIT(tracep,c+0,0,"a",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::VAR, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+1,0,"b",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::VAR, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+2,0,"cin",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::VAR, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+3,0,"sum",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+4,0,"cout",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_PUSH_PREFIX(tracep, "uut", VerilatedTracePrefixType::SCOPE_MODULE, 0, 0);
+    VL_TRACE_DECL_BIT(tracep,c+0,0,"a",-1, VerilatedTraceSigDirection::INPUT, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+1,0,"b",-1, VerilatedTraceSigDirection::INPUT, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+2,0,"cin",-1, VerilatedTraceSigDirection::INPUT, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+3,0,"sum",-1, VerilatedTraceSigDirection::OUTPUT, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+4,0,"cout",-1, VerilatedTraceSigDirection::OUTPUT, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+5,0,"x1",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+5,0,"x2",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+3,0,"x3",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+4,0,"x4",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_DECL_BIT(tracep,c+3,0,"temp",-1, VerilatedTraceSigDirection::NONE, VerilatedTraceSigKind::WIRE, VerilatedTraceSigType::LOGIC);
+    VL_TRACE_POP_PREFIX(tracep);
+    VL_TRACE_POP_PREFIX(tracep);
+}
+
+VL_ATTR_COLD void Vsim___024root__trace_init_top(Vsim___024root* vlSelf, VerilatedVcd* tracep) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_init_top\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    Vsim___024root__trace_init_sub__TOP__0(vlSelf, tracep);
+}
+
+VL_ATTR_COLD void Vsim___024root__trace_const_0(void* voidSelf, VerilatedVcd::Buffer* bufp);
+VL_ATTR_COLD void Vsim___024root__trace_full_0(void* voidSelf, VerilatedVcd::Buffer* bufp);
+void Vsim___024root__trace_chg_0(void* voidSelf, VerilatedVcd::Buffer* bufp);
+void Vsim___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/);
+
+VL_ATTR_COLD void Vsim___024root__trace_register(Vsim___024root* vlSelf, VerilatedVcd* tracep) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_register\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    tracep->addConstCb(&Vsim___024root__trace_const_0, 0, vlSelf);
+    tracep->addFullCb(&Vsim___024root__trace_full_0, 0, vlSelf);
+    tracep->addChgCb(&Vsim___024root__trace_chg_0, 0, vlSelf);
+    tracep->addCleanupCb(&Vsim___024root__trace_cleanup, vlSelf);
+}
+
+VL_ATTR_COLD void Vsim___024root__trace_const_0(void* voidSelf, VerilatedVcd::Buffer* bufp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_const_0\n"); );
+    // Body
+    Vsim___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Vsim___024root*>(voidSelf);
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+}
+
+VL_ATTR_COLD void Vsim___024root__trace_full_0_sub_0(Vsim___024root* vlSelf, VerilatedVcd::Buffer* bufp);
+
+VL_ATTR_COLD void Vsim___024root__trace_full_0(void* voidSelf, VerilatedVcd::Buffer* bufp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_full_0\n"); );
+    // Body
+    Vsim___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Vsim___024root*>(voidSelf);
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    Vsim___024root__trace_full_0_sub_0((&vlSymsp->TOP), bufp);
+}
+
+VL_ATTR_COLD void Vsim___024root__trace_full_0_sub_0(Vsim___024root* vlSelf, VerilatedVcd::Buffer* bufp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root__trace_full_0_sub_0\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    uint32_t* const oldp VL_ATTR_UNUSED = bufp->oldp(vlSymsp->__Vm_baseCode);
+    bufp->fullBit(oldp+0,(vlSelfRef.tb_full_adder__DOT__a));
+    bufp->fullBit(oldp+1,(vlSelfRef.tb_full_adder__DOT__b));
+    bufp->fullBit(oldp+2,(vlSelfRef.tb_full_adder__DOT__cin));
+    bufp->fullBit(oldp+3,(((IData)(vlSelfRef.tb_full_adder__DOT__cin) 
+                           ^ ((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                              ^ (IData)(vlSelfRef.tb_full_adder__DOT__b)))));
+    bufp->fullBit(oldp+4,((((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                            & (IData)(vlSelfRef.tb_full_adder__DOT__b)) 
+                           | ((IData)(vlSelfRef.tb_full_adder__DOT__cin) 
+                              & ((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                                 | (IData)(vlSelfRef.tb_full_adder__DOT__b))))));
+    bufp->fullBit(oldp+5,(((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                           ^ (IData)(vlSelfRef.tb_full_adder__DOT__b))));
+}

obj_dir/Vsim___024root.h

@@ -0,0 +1,52 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design internal header
+// See Vsim.h for the primary calling header
+
+#ifndef VERILATED_VSIM___024ROOT_H_
+#define VERILATED_VSIM___024ROOT_H_  // guard
+
+#include "verilated.h"
+#include "verilated_timing.h"
+
+
+class Vsim__Syms;
+
+class alignas(VL_CACHE_LINE_BYTES) Vsim___024root final {
+  public:
+
+    // DESIGN SPECIFIC STATE
+    CData/*0:0*/ tb_full_adder__DOT__a;
+    CData/*0:0*/ tb_full_adder__DOT__b;
+    CData/*0:0*/ tb_full_adder__DOT__cin;
+    CData/*0:0*/ tb_full_adder__DOT__uut__DOT__sum;
+    CData/*0:0*/ tb_full_adder__DOT__uut__DOT__cout;
+    CData/*0:0*/ __VstlFirstIteration;
+    CData/*0:0*/ __VstlPhaseResult;
+    CData/*0:0*/ __VactPhaseResult;
+    CData/*0:0*/ __VinactPhaseResult;
+    CData/*0:0*/ __VnbaPhaseResult;
+    IData/*31:0*/ __VactIterCount;
+    IData/*31:0*/ __VinactIterCount;
+    IData/*31:0*/ __Vi;
+    VlUnpacked<QData/*63:0*/, 1> __VstlTriggered;
+    VlUnpacked<QData/*63:0*/, 1> __VactTriggered;
+    VlUnpacked<QData/*63:0*/, 1> __VactTriggeredAcc;
+    VlUnpacked<QData/*63:0*/, 1> __VnbaTriggered;
+    VlUnpacked<CData/*0:0*/, 3> __Vm_traceActivity;
+    VlDelayScheduler __VdlySched;
+
+    // INTERNAL VARIABLES
+    Vsim__Syms* vlSymsp;
+    const char* vlNamep;
+
+    // CONSTRUCTORS
+    Vsim___024root(Vsim__Syms* symsp, const char* namep);
+    ~Vsim___024root();
+    VL_UNCOPYABLE(Vsim___024root);
+
+    // INTERNAL METHODS
+    void __Vconfigure(bool first);
+};
+
+
+#endif  // guard

obj_dir/Vsim___024root__0.cpp

@@ -0,0 +1,323 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vsim.h for the primary calling header
+
+#include "Vsim__pch.h"
+
+VlCoroutine Vsim___024root___eval_initial__TOP__Vtiming__0(Vsim___024root* vlSelf);
+
+void Vsim___024root___eval_initial(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_initial\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    Vsim___024root___eval_initial__TOP__Vtiming__0(vlSelf);
+    vlSelfRef.__Vm_traceActivity[1U] = 1U;
+}
+
+VlCoroutine Vsim___024root___eval_initial__TOP__Vtiming__0(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_initial__TOP__Vtiming__0\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    VL_WRITEF_NX("a b cin | sum cout\n-------------------\n",0);
+    vlSelfRef.tb_full_adder__DOT__a = 0U;
+    vlSelfRef.tb_full_adder__DOT__b = 0U;
+    vlSelfRef.tb_full_adder__DOT__cin = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         26);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    vlSelfRef.tb_full_adder__DOT__a = 0U;
+    vlSelfRef.tb_full_adder__DOT__b = 0U;
+    vlSelfRef.tb_full_adder__DOT__cin = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         29);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    vlSelfRef.tb_full_adder__DOT__a = 0U;
+    vlSelfRef.tb_full_adder__DOT__b = 1U;
+    vlSelfRef.tb_full_adder__DOT__cin = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         32);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    vlSelfRef.tb_full_adder__DOT__a = 0U;
+    vlSelfRef.tb_full_adder__DOT__b = 1U;
+    vlSelfRef.tb_full_adder__DOT__cin = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         35);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    vlSelfRef.tb_full_adder__DOT__a = 1U;
+    vlSelfRef.tb_full_adder__DOT__b = 0U;
+    vlSelfRef.tb_full_adder__DOT__cin = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         38);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    vlSelfRef.tb_full_adder__DOT__a = 1U;
+    vlSelfRef.tb_full_adder__DOT__b = 0U;
+    vlSelfRef.tb_full_adder__DOT__cin = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         41);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    vlSelfRef.tb_full_adder__DOT__a = 1U;
+    vlSelfRef.tb_full_adder__DOT__b = 1U;
+    vlSelfRef.tb_full_adder__DOT__cin = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         44);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    vlSelfRef.tb_full_adder__DOT__a = 1U;
+    vlSelfRef.tb_full_adder__DOT__b = 1U;
+    vlSelfRef.tb_full_adder__DOT__cin = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "/workspace/.tmp_verilator/testbench.sv", 
+                                         47);
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    VL_WRITEF_NX("%b %b  %b  |  %b   %b\n",5, '#',1,vlSelfRef.tb_full_adder__DOT__a
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__b)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__cin
+                 , '#',1,(IData)(vlSelfRef.tb_full_adder__DOT__uut__DOT__sum)
+                 , '#',1,vlSelfRef.tb_full_adder__DOT__uut__DOT__cout);
+    VL_FINISH_MT("/workspace/.tmp_verilator/testbench.sv", 50, "");
+    vlSelfRef.__Vm_traceActivity[2U] = 1U;
+    co_return;
+}
+
+void Vsim___024root___eval_triggers_vec__act(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_triggers_vec__act\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    vlSelfRef.__VactTriggered[0U] = (QData)((IData)(vlSelfRef.__VdlySched.awaitingCurrentTime()));
+}
+
+bool Vsim___024root___trigger_anySet__act(const VlUnpacked<QData/*63:0*/, 1> &in) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___trigger_anySet__act\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        if (in[n]) {
+            return (1U);
+        }
+        n = ((IData)(1U) + n);
+    } while ((1U > n));
+    return (0U);
+}
+
+void Vsim___024root___act_sequent__TOP__0(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___act_sequent__TOP__0\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    vlSelfRef.tb_full_adder__DOT__uut__DOT__sum = ((IData)(vlSelfRef.tb_full_adder__DOT__cin) 
+                                                   ^ 
+                                                   ((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+                                                    ^ (IData)(vlSelfRef.tb_full_adder__DOT__b)));
+    vlSelfRef.tb_full_adder__DOT__uut__DOT__cout = 
+        (((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+          & (IData)(vlSelfRef.tb_full_adder__DOT__b)) 
+         | ((IData)(vlSelfRef.tb_full_adder__DOT__cin) 
+            & ((IData)(vlSelfRef.tb_full_adder__DOT__a) 
+               | (IData)(vlSelfRef.tb_full_adder__DOT__b))));
+}
+
+void Vsim___024root___eval_act(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_act\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VactTriggered[0U])) {
+        Vsim___024root___act_sequent__TOP__0(vlSelf);
+    }
+}
+
+void Vsim___024root___eval_nba(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_nba\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VnbaTriggered[0U])) {
+        Vsim___024root___act_sequent__TOP__0(vlSelf);
+    }
+}
+
+void Vsim___024root___timing_resume(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___timing_resume\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VactTriggered[0U])) {
+        vlSelfRef.__VdlySched.resume();
+    }
+}
+
+void Vsim___024root___trigger_orInto__act_vec_vec(VlUnpacked<QData/*63:0*/, 1> &out, const VlUnpacked<QData/*63:0*/, 1> &in) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___trigger_orInto__act_vec_vec\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        out[n] = (out[n] | in[n]);
+        n = ((IData)(1U) + n);
+    } while ((0U >= n));
+}
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vsim___024root___dump_triggers__act(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag);
+#endif  // VL_DEBUG
+
+bool Vsim___024root___eval_phase__act(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_phase__act\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VactExecute;
+    // Body
+    Vsim___024root___eval_triggers_vec__act(vlSelf);
+    Vsim___024root___trigger_orInto__act_vec_vec(vlSelfRef.__VactTriggered, vlSelfRef.__VactTriggeredAcc);
+#ifdef VL_DEBUG
+    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
+        Vsim___024root___dump_triggers__act(vlSelfRef.__VactTriggered, "act"s);
+    }
+#endif
+    Vsim___024root___trigger_orInto__act_vec_vec(vlSelfRef.__VnbaTriggered, vlSelfRef.__VactTriggered);
+    __VactExecute = Vsim___024root___trigger_anySet__act(vlSelfRef.__VactTriggered);
+    if (__VactExecute) {
+        vlSelfRef.__VactTriggeredAcc.fill(0ULL);
+        Vsim___024root___timing_resume(vlSelf);
+        Vsim___024root___eval_act(vlSelf);
+    }
+    return (__VactExecute);
+}
+
+bool Vsim___024root___eval_phase__inact(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_phase__inact\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VinactExecute;
+    // Body
+    __VinactExecute = vlSelfRef.__VdlySched.awaitingZeroDelay();
+    if (__VinactExecute) {
+        VL_FATAL_MT("/workspace/.tmp_verilator/testbench.sv", 3, "", "ZERODLY: Design Verilated with '--no-sched-zero-delay', but #0 delay executed at runtime");
+    }
+    return (__VinactExecute);
+}
+
+void Vsim___024root___trigger_clear__act(VlUnpacked<QData/*63:0*/, 1> &out) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___trigger_clear__act\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        out[n] = 0ULL;
+        n = ((IData)(1U) + n);
+    } while ((1U > n));
+}
+
+bool Vsim___024root___eval_phase__nba(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_phase__nba\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VnbaExecute;
+    // Body
+    __VnbaExecute = Vsim___024root___trigger_anySet__act(vlSelfRef.__VnbaTriggered);
+    if (__VnbaExecute) {
+        Vsim___024root___eval_nba(vlSelf);
+        Vsim___024root___trigger_clear__act(vlSelfRef.__VnbaTriggered);
+    }
+    return (__VnbaExecute);
+}
+
+void Vsim___024root___eval(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    IData/*31:0*/ __VnbaIterCount;
+    // Body
+    __VnbaIterCount = 0U;
+    do {
+        if (VL_UNLIKELY(((0x00002710U < __VnbaIterCount)))) {
+#ifdef VL_DEBUG
+            Vsim___024root___dump_triggers__act(vlSelfRef.__VnbaTriggered, "nba"s);
+#endif
+            VL_FATAL_MT("/workspace/.tmp_verilator/testbench.sv", 3, "", "DIDNOTCONVERGE: NBA region did not converge after '--converge-limit' of 10000 tries");
+        }
+        __VnbaIterCount = ((IData)(1U) + __VnbaIterCount);
+        vlSelfRef.__VinactIterCount = 0U;
+        do {
+            if (VL_UNLIKELY(((0x00002710U < vlSelfRef.__VinactIterCount)))) {
+                VL_FATAL_MT("/workspace/.tmp_verilator/testbench.sv", 3, "", "DIDNOTCONVERGE: Inactive region did not converge after '--converge-limit' of 10000 tries");
+            }
+            vlSelfRef.__VinactIterCount = ((IData)(1U) 
+                                           + vlSelfRef.__VinactIterCount);
+            vlSelfRef.__VactIterCount = 0U;
+            do {
+                if (VL_UNLIKELY(((0x00002710U < vlSelfRef.__VactIterCount)))) {
+#ifdef VL_DEBUG
+                    Vsim___024root___dump_triggers__act(vlSelfRef.__VactTriggered, "act"s);
+#endif
+                    VL_FATAL_MT("/workspace/.tmp_verilator/testbench.sv", 3, "", "DIDNOTCONVERGE: Active region did not converge after '--converge-limit' of 10000 tries");
+                }
+                vlSelfRef.__VactIterCount = ((IData)(1U) 
+                                             + vlSelfRef.__VactIterCount);
+                vlSelfRef.__VactPhaseResult = Vsim___024root___eval_phase__act(vlSelf);
+            } while (vlSelfRef.__VactPhaseResult);
+            vlSelfRef.__VinactPhaseResult = Vsim___024root___eval_phase__inact(vlSelf);
+        } while (vlSelfRef.__VinactPhaseResult);
+        vlSelfRef.__VnbaPhaseResult = Vsim___024root___eval_phase__nba(vlSelf);
+    } while (vlSelfRef.__VnbaPhaseResult);
+}
+
+#ifdef VL_DEBUG
+void Vsim___024root___eval_debug_assertions(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_debug_assertions\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+}
+#endif  // VL_DEBUG

obj_dir/Vsim___024root__0__Slow.cpp

@@ -0,0 +1,166 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vsim.h for the primary calling header
+
+#include "Vsim__pch.h"
+
+VL_ATTR_COLD void Vsim___024root___eval_static(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_static\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    do {
+        vlSelfRef.__VactTriggeredAcc[vlSelfRef.__Vi] 
+            = vlSelfRef.__VactTriggered[vlSelfRef.__Vi];
+        vlSelfRef.__Vi = ((IData)(1U) + vlSelfRef.__Vi);
+    } while ((0U >= vlSelfRef.__Vi));
+}
+
+VL_ATTR_COLD void Vsim___024root___eval_final(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_final\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+}
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vsim___024root___dump_triggers__stl(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag);
+#endif  // VL_DEBUG
+VL_ATTR_COLD bool Vsim___024root___eval_phase__stl(Vsim___024root* vlSelf);
+
+VL_ATTR_COLD void Vsim___024root___eval_settle(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_settle\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    IData/*31:0*/ __VstlIterCount;
+    // Body
+    __VstlIterCount = 0U;
+    vlSelfRef.__VstlFirstIteration = 1U;
+    do {
+        if (VL_UNLIKELY(((0x00002710U < __VstlIterCount)))) {
+#ifdef VL_DEBUG
+            Vsim___024root___dump_triggers__stl(vlSelfRef.__VstlTriggered, "stl"s);
+#endif
+            VL_FATAL_MT("/workspace/.tmp_verilator/testbench.sv", 3, "", "DIDNOTCONVERGE: Settle region did not converge after '--converge-limit' of 10000 tries");
+        }
+        __VstlIterCount = ((IData)(1U) + __VstlIterCount);
+        vlSelfRef.__VstlPhaseResult = Vsim___024root___eval_phase__stl(vlSelf);
+        vlSelfRef.__VstlFirstIteration = 0U;
+    } while (vlSelfRef.__VstlPhaseResult);
+}
+
+VL_ATTR_COLD void Vsim___024root___eval_triggers_vec__stl(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_triggers_vec__stl\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    vlSelfRef.__VstlTriggered[0U] = ((0xfffffffffffffffeULL 
+                                      & vlSelfRef.__VstlTriggered[0U]) 
+                                     | (IData)((IData)(vlSelfRef.__VstlFirstIteration)));
+}
+
+VL_ATTR_COLD bool Vsim___024root___trigger_anySet__stl(const VlUnpacked<QData/*63:0*/, 1> &in);
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vsim___024root___dump_triggers__stl(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___dump_triggers__stl\n"); );
+    // Body
+    if ((1U & (~ (IData)(Vsim___024root___trigger_anySet__stl(triggers))))) {
+        VL_DBG_MSGS("         No '" + tag + "' region triggers active\n");
+    }
+    if ((1U & (IData)(triggers[0U]))) {
+        VL_DBG_MSGS("         '" + tag + "' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n");
+    }
+}
+#endif  // VL_DEBUG
+
+VL_ATTR_COLD bool Vsim___024root___trigger_anySet__stl(const VlUnpacked<QData/*63:0*/, 1> &in) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___trigger_anySet__stl\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        if (in[n]) {
+            return (1U);
+        }
+        n = ((IData)(1U) + n);
+    } while ((1U > n));
+    return (0U);
+}
+
+void Vsim___024root___act_sequent__TOP__0(Vsim___024root* vlSelf);
+
+VL_ATTR_COLD void Vsim___024root___eval_stl(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_stl\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VstlTriggered[0U])) {
+        Vsim___024root___act_sequent__TOP__0(vlSelf);
+    }
+}
+
+VL_ATTR_COLD bool Vsim___024root___eval_phase__stl(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___eval_phase__stl\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VstlExecute;
+    // Body
+    Vsim___024root___eval_triggers_vec__stl(vlSelf);
+#ifdef VL_DEBUG
+    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
+        Vsim___024root___dump_triggers__stl(vlSelfRef.__VstlTriggered, "stl"s);
+    }
+#endif
+    __VstlExecute = Vsim___024root___trigger_anySet__stl(vlSelfRef.__VstlTriggered);
+    if (__VstlExecute) {
+        Vsim___024root___eval_stl(vlSelf);
+    }
+    return (__VstlExecute);
+}
+
+bool Vsim___024root___trigger_anySet__act(const VlUnpacked<QData/*63:0*/, 1> &in);
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vsim___024root___dump_triggers__act(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___dump_triggers__act\n"); );
+    // Body
+    if ((1U & (~ (IData)(Vsim___024root___trigger_anySet__act(triggers))))) {
+        VL_DBG_MSGS("         No '" + tag + "' region triggers active\n");
+    }
+    if ((1U & (IData)(triggers[0U]))) {
+        VL_DBG_MSGS("         '" + tag + "' region trigger index 0 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
+    }
+}
+#endif  // VL_DEBUG
+
+VL_ATTR_COLD void Vsim___024root___ctor_var_reset(Vsim___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vsim___024root___ctor_var_reset\n"); );
+    Vsim__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    const uint64_t __VscopeHash = VL_MURMUR64_HASH(vlSelf->vlNamep);
+    vlSelf->tb_full_adder__DOT__a = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 13747735994981389321ull);
+    vlSelf->tb_full_adder__DOT__b = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 686105649783556071ull);
+    vlSelf->tb_full_adder__DOT__cin = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 4012772730186193120ull);
+    vlSelf->tb_full_adder__DOT__uut__DOT__sum = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 13287595272639865983ull);
+    vlSelf->tb_full_adder__DOT__uut__DOT__cout = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 13664396158812022014ull);
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VstlTriggered[__Vi0] = 0;
+    }
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VactTriggered[__Vi0] = 0;
+    }
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VactTriggeredAcc[__Vi0] = 0;
+    }
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VnbaTriggered[__Vi0] = 0;
+    }
+    vlSelf->__Vi = 0;
+    for (int __Vi0 = 0; __Vi0 < 3; ++__Vi0) {
+        vlSelf->__Vm_traceActivity[__Vi0] = 0;
+    }
+}

obj_dir/Vsim___024root__Slow.cpp

@@ -0,0 +1,24 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vsim.h for the primary calling header
+
+#include "Vsim__pch.h"
+
+void Vsim___024root___ctor_var_reset(Vsim___024root* vlSelf);
+
+Vsim___024root::Vsim___024root(Vsim__Syms* symsp, const char* namep)
+    : __VdlySched{*symsp->_vm_contextp__}
+ {
+    vlSymsp = symsp;
+    vlNamep = strdup(namep);
+    // Reset structure values
+    Vsim___024root___ctor_var_reset(this);
+}
+
+void Vsim___024root::__Vconfigure(bool first) {
+    (void)first;  // Prevent unused variable warning
+}
+
+Vsim___024root::~Vsim___024root() {
+    VL_DO_DANGLING(std::free(const_cast<char*>(vlNamep)), vlNamep);
+}

obj_dir/Vsim__main.cpp

@@ -0,0 +1,40 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: main() simulation loop, created with --main
+
+#include "verilated.h"
+#include "Vsim.h"
+
+//======================
+
+int main(int argc, char** argv, char**) {
+    // Setup context, defaults, and parse command line
+    Verilated::debug(0);
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    contextp->traceEverOn(true);
+    contextp->threads(1);
+    contextp->commandArgs(argc, argv);
+
+    // Construct the Verilated model, from Vtop.h generated from Verilating
+    const std::unique_ptr<Vsim> topp{new Vsim{contextp.get(), ""}};
+
+    // Simulate until $finish
+    while (VL_LIKELY(!contextp->gotFinish())) {
+        // Evaluate model
+        topp->eval();
+        // Advance time
+        if (!topp->eventsPending()) break;
+        contextp->time(topp->nextTimeSlot());
+    }
+
+    if (VL_LIKELY(!contextp->gotFinish())) {
+        VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
+    }
+
+    // Execute 'final' processes
+    topp->final();
+
+    // Print statistical summary report
+    contextp->statsPrintSummary();
+
+    return 0;
+}

obj_dir/Vsim__pch.h

@@ -0,0 +1,27 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Precompiled header
+//
+// Internal details; most user sources do not need this header,
+// unless using verilator public meta comments.
+// Suggest use Vsim.h instead.
+
+#ifndef VERILATED_VSIM__PCH_H_
+#define VERILATED_VSIM__PCH_H_  // guard
+
+// GCC and Clang only will precompile headers (PCH) for the first header.
+// So, make sure this is the one and only PCH.
+// If multiple module's includes are needed, use individual includes.
+#ifdef VL_PCH_INCLUDED
+# error "Including multiple precompiled header files"
+#endif
+#define VL_PCH_INCLUDED
+
+
+#include "verilated.h"
+
+#include "Vsim__Syms.h"
+#include "Vsim.h"
+
+// Additional include files added using '--compiler-include'
+
+#endif  // guard

obj_dir/Vsim__ver.d

@@ -0,0 +1 @@
+obj_dir/Vsim.cpp obj_dir/Vsim.h obj_dir/Vsim.mk obj_dir/Vsim__Syms.h obj_dir/Vsim__Syms__Slow.cpp obj_dir/Vsim__TraceDecls__0__Slow.cpp obj_dir/Vsim__Trace__0.cpp obj_dir/Vsim__Trace__0__Slow.cpp obj_dir/Vsim___024root.h obj_dir/Vsim___024root__0.cpp obj_dir/Vsim___024root__0__Slow.cpp obj_dir/Vsim___024root__Slow.cpp obj_dir/Vsim__main.cpp obj_dir/Vsim__pch.h obj_dir/Vsim__ver.d obj_dir/Vsim_classes.mk  : /opt/oss-cad-suite/libexec/verilator_bin /opt/oss-cad-suite/libexec/verilator_bin /opt/oss-cad-suite/share/verilator/include/verilated_std.sv /opt/oss-cad-suite/share/verilator/include/verilated_std_waiver.vlt /workspace/.tmp_verilator/design.sv /workspace/.tmp_verilator/testbench.sv 

obj_dir/Vsim__verFiles.dat

@@ -0,0 +1,24 @@
+# DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
+C "--prefix Vsim --binary --build-jobs 0 --build --trace-vcd --quiet-build -Wno-fatal --timescale 1ns/1ns /workspace/.tmp_verilator/design.sv /workspace/.tmp_verilator/testbench.sv"
+S  15470064   408335  1775589273   781926010  1775535881           0 "unhashed" "/opt/oss-cad-suite/libexec/verilator_bin"
+S      7905   417104  1775589275   228926010  1775535881           0 "vaoJo7Sb62R3p7xvCJKmh57f4Cpmx2GHt7zuj5gO" "/opt/oss-cad-suite/share/verilator/include/verilated_std.sv"
+S      3224   417105  1775589275   228926010  1775535881           0 "Hydzkv9X77JH03JyZeFi7tBFnQaHV7yknXQxBZFr" "/opt/oss-cad-suite/share/verilator/include/verilated_std_waiver.vlt"
+S       508       23  1775588927   379763036  1775588927   379763036 "RzP0e7y9BjAWuxPxEHd8sMbLhVMBBykyireN9BO5" "/workspace/.tmp_verilator/design.sv"
+S       994       22  1775588850   546387233  1775588850   546387233 "MJHSal6XoThtIDgaccnyRos1QWroJuR0B5ti7XBh" "/workspace/.tmp_verilator/testbench.sv"
+T      5052       28  1775589279   970070246  1775589279   970070246 "unhashed" "obj_dir/Vsim.cpp"
+T      3496       27  1775589279   969891205  1775589279   969891205 "unhashed" "obj_dir/Vsim.h"
+T      1850       39  1775589279   972469243  1775589279   972469243 "unhashed" "obj_dir/Vsim.mk"
+T      1100       26  1775589279   969740413  1775589279   969740413 "unhashed" "obj_dir/Vsim__Syms.h"
+T       851       25  1775589279   969551330  1775589279   969551330 "unhashed" "obj_dir/Vsim__Syms__Slow.cpp"
+T       291       34  1775589279   971867244  1775589279   971867244 "unhashed" "obj_dir/Vsim__TraceDecls__0__Slow.cpp"
+T      2687       36  1775589279   972046036  1775589279   972046036 "unhashed" "obj_dir/Vsim__Trace__0.cpp"
+T      6323       35  1775589279   971777952  1775589279   971777952 "unhashed" "obj_dir/Vsim__Trace__0__Slow.cpp"
+T      1476       30  1775589279   970559246  1775589279   970559246 "unhashed" "obj_dir/Vsim___024root.h"
+T     15367       33  1775589279   971426953  1775589279   971426953 "unhashed" "obj_dir/Vsim___024root__0.cpp"
+T      6982       32  1775589279   971074662  1775589279   971074662 "unhashed" "obj_dir/Vsim___024root__0__Slow.cpp"
+T       674       31  1775589279   970776829  1775589279   970776829 "unhashed" "obj_dir/Vsim___024root__Slow.cpp"
+T      1137       37  1775589279   972180619  1775589279   972180619 "unhashed" "obj_dir/Vsim__main.cpp"
+T       745       29  1775589279   970367704  1775589279   970367704 "unhashed" "obj_dir/Vsim__pch.h"
+T       696       40  1775589279   972557452  1775589279   972557452 "unhashed" "obj_dir/Vsim__ver.d"
+T         0        0  1775589279   972619952  1775589279   972619952 "unhashed" "obj_dir/Vsim__verFiles.dat"
+T      1745       38  1775589279   972333494  1775589279   972333494 "unhashed" "obj_dir/Vsim_classes.mk"

obj_dir/Vsim_classes.mk

@@ -0,0 +1,57 @@
+# Verilated -*- Makefile -*-
+# DESCRIPTION: Verilator output: Make include file with class lists
+#
+# This file lists generated Verilated files, for including in higher level makefiles.
+# See Vsim.mk for the caller.
+
+### Switches...
+# C11 constructs required?  0/1 (always on now)
+VM_C11 = 1
+# Timing enabled?  0/1
+VM_TIMING = 1
+# Coverage output mode?  0/1 (from --coverage)
+VM_COVERAGE = 0
+# Parallel builds?  0/1 (from --output-split)
+VM_PARALLEL_BUILDS = 0
+# Tracing output mode?  0/1 (from --trace-fst/--trace-saif/--trace-vcd)
+VM_TRACE = 1
+# Tracing output mode in FST format?  0/1 (from --trace-fst)
+VM_TRACE_FST = 0
+# Tracing output mode in SAIF format?  0/1 (from --trace-saif)
+VM_TRACE_SAIF = 0
+# Tracing output mode in VCD format?  0/1 (from --trace-vcd)
+VM_TRACE_VCD = 1
+
+### Object file lists...
+# Generated module classes, fast-path, compile with highest optimization
+VM_CLASSES_FAST += \
+  Vsim \
+  Vsim___024root__0 \
+  Vsim__main \
+
+# Generated module classes, non-fast-path, compile with low/medium optimization
+VM_CLASSES_SLOW += \
+  Vsim___024root__Slow \
+  Vsim___024root__0__Slow \
+
+# Generated support classes, fast-path, compile with highest optimization
+VM_SUPPORT_FAST += \
+  Vsim__Trace__0 \
+
+# Generated support classes, non-fast-path, compile with low/medium optimization
+VM_SUPPORT_SLOW += \
+  Vsim__Syms__Slow \
+  Vsim__Trace__0__Slow \
+  Vsim__TraceDecls__0__Slow \
+
+# Global classes, need linked once per executable, fast-path, compile with highest optimization
+VM_GLOBAL_FAST += \
+  verilated \
+  verilated_vcd_c \
+  verilated_timing \
+  verilated_threads \
+
+# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
+VM_GLOBAL_SLOW += \
+
+# Verilated -*- Makefile -*-

obj_dir/verilated.d

@@ -0,0 +1,12 @@
+verilated.o: /opt/oss-cad-suite/share/verilator/include/verilated.cpp \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_imp.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_syms.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_sym_props.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_threads.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_trace.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos_c.h

obj_dir/verilated.o

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c15e0086becf59dedb31cd5b4e20cfab3c618ecba86e0aeda2d5e8c2bf9c6177
+size 254520

obj_dir/verilated_threads.d

@@ -0,0 +1,8 @@
+verilated_threads.o: \
+ /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_threads.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h

obj_dir/verilated_timing.d

@@ -0,0 +1,8 @@
+verilated_timing.o: \
+ /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp \
+ /opt/oss-cad-suite/share/verilator/include/verilated_timing.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h

obj_dir/verilated_vcd_c.d

@@ -0,0 +1,12 @@
+verilated_vcd_c.o: \
+ /opt/oss-cad-suite/share/verilator/include/verilated_vcd_c.cpp \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_vcd_c.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_trace.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_trace_imp.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_intrinsics.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_threads.h

obj_dir/verilated_vcd_c.o

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:2669196c2cea7409e4fab856394490d9fab4a106e07737af067725680845979f
+size 132968

openenv.yaml

@@ -0,0 +1,7 @@
+spec_version: 1
+name: chipforge
+type: space
+runtime: fastapi
+app: server.app:app
+port: 8000
+

openenv_chipforge.egg-info/PKG-INFO

@@ -0,0 +1,12 @@
+Metadata-Version: 2.4
+Name: openenv-chipforge
+Version: 0.1.0
+Summary: Chipforge environment for OpenEnv
+Requires-Python: >=3.10
+Requires-Dist: openenv-core[core]>=0.2.2
+Requires-Dist: mistralai>=1.0.0
+Requires-Dist: python-dotenv>=1.0.0
+Requires-Dist: websocket-client>=1.9.0
+Provides-Extra: dev
+Requires-Dist: pytest>=8.0.0; extra == "dev"
+Requires-Dist: pytest-cov>=4.0.0; extra == "dev"

openenv_chipforge.egg-info/SOURCES.txt

@@ -0,0 +1,19 @@
+README.md
+__init__.py
+client.py
+inference.py
+models.py
+pyproject.toml
+./__init__.py
+./client.py
+./inference.py
+./models.py
+openenv_chipforge.egg-info/PKG-INFO
+openenv_chipforge.egg-info/SOURCES.txt
+openenv_chipforge.egg-info/dependency_links.txt
+openenv_chipforge.egg-info/entry_points.txt
+openenv_chipforge.egg-info/requires.txt
+openenv_chipforge.egg-info/top_level.txt
+server/__init__.py
+server/app.py
+server/chipforge_environment.py

openenv_chipforge.egg-info/dependency_links.txt

@@ -0,0 +1 @@
+

openenv_chipforge.egg-info/entry_points.txt

@@ -0,0 +1,2 @@
+[console_scripts]
+server = chipforge.server.app:main

openenv_chipforge.egg-info/requires.txt

@@ -0,0 +1,8 @@
+openenv-core[core]>=0.2.2
+mistralai>=1.0.0
+python-dotenv>=1.0.0
+websocket-client>=1.9.0
+
+[dev]
+pytest>=8.0.0
+pytest-cov>=4.0.0

openenv_chipforge.egg-info/top_level.txt

@@ -0,0 +1 @@
+chipforge

pyproject.toml

@@ -0,0 +1,42 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+[build-system]
+requires = ["setuptools>=45", "wheel"]
+build-backend = "setuptools.build_meta"
+
+[project]
+name = "openenv-chipforge"
+version = "0.1.0"
+description = "Chipforge environment for OpenEnv"
+requires-python = ">=3.10"
+dependencies = [
+    # Core OpenEnv runtime (provides FastAPI server + HTTP client types)
+    # install from github
+    # "openenv-core[core] @ git+https://github.com/meta-pytorch/OpenEnv.git",
+    "openenv-core[core]>=0.2.2",
+    # Environment-specific dependencies
+    # (none needed — Verilator + Yosys are installed in the Docker image)
+    "mistralai>=1.0.0",
+    "python-dotenv>=1.0.0",
+    "websocket-client>=1.9.0",
+]
+
+[project.optional-dependencies]
+dev = [
+    "pytest>=8.0.0",
+    "pytest-cov>=4.0.0",
+]
+
+[project.scripts]
+# Server entry point - enables running via: uv run --project . server
+# or: python -m chipforge.server.app
+server = "chipforge.server.app:main"
+
+[tool.setuptools]
+include-package-data = true
+packages = ["chipforge", "chipforge.server"]
+package-dir = { "chipforge" = ".", "chipforge.server" = "server" }

server/__init__.py

@@ -0,0 +1,11 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+"""Chipforge environment server components."""
+
+from .chipforge_environment import ChipforgeEnvironment
+
+__all__ = ["ChipforgeEnvironment"]

server/app.py

@@ -0,0 +1,84 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+"""
+FastAPI application for the Chipforge Environment.
+
+This module creates an HTTP server that exposes the ChipforgeEnvironment
+over HTTP and WebSocket endpoints, compatible with EnvClient.
+
+Endpoints:
+    - POST /reset: Reset the environment
+    - POST /step: Execute an action
+    - GET /state: Get current environment state
+    - GET /schema: Get action/observation schemas
+    - WS /ws: WebSocket endpoint for persistent sessions
+
+Usage:
+    # Development (with auto-reload):
+    uvicorn server.app:app --reload --host 0.0.0.0 --port 8000
+
+    # Production:
+    uvicorn server.app:app --host 0.0.0.0 --port 8000 --workers 4
+
+    # Or run directly:
+    python -m server.app
+"""
+
+try:
+    from openenv.core.env_server.http_server import create_app
+except Exception as e:  # pragma: no cover
+    raise ImportError(
+        "openenv is required for the web interface. Install dependencies with '\n    uv sync\n'"
+    ) from e
+
+try:
+    from ..models import ChipforgeAction, ChipforgeObservation
+    from .chipforge_environment import ChipforgeEnvironment
+except ImportError:
+    from models import ChipforgeAction, ChipforgeObservation
+    from server.chipforge_environment import ChipforgeEnvironment
+
+
+# Create the app with web interface and README integration
+app = create_app(
+    ChipforgeEnvironment,
+    ChipforgeAction,
+    ChipforgeObservation,
+    env_name="chipforge",
+    max_concurrent_envs=1,  # increase this number to allow more concurrent WebSocket sessions
+)
+
+
+def main(host: str = "0.0.0.0", port: int = 8000):
+    """
+    Entry point for direct execution via uv run or python -m.
+
+    This function enables running the server without Docker:
+        uv run --project . server
+        uv run --project . server --port 8001
+        python -m chipforge.server.app
+
+    Args:
+        host: Host address to bind to (default: "0.0.0.0")
+        port: Port number to listen on (default: 8000)
+
+    For production deployments, consider using uvicorn directly with
+    multiple workers:
+        uvicorn chipforge.server.app:app --workers 4
+    """
+    import uvicorn
+
+    uvicorn.run(app, host=host, port=port)
+
+
+if __name__ == "__main__":
+    import argparse
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--port", type=int, default=8000)
+    args = parser.parse_args()
+    main(port=args.port)

server/chipforge_environment.py

@@ -0,0 +1,789 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+# All rights reserved.
+#
+# This source code is licensed under the BSD-style license found in the
+# LICENSE file in the root directory of this source tree.
+
+"""
+ChipForge RTL Debugging Environment — RL-optimized.
+
+Key RL design decisions:
+  1. OBSERVATION is a self-contained Markov state:
+     - RTL code always included (agent never wastes steps viewing)
+     - All tool statuses always present
+     - Action result feedback at every step
+
+  2. REWARD uses potential-based shaping (Andrew Ng's theorem):
+     - per_step_reward = new_potential - old_potential - step_cost
+     - Potential = quality score based on tool statuses (0.0 to 1.0)
+     - Gives dense learning signal without changing optimal policy
+     - Terminal bonus on submit
+
+  3. STATUS is NOT reset on edit:
+     - Prevents reward hacking (edit → artificially drop potential → re-run → gain)
+     - Agent must re-run tools to confirm fix worked
+     - On submit, all stale tools are automatically re-run
+"""
+
+import json
+import os
+import random
+import shutil
+import subprocess
+import tempfile
+from pathlib import Path
+from typing import Any, Dict, List, Optional
+from uuid import uuid4
+
+from openenv.core.env_server.interfaces import Environment
+from openenv.core.env_server.types import State
+
+try:
+    from ..models import ChipforgeAction, ChipforgeObservation
+except ImportError:
+    from models import ChipforgeAction, ChipforgeObservation
+
+
+# ---------------------------------------------------------------------------
+# Constants
+# ---------------------------------------------------------------------------
+
+MAX_STEPS = 20
+LOG_TRUNCATE = 2000  # max chars in observation logs
+TOOL_TIMEOUT = 30  # seconds
+STEP_COST = 0.02  # per-step penalty to encourage efficiency
+
+# Tool paths — absolute for OSS CAD Suite in Docker
+VERILATOR = os.environ.get("VERILATOR_PATH", "/opt/oss-cad-suite/bin/verilator")
+YOSYS = os.environ.get("YOSYS_PATH", "/opt/oss-cad-suite/bin/yosys")
+
+VALID_ACTIONS = {
+    "view_testbench",
+    "view_synthesis_log",
+    "view_lint_log",
+    "view_simulation_log",
+    "run_simulation",
+    "run_synthesis",
+    "run_lint",
+    "edit_line",
+    "append_line",
+    "edit_testbench_line",
+    "append_testbench_line",
+    "submit",
+}
+
+TASKS_DIR = Path(__file__).parent / "tasks"
+
+
+# ---------------------------------------------------------------------------
+# Helpers
+# ---------------------------------------------------------------------------
+
+
+def _discover_tasks() -> List[Path]:
+    """Return sorted list of task directories under TASKS_DIR (recursive)."""
+    if not TASKS_DIR.is_dir():
+        return []
+    return sorted(
+        p.parent
+        for p in TASKS_DIR.rglob("task.json")
+        if p.is_file() and p.parent.is_dir()
+    )
+
+
+def _run_tool(cmd: List[str], cwd: str, timeout: int = TOOL_TIMEOUT) -> Dict[str, Any]:
+    """Run a shell command and return stdout, stderr, returncode."""
+    try:
+        result = subprocess.run(
+            cmd,
+            cwd=cwd,
+            capture_output=True,
+            text=True,
+            timeout=timeout,
+        )
+        return {
+            "stdout": result.stdout,
+            "stderr": result.stderr,
+            "returncode": result.returncode,
+        }
+    except subprocess.TimeoutExpired:
+        return {
+            "stdout": "",
+            "stderr": f"Command timed out after {timeout}s",
+            "returncode": -1,
+        }
+    except FileNotFoundError as e:
+        return {
+            "stdout": "",
+            "stderr": f"Tool not found: {e}",
+            "returncode": -1,
+        }
+
+
+def _extract_error_summary(stderr: str, stdout: str = "") -> str:
+    """Extract a one-line error summary from tool output."""
+    combined = stderr + "\n" + stdout
+    for line in combined.splitlines():
+        line = line.strip()
+        if not line:
+            continue
+        lower = line.lower()
+        if any(kw in lower for kw in ("error", "syntax", "warning", "latch", "fail")):
+            return line[:200]
+    for line in stderr.splitlines():
+        line = line.strip()
+        if line:
+            return line[:200]
+    return ""
+
+
+# ---------------------------------------------------------------------------
+# Environment
+# ---------------------------------------------------------------------------
+
+
+class ChipforgeEnvironment(Environment):
+    """
+    RTL Debugging Environment for RL training.
+
+    Quality potential (φ) breakdown:
+      +0.2  code compiles (no syntax errors)
+      +0.3  simulation output matches expected
+      +0.3  synthesis clean (no warnings/errors)
+      +0.2  lint clean
+
+    Per-step reward = φ(s') - φ(s) - step_cost
+    Terminal bonus on submit = +0.1 if all pass, -0.2 if premature
+    """
+
+    SUPPORTS_CONCURRENT_SESSIONS: bool = False
+
+    def __init__(self) -> None:
+        self._state = State(episode_id=str(uuid4()), step_count=0)
+        self._tasks = _discover_tasks()
+        self._rng = random.Random()
+
+        # Episode state
+        self._rtl_lines: List[str] = []
+        self._testbench_code: str = ""
+        self._task_meta: Dict[str, Any] = {}
+        self._golden_code: str = ""
+        self._expected_output: str = ""
+
+        # Tool statuses & logs
+        self._sim_status: str = "not_run"
+        self._synth_status: str = "not_run"
+        self._lint_status: str = "not_run"
+        self._sim_log: str = ""
+        self._synth_log: str = ""
+        self._lint_log: str = ""
+        self._error_summary: str = ""
+
+        # Track if code has been edited since last tool run
+        self._code_dirty: bool = False
+        self._code_hash: str = ""
+        self._sim_validated_hash: str = ""
+        self._synth_validated_hash: str = ""
+        self._lint_validated_hash: str = ""
+
+        # Working directory
+        self._workdir: Optional[str] = None
+
+        # Episode signals
+        self._done: bool = False
+        self._potential: float = 0.0  # current quality potential
+        self._cumulative_reward: float = 0.0  # sum of per-step rewards
+
+    # -----------------------------------------------------------------------
+    # Potential-based reward
+    # -----------------------------------------------------------------------
+
+    def _compute_potential(self) -> float:
+        """
+        Quality potential φ(s) based on current tool statuses.
+        Range: [0.0, 1.0]. Only counts tools that have been run.
+        """
+        phi = 0.0
+
+        sim_fresh = self._sim_validated_hash == self._code_hash
+        synth_fresh = self._synth_validated_hash == self._code_hash
+        lint_fresh = self._lint_validated_hash == self._code_hash
+
+        # +0.2 if code compiles (sim ran and didn't error) on current code
+        if sim_fresh and self._sim_status in ("pass", "fail"):
+            phi += 0.2
+
+        # +0.3 if simulation passes on current code
+        if sim_fresh and self._sim_status == "pass":
+            phi += 0.3
+
+        # +0.3 if synthesis is clean on current code
+        if synth_fresh and self._synth_status == "pass":
+            phi += 0.3
+
+        # +0.2 if lint is clean on current code
+        if lint_fresh and self._lint_status == "clean":
+            phi += 0.2
+
+        return phi
+
+    def _current_code_hash(self) -> str:
+        return str(hash("\n".join(self._rtl_lines)))
+
+    # -----------------------------------------------------------------------
+    # OpenEnv Interface
+    # -----------------------------------------------------------------------
+
+    def reset(
+        self,
+        seed: Optional[int] = None,
+        episode_id: Optional[str] = None,
+        **kwargs: Any,
+    ) -> ChipforgeObservation:
+        """Load a task and return initial observation with RTL code."""
+
+        # Clean up
+        if self._workdir and os.path.isdir(self._workdir):
+            shutil.rmtree(self._workdir, ignore_errors=True)
+
+        if seed is not None:
+            self._rng.seed(seed)
+
+        if not self._tasks:
+            raise RuntimeError(f"No tasks found in {TASKS_DIR}")
+
+        # Pick task
+        task_name = kwargs.get("task_name")
+        if task_name:
+            task_dir = TASKS_DIR / task_name
+            if not task_dir.is_dir():
+                raise ValueError(f"Task not found: {task_name}")
+        else:
+            task_dir = self._rng.choice(self._tasks)
+
+        # Load files
+        with open(task_dir / "task.json") as f:
+            self._task_meta = json.load(f)
+
+        design_buggy = task_dir / "design_buggy.v"
+        if design_buggy.is_file():
+            with open(design_buggy) as f:
+                self._rtl_lines = f.read().splitlines()
+        else:
+            self._rtl_lines = []
+
+        testbench = task_dir / "testbench.v"
+        if testbench.is_file():
+            with open(testbench) as f:
+                self._testbench_code = f.read()
+        else:
+            self._testbench_code = ""
+
+        design_golden = task_dir / "design_golden.v"
+        if design_golden.is_file():
+            with open(design_golden) as f:
+                self._golden_code = f.read()
+        else:
+            self._golden_code = ""
+
+        self._expected_output = self._task_meta.get("expected_sim_output", "")
+
+        # Reset state
+        eid = episode_id or str(uuid4())
+        self._state = State(episode_id=eid, step_count=0)
+        self._sim_status = "not_run"
+        self._synth_status = "not_run"
+        self._lint_status = "not_run"
+        self._sim_log = ""
+        self._synth_log = ""
+        self._lint_log = ""
+        self._error_summary = ""
+        self._code_dirty = False
+        self._code_hash = self._current_code_hash()
+        self._sim_validated_hash = ""
+        self._synth_validated_hash = ""
+        self._lint_validated_hash = ""
+        self._done = False
+        self._potential = 0.0
+        self._cumulative_reward = 0.0
+
+        # Fresh workdir
+        self._workdir = tempfile.mkdtemp(prefix="chipforge_")
+
+        return self._make_obs(
+            last_action="reset",
+            action_result=f"Loaded task: {self._task_meta.get('description', '')}",
+            step_reward=0.0,
+        )
+
+    def step(  # type: ignore[override]
+        self,
+        action: ChipforgeAction,
+        timeout_s: Optional[float] = None,
+        **kwargs: Any,
+    ) -> ChipforgeObservation:
+        """Execute one action and return observation with per-step reward."""
+
+        if self._done:
+            return self._make_obs(
+                last_action="none",
+                action_result="Episode already finished. Call reset().",
+                step_reward=0.0,
+            )
+
+        self._state.step_count += 1
+        timeout = TOOL_TIMEOUT if timeout_s is None else max(1, int(timeout_s))
+        action_type = action.action_type.strip().lower()
+
+        if action_type not in VALID_ACTIONS:
+            return self._make_obs(
+                last_action=action_type,
+                action_result=f"Unknown action. Valid: {sorted(VALID_ACTIONS)}",
+                step_reward=-STEP_COST,
+            )
+
+        # Snapshot potential BEFORE action
+        old_potential = self._potential
+
+        # Dispatch action
+        obs_extras: Dict[str, Any] = {}
+        action_result = ""
+
+        if action_type == "view_testbench":
+            obs_extras["testbench_code"] = self._testbench_code
+            action_result = f"Testbench loaded ({self._testbench_code.count(chr(10))+1} lines)."
+
+        elif action_type == "view_synthesis_log":
+            obs_extras["log_output"] = self._synth_log[:LOG_TRUNCATE]
+            action_result = f"Viewing synthesis log ({len(self._synth_log)} chars)."
+
+        elif action_type == "view_lint_log":
+            obs_extras["log_output"] = self._lint_log[:LOG_TRUNCATE]
+            action_result = f"Viewing lint log ({len(self._lint_log)} chars)."
+
+        elif action_type == "view_simulation_log":
+            obs_extras["log_output"] = self._sim_log[:LOG_TRUNCATE]
+            action_result = f"Viewing simulation log ({len(self._sim_log)} chars)."
+
+        elif action_type == "run_simulation":
+            self._do_simulation(timeout=timeout)
+            obs_extras["log_output"] = self._sim_log[:LOG_TRUNCATE]
+            action_result = f"Simulation: {self._sim_status}. {self._error_summary}"
+
+        elif action_type == "run_synthesis":
+            self._do_synthesis(timeout=timeout)
+            obs_extras["log_output"] = self._synth_log[:LOG_TRUNCATE]
+            action_result = f"Synthesis: {self._synth_status}. {self._error_summary}"
+
+        elif action_type == "run_lint":
+            self._do_lint(timeout=timeout)
+            obs_extras["log_output"] = self._lint_log[:LOG_TRUNCATE]
+            action_result = f"Lint: {self._lint_status}. {self._error_summary}"
+
+        elif action_type == "edit_line":
+            action_result = self._do_edit(action.line_number, action.new_content)
+
+        elif action_type == "append_line":
+            action_result = self._do_append(action.new_content)
+
+        elif action_type == "edit_testbench_line":
+            action_result = self._do_edit_testbench(action.line_number, action.new_content)
+
+        elif action_type == "append_testbench_line":
+            action_result = self._do_append_testbench(action.new_content)
+
+        elif action_type == "submit":
+            action_result = self._do_submit(timeout=timeout)
+
+        # Compute new potential
+        new_potential = self._compute_potential()
+        self._potential = new_potential
+
+        # Per-step reward = potential delta - step cost + terminal bonus
+        step_reward = (new_potential - old_potential) - STEP_COST
+
+        # Terminal bonus/penalty on submit
+        if action_type == "submit":
+            if new_potential >= 1.0:
+                step_reward += 0.1  # bonus for perfect fix
+            elif new_potential >= 0.5:
+                step_reward += 0.0  # partial fix, no bonus
+            else:
+                step_reward -= 0.2  # premature submit penalty
+
+        self._cumulative_reward += step_reward
+
+        # Check step limit
+        if self._state.step_count >= MAX_STEPS and not self._done:
+            self._done = True
+            action_result += " Step limit reached."
+
+        return self._make_obs(
+            last_action=action_type,
+            action_result=action_result.strip(),
+            step_reward=step_reward,
+            **obs_extras,
+        )
+
+    @property
+    def state(self) -> State:
+        return self._state
+
+    # -----------------------------------------------------------------------
+    # Action Handlers
+    # -----------------------------------------------------------------------
+
+    def _do_simulation(self, timeout: int = TOOL_TIMEOUT) -> None:
+        """Compile + run with Verilator."""
+        if not self._workdir:
+            self._error_summary = "No working directory."
+            return
+
+        if not self._rtl_lines:
+            self._sim_status = "error"
+            self._sim_log = "No RTL design present. Build design first."
+            self._error_summary = "No RTL design present. Add lines with append_line."
+            self._sim_validated_hash = self._code_hash
+            return
+
+        if not self._testbench_code.strip():
+            self._sim_status = "error"
+            self._sim_log = "No testbench present. Build testbench first."
+            self._error_summary = (
+                "No testbench present. Add lines with append_testbench_line."
+            )
+            self._sim_validated_hash = self._code_hash
+            return
+
+        # Write current files
+        design_path = os.path.join(self._workdir, "design.v")
+        tb_path = os.path.join(self._workdir, "testbench.v")
+        with open(design_path, "w") as f:
+            f.write("\n".join(self._rtl_lines) + "\n")
+        with open(tb_path, "w") as f:
+            f.write(self._testbench_code)
+
+        # Clean previous build
+        obj_dir = os.path.join(self._workdir, "obj_dir")
+        if os.path.isdir(obj_dir):
+            shutil.rmtree(obj_dir, ignore_errors=True)
+
+        # Compile
+        compile_result = _run_tool(
+            [
+                VERILATOR,
+                "--prefix", "Vsim",
+                "--binary",
+                "--build-jobs", "0",
+                "--build",
+                "--quiet-build",
+                "-Wno-fatal",
+                "--timescale", "1ns/1ns",
+                "design.v",
+                "testbench.v",
+            ],
+            cwd=self._workdir,
+            timeout=timeout,
+        )
+
+        if compile_result["returncode"] != 0:
+            self._sim_status = "error"
+            self._sim_log = (
+                "=== COMPILATION FAILED ===\n"
+                + compile_result["stderr"] + "\n"
+                + compile_result["stdout"]
+            )
+            self._error_summary = _extract_error_summary(
+                compile_result["stderr"], compile_result["stdout"]
+            )
+            self._code_dirty = False
+            self._sim_validated_hash = self._code_hash
+            return
+
+        # Run simulation
+        sim_binary = os.path.join(self._workdir, "obj_dir", "Vsim")
+        if not os.path.isfile(sim_binary):
+            self._sim_status = "error"
+            self._sim_log = "Simulation binary not found."
+            self._error_summary = "Simulation binary not found."
+            return
+
+        run_result = _run_tool([sim_binary], cwd=self._workdir, timeout=timeout)
+        self._sim_log = run_result["stdout"] + run_result["stderr"]
+        self._code_dirty = False
+        self._sim_validated_hash = self._code_hash
+
+        # Compare output
+        if self._expected_output:
+            actual = [
+                l.strip() for l in run_result["stdout"].splitlines()
+                if l.strip() and not l.strip().startswith("-")
+            ]
+            expected = [
+                l.strip() for l in self._expected_output.splitlines()
+                if l.strip() and not l.strip().startswith("-")
+            ]
+            if actual == expected:
+                self._sim_status = "pass"
+                self._error_summary = "Simulation passed — output matches expected."
+            else:
+                self._sim_status = "fail"
+                self._error_summary = "Simulation output does not match expected."
+        else:
+            self._sim_status = "pass" if run_result["returncode"] == 0 else "fail"
+            self._error_summary = ""
+
+    def _do_synthesis(self, timeout: int = TOOL_TIMEOUT) -> None:
+        """Run Yosys synthesis."""
+        if not self._workdir:
+            self._error_summary = "No working directory."
+            return
+
+        design_path = os.path.join(self._workdir, "design.v")
+        with open(design_path, "w") as f:
+            f.write("\n".join(self._rtl_lines) + "\n")
+
+        yosys_script = (
+            "read_verilog design.v; "
+            "hierarchy -auto-top; "
+            "proc; opt; memory; opt; fsm; opt; "
+            "write_verilog synth_out.v"
+        )
+
+        result = _run_tool(
+            [YOSYS, "-p", yosys_script],
+            cwd=self._workdir,
+            timeout=timeout,
+        )
+
+        full_log = result["stdout"] + "\n" + result["stderr"]
+        self._synth_log = full_log
+        self._code_dirty = False
+
+        if result["returncode"] != 0:
+            self._synth_status = "error"
+            self._error_summary = _extract_error_summary(
+                result["stderr"], result["stdout"]
+            )
+            self._synth_validated_hash = self._code_hash
+        else:
+            lower_log = full_log.lower()
+            warning_patterns = ["latch inferred", "found and reported", "warning:"]
+            has_warning = any(p in lower_log for p in warning_patterns)
+
+            if has_warning:
+                self._synth_status = "warning"
+                self._error_summary = _extract_error_summary(
+                    result["stderr"], result["stdout"]
+                ) or "Synthesis completed with warnings."
+            else:
+                self._synth_status = "pass"
+                self._error_summary = "Synthesis clean."
+            self._synth_validated_hash = self._code_hash
+
+    def _do_lint(self, timeout: int = TOOL_TIMEOUT) -> None:
+        """Run Verilator lint."""
+        if not self._workdir:
+            self._error_summary = "No working directory."
+            return
+
+        design_path = os.path.join(self._workdir, "design.v")
+        with open(design_path, "w") as f:
+            f.write("\n".join(self._rtl_lines) + "\n")
+
+        result = _run_tool(
+            [VERILATOR, "--lint-only", "design.v"],
+            cwd=self._workdir,
+            timeout=timeout,
+        )
+
+        lint_output = result["stderr"] + "\n" + result["stdout"]
+        self._lint_log = lint_output
+        self._code_dirty = False
+
+        if result["returncode"] != 0:
+            lower = lint_output.lower()
+            self._lint_status = "error" if "error" in lower else "warning"
+            self._error_summary = _extract_error_summary(
+                result["stderr"], result["stdout"]
+            )
+            self._lint_validated_hash = self._code_hash
+        else:
+            if "warning" in lint_output.lower():
+                self._lint_status = "warning"
+                self._error_summary = _extract_error_summary(
+                    result["stderr"], result["stdout"]
+                )
+            else:
+                self._lint_status = "clean"
+                self._error_summary = "Lint clean."
+            self._lint_validated_hash = self._code_hash
+
+    def _do_edit(self, line_number: Optional[int], new_content: Optional[str]) -> str:
+        """Edit a single line. Returns action_result string."""
+        if line_number is None or new_content is None:
+            self._error_summary = "edit_line requires line_number and new_content."
+            return self._error_summary
+
+        if line_number < 1 or line_number > len(self._rtl_lines):
+            self._error_summary = (
+                f"Invalid line_number {line_number}. "
+                f"Valid range: 1–{len(self._rtl_lines)}."
+            )
+            return self._error_summary
+
+        old_line = self._rtl_lines[line_number - 1]
+        self._rtl_lines[line_number - 1] = new_content
+        self._code_dirty = True
+        self._code_hash = self._current_code_hash()
+
+        result = (
+            f"Line {line_number} updated. "
+            f"Old: '{old_line.strip()}' → New: '{new_content.strip()}'"
+        )
+        self._error_summary = result
+
+        # NOTE: We do NOT reset tool statuses here.
+        # This is intentional for RL — the potential stays the same
+        # after edit, so reward delta = -step_cost. The agent must
+        # re-run tools to measure the impact of the edit.
+        return result
+
+    def _do_append(self, new_content: Optional[str]) -> str:
+        """Append a single RTL line."""
+        if new_content is None:
+            self._error_summary = "append_line requires new_content."
+            return self._error_summary
+
+        self._rtl_lines.append(new_content)
+        self._code_dirty = True
+        self._code_hash = self._current_code_hash()
+        result = f"RTL line appended at {len(self._rtl_lines)}."
+        self._error_summary = result
+        return result
+
+    def _do_edit_testbench(self, line_number: Optional[int], new_content: Optional[str]) -> str:
+        """Edit a single line in testbench.v."""
+        if line_number is None or new_content is None:
+            self._error_summary = (
+                "edit_testbench_line requires line_number and new_content."
+            )
+            return self._error_summary
+
+        tb_lines = self._testbench_code.splitlines()
+        if line_number < 1 or line_number > len(tb_lines):
+            self._error_summary = (
+                f"Invalid testbench line_number {line_number}. "
+                f"Valid range: 1–{len(tb_lines)}."
+            )
+            return self._error_summary
+
+        old_line = tb_lines[line_number - 1]
+        tb_lines[line_number - 1] = new_content
+        self._testbench_code = "\n".join(tb_lines) + "\n"
+        self._code_dirty = True
+        self._code_hash = self._current_code_hash()
+
+        result = (
+            f"Testbench line {line_number} updated. "
+            f"Old: '{old_line.strip()}' → New: '{new_content.strip()}'"
+        )
+        self._error_summary = result
+        return result
+
+    def _do_append_testbench(self, new_content: Optional[str]) -> str:
+        """Append one line to testbench.v."""
+        if new_content is None:
+            self._error_summary = "append_testbench_line requires new_content."
+            return self._error_summary
+
+        tb_lines = self._testbench_code.splitlines()
+        tb_lines.append(new_content)
+        self._testbench_code = "\n".join(tb_lines) + "\n"
+        self._code_dirty = True
+        self._code_hash = self._current_code_hash()
+        result = f"Testbench line appended at {len(tb_lines)}."
+        self._error_summary = result
+        return result
+
+    def _do_submit(self, timeout: int = TOOL_TIMEOUT) -> str:
+        """Submit solution. Re-runs any stale tools, then marks done."""
+        self._done = True
+
+        # Force re-run all tools on the current (possibly edited) code
+        self._do_simulation(timeout=timeout)
+        self._do_synthesis(timeout=timeout)
+        self._do_lint(timeout=timeout)
+
+        return (
+            f"Submitted. sim={self._sim_status}, "
+            f"synth={self._synth_status}, lint={self._lint_status}."
+        )
+
+    # -----------------------------------------------------------------------
+    # Observation builder
+    # -----------------------------------------------------------------------
+
+    def _numbered_rtl(self) -> str:
+        """Return RTL code with line numbers."""
+        if not self._rtl_lines:
+            return "  1: // RTL is currently empty. Use append_line to create it."
+        return "\n".join(f"{i:3d}: {line}" for i, line in enumerate(self._rtl_lines, 1))
+
+    def _make_obs(
+        self,
+        last_action: str,
+        action_result: str,
+        step_reward: float,
+        **extra: Any,
+    ) -> ChipforgeObservation:
+        """Build a self-contained observation."""
+        return ChipforgeObservation(
+            # Always included — the Markov state
+            rtl_code=self._numbered_rtl(),
+            sim_status=self._sim_status,
+            synth_status=self._synth_status,
+            lint_status=self._lint_status,
+            error_summary=self._error_summary,
+            task_description=self._task_meta.get("description", ""),
+
+            # Action feedback
+            last_action=last_action,
+            action_result=action_result,
+
+            # Conditionally populated
+            testbench_code=extra.get("testbench_code", ""),
+            log_output=extra.get("log_output", ""),
+
+            # RL signals
+            step_count=self._state.step_count,
+            max_steps=MAX_STEPS,
+            reward=step_reward,
+            cumulative_reward=self._cumulative_reward,
+            done=self._done,
+            metadata={
+                "task_mode": self._task_meta.get("task_type", "debug_rtl"),
+                "missing_files": {
+                    "design_buggy.v": not bool(self._rtl_lines),
+                    "testbench.v": not bool(self._testbench_code.strip()),
+                    "design_golden.v": not bool(self._golden_code.strip()),
+                },
+                "code_dirty": self._code_dirty,
+                "tool_freshness": {
+                    "simulation": self._sim_validated_hash == self._code_hash,
+                    "synthesis": self._synth_validated_hash == self._code_hash,
+                    "lint": self._lint_validated_hash == self._code_hash,
+                },
+                "logs_available": {
+                    "simulation": bool(self._sim_log),
+                    "synthesis": bool(self._synth_log),
+                    "lint": bool(self._lint_log),
+                },
+            },
+        )
+
+    def close(self) -> None:
+        """Clean up."""
+        if self._workdir and os.path.isdir(self._workdir):
+            shutil.rmtree(self._workdir, ignore_errors=True)
+            self._workdir = None

server/tasks/easy/01_inverter_semicolon/design_buggy.v

@@ -0,0 +1,30 @@
+module inverter (
+    input a,
+    output y
+);
+
+wire stage0;
+wire stage1;
+wire stage2;
+wire stage3;
+wire stage4;
+wire stage5;
+wire stage6;
+wire stage7;
+wire stage8;
+wire stage9;
+
+assign stage0 = a;
+assign stage1 = stage0;
+assign stage2 = stage1;
+assign stage3 = stage2;
+assign stage4 = stage3;
+assign stage5 = stage4;
+assign stage6 = stage5;
+assign stage7 = stage6;
+assign stage8 = stage7;
+assign stage9 = stage8;
+
+assign y = ~stage9
+
+endmodule

server/tasks/easy/01_inverter_semicolon/design_golden.v

@@ -0,0 +1,30 @@
+module inverter (
+    input a,
+    output y
+);
+
+wire stage0;
+wire stage1;
+wire stage2;
+wire stage3;
+wire stage4;
+wire stage5;
+wire stage6;
+wire stage7;
+wire stage8;
+wire stage9;
+
+assign stage0 = a;
+assign stage1 = stage0;
+assign stage2 = stage1;
+assign stage3 = stage2;
+assign stage4 = stage3;
+assign stage5 = stage4;
+assign stage6 = stage5;
+assign stage7 = stage6;
+assign stage8 = stage7;
+assign stage9 = stage8;
+
+assign y = ~stage9;
+
+endmodule