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12ac0fd 3951517 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 | `timescale 1ns/1ps
module axi_fifo #(
parameter DATA_W = 8
) (
input wire clk,
input wire rst,
input wire s_valid,
output wire s_ready,
input wire [DATA_W-1:0] s_data,
output wire m_valid,
input wire m_ready,
output wire [DATA_W-1:0] m_data,
output wire full,
output wire empty
);
localparam DEPTH = 4;
reg [DATA_W-1:0] mem [0:DEPTH-1];
reg [1:0] head, tail;
reg [2:0] count; // 0..4
assign full = (count == DEPTH);
assign empty = (count == 0);
assign s_ready = !full;
assign m_valid = !empty;
assign m_data = mem[head];
wire enq = s_valid && s_ready;
wire deq = m_valid && m_ready;
always @(posedge clk) begin
if (rst) begin
head <= 0;
tail <= 0;
count <= 0;
end else begin
if (enq) begin
mem[tail] <= s_data;
tail <= tail + 1;
end
if (deq) begin
head <= head + 1;
end
case ({enq, deq})
2'b10: count <= count + 1;
2'b01: count <= count - 1;
default: count <= count;
endcase
end
end
endmodule
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