Update app.py

app.py

@@ -227,14 +227,14 @@ with gr.Blocks(css=custom_css) as demo:
     gr.Markdown("<h1 style='font-size:2.5em; color:#007dc3; margin-bottom:0;'>SR100 Model Compiler</h1>", elem_id="main_title")
     gr.Markdown("<h3 style='margin-top:0; color:#000;'>Bring a TFlite INT8 model and compile it for Synaptics Astra SR100. Learn more at <a href='https://developer.synaptics.com/docs/sr/sr100/quick-start?utm_source=hf' target='_blank' style='color:#007dc3; text-decoration:underline;'>Synaptics AI Developer Zone</a></h3>", elem_id="subtitle")
     gr.Markdown("""
-        SR100 includes the following on-chip SRAM memories:
-        - 1536 kB of Virtual Memory SRAM (VMEM) for high-speed operations.  
-        - 1536 kB of Low Power SRAM (LPMEM) for images, audio, and other less-performance-critical data.  
-        
-        The amount of memory allocated to the model is customizable. Any memory not allocated to the model is usable by the application.  
-        
-        For the best performance, ensure that the Arena cache size is smaller than the available VMEM to ensure it fits and runs optimally.
-        """, elem_id="memory_note"
+    <p style='margin-top:0; color:#000; font-style:italic;'>
+    SR100 includes the following on-chip SRAM memories:<br>
+    - 1536 kB of Virtual Memory SRAM (VMEM) for high-speed operations.<br>
+    - 1536 kB of Low Power SRAM (LPMEM) for images, audio, and other less-performance-critical data.<br><br>
+    The amount of memory allocated to the model is customizable. Any memory not allocated to the model is usable by the application.<br><br>
+    For the best performance, ensure that the Arena cache size is smaller than the available VMEM to ensure it fits and runs optimally.
+    </p>
+    """, elem_id="memory_note"
     )
 
     with gr.Row():