| cluster_info = { |
|
|
| 0:{ |
| "name":"Clock Domain Crossing Issues", |
| "description":"Failures related to clock synchronization, CDC bridges and timing violations", |
| "subsystem":"CLOCK_MANAGER" |
| }, |
|
|
| 1:{ |
| "name":"Memory Controller Operations", |
| "description":"General memory controller operations, refresh cycles and scheduling", |
| "subsystem":"MEM_CTRL" |
| }, |
|
|
| 2:{ |
| "name":"AXI Protocol Errors", |
| "description":"AXI transaction failures including burst violations and timeouts", |
| "subsystem":"AXI_CTRL" |
| }, |
|
|
| 3:{ |
| "name":"DMA Engine Failures", |
| "description":"DMA transfer problems and arbitration issues", |
| "subsystem":"DMA_ENGINE" |
| }, |
|
|
| 4:{ |
| "name":"Power Management Events", |
| "description":"Voltage rail monitoring and regulator stability events", |
| "subsystem":"POWER_CTRL" |
| }, |
|
|
| 5:{ |
| "name":"FIFO Buffer Errors", |
| "description":"FIFO overflow, underflow and parity failures", |
| "subsystem":"FIFO_BUF" |
| }, |
|
|
| 6:{ |
| "name":"PCIe Link Events", |
| "description":"PCIe link training and protocol layer issues", |
| "subsystem":"PCIE_CTRL" |
| }, |
|
|
| 7:{ |
| "name":"Voltage Sensor Issues", |
| "description":"Voltage sensor calibration or measurement failures", |
| "subsystem":"POWER_CTRL" |
| }, |
|
|
| 8:{ |
| "name":"DDR Signal Integrity Problems", |
| "description":"DDR chip select or signal glitch issues", |
| "subsystem":"DDR_CTRL" |
| }, |
|
|
| 9:{ |
| "name":"DVFS Management", |
| "description":"Dynamic voltage frequency scaling state transitions", |
| "subsystem":"POWER_CTRL" |
| } |
| } |