severity,module,message,text,cluster
ERROR,CLOCK_MANAGER,Clock domain crossing FIFO underflow,CLOCK_MANAGER Clock domain crossing FIFO underflow,0
WARNING,MEM_CTRL,Memory refresh cycle completion delayed,MEM_CTRL Memory refresh cycle completion delayed,1
INFO,INTERRUPT_CTRL,Interrupt queue empty,INTERRUPT_CTRL Interrupt queue empty,1
INFO,CACHE_CTRL,Cache controller entered low power state.,CACHE_CTRL Cache controller entered low power state.,-1
WARNING,MEM_CTRL,Bank conflicts increasing,MEM_CTRL Bank conflicts increasing,1
WARNING,AXI_CTRL,AXI write response delay from slave 'S3' exceeding threshold,AXI_CTRL AXI write response delay from slave 'S3' exceeding threshold,2
INFO,DDR_CTRL,DDR controller configured for optimal timing,DDR_CTRL DDR controller configured for optimal timing,1
ERROR,AXI_CTRL,AXI write data (WDATA) transaction ID mismatch.,AXI_CTRL AXI write data (WDATA) transaction ID mismatch.,2
INFO,POWER_CTRL,Power rail monitoring active,POWER_CTRL Power rail monitoring active,4
INFO,CACHE_CTRL,Cache line writeback completed for address 0xABCDEF00.,CACHE_CTRL Cache line writeback completed for address 0xABCDEF00.,1
WARNING,DMA_ENGINE,DMA transfer rate below expected performance on channel 0x4,DMA_ENGINE DMA transfer rate below expected performance on channel 0x4,3
ERROR,CLOCK_MANAGER,"Clock source switchover failed, defaulting to slow clock","CLOCK_MANAGER Clock source switchover failed, defaulting to slow clock",0
INFO,AXI_CTRL,Master arbitration request acknowledged,AXI_CTRL Master arbitration request acknowledged,2
CRITICAL,MEM_CTRL,Memory address bus corruption detected,MEM_CTRL Memory address bus corruption detected,1
INFO,POWER_CTRL,Thermal sensor checked OK,POWER_CTRL Thermal sensor checked OK,4
INFO,FIFO_BUF,FIFO 'rx_data' empty state confirmed,FIFO_BUF FIFO 'rx_data' empty state confirmed,-1
WARNING,CLOCK_MANAGER,Clock monitoring unit detected an out-of-spec frequency,CLOCK_MANAGER Clock monitoring unit detected an out-of-spec frequency,0
CRITICAL,FIFO_BUF,"FIFO internal memory parity error detected, data integrity compromised.","FIFO_BUF FIFO internal memory parity error detected, data integrity compromised.",5
ERROR,PCIE_CTRL,PCIe Root Complex failed to enumerate device 0x1000,PCIE_CTRL PCIe Root Complex failed to enumerate device 0x1000,6
INFO,INTERRUPT_CTRL,Interrupt mask register updated for critical IRQs,INTERRUPT_CTRL Interrupt mask register updated for critical IRQs,1
INFO,CACHE_CTRL,Cache line 0x12345678 successfully evicted.,CACHE_CTRL Cache line 0x12345678 successfully evicted.,1
ERROR,INTERRUPT_CTRL,Priority level misconfiguration detected,INTERRUPT_CTRL Priority level misconfiguration detected,1
CRITICAL,DDR_CTRL,DDR controller state machine entered invalid state,DDR_CTRL DDR controller state machine entered invalid state,1
ERROR,AXI_CTRL,AXI read data channel reported parity error,AXI_CTRL AXI read data channel reported parity error,2
ERROR,DDR_CTRL,DDR memory access to protected region 0x00FF_0000 denied.,DDR_CTRL DDR memory access to protected region 0x00FF_0000 denied.,-1
INFO,PCIE_CTRL,PCIe flow control credits updated,PCIE_CTRL PCIe flow control credits updated,6
CRITICAL,POWER_CTRL,On-chip regulator failed to stabilize,POWER_CTRL On-chip regulator failed to stabilize,4
ERROR,CLOCK_MANAGER,CLOCK_MANAGER encountered a hardware exception: clock domain crossing failure (asynchronous bridge synchronization failure).,CLOCK_MANAGER CLOCK_MANAGER encountered a hardware exception: clock domain crossing failure (asynchronous bridge synchronization failure).,0
CRITICAL,AXI_CTRL,"CRITICAL: AXI interconnect deadlock detected on master CPU, system halt.","AXI_CTRL CRITICAL: AXI interconnect deadlock detected on master CPU, system halt.",2
ERROR,PCIE_CTRL,Received TLP with poisoned bit set,PCIE_CTRL Received TLP with poisoned bit set,6
WARNING,DDR_CTRL,DDR read data eye margin nearing minimum,DDR_CTRL DDR read data eye margin nearing minimum,1
INFO,DDR_CTRL,Refresh cycle initiated by controller.,DDR_CTRL Refresh cycle initiated by controller.,1
INFO,DDR_CTRL,DDR controller entered low-power idle state,DDR_CTRL DDR controller entered low-power idle state,1
ERROR,AXI_CTRL,AXI write data (WDATA) asserted without WVALID,AXI_CTRL AXI write data (WDATA) asserted without WVALID,2
ERROR,DMA_ENGINE,"DMA channel arbitration failure, requests stalled indefinitely. (arbitration conflict)","DMA_ENGINE DMA channel arbitration failure, requests stalled indefinitely. (arbitration conflict)",3
ERROR,FIFO_BUF,Dual-clock FIFO metastable event detected,FIFO_BUF Dual-clock FIFO metastable event detected,5
ERROR,CACHE_CTRL,Cache line eviction policy misconfiguration detected,CACHE_CTRL Cache line eviction policy misconfiguration detected,1
WARNING,FIFO_BUF,FIFO_LOG buffer 80% full,FIFO_BUF FIFO_LOG buffer 80% full,5
INFO,MEM_CTRL,Memory read access granted to CPU core 0,MEM_CTRL Memory read access granted to CPU core 0,1
ERROR,MEM_CTRL,Memory write enable timing violation.,MEM_CTRL Memory write enable timing violation.,1
CRITICAL,MEM_CTRL,Unrecoverable data corruption in critical memory region,MEM_CTRL Unrecoverable data corruption in critical memory region,1
INFO,AXI_CTRL,AXI read data channel ready for new transaction.,AXI_CTRL AXI read data channel ready for new transaction.,2
INFO,DDR_CTRL,DDR auto-refresh enabled,DDR_CTRL DDR auto-refresh enabled,1
INFO,MEM_CTRL,Memory bank 1 refreshed successfully,MEM_CTRL Memory bank 1 refreshed successfully,1
CRITICAL,MEM_CTRL,Memory controller detected fatal bus error on data access.,MEM_CTRL Memory controller detected fatal bus error on data access.,1
ERROR,DDR_CTRL,Memory controller clock domain crossing failure,DDR_CTRL Memory controller clock domain crossing failure,0
WARNING,AXI_CTRL,AXI write response channel with unexpected error code,AXI_CTRL AXI write response channel with unexpected error code,2
CRITICAL,FIFO_BUF,Unrecoverable FIFO state,FIFO_BUF Unrecoverable FIFO state,5
ERROR,PCIE_CTRL,"PCIe link training failure detected, physical layer issue.","PCIE_CTRL PCIe link training failure detected, physical layer issue.",6
ERROR,INTERRUPT_CTRL,Interrupt arbitration priority conflict,INTERRUPT_CTRL Interrupt arbitration priority conflict,1
WARNING,CACHE_CTRL,Data cache write-back queue depth high,CACHE_CTRL Data cache write-back queue depth high,1
ERROR,DMA_ENGINE,DMA engine internal state machine error,DMA_ENGINE DMA engine internal state machine error,3
WARNING,CLOCK_MANAGER,Input clock source frequency drift detected,CLOCK_MANAGER Input clock source frequency drift detected,0
INFO,DDR_CTRL,DDR self-refresh entered.,DDR_CTRL DDR self-refresh entered.,1
INFO,MEM_CTRL,Memory protection unit configuration loaded,MEM_CTRL Memory protection unit configuration loaded,1
WARNING,MEM_CTRL,Memory controller arbitration stalls increasing,MEM_CTRL Memory controller arbitration stalls increasing,1
WARNING,POWER_CTRL,Power monitor reporting transient voltage drops,POWER_CTRL Power monitor reporting transient voltage drops,4
ERROR,AXI_CTRL,"AXI_CTRL: bus contention - bus arbitration failure detected. (Master ID: 1, AXI ID: 12)","AXI_CTRL AXI_CTRL: bus contention - bus arbitration failure detected. (Master ID: 1, AXI ID: 12)",2
INFO,FIFO_BUF,FIFO watermark set to 75%,FIFO_BUF FIFO watermark set to 75%,5
ERROR,FIFO_BUF,"FIFO overflow detected, write rejected.","FIFO_BUF FIFO overflow detected, write rejected.",5
ERROR,POWER_CTRL,Unexpected power state transition,POWER_CTRL Unexpected power state transition,4
INFO,PCIE_CTRL,PCIe Link Status Register indicates stable link.,PCIE_CTRL PCIe Link Status Register indicates stable link.,6
WARNING,MEM_CTRL,Memory bank power cycling requested,MEM_CTRL Memory bank power cycling requested,1
ERROR,POWER_CTRL,Voltage regulator overcurrent protection triggered,POWER_CTRL Voltage regulator overcurrent protection triggered,4
INFO,FIFO_BUF,Input FIFO cleared by software,FIFO_BUF Input FIFO cleared by software,5
WARNING,CLOCK_MANAGER,CLOCK_MANAGER internal buffer approaching capacity (86% full).,CLOCK_MANAGER CLOCK_MANAGER internal buffer approaching capacity (86% full).,-1
CRITICAL,CLOCK_MANAGER,Master system clock derived from unstable source,CLOCK_MANAGER Master system clock derived from unstable source,0
WARNING,CACHE_CTRL,L2 cache prefetcher detected patterns with low hit rate.,CACHE_CTRL L2 cache prefetcher detected patterns with low hit rate.,-1
WARNING,CACHE_CTRL,Cache write buffer backlog increasing,CACHE_CTRL Cache write buffer backlog increasing,1
INFO,INTERRUPT_CTRL,Interrupt vector 0x48 acknowledged,INTERRUPT_CTRL Interrupt vector 0x48 acknowledged,1
WARNING,DDR_CTRL,DDR power-down entry delayed by pending commands,DDR_CTRL DDR power-down entry delayed by pending commands,1
ERROR,AXI_CTRL,AXI burst length exceeding maximum for type,AXI_CTRL AXI burst length exceeding maximum for type,2
WARNING,MEM_CTRL,Memory refresh interval approaching limit (710 cycles remaining).,MEM_CTRL Memory refresh interval approaching limit (710 cycles remaining).,1
INFO,DMA_ENGINE,DMA channel 0 scatter-gather transfer setup,DMA_ENGINE DMA channel 0 scatter-gather transfer setup,3
WARNING,DMA_ENGINE,DMA address generator invalid sequence,DMA_ENGINE DMA address generator invalid sequence,3
ERROR,AXI_CTRL,AXI data phase error,AXI_CTRL AXI data phase error,2
INFO,FIFO_BUF,"Data written to FIFO, available for read","FIFO_BUF Data written to FIFO, available for read",5
INFO,CACHE_CTRL,Cache flushed,CACHE_CTRL Cache flushed,1
INFO,POWER_CTRL,System power-on self-test completed,POWER_CTRL System power-on self-test completed,4
INFO,POWER_CTRL,Voltage regulator V_CPU responsive to load changes,POWER_CTRL Voltage regulator V_CPU responsive to load changes,-1
INFO,FIFO_BUF,FIFO depth configuration applied,FIFO_BUF FIFO depth configuration applied,5
CRITICAL,PCIE_CTRL,"PCIe link training sequence failed multiple retries, link unusable","PCIE_CTRL PCIe link training sequence failed multiple retries, link unusable",6
WARNING,INTERRUPT_CTRL,Multiple pending interrupts in IRQ controller,INTERRUPT_CTRL Multiple pending interrupts in IRQ controller,1
ERROR,INTERRUPT_CTRL,Interrupt controller FIFO overflow detected,INTERRUPT_CTRL Interrupt controller FIFO overflow detected,1
INFO,MEM_CTRL,Write request acknowledged for address 0xCAFE,MEM_CTRL Write request acknowledged for address 0xCAFE,1
WARNING,FIFO_BUF,FIFO watermark threshold exceeded.,FIFO_BUF FIFO watermark threshold exceeded.,5
WARNING,PCIE_CTRL,PCIe device power state transition initiated,PCIE_CTRL PCIe device power state transition initiated,6
WARNING,PCIE_CTRL,Increased number of NAKs observed on PCIe link,PCIE_CTRL Increased number of NAKs observed on PCIe link,-1
INFO,DMA_ENGINE,New DMA descriptor queued for processing,DMA_ENGINE New DMA descriptor queued for processing,3
WARNING,INTERRUPT_CTRL,Interrupt line 7 glitch detected,INTERRUPT_CTRL Interrupt line 7 glitch detected,1
ERROR,CLOCK_MANAGER,Clock tree fan-out violation detected,CLOCK_MANAGER Clock tree fan-out violation detected,0
ERROR,DMA_ENGINE,DMA internal state machine error,DMA_ENGINE DMA internal state machine error,3
INFO,DDR_CTRL,DDR memory mapped registers accessed,DDR_CTRL DDR memory mapped registers accessed,1
WARNING,DDR_CTRL,Memory temperature nearing critical,DDR_CTRL Memory temperature nearing critical,1
CRITICAL,MEM_CTRL,Memory address mapping invalid,MEM_CTRL Memory address mapping invalid,1
WARNING,FIFO_BUF,FIFO write after read hazard detected,FIFO_BUF FIFO write after read hazard detected,5
WARNING,INTERRUPT_CTRL,"Unmasked interrupt detected from disabled device, check configuration.","INTERRUPT_CTRL Unmasked interrupt detected from disabled device, check configuration.",-1
WARNING,PCIE_CTRL,"PCIe CRC errors detected on link, retransmissions occurring","PCIE_CTRL PCIe CRC errors detected on link, retransmissions occurring",6
ERROR,DDR_CTRL,DDR read data bus floating during active cycle,DDR_CTRL DDR read data bus floating during active cycle,1
ERROR,FIFO_BUF,FIFO 'event_queue' experienced an undetected wrap-around,FIFO_BUF FIFO 'event_queue' experienced an undetected wrap-around,-1
WARNING,POWER_CTRL,Auxiliary rail voltage fluctuating,POWER_CTRL Auxiliary rail voltage fluctuating,4
INFO,AXI_CTRL,AXI burst write operation completed,AXI_CTRL AXI burst write operation completed,2
ERROR,CACHE_CTRL,"Cache write buffer overflow, data loss occurred","CACHE_CTRL Cache write buffer overflow, data loss occurred",1
ERROR,PCIE_CTRL,PCIe inbound memory access protection violation,PCIE_CTRL PCIe inbound memory access protection violation,6
WARNING,PCIE_CTRL,"PCIe link utilization high, potential bandwidth bottleneck","PCIE_CTRL PCIe link utilization high, potential bandwidth bottleneck",6
INFO,DDR_CTRL,DDR write latency optimized,DDR_CTRL DDR write latency optimized,1
INFO,INTERRUPT_CTRL,Interrupt mask updated for CPU 0,INTERRUPT_CTRL Interrupt mask updated for CPU 0,1
CRITICAL,INTERRUPT_CTRL,Global interrupt disable stuck enabled,INTERRUPT_CTRL Global interrupt disable stuck enabled,1
ERROR,DMA_ENGINE,DMA bus master arbitration conflict,DMA_ENGINE DMA bus master arbitration conflict,3
INFO,MEM_CTRL,Memory initialization sequence finished,MEM_CTRL Memory initialization sequence finished,1
ERROR,CLOCK_MANAGER,Clock domain crossing logic detected a data loss event,CLOCK_MANAGER Clock domain crossing logic detected a data loss event,0
INFO,POWER_CTRL,"Power cycle detected, rebooting system.","POWER_CTRL Power cycle detected, rebooting system.",-1
ERROR,INTERRUPT_CTRL,Unregistered interrupt source,INTERRUPT_CTRL Unregistered interrupt source,1
WARNING,MEM_CTRL,ECC correctable error detected,MEM_CTRL ECC correctable error detected,1
WARNING,CACHE_CTRL,Snoop latency detected above nominal range,CACHE_CTRL Snoop latency detected above nominal range,1
INFO,POWER_CTRL,Power domain isolation enabled for peripheral block,POWER_CTRL Power domain isolation enabled for peripheral block,4
WARNING,DMA_ENGINE,DMA transfer efficiency below expectation,DMA_ENGINE DMA transfer efficiency below expectation,3
WARNING,AXI_CTRL,AXI slave responded with RETRY,AXI_CTRL AXI slave responded with RETRY,2
CRITICAL,MEM_CTRL,Memory address map corruption detected,MEM_CTRL Memory address map corruption detected,1
WARNING,POWER_CTRL,Power consumption exceeding expected idle levels,POWER_CTRL Power consumption exceeding expected idle levels,4
WARNING,INTERRUPT_CTRL,Interrupt dispatcher latency exceeding limit,INTERRUPT_CTRL Interrupt dispatcher latency exceeding limit,1
CRITICAL,POWER_CTRL,Critical voltage supply failure on analog rail,POWER_CTRL Critical voltage supply failure on analog rail,4
CRITICAL,MEM_CTRL,Multi-bit ECC correction limit reached on bank 2,MEM_CTRL Multi-bit ECC correction limit reached on bank 2,1
ERROR,PCIE_CTRL,PCIe hot-plug event detected with invalid slot status.,PCIE_CTRL PCIe hot-plug event detected with invalid slot status.,6
INFO,POWER_CTRL,Low-power state entry successfully executed,POWER_CTRL Low-power state entry successfully executed,4
ERROR,CLOCK_MANAGER,Secondary clock domain synchronization failure,CLOCK_MANAGER Secondary clock domain synchronization failure,0
CRITICAL,PCIE_CTRL,PCIe physical layer equalization failure,PCIE_CTRL PCIe physical layer equalization failure,6
INFO,AXI_CTRL,AXI burst write to address 0xDEADBEEF,AXI_CTRL AXI burst write to address 0xDEADBEEF,2
INFO,CACHE_CTRL,"Cache initialized successfully (128KB, 4-way).","CACHE_CTRL Cache initialized successfully (128KB, 4-way).",1
INFO,FIFO_BUF,"Data available in FIFO, 5 entries populated","FIFO_BUF Data available in FIFO, 5 entries populated",5
WARNING,CACHE_CTRL,Instruction cache prefetcher disabled due to high miss rate,CACHE_CTRL Instruction cache prefetcher disabled due to high miss rate,1
WARNING,POWER_CTRL,Power domain clock gating inefficiency,POWER_CTRL Power domain clock gating inefficiency,-1
WARNING,CLOCK_MANAGER,Clock tree synthesis report shows high fanout path,CLOCK_MANAGER Clock tree synthesis report shows high fanout path,0
WARNING,POWER_CTRL,Temperature sensor X reporting high values.,POWER_CTRL Temperature sensor X reporting high values.,4
ERROR,POWER_CTRL,Power domain isolation switch failure.,POWER_CTRL Power domain isolation switch failure.,4
INFO,CACHE_CTRL,Cache line written back clean,CACHE_CTRL Cache line written back clean,1
WARNING,POWER_CTRL,Power-on reset (POR) signal instability,POWER_CTRL Power-on reset (POR) signal instability,4
INFO,INTERRUPT_CTRL,Interrupt pending bit for peripheral X cleared,INTERRUPT_CTRL Interrupt pending bit for peripheral X cleared,1
WARNING,CACHE_CTRL,Cache L1 data access latency increasing,CACHE_CTRL Cache L1 data access latency increasing,1
WARNING,FIFO_BUF,Output data buffer experiencing unexpected backpressure.,FIFO_BUF Output data buffer experiencing unexpected backpressure.,5
WARNING,MEM_CTRL,Memory region 0x17A610A7 - 0x17A64A24 under high contention,MEM_CTRL Memory region 0x17A610A7 - 0x17A64A24 under high contention,1
ERROR,AXI_CTRL,AXI write response channel deadlock,AXI_CTRL AXI write response channel deadlock,2
INFO,DMA_ENGINE,Transfer setup complete,DMA_ENGINE Transfer setup complete,3
ERROR,FIFO_BUF,FIFO 'request_queue' read request when empty caused corruption,FIFO_BUF FIFO 'request_queue' read request when empty caused corruption,5
ERROR,AXI_CTRL,AXI transaction with AWCACHE set to non-cacheable yet observed cache line fill.,AXI_CTRL AXI transaction with AWCACHE set to non-cacheable yet observed cache line fill.,-1
ERROR,INTERRUPT_CTRL,Critical interrupt missed due to controller disable,INTERRUPT_CTRL Critical interrupt missed due to controller disable,1
CRITICAL,DDR_CTRL,DDR PHY training sequence failed to converge,DDR_CTRL DDR PHY training sequence failed to converge,1
ERROR,DMA_ENGINE,DMA channel configuration register write error,DMA_ENGINE DMA channel configuration register write error,3
CRITICAL,MEM_CTRL,Memory controller reset sequence failed,MEM_CTRL Memory controller reset sequence failed,1
INFO,CLOCK_MANAGER,Gated clock enable signal verified,CLOCK_MANAGER Gated clock enable signal verified,0
CRITICAL,DMA_ENGINE,DMA hardware assertion failure: FIFO read past empty,DMA_ENGINE DMA hardware assertion failure: FIFO read past empty,-1
ERROR,MEM_CTRL,Memory address alignment fault: access to 0x1001 with 4-byte width,MEM_CTRL Memory address alignment fault: access to 0x1001 with 4-byte width,1
WARNING,POWER_CTRL,Temperature sensor 0 approaching critical limit (90C).,POWER_CTRL Temperature sensor 0 approaching critical limit (90C).,4
INFO,INTERRUPT_CTRL,Interrupt mask updated for timer peripheral,INTERRUPT_CTRL Interrupt mask updated for timer peripheral,1
WARNING,DMA_ENGINE,DMA channel transfer size miscompare,DMA_ENGINE DMA channel transfer size miscompare,3
WARNING,PCIE_CTRL,PCIE_CTRL performance counter for PCIE_CTRL indicating suboptimal behavior.,PCIE_CTRL PCIE_CTRL performance counter for PCIE_CTRL indicating suboptimal behavior.,-1
WARNING,DDR_CTRL,DDR controller busy for extended period,DDR_CTRL DDR controller busy for extended period,1
WARNING,DDR_CTRL,DDR CAS latency mismatch with configured value,DDR_CTRL DDR CAS latency mismatch with configured value,1
ERROR,MEM_CTRL,Memory write protection violation at 0x6e87a2a6.,MEM_CTRL Memory write protection violation at 0x6e87a2a6.,1
CRITICAL,POWER_CTRL,Power rail instability detected on 1.0V core rail,POWER_CTRL Power rail instability detected on 1.0V core rail,4
ERROR,CLOCK_MANAGER,Clock glitch detected on rising edge,CLOCK_MANAGER Clock glitch detected on rising edge,0
ERROR,POWER_CTRL,Power rail 'VCC_RTC' detected out of range,POWER_CTRL Power rail 'VCC_RTC' detected out of range,-1
WARNING,FIFO_BUF,FIFO almost full assertion detected on transmit path,FIFO_BUF FIFO almost full assertion detected on transmit path,-1
ERROR,MEM_CTRL,Memory write data mismatch verified,MEM_CTRL Memory write data mismatch verified,1
WARNING,PCIE_CTRL,PCIe link speed negotiation degraded to Gen1,PCIE_CTRL PCIe link speed negotiation degraded to Gen1,6
INFO,PCIE_CTRL,PCIe link bandwidth negotiated to Gen4 x8,PCIE_CTRL PCIe link bandwidth negotiated to Gen4 x8,6
WARNING,POWER_CTRL,Power supply unit (PSU) temperature approaching limit,POWER_CTRL Power supply unit (PSU) temperature approaching limit,-1
INFO,DMA_ENGINE,DMA engine idle,DMA_ENGINE DMA engine idle,3
CRITICAL,DDR_CTRL,"CRITICAL: DDR training sequence failed, memory unusable (channel 1).","DDR_CTRL CRITICAL: DDR training sequence failed, memory unusable (channel 1).",1
WARNING,PCIE_CTRL,Warning: PCIe link width degraded to x64 temporarily.,PCIE_CTRL Warning: PCIe link width degraded to x64 temporarily.,6
INFO,FIFO_BUF,FIFO_BUF_16 write operation successful,FIFO_BUF FIFO_BUF_16 write operation successful,5
ERROR,DDR_CTRL,DDR memory module 0x01 detected with internal error during scrub.,DDR_CTRL DDR memory module 0x01 detected with internal error during scrub.,1
ERROR,INTERRUPT_CTRL,Unmasked interrupt received during critical section.,INTERRUPT_CTRL Unmasked interrupt received during critical section.,1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller internal bus error, catastrophic failure","INTERRUPT_CTRL Interrupt controller internal bus error, catastrophic failure",1
WARNING,AXI_CTRL,AXI write data FIFO nearing full,AXI_CTRL AXI write data FIFO nearing full,2
INFO,DDR_CTRL,DDR refresh cycle performed,DDR_CTRL DDR refresh cycle performed,1
CRITICAL,MEM_CTRL,Memory controller internal state mismatch during reset,MEM_CTRL Memory controller internal state mismatch during reset,1
ERROR,POWER_CTRL,System power sequencing state machine error,POWER_CTRL System power sequencing state machine error,4
WARNING,INTERRUPT_CTRL,Spurious interrupt detected from source 11.,INTERRUPT_CTRL Spurious interrupt detected from source 11.,1
WARNING,CLOCK_MANAGER,Clock jitter margin reduced,CLOCK_MANAGER Clock jitter margin reduced,0
ERROR,PCIE_CTRL,"PCIe packet framing error, corrupted TLP header","PCIE_CTRL PCIe packet framing error, corrupted TLP header",6
INFO,CACHE_CTRL,Cache line writeback completed for 0x1234_5678,CACHE_CTRL Cache line writeback completed for 0x1234_5678,1
WARNING,CACHE_CTRL,Cache dirty line count increasing rapidly,CACHE_CTRL Cache dirty line count increasing rapidly,1
INFO,AXI_CTRL,AXI slave responded with OKAY.,AXI_CTRL AXI slave responded with OKAY.,2
INFO,CACHE_CTRL,Cache hit for address 0xe9345e22.,CACHE_CTRL Cache hit for address 0xe9345e22.,1
CRITICAL,MEM_CTRL,Memory controller detected catastrophic internal error,MEM_CTRL Memory controller detected catastrophic internal error,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout detected for IRQ 5,INTERRUPT_CTRL Interrupt acknowledge timeout detected for IRQ 5,1
ERROR,POWER_CTRL,Voltage level on 'VDD_HDMI' rail significantly below nominal,POWER_CTRL Voltage level on 'VDD_HDMI' rail significantly below nominal,-1
WARNING,CLOCK_MANAGER,Jitter on high-speed clock approaching limit,CLOCK_MANAGER Jitter on high-speed clock approaching limit,0
ERROR,MEM_CTRL,Memory controller page-close command timing violation,MEM_CTRL Memory controller page-close command timing violation,1
WARNING,MEM_CTRL,Memory access latency increasing,MEM_CTRL Memory access latency increasing,1
WARNING,CACHE_CTRL,Cache snoop filter misses rate increasing,CACHE_CTRL Cache snoop filter misses rate increasing,1
ERROR,POWER_CTRL,Voltage regulator current limit reached,POWER_CTRL Voltage regulator current limit reached,4
WARNING,FIFO_BUF,FIFO occupancy at 90% threshold.,FIFO_BUF FIFO occupancy at 90% threshold.,5
WARNING,DMA_ENGINE,DMA channel X priority inversion detected,DMA_ENGINE DMA channel X priority inversion detected,3
WARNING,DMA_ENGINE,DMA control register read error,DMA_ENGINE DMA control register read error,3
INFO,CACHE_CTRL,Cache 'L1I' reloaded from main memory,CACHE_CTRL Cache 'L1I' reloaded from main memory,1
ERROR,FIFO_BUF,FIFO underflow detected during burst read,FIFO_BUF FIFO underflow detected during burst read,5
INFO,DMA_ENGINE,DMA channel 3 configured for non-cached access,DMA_ENGINE DMA channel 3 configured for non-cached access,3
WARNING,CACHE_CTRL,Cache hit rate on L1 instruction cache dropping,CACHE_CTRL Cache hit rate on L1 instruction cache dropping,1
WARNING,FIFO_BUF,FIFO almost-full flag asserted for extended period,FIFO_BUF FIFO almost-full flag asserted for extended period,5
CRITICAL,MEM_CTRL,"Double-bit ECC error detected, data corrupted","MEM_CTRL Double-bit ECC error detected, data corrupted",1
ERROR,DMA_ENGINE,DMA address pointer increment error detected,DMA_ENGINE DMA address pointer increment error detected,3
ERROR,AXI_CTRL,AXI ID tag collision detected by arbiter,AXI_CTRL AXI ID tag collision detected by arbiter,2
ERROR,POWER_CTRL,Power-on reset deassertion timed out,POWER_CTRL Power-on reset deassertion timed out,4
WARNING,CLOCK_MANAGER,Clock mux selection changed due to source degradation,CLOCK_MANAGER Clock mux selection changed due to source degradation,0
WARNING,DDR_CTRL,"DDR write buffer fill level high, approaching threshold","DDR_CTRL DDR write buffer fill level high, approaching threshold",1
CRITICAL,CLOCK_MANAGER,Auxiliary clock source failed to lock,CLOCK_MANAGER Auxiliary clock source failed to lock,0
CRITICAL,MEM_CTRL,Memory controller detected external memory chip failure,MEM_CTRL Memory controller detected external memory chip failure,1
ERROR,AXI_CTRL,AXI write data integrity check failed on response,AXI_CTRL AXI write data integrity check failed on response,2
INFO,MEM_CTRL,Memory BIST (Built-In Self-Test) completed successfully,MEM_CTRL Memory BIST (Built-In Self-Test) completed successfully,1
INFO,CLOCK_MANAGER,Clock tree synthesis report loaded,CLOCK_MANAGER Clock tree synthesis report loaded,0
ERROR,DDR_CTRL,DDR memory initialization sequence failure,DDR_CTRL DDR memory initialization sequence failure,1
INFO,CACHE_CTRL,Cache prefetch initiated for address range.,CACHE_CTRL Cache prefetch initiated for address range.,1
INFO,DMA_ENGINE,DMA transfer completed on channel 9,DMA_ENGINE DMA transfer completed on channel 9,3
INFO,MEM_CTRL,Memory block 0x4000-0x5000 allocated,MEM_CTRL Memory block 0x4000-0x5000 allocated,1
INFO,FIFO_BUF,FIFO_TX_DATA flush operation completed.,FIFO_BUF FIFO_TX_DATA flush operation completed.,5
INFO,DMA_ENGINE,DMA channel 0 configured for scatter-gather operation,DMA_ENGINE DMA channel 0 configured for scatter-gather operation,3
CRITICAL,CLOCK_MANAGER,PLL feedback path broken,CLOCK_MANAGER PLL feedback path broken,0
ERROR,AXI_CTRL,AXI transaction protection settings violated by master 0x03.,AXI_CTRL AXI transaction protection settings violated by master 0x03.,2
CRITICAL,MEM_CTRL,Multi-level ECC error detected in crucial data,MEM_CTRL Multi-level ECC error detected in crucial data,1
WARNING,MEM_CTRL,Memory buffer fill level approaching critical point.,MEM_CTRL Memory buffer fill level approaching critical point.,1
INFO,POWER_CTRL,Voltage monitoring unit online,POWER_CTRL Voltage monitoring unit online,4
INFO,DMA_ENGINE,DMA transfer complete interrupt asserted for channel 1,DMA_ENGINE DMA transfer complete interrupt asserted for channel 1,3
ERROR,CLOCK_MANAGER,Clock signal loss on secondary clock tree,CLOCK_MANAGER Clock signal loss on secondary clock tree,0
ERROR,DDR_CTRL,DDR read data burst length mismatch,DDR_CTRL DDR read data burst length mismatch,1
WARNING,PCIE_CTRL,PCIe link speed negotiation taking longer than expected.,PCIE_CTRL PCIe link speed negotiation taking longer than expected.,6
WARNING,DMA_ENGINE,DMA descriptor queue depth increasing,DMA_ENGINE DMA descriptor queue depth increasing,3
INFO,DMA_ENGINE,DMA transfer to memory completed,DMA_ENGINE DMA transfer to memory completed,3
WARNING,DMA_ENGINE,DMA completion status not updated,DMA_ENGINE DMA completion status not updated,3
CRITICAL,CLOCK_MANAGER,Global clock network integrity compromised,CLOCK_MANAGER Global clock network integrity compromised,0
CRITICAL,MEM_CTRL,Uncorrectable double-bit ECC error in main memory,MEM_CTRL Uncorrectable double-bit ECC error in main memory,1
ERROR,CLOCK_MANAGER,Clock domain crossing failure on control signal,CLOCK_MANAGER Clock domain crossing failure on control signal,0
ERROR,DMA_ENGINE,DMA read data FIFO underflow detected,DMA_ENGINE DMA read data FIFO underflow detected,-1
CRITICAL,INTERRUPT_CTRL,"CPU unable to clear interrupt, fatal condition.","INTERRUPT_CTRL CPU unable to clear interrupt, fatal condition.",1
INFO,CLOCK_MANAGER,Clock domain enabled,CLOCK_MANAGER Clock domain enabled,0
ERROR,POWER_CTRL,Voltage monitor detected undershoot on 1.8V rail,POWER_CTRL Voltage monitor detected undershoot on 1.8V rail,4
ERROR,POWER_CTRL,Power sequencing fault,POWER_CTRL Power sequencing fault,4
WARNING,DDR_CTRL,DDR command queue depth exceeding 70%,DDR_CTRL DDR command queue depth exceeding 70%,1
ERROR,INTERRUPT_CTRL,"Interrupt queue overflow, pending IRQs dropped","INTERRUPT_CTRL Interrupt queue overflow, pending IRQs dropped",1
ERROR,MEM_CTRL,Memory controller address translation fault,MEM_CTRL Memory controller address translation fault,1
ERROR,FIFO_BUF,Read operation on empty FIFO (underflow) detected,FIFO_BUF Read operation on empty FIFO (underflow) detected,5
WARNING,INTERRUPT_CTRL,Interrupt source debounce warning,INTERRUPT_CTRL Interrupt source debounce warning,1
ERROR,AXI_CTRL,Transaction ID mismatch,AXI_CTRL Transaction ID mismatch,2
CRITICAL,FIFO_BUF,FIFO internal state machine entered invalid state (state machine fault),FIFO_BUF FIFO internal state machine entered invalid state (state machine fault),5
WARNING,FIFO_BUF,FIFO output data valid for shorter duration than expected,FIFO_BUF FIFO output data valid for shorter duration than expected,5
ERROR,PCIE_CTRL,PCIe descriptor fetch failed from host memory,PCIE_CTRL PCIe descriptor fetch failed from host memory,-1
INFO,DDR_CTRL,DDR controller entered active state,DDR_CTRL DDR controller entered active state,1
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for source 16.,INTERRUPT_CTRL Interrupt dispatch completed for source 16.,1
INFO,CACHE_CTRL,Cache data invalidation broadcast initiated,CACHE_CTRL Cache data invalidation broadcast initiated,1
ERROR,FIFO_BUF,FIFO 'rx_data' read pointer advanced without valid data,FIFO_BUF FIFO 'rx_data' read pointer advanced without valid data,5
WARNING,DDR_CTRL,DDR_CTRL internal buffer approaching capacity (82% full).,DDR_CTRL DDR_CTRL internal buffer approaching capacity (82% full).,1
ERROR,MEM_CTRL,Memory write protect violation detected,MEM_CTRL Memory write protect violation detected,1
CRITICAL,MEM_CTRL,Double bit ECC corruption detected.,MEM_CTRL Double bit ECC corruption detected.,1
INFO,PCIE_CTRL,PCIe device enumerated with Vender ID 0x1234,PCIE_CTRL PCIe device enumerated with Vender ID 0x1234,6
WARNING,CLOCK_MANAGER,Asynchronous reset propagation delay too high,CLOCK_MANAGER Asynchronous reset propagation delay too high,0
WARNING,POWER_CTRL,Power consumption on domain IO higher than expected.,POWER_CTRL Power consumption on domain IO higher than expected.,4
WARNING,AXI_CTRL,AXI burst length exceeds recommended maximum for slave,AXI_CTRL AXI burst length exceeds recommended maximum for slave,2
ERROR,FIFO_BUF,FIFO read data mismatch due to corruption,FIFO_BUF FIFO read data mismatch due to corruption,5
INFO,AXI_CTRL,AXI write transaction issued to slave ID 0x5,AXI_CTRL AXI write transaction issued to slave ID 0x5,2
ERROR,AXI_CTRL,AXI transaction ID wrapping error,AXI_CTRL AXI transaction ID wrapping error,2
ERROR,PCIE_CTRL,PCIe link retraining failed after reset,PCIE_CTRL PCIe link retraining failed after reset,6
ERROR,PCIE_CTRL,PCIe transaction layer CRC error detected on received TLP,PCIE_CTRL PCIe transaction layer CRC error detected on received TLP,6
CRITICAL,POWER_CTRL,Core voltage rail VDD_CORE experienced catastrophic sag,POWER_CTRL Core voltage rail VDD_CORE experienced catastrophic sag,4
ERROR,MEM_CTRL,Memory address decoding fault for region 0x8000_0000,MEM_CTRL Memory address decoding fault for region 0x8000_0000,1
ERROR,FIFO_BUF,FIFO overflow detected.,FIFO_BUF FIFO overflow detected.,5
ERROR,CLOCK_MANAGER,Clock source selection logic outputting incorrect frequency.,CLOCK_MANAGER Clock source selection logic outputting incorrect frequency.,0
INFO,DDR_CTRL,Memory device self-refresh exited,DDR_CTRL Memory device self-refresh exited,1
INFO,DDR_CTRL,DDR_CTRL resource allocation successful.,DDR_CTRL DDR_CTRL resource allocation successful.,1
INFO,FIFO_BUF,FIFO_BUF_8 capacity check passed,FIFO_BUF FIFO_BUF_8 capacity check passed,5
WARNING,AXI_CTRL,AXI handshake timeout on `AWREADY` signal,AXI_CTRL AXI handshake timeout on `AWREADY` signal,2
INFO,CACHE_CTRL,Cache prefetch operation successful.,CACHE_CTRL Cache prefetch operation successful.,1
WARNING,PCIE_CTRL,PCIe device hot-plug event detected,PCIE_CTRL PCIe device hot-plug event detected,6
ERROR,PCIE_CTRL,PCIe completion with error status,PCIE_CTRL PCIe completion with error status,6
INFO,MEM_CTRL,Memory bank opened,MEM_CTRL Memory bank opened,1
CRITICAL,PCIE_CTRL,PCIe Fatal Error detected by Root Port,PCIE_CTRL PCIe Fatal Error detected by Root Port,6
WARNING,FIFO_BUF,FIFO write pointer close to overflow,FIFO_BUF FIFO write pointer close to overflow,5
CRITICAL,PCIE_CTRL,"PCIe root complex internal state machine fault, link unusable. (state machine fault)","PCIE_CTRL PCIe root complex internal state machine fault, link unusable. (state machine fault)",6
CRITICAL,FIFO_BUF,FIFO internal state machine corrupted,FIFO_BUF FIFO internal state machine corrupted,5
ERROR,CACHE_CTRL,Cache write buffer overflow detected.,CACHE_CTRL Cache write buffer overflow detected.,1
INFO,DMA_ENGINE,DMA transfer complete for channel 4,DMA_ENGINE DMA transfer complete for channel 4,3
CRITICAL,DDR_CTRL,DDR SDRAM controller not responding to commands,DDR_CTRL DDR SDRAM controller not responding to commands,1
ERROR,PCIE_CTRL,PCIe packet framing error detected on ingress.,PCIE_CTRL PCIe packet framing error detected on ingress.,6
INFO,DDR_CTRL,DDR command queue depth reported,DDR_CTRL DDR command queue depth reported,1
CRITICAL,DMA_ENGINE,DMA engine hangs trying to fetch descriptors from invalid address,DMA_ENGINE DMA engine hangs trying to fetch descriptors from invalid address,3
ERROR,POWER_CTRL,Power sequence violation during transition.,POWER_CTRL Power sequence violation during transition.,4
ERROR,CLOCK_MANAGER,Clock 'REF_CLK' frequency deviation exceeds tolerance,CLOCK_MANAGER Clock 'REF_CLK' frequency deviation exceeds tolerance,0
ERROR,PCIE_CTRL,PCIe TLP (Transaction Layer Packet) parsing error,PCIE_CTRL PCIe TLP (Transaction Layer Packet) parsing error,6
INFO,INTERRUPT_CTRL,Pending interrupt served,INTERRUPT_CTRL Pending interrupt served,1
INFO,DMA_ENGINE,DMA channel 1 transfer started,DMA_ENGINE DMA channel 1 transfer started,3
WARNING,PCIE_CTRL,PCIe link data rate fluctuating,PCIE_CTRL PCIe link data rate fluctuating,6
INFO,FIFO_BUF,Data successfully pushed to FIFO,FIFO_BUF Data successfully pushed to FIFO,5
INFO,CACHE_CTRL,Cache flush operation initiated for all ways,CACHE_CTRL Cache flush operation initiated for all ways,1
ERROR,CACHE_CTRL,Cache line replacement policy logic error detected.,CACHE_CTRL Cache line replacement policy logic error detected.,1
INFO,FIFO_BUF,FIFO reset successful,FIFO_BUF FIFO reset successful,5
INFO,PCIE_CTRL,PCIe hot reset successfully applied to endpoint,PCIE_CTRL PCIe hot reset successfully applied to endpoint,6
ERROR,INTERRUPT_CTRL,Critical interrupt lost due to race condition,INTERRUPT_CTRL Critical interrupt lost due to race condition,1
INFO,INTERRUPT_CTRL,Interrupt status register read,INTERRUPT_CTRL Interrupt status register read,1
ERROR,MEM_CTRL,Memory access to reserved address space detected,MEM_CTRL Memory access to reserved address space detected,1
WARNING,AXI_CTRL,AXI master requesting too many exclusive accesses,AXI_CTRL AXI master requesting too many exclusive accesses,2
WARNING,PCIE_CTRL,PCIe link speed negotiation degraded,PCIE_CTRL PCIe link speed negotiation degraded,6
CRITICAL,CLOCK_MANAGER,PLL frequency lock lost after temperature change,CLOCK_MANAGER PLL frequency lock lost after temperature change,0
CRITICAL,POWER_CTRL,System power monitor reports critical event,POWER_CTRL System power monitor reports critical event,4
INFO,INTERRUPT_CTRL,All pending interrupts processed,INTERRUPT_CTRL All pending interrupts processed,1
INFO,DMA_ENGINE,DMA channel 0 enabled for transfer,DMA_ENGINE DMA channel 0 enabled for transfer,3
CRITICAL,DMA_ENGINE,"DMA internal bus error, engine halted","DMA_ENGINE DMA internal bus error, engine halted",3
INFO,POWER_CTRL,Power domain isolation enabled,POWER_CTRL Power domain isolation enabled,4
WARNING,AXI_CTRL,AXI read data channel backlog increasing,AXI_CTRL AXI read data channel backlog increasing,2
CRITICAL,POWER_CTRL,"Over-current protection tripped, system power off","POWER_CTRL Over-current protection tripped, system power off",4
INFO,CLOCK_MANAGER,System clock frequency successfully updated to 1GHz,CLOCK_MANAGER System clock frequency successfully updated to 1GHz,0
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected on channel CH1.,DMA_ENGINE DMA buffer pointer corruption detected on channel CH1.,3
ERROR,MEM_CTRL,Memory controller power management state failure,MEM_CTRL Memory controller power management state failure,1
WARNING,POWER_CTRL,Power domain VDD_DDR transition delay exceeding expected value,POWER_CTRL Power domain VDD_DDR transition delay exceeding expected value,4
WARNING,FIFO_BUF,FIFO almost-full flag toggling frequently,FIFO_BUF FIFO almost-full flag toggling frequently,5
INFO,MEM_CTRL,Page table walk completed for address translation.,MEM_CTRL Page table walk completed for address translation.,-1
INFO,MEM_CTRL,Memory ECC scrubbing completed.,MEM_CTRL Memory ECC scrubbing completed.,1
INFO,CLOCK_MANAGER,Clock source switched to secondary PLL,CLOCK_MANAGER Clock source switched to secondary PLL,0
CRITICAL,PCIE_CTRL,PCIe protocol layer detected a fatal error: undefined TLP type,PCIE_CTRL PCIe protocol layer detected a fatal error: undefined TLP type,6
ERROR,MEM_CTRL,Memory protection violation due to incorrect region access,MEM_CTRL Memory protection violation due to incorrect region access,1
INFO,CACHE_CTRL,Cache eviction policy switched to LRU,CACHE_CTRL Cache eviction policy switched to LRU,1
INFO,MEM_CTRL,Memory read data mismatch detected at 0xDEADBEEF,MEM_CTRL Memory read data mismatch detected at 0xDEADBEEF,1
WARNING,MEM_CTRL,Memory read retry count incremented for address 0xDEADBEEF.,MEM_CTRL Memory read retry count incremented for address 0xDEADBEEF.,1
INFO,POWER_CTRL,Voltage rail VDD_CORE enabled and stable,POWER_CTRL Voltage rail VDD_CORE enabled and stable,4
ERROR,CACHE_CTRL,Cache snoop filter entry corruption,CACHE_CTRL Cache snoop filter entry corruption,1
WARNING,DMA_ENGINE,DMA transfer completion status read failed,DMA_ENGINE DMA transfer completion status read failed,3
WARNING,DDR_CTRL,DDR self-refresh exit timing violation,DDR_CTRL DDR self-refresh exit timing violation,1
ERROR,POWER_CTRL,Power rail sequencing interlock violated,POWER_CTRL Power rail sequencing interlock violated,4
CRITICAL,POWER_CTRL,Power sequencing controller stuck in intermediate state,POWER_CTRL Power sequencing controller stuck in intermediate state,4
WARNING,AXI_CTRL,"AXI wait states inserted, impacting throughput","AXI_CTRL AXI wait states inserted, impacting throughput",2
ERROR,DDR_CTRL,DDR command scheduling deadlock detected,DDR_CTRL DDR command scheduling deadlock detected,1
WARNING,INTERRUPT_CTRL,Interrupt handler priority conflict,INTERRUPT_CTRL Interrupt handler priority conflict,1
WARNING,POWER_CTRL,Power state transition delayed by 100 cycles,POWER_CTRL Power state transition delayed by 100 cycles,4
WARNING,AXI_CTRL,AXI ARREADY signal held low by slave for extended cycles,AXI_CTRL AXI ARREADY signal held low by slave for extended cycles,2
INFO,POWER_CTRL,Configuration parameters loaded for POWER_CTRL.,POWER_CTRL Configuration parameters loaded for POWER_CTRL.,-1
ERROR,DDR_CTRL,DDR precharge command issued too early,DDR_CTRL DDR precharge command issued too early,1
WARNING,INTERRUPT_CTRL,Interrupt masking applied to low priority interrupts,INTERRUPT_CTRL Interrupt masking applied to low priority interrupts,1
CRITICAL,POWER_CTRL,Unrecoverable voltage supply fluctuation,POWER_CTRL Unrecoverable voltage supply fluctuation,4
INFO,CLOCK_MANAGER,Clock domain synchronizer configured,CLOCK_MANAGER Clock domain synchronizer configured,0
CRITICAL,PCIE_CTRL,PCIe fatal hardware error detected on core.,PCIE_CTRL PCIe fatal hardware error detected on core.,6
WARNING,DDR_CTRL,DDR read latency variations exceeding acceptable range,DDR_CTRL DDR read latency variations exceeding acceptable range,1
CRITICAL,DDR_CTRL,DDR PHY training unable to find stable clock eye,DDR_CTRL DDR PHY training unable to find stable clock eye,-1
WARNING,AXI_CTRL,AXI burst type changed unexpectedly,AXI_CTRL AXI burst type changed unexpectedly,2
CRITICAL,POWER_CTRL,System power-on self-test (POST) failed,POWER_CTRL System power-on self-test (POST) failed,4
WARNING,CLOCK_MANAGER,Clock distribution network congestion,CLOCK_MANAGER Clock distribution network congestion,0
CRITICAL,AXI_CTRL,AXI bus master 0x0 deadlock,AXI_CTRL AXI bus master 0x0 deadlock,2
CRITICAL,AXI_CTRL,AXI bus agent 5 failed to respond to AXI reset,AXI_CTRL AXI bus agent 5 failed to respond to AXI reset,2
WARNING,DMA_ENGINE,DMA channel 0 completion timeout predicted,DMA_ENGINE DMA channel 0 completion timeout predicted,3
INFO,MEM_CTRL,Memory access to protected region 0x00000000 denied,MEM_CTRL Memory access to protected region 0x00000000 denied,1
WARNING,POWER_CTRL,Power sequence step 4 delay exceeding specification,POWER_CTRL Power sequence step 4 delay exceeding specification,4
ERROR,DMA_ENGINE,DMA channel configuration mismatch,DMA_ENGINE DMA channel configuration mismatch,3
WARNING,DDR_CTRL,"DDR write queue nearing capacity, backpressure active","DDR_CTRL DDR write queue nearing capacity, backpressure active",1
WARNING,AXI_CTRL,AXI write response pending for too long,AXI_CTRL AXI write response pending for too long,2
INFO,FIFO_BUF,FIFO data path clear for new transactions,FIFO_BUF FIFO data path clear for new transactions,5
INFO,MEM_CTRL,Memory mapped register access successful,MEM_CTRL Memory mapped register access successful,1
ERROR,CACHE_CTRL,Cache way miss rate exceeding critical threshold (95%),CACHE_CTRL Cache way miss rate exceeding critical threshold (95%),1
ERROR,MEM_CTRL,Memory data bus stuck-at-fault detected,MEM_CTRL Memory data bus stuck-at-fault detected,1
CRITICAL,MEM_CTRL,Memory array integrity compromised,MEM_CTRL Memory array integrity compromised,1
WARNING,POWER_CTRL,Voltage fluctuation detected on VDD_CORE,POWER_CTRL Voltage fluctuation detected on VDD_CORE,4
INFO,AXI_CTRL,AXI channel initialized,AXI_CTRL AXI channel initialized,2
CRITICAL,FIFO_BUF,"FIFO depth check mismatch, incorrect capacity reported","FIFO_BUF FIFO depth check mismatch, incorrect capacity reported",5
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold,FIFO_BUF FIFO latency exceeding expected threshold,5
INFO,POWER_CTRL,Low power mode entry sequence initiated,POWER_CTRL Low power mode entry sequence initiated,4
ERROR,MEM_CTRL,Memory controller detected a double ECC error on read,MEM_CTRL Memory controller detected a double ECC error on read,1
WARNING,DDR_CTRL,DDR training sequence re-initiated due to marginal timing,DDR_CTRL DDR training sequence re-initiated due to marginal timing,1
INFO,DDR_CTRL,DDR bank X opened,DDR_CTRL DDR bank X opened,1
WARNING,POWER_CTRL,Voltage sensor reporting out of range,POWER_CTRL Voltage sensor reporting out of range,7
CRITICAL,INTERRUPT_CTRL,"Interrupt controller deadlock detected, system unresponsive","INTERRUPT_CTRL Interrupt controller deadlock detected, system unresponsive",1
ERROR,MEM_CTRL,Memory write data mismatch detected at 0x0000_1000,MEM_CTRL Memory write data mismatch detected at 0x0000_1000,1
ERROR,PCIE_CTRL,PCIe link training error.,PCIE_CTRL PCIe link training error.,6
ERROR,MEM_CTRL,Memory read modify write sequence aborted due to collision,MEM_CTRL Memory read modify write sequence aborted due to collision,1
ERROR,CLOCK_MANAGER,Clock tree buffer output drive strength degraded.,CLOCK_MANAGER Clock tree buffer output drive strength degraded.,0
ERROR,CLOCK_MANAGER,Clock MUX selection logic stuck in invalid state.,CLOCK_MANAGER Clock MUX selection logic stuck in invalid state.,0
CRITICAL,MEM_CTRL,Memory read operation returned incorrect data due to timing violation,MEM_CTRL Memory read operation returned incorrect data due to timing violation,1
WARNING,FIFO_BUF,FIFO read latency spike detected,FIFO_BUF FIFO read latency spike detected,5
WARNING,AXI_CTRL,AXI_WRITE_RESPONSE timeout approaching threshold,AXI_CTRL AXI_WRITE_RESPONSE timeout approaching threshold,2
CRITICAL,CLOCK_MANAGER,"Clock distribution network fault, certain modules unclocked","CLOCK_MANAGER Clock distribution network fault, certain modules unclocked",0
INFO,CACHE_CTRL,Cache data fetched from L1,CACHE_CTRL Cache data fetched from L1,1
INFO,FIFO_BUF,FIFO flush command acknowledged,FIFO_BUF FIFO flush command acknowledged,5
INFO,CACHE_CTRL,Cache line 0xABCDEF filled from memory,CACHE_CTRL Cache line 0xABCDEF filled from memory,1
ERROR,DMA_ENGINE,DMA chain link error detected in descriptor list,DMA_ENGINE DMA chain link error detected in descriptor list,3
WARNING,FIFO_BUF,"FIFO almost full threshold reached, asserting backpressure","FIFO_BUF FIFO almost full threshold reached, asserting backpressure",5
ERROR,PCIE_CTRL,PCIe device not responding to configuration requests,PCIE_CTRL PCIe device not responding to configuration requests,6
ERROR,MEM_CTRL,Memory bank controller internal error,MEM_CTRL Memory bank controller internal error,1
WARNING,DMA_ENGINE,DMA engine doorbell register access delay,DMA_ENGINE DMA engine doorbell register access delay,-1
ERROR,CLOCK_MANAGER,Clock domain crossing data path latency too high,CLOCK_MANAGER Clock domain crossing data path latency too high,0
WARNING,MEM_CTRL,Memory bank 2 experiencing higher error rate,MEM_CTRL Memory bank 2 experiencing higher error rate,1
CRITICAL,DMA_ENGINE,DMA engine controller state machine entered unreachable state,DMA_ENGINE DMA engine controller state machine entered unreachable state,3
WARNING,DMA_ENGINE,DMA controller configuration register access error,DMA_ENGINE DMA controller configuration register access error,3
WARNING,CACHE_CTRL,Cache line fills from slower memory,CACHE_CTRL Cache line fills from slower memory,1
CRITICAL,CLOCK_MANAGER,Reference clock input absent,CLOCK_MANAGER Reference clock input absent,0
INFO,POWER_CTRL,Core voltage rail enabled successfully,POWER_CTRL Core voltage rail enabled successfully,4
ERROR,MEM_CTRL,Memory controller state machine fault: unexpected state ERROR_STATE.,MEM_CTRL Memory controller state machine fault: unexpected state ERROR_STATE.,1
CRITICAL,CACHE_CTRL,Cache directory state corrupted,CACHE_CTRL Cache directory state corrupted,1
INFO,CLOCK_MANAGER,Clock gate enable sequence completed,CLOCK_MANAGER Clock gate enable sequence completed,0
CRITICAL,MEM_CTRL,Memory protection fault on write to read-only region,MEM_CTRL Memory protection fault on write to read-only region,1
INFO,AXI_CTRL,AXI transaction queue cleared,AXI_CTRL AXI transaction queue cleared,2
WARNING,INTERRUPT_CTRL,Interrupt handler execution latency exceeding max,INTERRUPT_CTRL Interrupt handler execution latency exceeding max,1
WARNING,DMA_ENGINE,DMA descriptor fetch taking longer than expected,DMA_ENGINE DMA descriptor fetch taking longer than expected,3
INFO,POWER_CTRL,Voltage regulator VDD_SOC output 0.9V,POWER_CTRL Voltage regulator VDD_SOC output 0.9V,-1
INFO,FIFO_BUF,Write pointer advanced,FIFO_BUF Write pointer advanced,5
INFO,AXI_CTRL,AXI write burst completed,AXI_CTRL AXI write burst completed,2
WARNING,DMA_ENGINE,DMA channel bandwidth utilization high,DMA_ENGINE DMA channel bandwidth utilization high,3
ERROR,CLOCK_MANAGER,Clock mux selection logic error,CLOCK_MANAGER Clock mux selection logic error,0
WARNING,AXI_CTRL,AXI read channel backpressure approaching limits,AXI_CTRL AXI read channel backpressure approaching limits,2
WARNING,DMA_ENGINE,DMA descriptor fetch rate decreasing,DMA_ENGINE DMA descriptor fetch rate decreasing,3
WARNING,MEM_CTRL,Memory refresh scheduler detected missed cycle,MEM_CTRL Memory refresh scheduler detected missed cycle,1
INFO,CLOCK_MANAGER,Clock generator frequency fine-tuning complete,CLOCK_MANAGER Clock generator frequency fine-tuning complete,-1
INFO,DDR_CTRL,DDR calibration values fine-tuned,DDR_CTRL DDR calibration values fine-tuned,1
INFO,INTERRUPT_CTRL,Interrupt vector table loaded.,INTERRUPT_CTRL Interrupt vector table loaded.,1
CRITICAL,MEM_CTRL,Double bit ECC corruption detected on system stack,MEM_CTRL Double bit ECC corruption detected on system stack,1
ERROR,AXI_CTRL,AXI read burst length exceeds maximum supported,AXI_CTRL AXI read burst length exceeds maximum supported,2
ERROR,CLOCK_MANAGER,Clock buffer integrity check failed,CLOCK_MANAGER Clock buffer integrity check failed,0
INFO,DMA_ENGINE,DMA engine enabled,DMA_ENGINE DMA engine enabled,3
INFO,DMA_ENGINE,DMA channel 3 transfer initiated,DMA_ENGINE DMA channel 3 transfer initiated,3
WARNING,POWER_CTRL,System temperature exceeding 70 degrees Celsius,POWER_CTRL System temperature exceeding 70 degrees Celsius,-1
CRITICAL,POWER_CTRL,System power-off initiated due to fault,POWER_CTRL System power-off initiated due to fault,4
WARNING,POWER_CTRL,Power supply glitch detected,POWER_CTRL Power supply glitch detected,4
ERROR,DDR_CTRL,DDR write levelization failed,DDR_CTRL DDR write levelization failed,1
ERROR,CACHE_CTRL,Cache coherence violation detected between CPU and DMA. (protocol mismatch),CACHE_CTRL Cache coherence violation detected between CPU and DMA. (protocol mismatch),1
INFO,INTERRUPT_CTRL,Interrupt controller debug port enabled,INTERRUPT_CTRL Interrupt controller debug port enabled,1
WARNING,AXI_CTRL,AXI transaction issued with invalid memory type,AXI_CTRL AXI transaction issued with invalid memory type,2
INFO,POWER_CTRL,Power domain CPU_PD entered low power state,POWER_CTRL Power domain CPU_PD entered low power state,4
ERROR,POWER_CTRL,Power-on reset sequence failure,POWER_CTRL Power-on reset sequence failure,4
ERROR,DDR_CTRL,DDR timing specification violation on write command,DDR_CTRL DDR timing specification violation on write command,1
CRITICAL,POWER_CTRL,System power-on-reset (POR) pulse malformed,POWER_CTRL System power-on-reset (POR) pulse malformed,4
WARNING,CACHE_CTRL,L1 data cache miss rate exceeding 12% threshold.,CACHE_CTRL L1 data cache miss rate exceeding 12% threshold.,1
ERROR,MEM_CTRL,Memory controller detected an invalid read address,MEM_CTRL Memory controller detected an invalid read address,1
ERROR,FIFO_BUF,FIFO overflow condition detected during sustained writes,FIFO_BUF FIFO overflow condition detected during sustained writes,5
INFO,PCIE_CTRL,PCIe TLP posted successfully.,PCIE_CTRL PCIe TLP posted successfully.,6
INFO,INTERRUPT_CTRL,Interrupt priority level adjusted,INTERRUPT_CTRL Interrupt priority level adjusted,1
INFO,DMA_ENGINE,DMA Scatter-Gather list processed,DMA_ENGINE DMA Scatter-Gather list processed,3
ERROR,PCIE_CTRL,PCIe Non-Fatal Error status bit set due to advisory non-fatal error.,PCIE_CTRL PCIe Non-Fatal Error status bit set due to advisory non-fatal error.,6
INFO,DMA_ENGINE,DMA channel 14 transfer completed successfully,DMA_ENGINE DMA channel 14 transfer completed successfully,3
INFO,INTERRUPT_CTRL,Interrupt vector table reload initiated,INTERRUPT_CTRL Interrupt vector table reload initiated,1
INFO,INTERRUPT_CTRL,Interrupt 19 enabled in mask register.,INTERRUPT_CTRL Interrupt 19 enabled in mask register.,1
INFO,CACHE_CTRL,Cache invalidate command issued for address range,CACHE_CTRL Cache invalidate command issued for address range,1
WARNING,FIFO_BUF,FIFO pointer wrap-around warning,FIFO_BUF FIFO pointer wrap-around warning,5
INFO,CACHE_CTRL,Cache configuration loaded successfully,CACHE_CTRL Cache configuration loaded successfully,1
CRITICAL,DMA_ENGINE,DMA engine internal state machine entered illegal state.,DMA_ENGINE DMA engine internal state machine entered illegal state.,3
CRITICAL,CLOCK_MANAGER,Clock generation PLL lock lost for main system clock. (PLL lock lost),CLOCK_MANAGER Clock generation PLL lock lost for main system clock. (PLL lock lost),0
WARNING,CACHE_CTRL,"Cache miss rate elevated (15%), impacting performance","CACHE_CTRL Cache miss rate elevated (15%), impacting performance",1
INFO,INTERRUPT_CTRL,Interrupt line 'GPIO_INT' de-asserted,INTERRUPT_CTRL Interrupt line 'GPIO_INT' de-asserted,1
WARNING,CACHE_CTRL,Cache directory entry corruption detected,CACHE_CTRL Cache directory entry corruption detected,1
ERROR,PCIE_CTRL,PCIe Completion Timeout (CTO) on outbound transaction.,PCIE_CTRL PCIe Completion Timeout (CTO) on outbound transaction.,6
CRITICAL,PCIE_CTRL,PCIe fatal error: device enumeration failure,PCIE_CTRL PCIe fatal error: device enumeration failure,6
ERROR,CACHE_CTRL,Cache tag match logic reported false positive,CACHE_CTRL Cache tag match logic reported false positive,1
INFO,MEM_CTRL,Memory read operation completed successfully,MEM_CTRL Memory read operation completed successfully,1
INFO,DMA_ENGINE,DMA channel transfer aborted by software,DMA_ENGINE DMA channel transfer aborted by software,3
WARNING,CLOCK_MANAGER,Clock domain crossing bridge data loss detected,CLOCK_MANAGER Clock domain crossing bridge data loss detected,0
INFO,DMA_ENGINE,DMA channel 0 enabled and ready for transfers.,DMA_ENGINE DMA channel 0 enabled and ready for transfers.,3
ERROR,CACHE_CTRL,Cache line replacement policy logic error,CACHE_CTRL Cache line replacement policy logic error,1
ERROR,FIFO_BUF,Write pointer advanced without valid data,FIFO_BUF Write pointer advanced without valid data,5
CRITICAL,POWER_CTRL,Core power supply voltage droop below critical threshold,POWER_CTRL Core power supply voltage droop below critical threshold,4
ERROR,CLOCK_MANAGER,Clock multiplexer selection error,CLOCK_MANAGER Clock multiplexer selection error,0
CRITICAL,MEM_CTRL,Memory controller unable to respond to critical request.,MEM_CTRL Memory controller unable to respond to critical request.,1
WARNING,AXI_CTRL,AXI write response `BRESP` received as `SLVERR`,AXI_CTRL AXI write response `BRESP` received as `SLVERR`,2
INFO,DDR_CTRL,DDR memory training phase 5 completed.,DDR_CTRL DDR memory training phase 5 completed.,1
CRITICAL,POWER_CTRL,Entire system power-off initiated due to fault,POWER_CTRL Entire system power-off initiated due to fault,4
WARNING,MEM_CTRL,Memory controller read latency exceeding expected range,MEM_CTRL Memory controller read latency exceeding expected range,1
WARNING,CLOCK_MANAGER,Clock domain crossing handshaking failure,CLOCK_MANAGER Clock domain crossing handshaking failure,0
CRITICAL,PCIE_CTRL,"PCIe PHY link training fatal error, link down","PCIE_CTRL PCIe PHY link training fatal error, link down",6
INFO,DMA_ENGINE,DMA engine initialized.,DMA_ENGINE DMA engine initialized.,3
WARNING,CACHE_CTRL,L1 cache eviction rate unusually high,CACHE_CTRL L1 cache eviction rate unusually high,1
WARNING,PCIE_CTRL,PCIe device link width negotiation unstable,PCIE_CTRL PCIe device link width negotiation unstable,6
WARNING,DMA_ENGINE,DMA_ENGINE encountered a minor timing deviation.,DMA_ENGINE DMA_ENGINE encountered a minor timing deviation.,3
INFO,DMA_ENGINE,DMA channel 1 activated for peripheral transfer,DMA_ENGINE DMA channel 1 activated for peripheral transfer,3
WARNING,PCIE_CTRL,PCIe link throughput degraded by error rate,PCIE_CTRL PCIe link throughput degraded by error rate,6
WARNING,CACHE_CTRL,L1 cache miss rate above 15%,CACHE_CTRL L1 cache miss rate above 15%,1
ERROR,CLOCK_MANAGER,Clock domain crossing error: data path desynchronization,CLOCK_MANAGER Clock domain crossing error: data path desynchronization,0
CRITICAL,DMA_ENGINE,DMA engine internal state machine entered invalid state,DMA_ENGINE DMA engine internal state machine entered invalid state,3
ERROR,MEM_CTRL,Memory address alignment fault for access at 0xCD2225B5,MEM_CTRL Memory address alignment fault for access at 0xCD2225B5,1
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lock lost, system wide","CLOCK_MANAGER Clock generation PLL lock lost, system wide",0
INFO,INTERRUPT_CTRL,Software interrupt generated and handled,INTERRUPT_CTRL Software interrupt generated and handled,1
WARNING,CACHE_CTRL,Cache write-through path congestion,CACHE_CTRL Cache write-through path congestion,1
CRITICAL,MEM_CTRL,Data bus parity error on memory write operation,MEM_CTRL Data bus parity error on memory write operation,1
INFO,FIFO_BUF,Threshold set for FIFO watermark,FIFO_BUF Threshold set for FIFO watermark,5
ERROR,FIFO_BUF,FIFO 'cmd_out' write pointer advanced past full condition,FIFO_BUF FIFO 'cmd_out' write pointer advanced past full condition,5
WARNING,AXI_CTRL,AXI channel arbitration latency high,AXI_CTRL AXI channel arbitration latency high,2
CRITICAL,POWER_CTRL,Voltage regulator unable to stabilize output voltage,POWER_CTRL Voltage regulator unable to stabilize output voltage,4
WARNING,CACHE_CTRL,Cache flush operation stalled,CACHE_CTRL Cache flush operation stalled,1
WARNING,AXI_CTRL,AXI master requesting unsupported burst type,AXI_CTRL AXI master requesting unsupported burst type,2
ERROR,MEM_CTRL,Multiple bit ECC error detected (correctable),MEM_CTRL Multiple bit ECC error detected (correctable),1
WARNING,INTERRUPT_CTRL,Interrupt dispatcher queue backlogging,INTERRUPT_CTRL Interrupt dispatcher queue backlogging,-1
CRITICAL,DDR_CTRL,DDR chip select signal unresponsive,DDR_CTRL DDR chip select signal unresponsive,8
WARNING,AXI_CTRL,AXI read data channel stall detected,AXI_CTRL AXI read data channel stall detected,2
ERROR,MEM_CTRL,Memory controller write-protection violation,MEM_CTRL Memory controller write-protection violation,1
INFO,CACHE_CTRL,Cache fill operation completed,CACHE_CTRL Cache fill operation completed,1
INFO,MEM_CTRL,Memory region 0x8000-0x9000 validated,MEM_CTRL Memory region 0x8000-0x9000 validated,1
WARNING,AXI_CTRL,AXI burst size negotiation conflict,AXI_CTRL AXI burst size negotiation conflict,2
WARNING,CACHE_CTRL,Cache line replacement policy causing thrashing.,CACHE_CTRL Cache line replacement policy causing thrashing.,1
WARNING,DDR_CTRL,DDR refresh interval exceeding design limits,DDR_CTRL DDR refresh interval exceeding design limits,1
INFO,FIFO_BUF,FIFO_BUF_20 cleared all pending data,FIFO_BUF FIFO_BUF_20 cleared all pending data,5
INFO,PCIE_CTRL,PCIe endpoint received Configuration Write,PCIE_CTRL PCIe endpoint received Configuration Write,6
CRITICAL,DMA_ENGINE,DMA channel 10 attempted to write to a protected kernel memory region,DMA_ENGINE DMA channel 10 attempted to write to a protected kernel memory region,3
WARNING,MEM_CTRL,Partial write detected,MEM_CTRL Partial write detected,1
ERROR,POWER_CTRL,Power sequencing error detected during system boot.,POWER_CTRL Power sequencing error detected during system boot.,4
ERROR,AXI_CTRL,AXI write channel protocol mismatch,AXI_CTRL AXI write channel protocol mismatch,2
CRITICAL,CACHE_CTRL,Cache directory coherence protocol violation,CACHE_CTRL Cache directory coherence protocol violation,1
WARNING,DDR_CTRL,DDR controller reports increasing memory bus errors,DDR_CTRL DDR controller reports increasing memory bus errors,1
ERROR,MEM_CTRL,Memory controller address generation unit fault,MEM_CTRL Memory controller address generation unit fault,1
ERROR,AXI_CTRL,AXI protocol violation on AWVALID/AWREADY sequence,AXI_CTRL AXI protocol violation on AWVALID/AWREADY sequence,2
ERROR,INTERRUPT_CTRL,Interrupt service routine (ISR) timeout,INTERRUPT_CTRL Interrupt service routine (ISR) timeout,1
ERROR,FIFO_BUF,"FIFO write enable asserted when full, buffer overflow.","FIFO_BUF FIFO write enable asserted when full, buffer overflow.",5
INFO,DDR_CTRL,DDR_CTRL self-test passed.,DDR_CTRL DDR_CTRL self-test passed.,1
CRITICAL,DMA_ENGINE,"Persistent DMA buffer descriptor corruption, data loss certain","DMA_ENGINE Persistent DMA buffer descriptor corruption, data loss certain",3
ERROR,FIFO_BUF,Data integrity check failed on read,FIFO_BUF Data integrity check failed on read,5
ERROR,CACHE_CTRL,Cache write-back failure,CACHE_CTRL Cache write-back failure,1
INFO,CACHE_CTRL,CACHE_CTRL entered idle state.,CACHE_CTRL CACHE_CTRL entered idle state.,-1
INFO,FIFO_BUF,FIFO reset completed,FIFO_BUF FIFO reset completed,5
CRITICAL,POWER_CTRL,System power supply integrity compromised,POWER_CTRL System power supply integrity compromised,-1
ERROR,DMA_ENGINE,DMA channel 12 transfer abort due to error,DMA_ENGINE DMA channel 12 transfer abort due to error,3
CRITICAL,INTERRUPT_CTRL,"Critical interrupt pending for too long, watchdog triggered for IRQ 0x1","INTERRUPT_CTRL Critical interrupt pending for too long, watchdog triggered for IRQ 0x1",1
INFO,PCIE_CTRL,"PCIe link established successfully, speed negotiated.","PCIE_CTRL PCIe link established successfully, speed negotiated.",6
WARNING,DMA_ENGINE,"DMA channel 1 awaiting target acknowledge, stall detected","DMA_ENGINE DMA channel 1 awaiting target acknowledge, stall detected",3
INFO,DMA_ENGINE,DMA channel 0 requested arbitration.,DMA_ENGINE DMA channel 0 requested arbitration.,3
CRITICAL,POWER_CTRL,"Core rail voltage collapse, hardware damage risk","POWER_CTRL Core rail voltage collapse, hardware damage risk",4
INFO,CACHE_CTRL,Cache prefetcher activated,CACHE_CTRL Cache prefetcher activated,1
ERROR,MEM_CTRL,Memory access permission violation detected,MEM_CTRL Memory access permission violation detected,1
WARNING,DMA_ENGINE,DMA channel arbitration latency observed as higher than average,DMA_ENGINE DMA channel arbitration latency observed as higher than average,3
WARNING,DMA_ENGINE,DMA channel 6 experienced multiple bus contention retries.,DMA_ENGINE DMA channel 6 experienced multiple bus contention retries.,3
ERROR,PCIE_CTRL,PCIe TLP header checksum mismatch,PCIE_CTRL PCIe TLP header checksum mismatch,6
ERROR,MEM_CTRL,Memory controller arbitration logic inconsistency,MEM_CTRL Memory controller arbitration logic inconsistency,1
INFO,MEM_CTRL,Memory address 0x5D7B7 successfully written,MEM_CTRL Memory address 0x5D7B7 successfully written,1
ERROR,PCIE_CTRL,PCIe received PERR_N assertion from downstream device.,PCIE_CTRL PCIe received PERR_N assertion from downstream device.,-1
ERROR,MEM_CTRL,Memory controller arbitration conflict detected for banks,MEM_CTRL Memory controller arbitration conflict detected for banks,1
INFO,POWER_CTRL,Low power sleep state entered by CPU,POWER_CTRL Low power sleep state entered by CPU,4
ERROR,INTERRUPT_CTRL,Unexpected interrupt source asserted,INTERRUPT_CTRL Unexpected interrupt source asserted,1
INFO,INTERRUPT_CTRL,Interrupt controller in idle state.,INTERRUPT_CTRL Interrupt controller in idle state.,1
WARNING,INTERRUPT_CTRL,Interrupt source debounce timeout extended.,INTERRUPT_CTRL Interrupt source debounce timeout extended.,1
CRITICAL,DDR_CTRL,DDR memory rank 3 unrecoverable data error,DDR_CTRL DDR memory rank 3 unrecoverable data error,1
WARNING,PCIE_CTRL,PCIe error counter threshold reached,PCIE_CTRL PCIe error counter threshold reached,6
ERROR,CACHE_CTRL,Cache instruction prefetch buffer overflow.,CACHE_CTRL Cache instruction prefetch buffer overflow.,1
WARNING,DMA_ENGINE,DMA descriptor queue nearing capacity,DMA_ENGINE DMA descriptor queue nearing capacity,3
CRITICAL,INTERRUPT_CTRL,Persistent high-priority interrupt storm.,INTERRUPT_CTRL Persistent high-priority interrupt storm.,1
WARNING,CACHE_CTRL,Cache hit rate dropping,CACHE_CTRL Cache hit rate dropping,1
WARNING,INTERRUPT_CTRL,Interrupt mask changed unexpectedly,INTERRUPT_CTRL Interrupt mask changed unexpectedly,1
WARNING,DDR_CTRL,DDR training parameters sub-optimal for current temperature,DDR_CTRL DDR training parameters sub-optimal for current temperature,-1
ERROR,POWER_CTRL,"Power domain isolation logic failure, unintended voltage bleed.","POWER_CTRL Power domain isolation logic failure, unintended voltage bleed.",4
ERROR,PCIE_CTRL,PCIe configuration read failed for device 0:0:0,PCIE_CTRL PCIe configuration read failed for device 0:0:0,6
WARNING,AXI_CTRL,AXI read latency elevated.,AXI_CTRL AXI read latency elevated.,2
CRITICAL,INTERRUPT_CTRL,"Interrupt vector table corruption, system crash imminent","INTERRUPT_CTRL Interrupt vector table corruption, system crash imminent",1
INFO,CACHE_CTRL,L1 data cache invalidate by address range complete,CACHE_CTRL L1 data cache invalidate by address range complete,1
WARNING,PCIE_CTRL,PCIe transaction layer CRC error rate increasing,PCIE_CTRL PCIe transaction layer CRC error rate increasing,6
CRITICAL,DMA_ENGINE,DMA engine experiencing complete resource deadlock,DMA_ENGINE DMA engine experiencing complete resource deadlock,3
CRITICAL,PCIE_CTRL,PCIe transaction layer protocol fatal error,PCIE_CTRL PCIe transaction layer protocol fatal error,6
ERROR,MEM_CTRL,Memory controller state machine entered an unexpected state,MEM_CTRL Memory controller state machine entered an unexpected state,1
INFO,MEM_CTRL,Memory controller operating in safe mode,MEM_CTRL Memory controller operating in safe mode,1
INFO,CLOCK_MANAGER,Clock domain synchronization FIFO empty,CLOCK_MANAGER Clock domain synchronization FIFO empty,0
ERROR,POWER_CTRL,"Power sequence out of order during boot-up, unexpected state","POWER_CTRL Power sequence out of order during boot-up, unexpected state",4
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, potential underflow.","FIFO_BUF FIFO read pointer approaching write pointer, potential underflow.",5
WARNING,PCIE_CTRL,PCIe configuration space access timeout,PCIE_CTRL PCIe configuration space access timeout,6
INFO,CACHE_CTRL,Cache line successfully evicted,CACHE_CTRL Cache line successfully evicted,1
WARNING,CACHE_CTRL,Cache prefetch efficiency degradation,CACHE_CTRL Cache prefetch efficiency degradation,1
INFO,POWER_CTRL,Power state changed to ON,POWER_CTRL Power state changed to ON,4
INFO,POWER_CTRL,High power state entered for performance boost,POWER_CTRL High power state entered for performance boost,4
ERROR,AXI_CTRL,AXI read response ID mismatch,AXI_CTRL AXI read response ID mismatch,2
INFO,AXI_CTRL,AXI slave 'FLASH_CTRL' responded with EXOKAY for write,AXI_CTRL AXI slave 'FLASH_CTRL' responded with EXOKAY for write,2
INFO,CLOCK_MANAGER,Clock domain crossing bridge statistics cleared,CLOCK_MANAGER Clock domain crossing bridge statistics cleared,0
WARNING,INTERRUPT_CTRL,Interrupt line toggling at excessive rate,INTERRUPT_CTRL Interrupt line toggling at excessive rate,1
ERROR,AXI_CTRL,AXI burst length violation detected on master 0x03,AXI_CTRL AXI burst length violation detected on master 0x03,2
ERROR,CACHE_CTRL,Cache miss-speculation resulted in erroneous fetch,CACHE_CTRL Cache miss-speculation resulted in erroneous fetch,1
WARNING,CLOCK_MANAGER,Clock tree delay budget violation detected in static timing analysis,CLOCK_MANAGER Clock tree delay budget violation detected in static timing analysis,0
CRITICAL,INTERRUPT_CTRL,Interrupt controller failed to acknowledge critical system interrupt,INTERRUPT_CTRL Interrupt controller failed to acknowledge critical system interrupt,1
INFO,PCIE_CTRL,PCIe link state change to L0,PCIE_CTRL PCIe link state change to L0,6
ERROR,CLOCK_MANAGER,Clock divider bypass mode entered incorrectly,CLOCK_MANAGER Clock divider bypass mode entered incorrectly,0
ERROR,PCIE_CTRL,PCIE_CTRL: protocol mismatch - protocol header error detected.,PCIE_CTRL PCIE_CTRL: protocol mismatch - protocol header error detected.,6
INFO,INTERRUPT_CTRL,Interrupt source 12 asserted,INTERRUPT_CTRL Interrupt source 12 asserted,1
ERROR,MEM_CTRL,Memory controller internal data path error,MEM_CTRL Memory controller internal data path error,1
INFO,PCIE_CTRL,PCIe link detected at Gen3 speed,PCIE_CTRL PCIe link detected at Gen3 speed,6
ERROR,DMA_ENGINE,DMA channel 11 detected an uncorrectable ECC error in its descriptor table,DMA_ENGINE DMA channel 11 detected an uncorrectable ECC error in its descriptor table,-1
WARNING,CACHE_CTRL,"Cache tag parity error detected, single-bit corrected","CACHE_CTRL Cache tag parity error detected, single-bit corrected",1
WARNING,INTERRUPT_CTRL,Interrupt service routine timeout,INTERRUPT_CTRL Interrupt service routine timeout,1
INFO,DDR_CTRL,DDR BIST initiated,DDR_CTRL DDR BIST initiated,1
WARNING,FIFO_BUF,FIFO empty status signal oscillating,FIFO_BUF FIFO empty status signal oscillating,5
INFO,DDR_CTRL,DDR interface initialized.,DDR_CTRL DDR interface initialized.,1
WARNING,DMA_ENGINE,DMA scatter-gather list incomplete.,DMA_ENGINE DMA scatter-gather list incomplete.,3
ERROR,AXI_CTRL,AXI outstanding transaction count exceeds maximum,AXI_CTRL AXI outstanding transaction count exceeds maximum,2
WARNING,INTERRUPT_CTRL,"Masked interrupt detected, but source still asserted","INTERRUPT_CTRL Masked interrupt detected, but source still asserted",1
CRITICAL,AXI_CTRL,AXI interconnect critical protocol mismatch,AXI_CTRL AXI interconnect critical protocol mismatch,2
WARNING,PCIE_CTRL,"PCIe error statistics increasing, monitoring required (CRC errors)","PCIE_CTRL PCIe error statistics increasing, monitoring required (CRC errors)",6
ERROR,POWER_CTRL,Voltage rail X feedback loop open,POWER_CTRL Voltage rail X feedback loop open,-1
ERROR,CACHE_CTRL,Cache coherency manager deadlock,CACHE_CTRL Cache coherency manager deadlock,1
ERROR,DDR_CTRL,DDR memory address parity error,DDR_CTRL DDR memory address parity error,1
ERROR,MEM_CTRL,Memory address alignment fault detected on write access to 0x1003.,MEM_CTRL Memory address alignment fault detected on write access to 0x1003.,1
CRITICAL,AXI_CTRL,"AXI fabric critical error, all transactions failing","AXI_CTRL AXI fabric critical error, all transactions failing",2
CRITICAL,MEM_CTRL,Memory bank 2 unable to respond to read/write commands,MEM_CTRL Memory bank 2 unable to respond to read/write commands,1
INFO,CACHE_CTRL,Cache line 0xABCDEF01 successfully evicted.,CACHE_CTRL Cache line 0xABCDEF01 successfully evicted.,1
CRITICAL,PCIE_CTRL,"PCIe PHY layer error, link re-initialization failed","PCIE_CTRL PCIe PHY layer error, link re-initialization failed",6
WARNING,CACHE_CTRL,Cache eviction queue nearing capacity (93 entries).,CACHE_CTRL Cache eviction queue nearing capacity (93 entries).,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal asserted too early,INTERRUPT_CTRL Interrupt acknowledge signal asserted too early,1
WARNING,MEM_CTRL,"Memory controller command queue nearing capacity, potential buffer overflow.","MEM_CTRL Memory controller command queue nearing capacity, potential buffer overflow.",1
ERROR,FIFO_BUF,Data written to FIFO corrupted upon read,FIFO_BUF Data written to FIFO corrupted upon read,5
CRITICAL,CLOCK_MANAGER,Clock source unrecoverable failure,CLOCK_MANAGER Clock source unrecoverable failure,0
WARNING,AXI_CTRL,AXI slave response delay for write data channel exceeding average,AXI_CTRL AXI slave response delay for write data channel exceeding average,2
ERROR,CLOCK_MANAGER,Clock domain crossing metastability detected on 'control_signal',CLOCK_MANAGER Clock domain crossing metastability detected on 'control_signal',0
WARNING,DDR_CTRL,DDR memory scrub task completion delayed,DDR_CTRL DDR memory scrub task completion delayed,-1
ERROR,INTERRUPT_CTRL,Interrupt request line stuck active,INTERRUPT_CTRL Interrupt request line stuck active,1
INFO,CLOCK_MANAGER,Clock source switched to backup oscillator,CLOCK_MANAGER Clock source switched to backup oscillator,0
INFO,POWER_CTRL,Power state transition completed to D0.,POWER_CTRL Power state transition completed to D0.,4
WARNING,DMA_ENGINE,DMA internal buffer utilization at 80%,DMA_ENGINE DMA internal buffer utilization at 80%,3
ERROR,DDR_CTRL,DDR memory controller detected a command timing violation,DDR_CTRL DDR memory controller detected a command timing violation,1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller internal data corruption detected, system halt imminent.","INTERRUPT_CTRL Interrupt controller internal data corruption detected, system halt imminent.",1
ERROR,MEM_CTRL,Memory address bus contention,MEM_CTRL Memory address bus contention,1
WARNING,CLOCK_MANAGER,"Clock source switching detected, momentary instability.","CLOCK_MANAGER Clock source switching detected, momentary instability.",0
CRITICAL,CACHE_CTRL,"Cache directory corruption detected, cache state inconsistent. (data corruption)","CACHE_CTRL Cache directory corruption detected, cache state inconsistent. (data corruption)",1
ERROR,CLOCK_MANAGER,Clock gate enable logic race condition,CLOCK_MANAGER Clock gate enable logic race condition,0
WARNING,INTERRUPT_CTRL,Pending interrupt queue nearing capacity.,INTERRUPT_CTRL Pending interrupt queue nearing capacity.,1
INFO,MEM_CTRL,Memory controller arbitration scheme changed,MEM_CTRL Memory controller arbitration scheme changed,1
INFO,CACHE_CTRL,L1 data cache write-through completed,CACHE_CTRL L1 data cache write-through completed,1
ERROR,MEM_CTRL,"Memory write data ECC error, correctable","MEM_CTRL Memory write data ECC error, correctable",1
CRITICAL,DMA_ENGINE,DMA channel security violation,DMA_ENGINE DMA channel security violation,3
ERROR,MEM_CTRL,Memory access to unallocated region detected,MEM_CTRL Memory access to unallocated region detected,1
WARNING,DDR_CTRL,DDR read data setup/hold time margin very low,DDR_CTRL DDR read data setup/hold time margin very low,1
ERROR,INTERRUPT_CTRL,Interrupt priority arbitration failure.,INTERRUPT_CTRL Interrupt priority arbitration failure.,1
INFO,PCIE_CTRL,PCIe transaction layer packet sent with completion status,PCIE_CTRL PCIe transaction layer packet sent with completion status,6
WARNING,CACHE_CTRL,Cache replacement algorithm thrashing,CACHE_CTRL Cache replacement algorithm thrashing,1
WARNING,FIFO_BUF,FIFO_BUF response latency marginally increased.,FIFO_BUF FIFO_BUF response latency marginally increased.,5
INFO,MEM_CTRL,Memory precharge command issued,MEM_CTRL Memory precharge command issued,1
ERROR,DMA_ENGINE,DMA channel 0 burst length configured improperly,DMA_ENGINE DMA channel 0 burst length configured improperly,3
ERROR,CLOCK_MANAGER,Clock 'UART_CLK' stuck at low state,CLOCK_MANAGER Clock 'UART_CLK' stuck at low state,-1
INFO,PCIE_CTRL,PCIe device driver loaded successfully,PCIE_CTRL PCIe device driver loaded successfully,6
WARNING,CLOCK_MANAGER,Clock recovery circuit for SerDes lane 0 margin is low.,CLOCK_MANAGER Clock recovery circuit for SerDes lane 0 margin is low.,-1
INFO,FIFO_BUF,FIFO read operation successful,FIFO_BUF FIFO read operation successful,5
CRITICAL,POWER_CTRL,Core voltage rail collapse detected,POWER_CTRL Core voltage rail collapse detected,4
ERROR,MEM_CTRL,Memory data integrity check protocol mismatch.,MEM_CTRL Memory data integrity check protocol mismatch.,1
ERROR,AXI_CTRL,AXI read address channel protocol violation,AXI_CTRL AXI read address channel protocol violation,2
CRITICAL,POWER_CTRL,System shutdown due to unrecoverable power fault,POWER_CTRL System shutdown due to unrecoverable power fault,4
ERROR,PCIE_CTRL,CRC error on TLP received,PCIE_CTRL CRC error on TLP received,6
ERROR,CACHE_CTRL,Cache coherence protocol violation detected at address 0x20004000.,CACHE_CTRL Cache coherence protocol violation detected at address 0x20004000.,1
INFO,AXI_CTRL,AXI master 1 granted bus access for read burst,AXI_CTRL AXI master 1 granted bus access for read burst,2
INFO,FIFO_BUF,FIFO reset complete,FIFO_BUF FIFO reset complete,5
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal FSM entered invalid state,INTERRUPT_CTRL Interrupt controller internal FSM entered invalid state,1
ERROR,POWER_CTRL,Power domain VDD_GPU reported under-voltage,POWER_CTRL Power domain VDD_GPU reported under-voltage,4
CRITICAL,POWER_CTRL,System power domain isolation failure,POWER_CTRL System power domain isolation failure,4
ERROR,POWER_CTRL,Power management unit communication error,POWER_CTRL Power management unit communication error,4
INFO,DMA_ENGINE,DMA channel 2 status: ready for new transfer,DMA_ENGINE DMA channel 2 status: ready for new transfer,3
ERROR,CLOCK_MANAGER,Reset deassertion timing violation detected,CLOCK_MANAGER Reset deassertion timing violation detected,0
ERROR,INTERRUPT_CTRL,"Interrupt vector mismatch, unexpected source ID from device 'SPI'.","INTERRUPT_CTRL Interrupt vector mismatch, unexpected source ID from device 'SPI'.",1
WARNING,POWER_CTRL,Voltage drop prediction on rail V_CORE,POWER_CTRL Voltage drop prediction on rail V_CORE,4
WARNING,POWER_CTRL,Supply voltage fluctuation detected,POWER_CTRL Supply voltage fluctuation detected,4
CRITICAL,DDR_CTRL,DDR PHY calibration coefficients invalid,DDR_CTRL DDR PHY calibration coefficients invalid,1
CRITICAL,MEM_CTRL,Memory access permissions table corrupted,MEM_CTRL Memory access permissions table corrupted,1
WARNING,FIFO_BUF,"FIFO nearly full, write backpressure asserted","FIFO_BUF FIFO nearly full, write backpressure asserted",5
INFO,PCIE_CTRL,PCIe transaction layer packet (TLP) sent,PCIE_CTRL PCIe transaction layer packet (TLP) sent,6
ERROR,PCIE_CTRL,PCIe poisoned TLP received,PCIE_CTRL PCIe poisoned TLP received,6
WARNING,MEM_CTRL,Memory controller command queue nearly full,MEM_CTRL Memory controller command queue nearly full,1
INFO,INTERRUPT_CTRL,Interrupt priority level for IRQ 6 set to high.,INTERRUPT_CTRL Interrupt priority level for IRQ 6 set to high.,1
ERROR,CLOCK_MANAGER,Clock gating logic for module X failed to disable clock.,CLOCK_MANAGER Clock gating logic for module X failed to disable clock.,0
CRITICAL,POWER_CTRL,"Power management unit enters safe mode, limiting functionality","POWER_CTRL Power management unit enters safe mode, limiting functionality",4
CRITICAL,MEM_CTRL,Memory arbiter stuck in a circular dependency.,MEM_CTRL Memory arbiter stuck in a circular dependency.,1
WARNING,AXI_CTRL,AXI burst size negotiation mismatch,AXI_CTRL AXI burst size negotiation mismatch,2
CRITICAL,INTERRUPT_CTRL,"Interrupt controller hardware error, no interrupts asserted","INTERRUPT_CTRL Interrupt controller hardware error, no interrupts asserted",1
INFO,MEM_CTRL,Memory refresh operation completed,MEM_CTRL Memory refresh operation completed,1
INFO,DMA_ENGINE,DMA descriptor table loaded successfully,DMA_ENGINE DMA descriptor table loaded successfully,3
CRITICAL,PCIE_CTRL,"PCIe link layer assertion failure, forcing link down","PCIE_CTRL PCIe link layer assertion failure, forcing link down",6
ERROR,INTERRUPT_CTRL,Interrupt status register read error,INTERRUPT_CTRL Interrupt status register read error,1
ERROR,CACHE_CTRL,"Cache tag comparison error, potential corruption","CACHE_CTRL Cache tag comparison error, potential corruption",1
WARNING,PCIE_CTRL,PCIe device hot-plug removal detected,PCIE_CTRL PCIe device hot-plug removal detected,6
ERROR,DMA_ENGINE,DMA source/destination address invalid on channel 0x0,DMA_ENGINE DMA source/destination address invalid on channel 0x0,3
CRITICAL,DMA_ENGINE,DMA engine global configuration registers corrupted,DMA_ENGINE DMA engine global configuration registers corrupted,3
INFO,INTERRUPT_CTRL,Interrupt controller debug register read,INTERRUPT_CTRL Interrupt controller debug register read,1
ERROR,FIFO_BUF,FIFO read data mismatch due to race condition,FIFO_BUF FIFO read data mismatch due to race condition,5
INFO,PCIE_CTRL,PCIe hot-plug event detected,PCIE_CTRL PCIe hot-plug event detected,6
INFO,DDR_CTRL,DDR memory content scrub initiated,DDR_CTRL DDR memory content scrub initiated,1
INFO,CLOCK_MANAGER,Internal oscillator locked to reference.,CLOCK_MANAGER Internal oscillator locked to reference.,0
INFO,INTERRUPT_CTRL,Interrupt queue depth reset,INTERRUPT_CTRL Interrupt queue depth reset,1
CRITICAL,POWER_CTRL,Core power rail completely collapsed,POWER_CTRL Core power rail completely collapsed,4
WARNING,DMA_ENGINE,DMA channel 1 bandwidth saturation,DMA_ENGINE DMA channel 1 bandwidth saturation,3
ERROR,MEM_CTRL,Memory access permissions violation,MEM_CTRL Memory access permissions violation,1
ERROR,INTERRUPT_CTRL,Interrupt controller clock domain crossing hazard,INTERRUPT_CTRL Interrupt controller clock domain crossing hazard,-1
WARNING,AXI_CTRL,AXI write channel queue depth exceeding optimal.,AXI_CTRL AXI write channel queue depth exceeding optimal.,2
INFO,PCIE_CTRL,Configuration register read from endpoint 0,PCIE_CTRL Configuration register read from endpoint 0,6
ERROR,CLOCK_MANAGER,Clock tree integrity violation detected on secondary clock,CLOCK_MANAGER Clock tree integrity violation detected on secondary clock,0
WARNING,CLOCK_MANAGER,Synchronizer chain detected potential metastability,CLOCK_MANAGER Synchronizer chain detected potential metastability,0
ERROR,DDR_CTRL,"DDR_CTRL: timing violation - clock period violation detected. (Command: READ, Bank: 3)","DDR_CTRL DDR_CTRL: timing violation - clock period violation detected. (Command: READ, Bank: 3)",1
ERROR,CACHE_CTRL,Cache tag RAM corruption detected,CACHE_CTRL Cache tag RAM corruption detected,1
ERROR,DMA_ENGINE,DMA target address beyond valid memory range.,DMA_ENGINE DMA target address beyond valid memory range.,3
INFO,MEM_CTRL,Memory access permissions updated,MEM_CTRL Memory access permissions updated,1
CRITICAL,PCIE_CTRL,PCIe endpoint internal state machine entered an illegal state,PCIE_CTRL PCIe endpoint internal state machine entered an illegal state,6
CRITICAL,CLOCK_MANAGER,Reference clock input lost,CLOCK_MANAGER Reference clock input lost,0
INFO,MEM_CTRL,Memory protection enabled,MEM_CTRL Memory protection enabled,1
WARNING,PCIE_CTRL,PCIe received TLP CRC error count increasing,PCIE_CTRL PCIe received TLP CRC error count increasing,6
WARNING,FIFO_BUF,FIFO write operation blocked due to full condition,FIFO_BUF FIFO write operation blocked due to full condition,5
CRITICAL,PCIE_CTRL,PCIe root complex link down,PCIE_CTRL PCIe root complex link down,6
WARNING,POWER_CTRL,"Power domain transition delay detected, timing violation.","POWER_CTRL Power domain transition delay detected, timing violation.",4
ERROR,DMA_ENGINE,DMA channel 2 unexpected completion status,DMA_ENGINE DMA channel 2 unexpected completion status,3
WARNING,DDR_CTRL,DDR refresh cycle delayed due to high priority access,DDR_CTRL DDR refresh cycle delayed due to high priority access,1
INFO,MEM_CTRL,Memory controller debug registers cleared,MEM_CTRL Memory controller debug registers cleared,1
ERROR,CACHE_CTRL,Cache dirty bit inconsistency,CACHE_CTRL Cache dirty bit inconsistency,1
INFO,CLOCK_MANAGER,PLL re-locked to target frequency,CLOCK_MANAGER PLL re-locked to target frequency,0
CRITICAL,MEM_CTRL,"Memory controller stuck in arbitration loop, no progress","MEM_CTRL Memory controller stuck in arbitration loop, no progress",1
INFO,FIFO_BUF,FIFO capacity: 256 entries,FIFO_BUF FIFO capacity: 256 entries,5
WARNING,CLOCK_MANAGER,Clock jitter outside permissible range,CLOCK_MANAGER Clock jitter outside permissible range,0
CRITICAL,CLOCK_MANAGER,"Main system clock PLL lost lock, system unstable","CLOCK_MANAGER Main system clock PLL lost lock, system unstable",0
WARNING,DDR_CTRL,DDR command bus busy for extended period,DDR_CTRL DDR command bus busy for extended period,1
WARNING,FIFO_BUF,FIFO almost_empty condition persists,FIFO_BUF FIFO almost_empty condition persists,5
INFO,PCIE_CTRL,PCIe link power management state transition to L1 entered,PCIE_CTRL PCIe link power management state transition to L1 entered,6
CRITICAL,FIFO_BUF,"FIFO deadlock detected, system halt","FIFO_BUF FIFO deadlock detected, system halt",5
WARNING,AXI_CTRL,AXI slave 0x2000 exhibiting increased response latency,AXI_CTRL AXI slave 0x2000 exhibiting increased response latency,2
ERROR,POWER_CTRL,Power rail BIST failure detected,POWER_CTRL Power rail BIST failure detected,-1
WARNING,PCIE_CTRL,"PCIe link training retrying, minor negotiation issue","PCIE_CTRL PCIe link training retrying, minor negotiation issue",6
ERROR,AXI_CTRL,AXI interconnect arbitration failure.,AXI_CTRL AXI interconnect arbitration failure.,2
CRITICAL,MEM_CTRL,"Double bit ECC error detected, memory block unusable","MEM_CTRL Double bit ECC error detected, memory block unusable",1
WARNING,CACHE_CTRL,Cache line replacement algorithm inefficiency detected.,CACHE_CTRL Cache line replacement algorithm inefficiency detected.,1
WARNING,PCIE_CTRL,PCIe link retraining event detected,PCIE_CTRL PCIe link retraining event detected,6
CRITICAL,MEM_CTRL,Memory controller entered unrecoverable error state,MEM_CTRL Memory controller entered unrecoverable error state,1
ERROR,DMA_ENGINE,DMA transfer abort request failed,DMA_ENGINE DMA transfer abort request failed,3
INFO,PCIE_CTRL,PCIe device enumeration complete,PCIE_CTRL PCIe device enumeration complete,6
ERROR,CACHE_CTRL,L1 data cache eviction policy misbehavior,CACHE_CTRL L1 data cache eviction policy misbehavior,1
INFO,DMA_ENGINE,DMA channel reset successful,DMA_ENGINE DMA channel reset successful,3
WARNING,AXI_CTRL,AXI slave not responding to initial handshake,AXI_CTRL AXI slave not responding to initial handshake,2
ERROR,FIFO_BUF,"FIFO_USB_TX overflow detected, data lost","FIFO_BUF FIFO_USB_TX overflow detected, data lost",5
ERROR,INTERRUPT_CTRL,Interrupt controller hardware deadlock detected,INTERRUPT_CTRL Interrupt controller hardware deadlock detected,1
INFO,DMA_ENGINE,DMA channel 1 transfer started with 256-byte bursts,DMA_ENGINE DMA channel 1 transfer started with 256-byte bursts,3
ERROR,FIFO_BUF,FIFO 'cmd_resp' experienced an unexpected write when full,FIFO_BUF FIFO 'cmd_resp' experienced an unexpected write when full,-1
CRITICAL,FIFO_BUF,FIFO control logic completely unresponsive,FIFO_BUF FIFO control logic completely unresponsive,5
ERROR,POWER_CTRL,Power-good signal lost,POWER_CTRL Power-good signal lost,4
CRITICAL,POWER_CTRL,System power-on reset failed,POWER_CTRL System power-on reset failed,4
ERROR,PCIE_CTRL,PCIe device configuration error detected,PCIE_CTRL PCIe device configuration error detected,6
INFO,INTERRUPT_CTRL,Interrupt cleared by software,INTERRUPT_CTRL Interrupt cleared by software,1
INFO,FIFO_BUF,Async FIFO depth configured to 256 entries,FIFO_BUF Async FIFO depth configured to 256 entries,5
WARNING,PCIE_CTRL,PCIe upstream port performance degradation observed,PCIE_CTRL PCIe upstream port performance degradation observed,6
CRITICAL,CACHE_CTRL,Cache RAM data integrity compromised,CACHE_CTRL Cache RAM data integrity compromised,1
WARNING,DDR_CTRL,Memory utilization high,DDR_CTRL Memory utilization high,1
ERROR,DDR_CTRL,DDR controller internal timer overflow,DDR_CTRL DDR controller internal timer overflow,1
WARNING,DDR_CTRL,DDR timing parameter violation detected.,DDR_CTRL DDR timing parameter violation detected.,1
WARNING,PCIE_CTRL,PCIe link training equalization failed,PCIE_CTRL PCIe link training equalization failed,6
ERROR,DMA_ENGINE,DMA channel in unexpected busy state,DMA_ENGINE DMA channel in unexpected busy state,3
ERROR,AXI_CTRL,AXI response channel assertion of SLVERR,AXI_CTRL AXI response channel assertion of SLVERR,2
ERROR,DDR_CTRL,DDR command timing violation: tRP (Row Precharge Time),DDR_CTRL DDR command timing violation: tRP (Row Precharge Time),1
CRITICAL,AXI_CTRL,AXI system-wide bus contention detected,AXI_CTRL AXI system-wide bus contention detected,2
WARNING,AXI_CTRL,AXI slave response delay,AXI_CTRL AXI slave response delay,2
WARNING,PCIE_CTRL,PCIe receiver lane equalization error rate increasing,PCIE_CTRL PCIe receiver lane equalization error rate increasing,6
CRITICAL,CLOCK_MANAGER,"Main system PLL lost lock, clock output unstable","CLOCK_MANAGER Main system PLL lost lock, clock output unstable",0
ERROR,FIFO_BUF,FIFO pointer mismatch after reset,FIFO_BUF FIFO pointer mismatch after reset,5
ERROR,PCIE_CTRL,PCIe device configuration register access error,PCIE_CTRL PCIe device configuration register access error,6
ERROR,DDR_CTRL,DDR memory data strobe (DQS) phase error,DDR_CTRL DDR memory data strobe (DQS) phase error,-1
INFO,DDR_CTRL,DDR memory training in progress,DDR_CTRL DDR memory training in progress,1
WARNING,CACHE_CTRL,Cache invalidation latency high,CACHE_CTRL Cache invalidation latency high,1
ERROR,INTERRUPT_CTRL,"Interrupt acknowledge timeout detected, no response from handler.","INTERRUPT_CTRL Interrupt acknowledge timeout detected, no response from handler.",1
INFO,INTERRUPT_CTRL,Interrupt controller in active state,INTERRUPT_CTRL Interrupt controller in active state,1
INFO,INTERRUPT_CTRL,Interrupt 28 enabled in mask register.,INTERRUPT_CTRL Interrupt 28 enabled in mask register.,1
WARNING,DDR_CTRL,DDR access patterns indicate potential row hammer effect at 0xABCDEF01.,DDR_CTRL DDR access patterns indicate potential row hammer effect at 0xABCDEF01.,-1
WARNING,DMA_ENGINE,DMA destination buffer overflow impending,DMA_ENGINE DMA destination buffer overflow impending,3
WARNING,DMA_ENGINE,DMA engine queue depth for urgent requests is low,DMA_ENGINE DMA engine queue depth for urgent requests is low,3
WARNING,FIFO_BUF,FIFO read latency showing increased variance,FIFO_BUF FIFO read latency showing increased variance,5
INFO,CACHE_CTRL,Cache flush operation successful,CACHE_CTRL Cache flush operation successful,1
INFO,POWER_CTRL,Core voltage rail set to 0.9V,POWER_CTRL Core voltage rail set to 0.9V,4
WARNING,CACHE_CTRL,Cache coherency probe timeout,CACHE_CTRL Cache coherency probe timeout,1
WARNING,AXI_CTRL,"AXI ID re-use detected before response, potential protocol issue.","AXI_CTRL AXI ID re-use detected before response, potential protocol issue.",2
WARNING,CACHE_CTRL,Cache tag RAM access latency exceeding threshold,CACHE_CTRL Cache tag RAM access latency exceeding threshold,1
ERROR,PCIE_CTRL,PCIe transaction timeout for non-posted write,PCIE_CTRL PCIe transaction timeout for non-posted write,6
INFO,PCIE_CTRL,PCIe device hot-reset initiated,PCIE_CTRL PCIe device hot-reset initiated,6
ERROR,POWER_CTRL,System PMU attempted illegal power state transition,POWER_CTRL System PMU attempted illegal power state transition,4
INFO,CLOCK_MANAGER,Clock divider configured.,CLOCK_MANAGER Clock divider configured.,0
ERROR,PCIE_CTRL,PCIe transaction layer detected unsupported request,PCIE_CTRL PCIe transaction layer detected unsupported request,6
WARNING,AXI_CTRL,AXI bus interface showing excessive wait states,AXI_CTRL AXI bus interface showing excessive wait states,2
INFO,FIFO_BUF,Read operation successful,FIFO_BUF Read operation successful,5
INFO,MEM_CTRL,Memory bank 0 refresh cycle completed,MEM_CTRL Memory bank 0 refresh cycle completed,1
INFO,FIFO_BUF,Buffer cleared for new transactions,FIFO_BUF Buffer cleared for new transactions,5
INFO,AXI_CTRL,AXI interface configured for 350MHz.,AXI_CTRL AXI interface configured for 350MHz.,-1
WARNING,CACHE_CTRL,Cache write-buffer utilization high,CACHE_CTRL Cache write-buffer utilization high,1
INFO,FIFO_BUF,FIFO write pointer advanced.,FIFO_BUF FIFO write pointer advanced.,5
INFO,POWER_CTRL,Power state transition completed (P4).,POWER_CTRL Power state transition completed (P4).,4
INFO,AXI_CTRL,AXI handshake sequence completed for read access.,AXI_CTRL AXI handshake sequence completed for read access.,2
CRITICAL,FIFO_BUF,FIFO data integrity validation failed,FIFO_BUF FIFO data integrity validation failed,5
INFO,CACHE_CTRL,Cache line written to L1 with modified state,CACHE_CTRL Cache line written to L1 with modified state,1
INFO,MEM_CTRL,Memory region 0x4000 to 0x4FFF deallocated,MEM_CTRL Memory region 0x4000 to 0x4FFF deallocated,1
WARNING,POWER_CTRL,System temperature exceeding operational limits,POWER_CTRL System temperature exceeding operational limits,4
WARNING,POWER_CTRL,Voltage regulator ripple exceeding specification,POWER_CTRL Voltage regulator ripple exceeding specification,4
ERROR,AXI_CTRL,AXI address decoding error detected for target 0xABCD0000,AXI_CTRL AXI address decoding error detected for target 0xABCD0000,2
INFO,DDR_CTRL,DDR memory frequency locked,DDR_CTRL DDR memory frequency locked,1
CRITICAL,CLOCK_MANAGER,System reset deassertion timing violated,CLOCK_MANAGER System reset deassertion timing violated,0
ERROR,AXI_CTRL,AXI slave 'gpio_block' returned SLVERR on valid transaction,AXI_CTRL AXI slave 'gpio_block' returned SLVERR on valid transaction,2
ERROR,CACHE_CTRL,Cache Way prediction logic output mismatch,CACHE_CTRL Cache Way prediction logic output mismatch,1
WARNING,CACHE_CTRL,Cache tag RAM integrity check showing discrepancies,CACHE_CTRL Cache tag RAM integrity check showing discrepancies,1
WARNING,CLOCK_MANAGER,Clock enable gate input unstable,CLOCK_MANAGER Clock enable gate input unstable,0
INFO,MEM_CTRL,Memory BIST complete with no errors,MEM_CTRL Memory BIST complete with no errors,1
CRITICAL,AXI_CTRL,AXI bridge encountered unrecoverable protocol error.,AXI_CTRL AXI bridge encountered unrecoverable protocol error.,2
INFO,FIFO_BUF,FIFO watermark level configured,FIFO_BUF FIFO watermark level configured,5
INFO,AXI_CTRL,"AWREADY asserted, write address accepted.","AXI_CTRL AWREADY asserted, write address accepted.",-1
INFO,CLOCK_MANAGER,Clock multiplier locked to reference,CLOCK_MANAGER Clock multiplier locked to reference,-1
WARNING,FIFO_BUF,"Output FIFO almost empty, potential underflow","FIFO_BUF Output FIFO almost empty, potential underflow",5
WARNING,INTERRUPT_CTRL,"IRQ line 0 asserted, but no corresponding handler active","INTERRUPT_CTRL IRQ line 0 asserted, but no corresponding handler active",1
ERROR,POWER_CTRL,Voltage brown-out detected on primary rail VDD_MAIN,POWER_CTRL Voltage brown-out detected on primary rail VDD_MAIN,4
INFO,POWER_CTRL,Core rail voltage stable at 1.05V,POWER_CTRL Core rail voltage stable at 1.05V,4
WARNING,FIFO_BUF,FIFO fill level at 85%,FIFO_BUF FIFO fill level at 85%,5
WARNING,FIFO_BUF,FIFO_DEBUG_FIFO nearing maximum configurable depth.,FIFO_BUF FIFO_DEBUG_FIFO nearing maximum configurable depth.,5
INFO,DDR_CTRL,"DDR read data valid, operation successful","DDR_CTRL DDR read data valid, operation successful",1
CRITICAL,CLOCK_MANAGER,Clock synthesizer frequency drift exceeding tolerance,CLOCK_MANAGER Clock synthesizer frequency drift exceeding tolerance,0
CRITICAL,MEM_CTRL,Memory controller entered a non-recoverable debug state,MEM_CTRL Memory controller entered a non-recoverable debug state,1
CRITICAL,CLOCK_MANAGER,Clock generation hardware failure,CLOCK_MANAGER Clock generation hardware failure,0
CRITICAL,AXI_CTRL,AXI bridge detected unrecoverable protocol violation,AXI_CTRL AXI bridge detected unrecoverable protocol violation,2
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal not received from processor,INTERRUPT_CTRL Interrupt acknowledge signal not received from processor,1
WARNING,INTERRUPT_CTRL,Priority level change detected,INTERRUPT_CTRL Priority level change detected,1
INFO,CLOCK_MANAGER,Clock domain crossing bridge initialized,CLOCK_MANAGER Clock domain crossing bridge initialized,0
INFO,FIFO_BUF,FIFO data available count: 12,FIFO_BUF FIFO data available count: 12,5
INFO,CLOCK_MANAGER,Clock output verified on all active paths.,CLOCK_MANAGER Clock output verified on all active paths.,0
WARNING,INTERRUPT_CTRL,INTERRUPT_CTRL observed higher than expected transaction latency (TxID: 247).,INTERRUPT_CTRL INTERRUPT_CTRL observed higher than expected transaction latency (TxID: 247).,1
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on data path,CLOCK_MANAGER Clock domain crossing synchronization failure on data path,0
INFO,INTERRUPT_CTRL,Interrupt threshold configured,INTERRUPT_CTRL Interrupt threshold configured,1
WARNING,PCIE_CTRL,PCIe link retraining initiated due to correctable errors.,PCIE_CTRL PCIe link retraining initiated due to correctable errors.,6
WARNING,CLOCK_MANAGER,Clock MUX selection instability detected,CLOCK_MANAGER Clock MUX selection instability detected,0
ERROR,MEM_CTRL,Memory controller internal FSM error,MEM_CTRL Memory controller internal FSM error,1
WARNING,PCIE_CTRL,PCIe link bandwidth utilization approaching 90%,PCIE_CTRL PCIe link bandwidth utilization approaching 90%,6
ERROR,DMA_ENGINE,DMA channel deadlock detected.,DMA_ENGINE DMA channel deadlock detected.,3
INFO,CLOCK_MANAGER,PLL locked successfully.,CLOCK_MANAGER PLL locked successfully.,0
WARNING,POWER_CTRL,Power consumption exceeding budgeted threshold.,POWER_CTRL Power consumption exceeding budgeted threshold.,4
WARNING,MEM_CTRL,Memory controller pending write queue backlog,MEM_CTRL Memory controller pending write queue backlog,1
WARNING,DDR_CTRL,DDR read data burst truncation,DDR_CTRL DDR read data burst truncation,1
CRITICAL,PCIE_CTRL,"PCIe fatal error detected, link down","PCIE_CTRL PCIe fatal error detected, link down",6
ERROR,AXI_CTRL,AXI transaction ID mismatch,AXI_CTRL AXI transaction ID mismatch,2
ERROR,CACHE_CTRL,Cache tag parity error in way 2,CACHE_CTRL Cache tag parity error in way 2,1
INFO,DDR_CTRL,DDR command queue cleared.,DDR_CTRL DDR command queue cleared.,1
INFO,DDR_CTRL,Power-up sequence finished,DDR_CTRL Power-up sequence finished,1
ERROR,POWER_CTRL,POWER_CTRL: invalid state transition - FSM entered illegal state detected.,POWER_CTRL POWER_CTRL: invalid state transition - FSM entered illegal state detected.,4
INFO,DMA_ENGINE,DMA channel 3 configured for peripheral transfer,DMA_ENGINE DMA channel 3 configured for peripheral transfer,3
CRITICAL,POWER_CTRL,"System power failure, immediate shutdown.","POWER_CTRL System power failure, immediate shutdown.",4
ERROR,AXI_CTRL,AXI outstanding transaction limit exceeded by master,AXI_CTRL AXI outstanding transaction limit exceeded by master,2
WARNING,POWER_CTRL,"Temperature sensor reading high, overheating risk.","POWER_CTRL Temperature sensor reading high, overheating risk.",4
INFO,CACHE_CTRL,Data path reset for CACHE_CTRL completed.,CACHE_CTRL Data path reset for CACHE_CTRL completed.,1
CRITICAL,DMA_ENGINE,DMA master port unrecoverable error.,DMA_ENGINE DMA master port unrecoverable error.,3
WARNING,MEM_CTRL,Memory access to page 0x1000 consistently misses in cache.,MEM_CTRL Memory access to page 0x1000 consistently misses in cache.,1
ERROR,DMA_ENGINE,DMA engine 'AUDIO' encountered an unrecoverable descriptor fault.,DMA_ENGINE DMA engine 'AUDIO' encountered an unrecoverable descriptor fault.,3
CRITICAL,DDR_CTRL,"DDR memory interface clock integrity lost, severe clock domain crossing failure.","DDR_CTRL DDR memory interface clock integrity lost, severe clock domain crossing failure.",1
ERROR,DDR_CTRL,DDR command timing violation detected for WRITE command to bank 1,DDR_CTRL DDR command timing violation detected for WRITE command to bank 1,1
INFO,AXI_CTRL,AXI read burst from 'flash_controller' completed,AXI_CTRL AXI read burst from 'flash_controller' completed,2
CRITICAL,PCIE_CTRL,PCIe configuration space read returned all F's for critical register,PCIE_CTRL PCIe configuration space read returned all F's for critical register,6
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL entered idle state.,INTERRUPT_CTRL INTERRUPT_CTRL entered idle state.,-1
ERROR,DMA_ENGINE,DMA request line stuck high,DMA_ENGINE DMA request line stuck high,3
INFO,PCIE_CTRL,PCIe vendor ID read successful,PCIE_CTRL PCIe vendor ID read successful,6
INFO,FIFO_BUF,"Data written to FIFO buffer, current fill level 50%","FIFO_BUF Data written to FIFO buffer, current fill level 50%",5
ERROR,PCIE_CTRL,PCIe endpoint received malformed TLP header,PCIE_CTRL PCIe endpoint received malformed TLP header,6
INFO,INTERRUPT_CTRL,All pending interrupts cleared.,INTERRUPT_CTRL All pending interrupts cleared.,1
WARNING,CLOCK_MANAGER,System clock source switching delay detected,CLOCK_MANAGER System clock source switching delay detected,0
CRITICAL,POWER_CTRL,Power rail instability detected on VDD_DDR,POWER_CTRL Power rail instability detected on VDD_DDR,4
INFO,DMA_ENGINE,DMA channel 13 configured with priority,DMA_ENGINE DMA channel 13 configured with priority,3
INFO,POWER_CTRL,Rail voltage check passed for all domains,POWER_CTRL Rail voltage check passed for all domains,-1
ERROR,CLOCK_MANAGER,PLL feedback path error,CLOCK_MANAGER PLL feedback path error,0
CRITICAL,INTERRUPT_CTRL,Critical interrupt handling failure,INTERRUPT_CTRL Critical interrupt handling failure,1
WARNING,AXI_CTRL,AR channel bandwidth nearing saturation,AXI_CTRL AR channel bandwidth nearing saturation,-1
WARNING,PCIE_CTRL,"PCIe unexpected completion received, protocol mismatch.","PCIE_CTRL PCIe unexpected completion received, protocol mismatch.",6
CRITICAL,POWER_CTRL,System power supply rail collapse detected,POWER_CTRL System power supply rail collapse detected,4
ERROR,CACHE_CTRL,Cache line state machine invalid transition,CACHE_CTRL Cache line state machine invalid transition,1
CRITICAL,POWER_CTRL,Critical power rail voltage drop,POWER_CTRL Critical power rail voltage drop,4
ERROR,CACHE_CTRL,Cache way predictor error,CACHE_CTRL Cache way predictor error,1
ERROR,CACHE_CTRL,L2 cache controller hit/miss logic inconsistency,CACHE_CTRL L2 cache controller hit/miss logic inconsistency,1
WARNING,AXI_CTRL,AXI outstanding transaction count for read channel at 95%,AXI_CTRL AXI outstanding transaction count for read channel at 95%,2
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range (128ps between DDR_CLK and SYS_CLK).,CLOCK_MANAGER Clock skew approaching unsafe range (128ps between DDR_CLK and SYS_CLK).,0
INFO,PCIE_CTRL,PCIe endpoint enumerated,PCIE_CTRL PCIe endpoint enumerated,6
ERROR,CACHE_CTRL,Cache refill operation timed out,CACHE_CTRL Cache refill operation timed out,1
CRITICAL,PCIE_CTRL,PCIe fatal error detected by upstream device,PCIE_CTRL PCIe fatal error detected by upstream device,6
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance on high-speed interface,CLOCK_MANAGER Clock jitter exceeding tolerance on high-speed interface,0
INFO,DDR_CTRL,DDR controller enters low power state,DDR_CTRL DDR controller enters low power state,1
ERROR,PCIE_CTRL,PCIe transaction layer packet (TLP) error,PCIE_CTRL PCIe transaction layer packet (TLP) error,6
WARNING,PCIE_CTRL,PCIe completion without data received,PCIE_CTRL PCIe completion without data received,6
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold of 395 cycles,FIFO_BUF FIFO latency exceeding expected threshold of 395 cycles,5
WARNING,POWER_CTRL,Power rail current draw exceeding average,POWER_CTRL Power rail current draw exceeding average,4
CRITICAL,MEM_CTRL,"Memory controller response to read request timeout, system hung","MEM_CTRL Memory controller response to read request timeout, system hung",1
ERROR,FIFO_BUF,FIFO synchronization error detected on read_clock.,FIFO_BUF FIFO synchronization error detected on read_clock.,5
INFO,FIFO_BUF,FIFO status register polled,FIFO_BUF FIFO status register polled,5
INFO,CLOCK_MANAGER,External clock source validation passed,CLOCK_MANAGER External clock source validation passed,-1
WARNING,MEM_CTRL,Memory burst access incomplete,MEM_CTRL Memory burst access incomplete,1
WARNING,POWER_CTRL,Voltage regulator slew rate too slow,POWER_CTRL Voltage regulator slew rate too slow,4
WARNING,DMA_ENGINE,DMA channel 12 transfer size exceeds optimal burst length.,DMA_ENGINE DMA channel 12 transfer size exceeds optimal burst length.,3
ERROR,CACHE_CTRL,Cache tag RAM uninitialized access,CACHE_CTRL Cache tag RAM uninitialized access,1
INFO,MEM_CTRL,Memory block 0x100000 to 0x1FFFFF successfully accessed,MEM_CTRL Memory block 0x100000 to 0x1FFFFF successfully accessed,1
CRITICAL,POWER_CTRL,System power rail voltage dropped below brown-out threshold,POWER_CTRL System power rail voltage dropped below brown-out threshold,4
ERROR,DMA_ENGINE,DMA transfer timeout due to stalled peripheral,DMA_ENGINE DMA transfer timeout due to stalled peripheral,3
WARNING,CACHE_CTRL,Cache dirty line count exceeding threshold,CACHE_CTRL Cache dirty line count exceeding threshold,1
ERROR,INTERRUPT_CTRL,"Interrupt handler address invalid, memory alignment fault.","INTERRUPT_CTRL Interrupt handler address invalid, memory alignment fault.",1
INFO,DDR_CTRL,DDR precharge command issued,DDR_CTRL DDR precharge command issued,1
INFO,DDR_CTRL,DDR memory controller reset asserted,DDR_CTRL DDR memory controller reset asserted,1
ERROR,PCIE_CTRL,PCIe completion timeout detected.,PCIE_CTRL PCIe completion timeout detected.,6
WARNING,FIFO_BUF,"FIFO almost full, asserting flow control","FIFO_BUF FIFO almost full, asserting flow control",5
INFO,MEM_CTRL,Memory BIST (Built-In Self-Test) completed,MEM_CTRL Memory BIST (Built-In Self-Test) completed,1
INFO,DMA_ENGINE,DMA configuration for channel 1 updated,DMA_ENGINE DMA configuration for channel 1 updated,3
WARNING,AXI_CTRL,AXI bus contention detected on shared resource.,AXI_CTRL AXI bus contention detected on shared resource.,2
INFO,AXI_CTRL,AXI write burst with all data bytes completed,AXI_CTRL AXI write burst with all data bytes completed,2
CRITICAL,MEM_CTRL,Memory access violation from untrusted source,MEM_CTRL Memory access violation from untrusted source,1
ERROR,DMA_ENGINE,DMA channel 6 loopback test failed,DMA_ENGINE DMA channel 6 loopback test failed,3
INFO,CLOCK_MANAGER,Clock frequency verified to be 100MHz,CLOCK_MANAGER Clock frequency verified to be 100MHz,0
INFO,PCIE_CTRL,PCIe link established successfully (Gen3).,PCIE_CTRL PCIe link established successfully (Gen3).,6
ERROR,DMA_ENGINE,DMA channel 8 configuration register written with invalid value,DMA_ENGINE DMA channel 8 configuration register written with invalid value,3
ERROR,PCIE_CTRL,"PCIe link training failure, unable to achieve Gen3 speeds","PCIE_CTRL PCIe link training failure, unable to achieve Gen3 speeds",6
CRITICAL,POWER_CTRL,System power rail 'VCC_MAIN' detected critical instability,POWER_CTRL System power rail 'VCC_MAIN' detected critical instability,4
ERROR,DMA_ENGINE,DMA transfer completion timeout for channel 1,DMA_ENGINE DMA transfer completion timeout for channel 1,3
INFO,CACHE_CTRL,Cache line 0xABCDEF evicted to main memory,CACHE_CTRL Cache line 0xABCDEF evicted to main memory,1
WARNING,AXI_CTRL,AXI arbitration grant delay exceeding threshold,AXI_CTRL AXI arbitration grant delay exceeding threshold,2
WARNING,CLOCK_MANAGER,Clock distribution network voltage margin degraded,CLOCK_MANAGER Clock distribution network voltage margin degraded,-1
ERROR,PCIE_CTRL,PCIe hot-reset assertion failed,PCIE_CTRL PCIe hot-reset assertion failed,6
INFO,CLOCK_MANAGER,Clock frequency configured to 1000 MHz.,CLOCK_MANAGER Clock frequency configured to 1000 MHz.,0
ERROR,DMA_ENGINE,DMA channel configuration locked,DMA_ENGINE DMA channel configuration locked,3
WARNING,AXI_CTRL,AXI outstanding transactions count nearing limit (10).,AXI_CTRL AXI outstanding transactions count nearing limit (10).,2
ERROR,CACHE_CTRL,Cache coherence violation: dirty data not written back,CACHE_CTRL Cache coherence violation: dirty data not written back,1
ERROR,AXI_CTRL,AXI write response channel RRESP error detected,AXI_CTRL AXI write response channel RRESP error detected,2
ERROR,AXI_CTRL,AXI data phase error on write.,AXI_CTRL AXI data phase error on write.,2
INFO,DDR_CTRL,DDR refresh interval reconfigured,DDR_CTRL DDR refresh interval reconfigured,1
WARNING,PCIE_CTRL,PCIe received unexpected completion with poison,PCIE_CTRL PCIe received unexpected completion with poison,6
ERROR,CLOCK_MANAGER,"Clock domain crossing data path ""path_A_B"" reported synchronization failure.","CLOCK_MANAGER Clock domain crossing data path ""path_A_B"" reported synchronization failure.",0
INFO,DMA_ENGINE,DMA channel 4 transfer request acknowledged,DMA_ENGINE DMA channel 4 transfer request acknowledged,3
CRITICAL,POWER_CTRL,Power rail instability detected (critical),POWER_CTRL Power rail instability detected (critical),4
CRITICAL,CLOCK_MANAGER,Phase-locked loop (PLL) jitter exceeding specification,CLOCK_MANAGER Phase-locked loop (PLL) jitter exceeding specification,0
ERROR,MEM_CTRL,Memory protection unit access violation,MEM_CTRL Memory protection unit access violation,1
WARNING,CACHE_CTRL,Cache invalidation queue growing,CACHE_CTRL Cache invalidation queue growing,1
INFO,INTERRUPT_CTRL,Non-maskable interrupt (NMI) handled,INTERRUPT_CTRL Non-maskable interrupt (NMI) handled,1
WARNING,CLOCK_MANAGER,Clock domain crossing path showing excessive setup time violations,CLOCK_MANAGER Clock domain crossing path showing excessive setup time violations,0
WARNING,DDR_CTRL,DDR command queue depth approaching full,DDR_CTRL DDR command queue depth approaching full,1
ERROR,DMA_ENGINE,DMA descriptor checksum mismatch detected,DMA_ENGINE DMA descriptor checksum mismatch detected,3
WARNING,AXI_CTRL,Write data channel stalled,AXI_CTRL Write data channel stalled,2
CRITICAL,CLOCK_MANAGER,Clock gating logic failure leading to clock domain shutdown,CLOCK_MANAGER Clock gating logic failure leading to clock domain shutdown,0
INFO,PCIE_CTRL,PCIe Root Port hot reset asserted,PCIE_CTRL PCIe Root Port hot reset asserted,6
INFO,FIFO_BUF,"FIFO write operation completed, current occupancy: 12","FIFO_BUF FIFO write operation completed, current occupancy: 12",5
INFO,POWER_CTRL,Dynamic Voltage Frequency Scaling (DVFS) level updated,POWER_CTRL Dynamic Voltage Frequency Scaling (DVFS) level updated,9
ERROR,CLOCK_MANAGER,Clock integrity check failed on secondary clock,CLOCK_MANAGER Clock integrity check failed on secondary clock,0
WARNING,DMA_ENGINE,DMA descriptor chain nearing end.,DMA_ENGINE DMA descriptor chain nearing end.,3
WARNING,DDR_CTRL,DDR controller refresh logic not active,DDR_CTRL DDR controller refresh logic not active,1
INFO,CLOCK_MANAGER,Frequency scaled down,CLOCK_MANAGER Frequency scaled down,0
CRITICAL,PCIE_CTRL,"PCIe physical layer error rate too high, link unstable","PCIE_CTRL PCIe physical layer error rate too high, link unstable",6
INFO,DMA_ENGINE,DMA channel 5 transfer aborted by user,DMA_ENGINE DMA channel 5 transfer aborted by user,3
INFO,POWER_CTRL,Power state D0 entered for CPU core,POWER_CTRL Power state D0 entered for CPU core,4
WARNING,DMA_ENGINE,"DMA queue nearing saturation, channel preemption active","DMA_ENGINE DMA queue nearing saturation, channel preemption active",3
ERROR,AXI_CTRL,AXI `AWREADY` asserted without `AWVALID` being set,AXI_CTRL AXI `AWREADY` asserted without `AWVALID` being set,2
WARNING,AXI_CTRL,AXI read address channel backpressure detected,AXI_CTRL AXI read address channel backpressure detected,2
WARNING,FIFO_BUF,"FIFO almost empty, read pointer approaching write pointer","FIFO_BUF FIFO almost empty, read pointer approaching write pointer",5
WARNING,MEM_CTRL,Memory read latency exceeding system performance budget.,MEM_CTRL Memory read latency exceeding system performance budget.,1
INFO,POWER_CTRL,Current consumption within limits,POWER_CTRL Current consumption within limits,4
CRITICAL,PCIE_CTRL,PCIe data link layer (DLL) state machine error,PCIE_CTRL PCIe data link layer (DLL) state machine error,6
CRITICAL,DDR_CTRL,"DDR PLL lock lost, memory clock unstable (PLL_DDR)","DDR_CTRL DDR PLL lock lost, memory clock unstable (PLL_DDR)",1
INFO,DMA_ENGINE,DMA transfer of 4KB completed successfully for channel 0.,DMA_ENGINE DMA transfer of 4KB completed successfully for channel 0.,3
ERROR,CLOCK_MANAGER,Clock distribution network error for clock Core.,CLOCK_MANAGER Clock distribution network error for clock Core.,0
INFO,CLOCK_MANAGER,Clock gate enable for module AXI_CTRL asserted,CLOCK_MANAGER Clock gate enable for module AXI_CTRL asserted,0
INFO,AXI_CTRL,AXI write completion received,AXI_CTRL AXI write completion received,2
WARNING,FIFO_BUF,FIFO read pointer lagging too far behind write pointer,FIFO_BUF FIFO read pointer lagging too far behind write pointer,5
ERROR,DDR_CTRL,Training sequence failed,DDR_CTRL Training sequence failed,1
ERROR,INTERRUPT_CTRL,External interrupt line spurious assertion,INTERRUPT_CTRL External interrupt line spurious assertion,1
WARNING,INTERRUPT_CTRL,Interrupt queue approaching limit.,INTERRUPT_CTRL Interrupt queue approaching limit.,1
INFO,DMA_ENGINE,DMA transfer to memory completed without error,DMA_ENGINE DMA transfer to memory completed without error,3
INFO,MEM_CTRL,Memory BIST (Built-In Self Test) completed successfully,MEM_CTRL Memory BIST (Built-In Self Test) completed successfully,1
WARNING,CACHE_CTRL,Cache write-back buffer utilization high (at 90%).,CACHE_CTRL Cache write-back buffer utilization high (at 90%).,1
CRITICAL,CACHE_CTRL,"Critical cache ways corrupted, disabling cache","CACHE_CTRL Critical cache ways corrupted, disabling cache",1
WARNING,INTERRUPT_CTRL,Pending interrupt queue approaching capacity,INTERRUPT_CTRL Pending interrupt queue approaching capacity,1
INFO,AXI_CTRL,AXI write transaction completed,AXI_CTRL AXI write transaction completed,2
ERROR,PCIE_CTRL,PCIE_CTRL: deadlock detected - resource contention deadlock detected.,PCIE_CTRL PCIE_CTRL: deadlock detected - resource contention deadlock detected.,6
ERROR,POWER_CTRL,Power-on sequence failed to meet timing constraints,POWER_CTRL Power-on sequence failed to meet timing constraints,4
WARNING,INTERRUPT_CTRL,Interrupt controller internal registers showing inconsistent values,INTERRUPT_CTRL Interrupt controller internal registers showing inconsistent values,1
CRITICAL,PCIE_CTRL,PCIe transaction layer flow control error,PCIE_CTRL PCIe transaction layer flow control error,6
ERROR,PCIE_CTRL,PCIe upstream/downstream buffer overflow,PCIE_CTRL PCIe upstream/downstream buffer overflow,6
INFO,PCIE_CTRL,"PCIe training sequence completed, 2.5 GT/s link established","PCIE_CTRL PCIe training sequence completed, 2.5 GT/s link established",6
ERROR,DDR_CTRL,DDR memory 'DIMM_A' reported thermal warning,DDR_CTRL DDR memory 'DIMM_A' reported thermal warning,1
WARNING,PCIE_CTRL,PCIe hot-reset requested but not acknowledged,PCIE_CTRL PCIe hot-reset requested but not acknowledged,6
CRITICAL,MEM_CTRL,Address translation unit (ATU) deadlock,MEM_CTRL Address translation unit (ATU) deadlock,1
WARNING,DDR_CTRL,DDR memory access patterns are sub-optimal,DDR_CTRL DDR memory access patterns are sub-optimal,1
INFO,MEM_CTRL,Memory controller in normal operating mode,MEM_CTRL Memory controller in normal operating mode,1
CRITICAL,DDR_CTRL,DDR memory controller internal arbitration deadlock,DDR_CTRL DDR memory controller internal arbitration deadlock,1
ERROR,CLOCK_MANAGER,Clock enable glitch detected,CLOCK_MANAGER Clock enable glitch detected,0
CRITICAL,DDR_CTRL,DDR memory training detected unrecoverable setup/hold violation,DDR_CTRL DDR memory training detected unrecoverable setup/hold violation,1
CRITICAL,FIFO_BUF,CRITICAL: FIFO full/empty logic failure leading to system stall.,FIFO_BUF CRITICAL: FIFO full/empty logic failure leading to system stall.,5
CRITICAL,MEM_CTRL,Memory management unit protection violation,MEM_CTRL Memory management unit protection violation,1
CRITICAL,POWER_CTRL,"Power management unit entered invalid state, uncontrolled power rails","POWER_CTRL Power management unit entered invalid state, uncontrolled power rails",4
INFO,DMA_ENGINE,DMA channel 5 configuration updated.,DMA_ENGINE DMA channel 5 configuration updated.,3
INFO,POWER_CTRL,Power state transition completed,POWER_CTRL Power state transition completed,4
WARNING,DMA_ENGINE,DMA engine unable to obtain bus mastership for prolonged period,DMA_ENGINE DMA engine unable to obtain bus mastership for prolonged period,3
ERROR,DDR_CTRL,"DDR_CTRL control logic stalled due to timing violation (asynchronous path timing error). (Command: WRITE, Bank: 0)","DDR_CTRL DDR_CTRL control logic stalled due to timing violation (asynchronous path timing error). (Command: WRITE, Bank: 0)",1
INFO,DMA_ENGINE,DMA transfer progress: 75%,DMA_ENGINE DMA transfer progress: 75%,3
WARNING,INTERRUPT_CTRL,Interrupt controller internal buffer almost full.,INTERRUPT_CTRL Interrupt controller internal buffer almost full.,1
INFO,INTERRUPT_CTRL,Interrupt mask updated,INTERRUPT_CTRL Interrupt mask updated,1
ERROR,DDR_CTRL,DDR multi-rank access contention detected,DDR_CTRL DDR multi-rank access contention detected,-1
CRITICAL,AXI_CTRL,"AXI system watchdog timeout, system halt initiated.","AXI_CTRL AXI system watchdog timeout, system halt initiated.",2
ERROR,AXI_CTRL,AXI write address channel (AW) transaction timeout,AXI_CTRL AXI write address channel (AW) transaction timeout,2
INFO,FIFO_BUF,FIFO 'video_frames' reset to empty,FIFO_BUF FIFO 'video_frames' reset to empty,-1
ERROR,CACHE_CTRL,Cache Way D access violation,CACHE_CTRL Cache Way D access violation,1
ERROR,DMA_ENGINE,DMA channel access violation to protected memory region,DMA_ENGINE DMA channel access violation to protected memory region,3
ERROR,CACHE_CTRL,Cache line invalidation sequence failed,CACHE_CTRL Cache line invalidation sequence failed,1
ERROR,AXI_CTRL,AXI master attempted write to read-only register,AXI_CTRL AXI master attempted write to read-only register,2
CRITICAL,PCIE_CTRL,PCIe PHY layer reported unrecoverable lane degradation,PCIE_CTRL PCIe PHY layer reported unrecoverable lane degradation,6
WARNING,AXI_CTRL,AXI master requesting too many outstanding transactions,AXI_CTRL AXI master requesting too many outstanding transactions,2
ERROR,FIFO_BUF,FIFO write data dropped due to full status,FIFO_BUF FIFO write data dropped due to full status,5
INFO,DDR_CTRL,DDR frequency switched from 800MHz to 1066MHz,DDR_CTRL DDR frequency switched from 800MHz to 1066MHz,1
CRITICAL,MEM_CTRL,Memory controller internal FSM entered an illegal state.,MEM_CTRL Memory controller internal FSM entered an illegal state.,1
INFO,PCIE_CTRL,PCIe link width successfully negotiated to x8,PCIE_CTRL PCIe link width successfully negotiated to x8,6
ERROR,CACHE_CTRL,L1 data cache parity error,CACHE_CTRL L1 data cache parity error,1
WARNING,AXI_CTRL,AXI handshake delay approaching threshold (41 cycles).,AXI_CTRL AXI handshake delay approaching threshold (41 cycles).,2
INFO,AXI_CTRL,AXI transaction timeout parameter updated to 1000 cycles,AXI_CTRL AXI transaction timeout parameter updated to 1000 cycles,2
WARNING,INTERRUPT_CTRL,Interrupt controller register access timeout,INTERRUPT_CTRL Interrupt controller register access timeout,1
CRITICAL,AXI_CTRL,AXI transaction timeout on critical control path,AXI_CTRL AXI transaction timeout on critical control path,2
WARNING,AXI_CTRL,AXI RDATA channel idle time prolonged,AXI_CTRL AXI RDATA channel idle time prolonged,2
WARNING,DDR_CTRL,DDR refresh command queue length high,DDR_CTRL DDR refresh command queue length high,1
CRITICAL,POWER_CTRL,Over-temperature shutdown initiated due to thermal runaway,POWER_CTRL Over-temperature shutdown initiated due to thermal runaway,4
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal state machine failure,INTERRUPT_CTRL Interrupt controller internal state machine failure,1
WARNING,CLOCK_MANAGER,Clock jitter peak-to-peak amplitude increased,CLOCK_MANAGER Clock jitter peak-to-peak amplitude increased,0
WARNING,CLOCK_MANAGER,Clock tree synthesis warning: high fanout net,CLOCK_MANAGER Clock tree synthesis warning: high fanout net,0
ERROR,AXI_CTRL,AXI response channel handshake timing violation,AXI_CTRL AXI response channel handshake timing violation,2
CRITICAL,POWER_CTRL,Critical power management unit fault,POWER_CTRL Critical power management unit fault,4
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal logic parity error,INTERRUPT_CTRL Interrupt controller internal logic parity error,1
ERROR,FIFO_BUF,FIFO_BUF: buffer underflow - insufficient data in buffer detected. (FIFO 'FIFO_BUF' Depth: 213),FIFO_BUF FIFO_BUF: buffer underflow - insufficient data in buffer detected. (FIFO 'FIFO_BUF' Depth: 213),5
WARNING,CLOCK_MANAGER,Frequency scaling operation delayed,CLOCK_MANAGER Frequency scaling operation delayed,0
ERROR,POWER_CTRL,Power domain VDD_PCIE failed to stabilize,POWER_CTRL Power domain VDD_PCIE failed to stabilize,4
WARNING,FIFO_BUF,Input FIFO latency exceeding expected threshold,FIFO_BUF Input FIFO latency exceeding expected threshold,5
INFO,CACHE_CTRL,Cache hit rate statistics logged,CACHE_CTRL Cache hit rate statistics logged,1
ERROR,MEM_CTRL,Memory controller read data CRC error,MEM_CTRL Memory controller read data CRC error,1
WARNING,DDR_CTRL,DDR chip select signal glitch observed,DDR_CTRL DDR chip select signal glitch observed,8
CRITICAL,AXI_CTRL,Global AXI bus corruption detected,AXI_CTRL Global AXI bus corruption detected,2
CRITICAL,PCIE_CTRL,PCIe link state machine stuck in 'Detect' state,PCIE_CTRL PCIe link state machine stuck in 'Detect' state,6
ERROR,CACHE_CTRL,Cache line state corruption detected for address 0x10001000.,CACHE_CTRL Cache line state corruption detected for address 0x10001000.,1
ERROR,DDR_CTRL,Memory address alignment fault for 64-bit access at 0x10000004.,DDR_CTRL Memory address alignment fault for 64-bit access at 0x10000004.,1
ERROR,CLOCK_MANAGER,Clock gate logic output unstable,CLOCK_MANAGER Clock gate logic output unstable,0
CRITICAL,DDR_CTRL,DDR memory training sequence failed at write leveling,DDR_CTRL DDR memory training sequence failed at write leveling,1
INFO,INTERRUPT_CTRL,Interrupt service routine started for ID 12,INTERRUPT_CTRL Interrupt service routine started for ID 12,1
ERROR,CLOCK_MANAGER,CDC metastability detected,CLOCK_MANAGER CDC metastability detected,0
CRITICAL,MEM_CTRL,"Memory controller arbiter stuck, preventing all access","MEM_CTRL Memory controller arbiter stuck, preventing all access",1
INFO,DMA_ENGINE,DMA channel 2 configured for burst transfer.,DMA_ENGINE DMA channel 2 configured for burst transfer.,3
ERROR,PCIE_CTRL,"PCIe flow control credits exhausted, prolonged stall","PCIE_CTRL PCIe flow control credits exhausted, prolonged stall",6
WARNING,FIFO_BUF,FIFO data path congestion,FIFO_BUF FIFO data path congestion,-1
ERROR,CACHE_CTRL,Cache block lookup failed due to invalid tag hash,CACHE_CTRL Cache block lookup failed due to invalid tag hash,1
INFO,FIFO_BUF,FIFO fill level at 25%,FIFO_BUF FIFO fill level at 25%,5
INFO,CACHE_CTRL,Cache write-allocate policy active,CACHE_CTRL Cache write-allocate policy active,1
CRITICAL,MEM_CTRL,Memory controller test mode entered invalid state,MEM_CTRL Memory controller test mode entered invalid state,1
ERROR,DMA_ENGINE,DMA channel access violation,DMA_ENGINE DMA channel access violation,3
CRITICAL,PCIE_CTRL,PCIe link partner detected fatal error,PCIE_CTRL PCIe link partner detected fatal error,6
INFO,CACHE_CTRL,Cache line writeback completed for address 0x1234ABCD,CACHE_CTRL Cache line writeback completed for address 0x1234ABCD,1
INFO,CLOCK_MANAGER,System clock source switched to internal PLL,CLOCK_MANAGER System clock source switched to internal PLL,0
WARNING,INTERRUPT_CTRL,Excessive interrupt rate detected,INTERRUPT_CTRL Excessive interrupt rate detected,1
CRITICAL,POWER_CTRL,"Brownout detected on VDD_FPGA rail, unexpected shutdown","POWER_CTRL Brownout detected on VDD_FPGA rail, unexpected shutdown",4
WARNING,CACHE_CTRL,L1 instruction cache eviction rate increased,CACHE_CTRL L1 instruction cache eviction rate increased,1
WARNING,POWER_CTRL,Power domain X voltage droop observed,POWER_CTRL Power domain X voltage droop observed,4
INFO,INTERRUPT_CTRL,Software interrupt service routine invoked,INTERRUPT_CTRL Software interrupt service routine invoked,1
WARNING,MEM_CTRL,Bank conflict rate exceeding expected threshold,MEM_CTRL Bank conflict rate exceeding expected threshold,-1
WARNING,CLOCK_MANAGER,Clock domain crossing 'axi_clk_to_sys_clk' bridge utilization high,CLOCK_MANAGER Clock domain crossing 'axi_clk_to_sys_clk' bridge utilization high,-1
ERROR,FIFO_BUF,FIFO write to full buffer without full status,FIFO_BUF FIFO write to full buffer without full status,5
WARNING,AXI_CTRL,AXI_CTRL resource allocation nearing limit (96% utilized).,AXI_CTRL AXI_CTRL resource allocation nearing limit (96% utilized).,2
ERROR,CLOCK_MANAGER,Clock domain crossing bridge data loss,CLOCK_MANAGER Clock domain crossing bridge data loss,0
ERROR,PCIE_CTRL,PCIe physical layer reported lane deskew error,PCIE_CTRL PCIe physical layer reported lane deskew error,6
INFO,CACHE_CTRL,Cache line hit rate statistics reset,CACHE_CTRL Cache line hit rate statistics reset,1
WARNING,FIFO_BUF,Write access to FIFO stalled by full condition,FIFO_BUF Write access to FIFO stalled by full condition,5
WARNING,CLOCK_MANAGER,Clock domain crossing buffer latency significantly high,CLOCK_MANAGER Clock domain crossing buffer latency significantly high,0
INFO,FIFO_BUF,FIFO empty flag asserted correctly after last read,FIFO_BUF FIFO empty flag asserted correctly after last read,5
WARNING,INTERRUPT_CTRL,Global interrupt disable active for extended duration,INTERRUPT_CTRL Global interrupt disable active for extended duration,1
INFO,DMA_ENGINE,DMA channel 0 configured for scatter-gather,DMA_ENGINE DMA channel 0 configured for scatter-gather,3
WARNING,PCIE_CTRL,PCIe link state change to L2 failed,PCIE_CTRL PCIe link state change to L2 failed,6
ERROR,DDR_CTRL,Memory rank initialization failure,DDR_CTRL Memory rank initialization failure,1
CRITICAL,DDR_CTRL,Fatal DDR command queue deadlock,DDR_CTRL Fatal DDR command queue deadlock,1
ERROR,MEM_CTRL,Memory controller internal state machine entered invalid configuration,MEM_CTRL Memory controller internal state machine entered invalid configuration,1
WARNING,FIFO_BUF,FIFO buffer usage nearing high watermark (90%),FIFO_BUF FIFO buffer usage nearing high watermark (90%),5
ERROR,POWER_CTRL,System thermal sensor tripped,POWER_CTRL System thermal sensor tripped,4
WARNING,AXI_CTRL,AXI outstanding read transactions nearing limit,AXI_CTRL AXI outstanding read transactions nearing limit,2
ERROR,FIFO_BUF,FIFO 'command_fifo' write pointer corruption detected,FIFO_BUF FIFO 'command_fifo' write pointer corruption detected,5
CRITICAL,DDR_CTRL,DDR memory controller deadlock.,DDR_CTRL DDR memory controller deadlock.,1
ERROR,AXI_CTRL,AXI master issued an illegal transaction address,AXI_CTRL AXI master issued an illegal transaction address,2
INFO,PCIE_CTRL,PCIe configuration space read successful,PCIE_CTRL PCIe configuration space read successful,6
ERROR,MEM_CTRL,Memory controller address decoder output floating,MEM_CTRL Memory controller address decoder output floating,1
ERROR,INTERRUPT_CTRL,Multiple interrupts asserted simultaneously with same priority,INTERRUPT_CTRL Multiple interrupts asserted simultaneously with same priority,1
INFO,CACHE_CTRL,Cache prefetcher statistics reset,CACHE_CTRL Cache prefetcher statistics reset,1
ERROR,AXI_CTRL,AXI exclusive access not granted,AXI_CTRL AXI exclusive access not granted,2
CRITICAL,MEM_CTRL,Double bit ECC corruption detected in critical kernel memory region,MEM_CTRL Double bit ECC corruption detected in critical kernel memory region,1
CRITICAL,FIFO_BUF,FIFO completely unresponsive to read/write requests,FIFO_BUF FIFO completely unresponsive to read/write requests,5
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure detected.,CLOCK_MANAGER Clock domain crossing synchronization failure detected.,0
ERROR,CACHE_CTRL,Cache line eviction policy misconfiguration,CACHE_CTRL Cache line eviction policy misconfiguration,1
CRITICAL,AXI_CTRL,"AXI interconnect deadlock detected, system stalled","AXI_CTRL AXI interconnect deadlock detected, system stalled",2
WARNING,DDR_CTRL,DDR refresh operation taking longer than expected,DDR_CTRL DDR refresh operation taking longer than expected,1
WARNING,CLOCK_MANAGER,Clock 'PERIPH_CLK' jitter exceeding tolerance,CLOCK_MANAGER Clock 'PERIPH_CLK' jitter exceeding tolerance,0
WARNING,MEM_CTRL,Memory page table entry consistency warning,MEM_CTRL Memory page table entry consistency warning,1
ERROR,DDR_CTRL,DDR memory address alignment fault,DDR_CTRL DDR memory address alignment fault,1
WARNING,CLOCK_MANAGER,Clock gating logic reports potential glitch,CLOCK_MANAGER Clock gating logic reports potential glitch,0
WARNING,POWER_CTRL,"Voltage regulator output ripple detected, within spec on VDD_CORE","POWER_CTRL Voltage regulator output ripple detected, within spec on VDD_CORE",4
ERROR,MEM_CTRL,"Uncorrectable ECC error on bank 0, address 0x12345678","MEM_CTRL Uncorrectable ECC error on bank 0, address 0x12345678",1
WARNING,CLOCK_MANAGER,Global clock buffer output slew rate variation,CLOCK_MANAGER Global clock buffer output slew rate variation,-1
WARNING,INTERRUPT_CTRL,Interrupt mask register configuration might lead to missed interrupts.,INTERRUPT_CTRL Interrupt mask register configuration might lead to missed interrupts.,1
ERROR,DDR_CTRL,DDR read data bus corruption,DDR_CTRL DDR read data bus corruption,1
INFO,DDR_CTRL,DDR controller operating in normal mode,DDR_CTRL DDR controller operating in normal mode,1
WARNING,MEM_CTRL,Memory controller write buffer nearing capacity,MEM_CTRL Memory controller write buffer nearing capacity,1
INFO,CLOCK_MANAGER,Clock buffer bypassed for speed optimization,CLOCK_MANAGER Clock buffer bypassed for speed optimization,0
WARNING,AXI_CTRL,AXI slave responded with `DECERR`,AXI_CTRL AXI slave responded with `DECERR`,2
CRITICAL,MEM_CTRL,Memory controller entered undefined state 0xDEADBEEF,MEM_CTRL Memory controller entered undefined state 0xDEADBEEF,1
INFO,AXI_CTRL,AXI master interface initialized successfully,AXI_CTRL AXI master interface initialized successfully,2
CRITICAL,FIFO_BUF,"FIFO internal buffer pointer desynchronization, unrecoverable state","FIFO_BUF FIFO internal buffer pointer desynchronization, unrecoverable state",5
WARNING,DMA_ENGINE,DMA controller internal buffer nearing capacity,DMA_ENGINE DMA controller internal buffer nearing capacity,3
WARNING,DMA_ENGINE,DMA channel 0 transfer rate degraded,DMA_ENGINE DMA channel 0 transfer rate degraded,3
WARNING,DDR_CTRL,DDR initialization sequence took too long,DDR_CTRL DDR initialization sequence took too long,1
WARNING,CLOCK_MANAGER,Clock source switching detected with momentary glitch,CLOCK_MANAGER Clock source switching detected with momentary glitch,0
ERROR,DDR_CTRL,DDR training sequence failed to lock DQS to DQ.,DDR_CTRL DDR training sequence failed to lock DQS to DQ.,1
WARNING,MEM_CTRL,Memory controller buffer nearly full,MEM_CTRL Memory controller buffer nearly full,1
WARNING,POWER_CTRL,Power domain X current draw exceeding typical operating range,POWER_CTRL Power domain X current draw exceeding typical operating range,4
ERROR,INTERRUPT_CTRL,Interrupt pending register stuck set for IRQ 4,INTERRUPT_CTRL Interrupt pending register stuck set for IRQ 4,1
WARNING,DMA_ENGINE,DMA channel 8 prefetch buffer nearing capacity.,DMA_ENGINE DMA channel 8 prefetch buffer nearing capacity.,3
INFO,DMA_ENGINE,DMA transfer to peripheral completed with zero errors,DMA_ENGINE DMA transfer to peripheral completed with zero errors,3
INFO,PCIE_CTRL,PCIe virtual channel 0 configuration updated,PCIE_CTRL PCIe virtual channel 0 configuration updated,6
INFO,DMA_ENGINE,DMA channel 0 transfer completed.,DMA_ENGINE DMA channel 0 transfer completed.,3
CRITICAL,AXI_CTRL,AXI fabric detected unrecoverable deadlock between master 0x05 and slave 0x12.,AXI_CTRL AXI fabric detected unrecoverable deadlock between master 0x05 and slave 0x12.,2
ERROR,FIFO_BUF,"FIFO overflow detected, data loss occurred (queue full)","FIFO_BUF FIFO overflow detected, data loss occurred (queue full)",5
WARNING,FIFO_BUF,FIFO 'tx_meta' almost-empty flag asserted continuously,FIFO_BUF FIFO 'tx_meta' almost-empty flag asserted continuously,5
ERROR,CACHE_CTRL,Cache way 0 tag mismatch during lookup.,CACHE_CTRL Cache way 0 tag mismatch during lookup.,1
INFO,INTERRUPT_CTRL,Interrupt controller debug registers accessed,INTERRUPT_CTRL Interrupt controller debug registers accessed,1
CRITICAL,DDR_CTRL,DDR controller critical path timing violation,DDR_CTRL DDR controller critical path timing violation,1
WARNING,FIFO_BUF,"FIFO write stall condition detected, backpressure asserted","FIFO_BUF FIFO write stall condition detected, backpressure asserted",5
ERROR,INTERRUPT_CTRL,Critical interrupt handler not invoked within deadline,INTERRUPT_CTRL Critical interrupt handler not invoked within deadline,1
WARNING,AXI_CTRL,AXI outstanding write transaction count above recommendation,AXI_CTRL AXI outstanding write transaction count above recommendation,2
ERROR,DMA_ENGINE,DMA descriptor address out of bounds,DMA_ENGINE DMA descriptor address out of bounds,3
ERROR,INTERRUPT_CTRL,Unmasked interrupt asserted without source,INTERRUPT_CTRL Unmasked interrupt asserted without source,1
CRITICAL,DMA_ENGINE,DMA engine control unit state machine entered illegal and unrecoverable state.,DMA_ENGINE DMA engine control unit state machine entered illegal and unrecoverable state.,3
CRITICAL,MEM_CTRL,Memory protection unit violation detected at address 0xDEADBEEF,MEM_CTRL Memory protection unit violation detected at address 0xDEADBEEF,1
ERROR,FIFO_BUF,FIFO write attempt when output enable active,FIFO_BUF FIFO write attempt when output enable active,5
CRITICAL,INTERRUPT_CTRL,Critical interrupt source permanently masked due to controller failure,INTERRUPT_CTRL Critical interrupt source permanently masked due to controller failure,1
WARNING,INTERRUPT_CTRL,Interrupt controller received unexpected interrupt ID,INTERRUPT_CTRL Interrupt controller received unexpected interrupt ID,1
WARNING,FIFO_BUF,Read data valid delay observed,FIFO_BUF Read data valid delay observed,5
WARNING,POWER_CTRL,"Brown-out detection circuit triggered, low voltage.","POWER_CTRL Brown-out detection circuit triggered, low voltage.",4
INFO,DMA_ENGINE,DMA transfer to main memory completed,DMA_ENGINE DMA transfer to main memory completed,3
WARNING,DMA_ENGINE,DMA descriptor fetch latency exceeding threshold,DMA_ENGINE DMA descriptor fetch latency exceeding threshold,3
CRITICAL,POWER_CTRL,System power supply current surge detected,POWER_CTRL System power supply current surge detected,-1
ERROR,PCIE_CTRL,PCIe link training failure detected.,PCIE_CTRL PCIe link training failure detected.,6
ERROR,CACHE_CTRL,Cache line data corruption detected during writeback,CACHE_CTRL Cache line data corruption detected during writeback,1
WARNING,CACHE_CTRL,Cache conflict misses becoming excessive,CACHE_CTRL Cache conflict misses becoming excessive,1
ERROR,DDR_CTRL,Memory burst length violation detected,DDR_CTRL Memory burst length violation detected,1
CRITICAL,MEM_CTRL,System memory controller entering undefined state,MEM_CTRL System memory controller entering undefined state,1
ERROR,FIFO_BUF,FIFO overflow detected during write.,FIFO_BUF FIFO overflow detected during write.,5
ERROR,MEM_CTRL,"Memory ECC double bit error on bank 1, uncorrectable","MEM_CTRL Memory ECC double bit error on bank 1, uncorrectable",1
INFO,DMA_ENGINE,DMA transfer completed successfully on channel 0,DMA_ENGINE DMA transfer completed successfully on channel 0,3
ERROR,DMA_ENGINE,DMA transaction timeout for channel CH1.,DMA_ENGINE DMA transaction timeout for channel CH1.,3
WARNING,AXI_CTRL,AXI write data channel back-pressure detected,AXI_CTRL AXI write data channel back-pressure detected,2
CRITICAL,POWER_CTRL,Core voltage rail completely unresponsive,POWER_CTRL Core voltage rail completely unresponsive,4
CRITICAL,DMA_ENGINE,DMA engine experienced a hard stall due to internal resource conflict.,DMA_ENGINE DMA engine experienced a hard stall due to internal resource conflict.,3
ERROR,PCIE_CTRL,PCIe Receiver Error (RCV_ERR) detected,PCIE_CTRL PCIe Receiver Error (RCV_ERR) detected,6
INFO,FIFO_BUF,FIFO not full condition.,FIFO_BUF FIFO not full condition.,5
CRITICAL,PCIE_CTRL,PCIe internal state machine entered an unrecoverable state.,PCIE_CTRL PCIe internal state machine entered an unrecoverable state.,6
WARNING,INTERRUPT_CTRL,Interrupt acknowledge latency exceeding expected value.,INTERRUPT_CTRL Interrupt acknowledge latency exceeding expected value.,1
ERROR,CACHE_CTRL,Cache invalidation queue overflow,CACHE_CTRL Cache invalidation queue overflow,1
CRITICAL,POWER_CTRL,System power supply current limit exceeded,POWER_CTRL System power supply current limit exceeded,4
WARNING,MEM_CTRL,Memory access latency increasing under load,MEM_CTRL Memory access latency increasing under load,1
ERROR,CLOCK_MANAGER,PLL frequency out of range,CLOCK_MANAGER PLL frequency out of range,0
WARNING,CLOCK_MANAGER,Clock domain crossing buffer latency increasing,CLOCK_MANAGER Clock domain crossing buffer latency increasing,0
WARNING,CLOCK_MANAGER,PLL lock status oscillating,CLOCK_MANAGER PLL lock status oscillating,0
WARNING,CACHE_CTRL,Cache dirty line count increasing rapidly.,CACHE_CTRL Cache dirty line count increasing rapidly.,1
ERROR,DMA_ENGINE,DMA channel 0 request timeout,DMA_ENGINE DMA channel 0 request timeout,3
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold of 68%,CACHE_CTRL Cache miss rate exceeding expected threshold of 68%,1
WARNING,POWER_CTRL,Voltage rail 3.3V fluctuating beyond tolerance,POWER_CTRL Voltage rail 3.3V fluctuating beyond tolerance,4
WARNING,INTERRUPT_CTRL,Interrupt vector 0x05 experiencing high assertion rate.,INTERRUPT_CTRL Interrupt vector 0x05 experiencing high assertion rate.,-1
INFO,INTERRUPT_CTRL,Configuration parameters loaded for INTERRUPT_CTRL.,INTERRUPT_CTRL Configuration parameters loaded for INTERRUPT_CTRL.,1
INFO,DMA_ENGINE,DMA channel N configured for cyclic mode,DMA_ENGINE DMA channel N configured for cyclic mode,3
WARNING,DDR_CTRL,DDR refresh cycle delayed,DDR_CTRL DDR refresh cycle delayed,1
CRITICAL,MEM_CTRL,MEM_CTRL: System-level ECC failure detected. Unrecoverable hardware state. (multi-bit ECC error detected),MEM_CTRL MEM_CTRL: System-level ECC failure detected. Unrecoverable hardware state. (multi-bit ECC error detected),1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge not received by source module,INTERRUPT_CTRL Interrupt acknowledge not received by source module,1
INFO,CACHE_CTRL,Cache hit for address 0x93361e67.,CACHE_CTRL Cache hit for address 0x93361e67.,1
CRITICAL,DMA_ENGINE,DMA engine core logic failed self-test,DMA_ENGINE DMA engine core logic failed self-test,3
ERROR,DMA_ENGINE,DMA descriptor write-back error,DMA_ENGINE DMA descriptor write-back error,3
WARNING,AXI_CTRL,AXI transaction reordering for write channel,AXI_CTRL AXI transaction reordering for write channel,2
INFO,AXI_CTRL,AXI transaction ID 0x62C4C initiated,AXI_CTRL AXI transaction ID 0x62C4C initiated,2
WARNING,FIFO_BUF,FIFO read latency showing unusual spikes,FIFO_BUF FIFO read latency showing unusual spikes,5
CRITICAL,MEM_CTRL,Uncorrectable ECC error detected on main memory block,MEM_CTRL Uncorrectable ECC error detected on main memory block,1
INFO,INTERRUPT_CTRL,Interrupt masking enabled for all low priority interrupts,INTERRUPT_CTRL Interrupt masking enabled for all low priority interrupts,1
WARNING,DDR_CTRL,DDR memory clock frequency deviation,DDR_CTRL DDR memory clock frequency deviation,1
INFO,FIFO_BUF,FIFO read pointer advanced,FIFO_BUF FIFO read pointer advanced,5
INFO,INTERRUPT_CTRL,Interrupt pending for IRQ_CAN,INTERRUPT_CTRL Interrupt pending for IRQ_CAN,1
WARNING,DMA_ENGINE,DMA buffer pointer nearing saturation for channel 5,DMA_ENGINE DMA buffer pointer nearing saturation for channel 5,3
WARNING,INTERRUPT_CTRL,INTERRUPT_CTRL response latency marginally increased.,INTERRUPT_CTRL INTERRUPT_CTRL response latency marginally increased.,1
ERROR,PCIE_CTRL,PCIe configuration space access error for device B at 0x12345678.,PCIE_CTRL PCIe configuration space access error for device B at 0x12345678.,6
WARNING,AXI_CTRL,AXI read data channel (R) asserts last (RLAST) prematurely,AXI_CTRL AXI read data channel (R) asserts last (RLAST) prematurely,2
ERROR,PCIE_CTRL,"PCIe hot-plug event detected, but device not enumerated","PCIE_CTRL PCIe hot-plug event detected, but device not enumerated",6
WARNING,CLOCK_MANAGER,"Input clock stability warning, minor frequency fluctuations.","CLOCK_MANAGER Input clock stability warning, minor frequency fluctuations.",0
ERROR,PCIE_CTRL,PCIe flow control credit corruption,PCIE_CTRL PCIe flow control credit corruption,6
ERROR,POWER_CTRL,Power management controller reported unexpected power state change,POWER_CTRL Power management controller reported unexpected power state change,4
ERROR,PCIE_CTRL,PCIe link CRC error detected,PCIE_CTRL PCIe link CRC error detected,6
WARNING,POWER_CTRL,Power domain 'PERIPH' transition delay observed,POWER_CTRL Power domain 'PERIPH' transition delay observed,4
INFO,POWER_CTRL,Power domain F shut down successfully,POWER_CTRL Power domain F shut down successfully,4
INFO,AXI_CTRL,AXI bridge reconfigured,AXI_CTRL AXI bridge reconfigured,-1
ERROR,DMA_ENGINE,"DMA transfer of zero length requested, ignored","DMA_ENGINE DMA transfer of zero length requested, ignored",3
WARNING,PCIE_CTRL,PCIe RX lane re-synchronization taking excessive time,PCIE_CTRL PCIe RX lane re-synchronization taking excessive time,6
WARNING,INTERRUPT_CTRL,Interrupt source 7 generating too many events,INTERRUPT_CTRL Interrupt source 7 generating too many events,-1
WARNING,PCIE_CTRL,PCIe link down due to physical layer error,PCIE_CTRL PCIe link down due to physical layer error,6
WARNING,AXI_CTRL,AXI outstanding transaction count approaching maximum limit,AXI_CTRL AXI outstanding transaction count approaching maximum limit,2
INFO,POWER_CTRL,Power sequence completed successfully,POWER_CTRL Power sequence completed successfully,4
WARNING,POWER_CTRL,Voltage rail transient detected,POWER_CTRL Voltage rail transient detected,4
WARNING,CACHE_CTRL,Cache line dirty status mismatch,CACHE_CTRL Cache line dirty status mismatch,1
WARNING,PCIE_CTRL,PCIe receive buffer parity error detected,PCIE_CTRL PCIe receive buffer parity error detected,6
INFO,FIFO_BUF,FIFO 'spi_rx' depth is 16,FIFO_BUF FIFO 'spi_rx' depth is 16,5
CRITICAL,POWER_CTRL,"Brown-out detected, unrecoverable power loss.","POWER_CTRL Brown-out detected, unrecoverable power loss.",4
ERROR,FIFO_BUF,FIFO internal read/write pointer race condition,FIFO_BUF FIFO internal read/write pointer race condition,5
WARNING,INTERRUPT_CTRL,Interrupt masking register unexpectedly modified,INTERRUPT_CTRL Interrupt masking register unexpectedly modified,1
ERROR,AXI_CTRL,AXI burst address wrap boundary violation,AXI_CTRL AXI burst address wrap boundary violation,2
CRITICAL,PCIE_CTRL,PCIe unrecoverable link error,PCIE_CTRL PCIe unrecoverable link error,6
INFO,DMA_ENGINE,DMA channel 0 transfer rate optimized,DMA_ENGINE DMA channel 0 transfer rate optimized,3
WARNING,POWER_CTRL,Auxiliary power rail voltage fluctuating,POWER_CTRL Auxiliary power rail voltage fluctuating,4
INFO,MEM_CTRL,Memory address range registered,MEM_CTRL Memory address range registered,1
INFO,CLOCK_MANAGER,Clock domain power gating state confirmed,CLOCK_MANAGER Clock domain power gating state confirmed,-1
INFO,AXI_CTRL,AXI transaction ID pool reset,AXI_CTRL AXI transaction ID pool reset,2
INFO,INTERRUPT_CTRL,Interrupt line 7 deasserted by peripheral,INTERRUPT_CTRL Interrupt line 7 deasserted by peripheral,1
INFO,AXI_CTRL,"AXI transaction count for master 'CPU' is 10,000","AXI_CTRL AXI transaction count for master 'CPU' is 10,000",2
WARNING,CACHE_CTRL,Cache dirty line writeback delayed,CACHE_CTRL Cache dirty line writeback delayed,1
ERROR,DMA_ENGINE,DMA channel 0 state machine fault,DMA_ENGINE DMA channel 0 state machine fault,3
WARNING,DMA_ENGINE,DMA buffer pointer nearing critical region,DMA_ENGINE DMA buffer pointer nearing critical region,3
ERROR,DDR_CTRL,Memory address alignment fault.,DDR_CTRL Memory address alignment fault.,1
INFO,CLOCK_MANAGER,Clock domain crossing (CDC) handshake successful.,CLOCK_MANAGER Clock domain crossing (CDC) handshake successful.,0
WARNING,PCIE_CTRL,PCIe M.2 hotplug not responding,PCIE_CTRL PCIe M.2 hotplug not responding,6
CRITICAL,INTERRUPT_CTRL,Persistent interrupt storm detected,INTERRUPT_CTRL Persistent interrupt storm detected,1
WARNING,AXI_CTRL,AXI slave asserting perpetual back-pressure,AXI_CTRL AXI slave asserting perpetual back-pressure,2
WARNING,AXI_CTRL,AXI read channel experiencing frequent stall signals.,AXI_CTRL AXI read channel experiencing frequent stall signals.,2
CRITICAL,CLOCK_MANAGER,Clock manager reported catastrophic frequency instability.,CLOCK_MANAGER Clock manager reported catastrophic frequency instability.,0
CRITICAL,INTERRUPT_CTRL,Interrupt controller hardware failure.,INTERRUPT_CTRL Interrupt controller hardware failure.,1
ERROR,DMA_ENGINE,DMA channel 1 burst length mismatch with hardware capabilities,DMA_ENGINE DMA channel 1 burst length mismatch with hardware capabilities,3
CRITICAL,DDR_CTRL,DDR controller in unrecoverable error state,DDR_CTRL DDR controller in unrecoverable error state,1
ERROR,DDR_CTRL,"DDR read data integrity error, potential parity issue.","DDR_CTRL DDR read data integrity error, potential parity issue.",1
ERROR,POWER_CTRL,Voltage rail 'VCC_AUX' failed to power up,POWER_CTRL Voltage rail 'VCC_AUX' failed to power up,-1
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected on channel 1.,DMA_ENGINE DMA buffer pointer corruption detected on channel 1.,3
INFO,AXI_CTRL,AXI transaction ID 0x123 completed successfully,AXI_CTRL AXI transaction ID 0x123 completed successfully,2
WARNING,CLOCK_MANAGER,Clock fanout analysis warning,CLOCK_MANAGER Clock fanout analysis warning,0
ERROR,POWER_CTRL,Overcurrent detection on 3.3V rail,POWER_CTRL Overcurrent detection on 3.3V rail,4
WARNING,FIFO_BUF,Backpressure asserted on write interface,FIFO_BUF Backpressure asserted on write interface,5
INFO,POWER_CTRL,System voltage rails stable,POWER_CTRL System voltage rails stable,4
INFO,CACHE_CTRL,Cache line refill initiated,CACHE_CTRL Cache line refill initiated,1
WARNING,CACHE_CTRL,Cache line fills from external memory increasing,CACHE_CTRL Cache line fills from external memory increasing,1
WARNING,PCIE_CTRL,PCIe AER (Advanced Error Reporting) flagged minor error.,PCIE_CTRL PCIe AER (Advanced Error Reporting) flagged minor error.,6
WARNING,CLOCK_MANAGER,Clock frequency deviation detected from target,CLOCK_MANAGER Clock frequency deviation detected from target,0
INFO,CLOCK_MANAGER,Secondary clock switchover successful,CLOCK_MANAGER Secondary clock switchover successful,0
ERROR,FIFO_BUF,FIFO data integrity check failed,FIFO_BUF FIFO data integrity check failed,5
CRITICAL,CLOCK_MANAGER,System clock synchronization lost,CLOCK_MANAGER System clock synchronization lost,0
WARNING,CACHE_CTRL,Cache eviction queue approaching full capacity,CACHE_CTRL Cache eviction queue approaching full capacity,1
CRITICAL,DMA_ENGINE,DMA engine deadlocked due to resource contention,DMA_ENGINE DMA engine deadlocked due to resource contention,3
ERROR,FIFO_BUF,FIFO 'data_out' read pointer corrupted,FIFO_BUF FIFO 'data_out' read pointer corrupted,5
CRITICAL,AXI_CTRL,AXI slave device 0x1000 failed to acknowledge any request,AXI_CTRL AXI slave device 0x1000 failed to acknowledge any request,2
WARNING,PCIE_CTRL,PCIe TLP poisoning detected in upstream path,PCIE_CTRL PCIe TLP poisoning detected in upstream path,6
ERROR,AXI_CTRL,AXI read data channel protocol error,AXI_CTRL AXI read data channel protocol error,2
ERROR,FIFO_BUF,FIFO depth reported inconsistently,FIFO_BUF FIFO depth reported inconsistently,5
INFO,CLOCK_MANAGER,Clock distribution network re-synced,CLOCK_MANAGER Clock distribution network re-synced,0
ERROR,MEM_CTRL,Memory bank controller address translation error,MEM_CTRL Memory bank controller address translation error,1
ERROR,AXI_CTRL,AXI write response (BRESP) indicating slave error,AXI_CTRL AXI write response (BRESP) indicating slave error,2
INFO,INTERRUPT_CTRL,Interrupt handler registered for event,INTERRUPT_CTRL Interrupt handler registered for event,1
CRITICAL,CLOCK_MANAGER,"Critical clock domain crossing path failure, data integrity compromised.","CLOCK_MANAGER Critical clock domain crossing path failure, data integrity compromised.",0
ERROR,MEM_CTRL,Memory write data corruption at address 0x00000000.,MEM_CTRL Memory write data corruption at address 0x00000000.,1
INFO,CLOCK_MANAGER,PLL re-lock successful,CLOCK_MANAGER PLL re-lock successful,0
CRITICAL,MEM_CTRL,Double bit ECC corruption detected at 0x981882d9.,MEM_CTRL Double bit ECC corruption detected at 0x981882d9.,1
INFO,PCIE_CTRL,PCIe link entered L1 power state,PCIE_CTRL PCIe link entered L1 power state,6
ERROR,POWER_CTRL,Voltage sequencing error during power-up,POWER_CTRL Voltage sequencing error during power-up,4
WARNING,DMA_ENGINE,DMA channel 3 descriptor fetch latency high,DMA_ENGINE DMA channel 3 descriptor fetch latency high,3
WARNING,DDR_CTRL,DDR command queue nearing saturation,DDR_CTRL DDR command queue nearing saturation,1
CRITICAL,CLOCK_MANAGER,"Main system clock PLL lost lock, system halted","CLOCK_MANAGER Main system clock PLL lost lock, system halted",0
INFO,FIFO_BUF,FIFO_METADATA read operation successful.,FIFO_BUF FIFO_METADATA read operation successful.,5
WARNING,FIFO_BUF,FIFO data re-ordering detected,FIFO_BUF FIFO data re-ordering detected,5
INFO,AXI_CTRL,AXI read response RLAST asserted,AXI_CTRL AXI read response RLAST asserted,2
CRITICAL,MEM_CTRL,Double bit ECC corruption detected at 0x93946221.,MEM_CTRL Double bit ECC corruption detected at 0x93946221.,1
ERROR,POWER_CTRL,Thermal shutdown initiated due to critical temperature of 85C.,POWER_CTRL Thermal shutdown initiated due to critical temperature of 85C.,4
WARNING,POWER_CTRL,Voltage rail PLL_V ripple exceeding tolerance (31.7mV).,POWER_CTRL Voltage rail PLL_V ripple exceeding tolerance (31.7mV).,4
CRITICAL,MEM_CTRL,Uncorrectable double bit ECC error on address 0xDEADBEEF,MEM_CTRL Uncorrectable double bit ECC error on address 0xDEADBEEF,1
INFO,CLOCK_MANAGER,Clock source switched,CLOCK_MANAGER Clock source switched,0
CRITICAL,PCIE_CTRL,"Multiple PCIe fatal errors detected, system instability","PCIE_CTRL Multiple PCIe fatal errors detected, system instability",6
CRITICAL,POWER_CTRL,Power sequencing hardware fault,POWER_CTRL Power sequencing hardware fault,4
INFO,AXI_CTRL,AXI slave responded with OKAY status,AXI_CTRL AXI slave responded with OKAY status,2
ERROR,CLOCK_MANAGER,Main PLL frequency drifting out of specification,CLOCK_MANAGER Main PLL frequency drifting out of specification,0
INFO,DMA_ENGINE,DMA channel reset completed successfully,DMA_ENGINE DMA channel reset completed successfully,3
WARNING,DDR_CTRL,DDR controller command queue nearing full,DDR_CTRL DDR controller command queue nearing full,1
INFO,PCIE_CTRL,PCIe link established at Gen4 x8 speed.,PCIE_CTRL PCIe link established at Gen4 x8 speed.,6
INFO,MEM_CTRL,Uncorrectable ECC error corrected (single bit),MEM_CTRL Uncorrectable ECC error corrected (single bit),1
ERROR,CACHE_CTRL,"Cache way miss rate critically high, thrashing suspected","CACHE_CTRL Cache way miss rate critically high, thrashing suspected",1
ERROR,CLOCK_MANAGER,PLL re-lock sequence failed after transient,CLOCK_MANAGER PLL re-lock sequence failed after transient,0
ERROR,CACHE_CTRL,Cache line not found in directory,CACHE_CTRL Cache line not found in directory,1
WARNING,CACHE_CTRL,Cache line 0xABCDEF01 frequently being invalidated.,CACHE_CTRL Cache line 0xABCDEF01 frequently being invalidated.,1
CRITICAL,CACHE_CTRL,Cache controller state machine entered an invalid state,CACHE_CTRL Cache controller state machine entered an invalid state,1
INFO,CACHE_CTRL,Cache line fill policy set to critical word first,CACHE_CTRL Cache line fill policy set to critical word first,-1
CRITICAL,DDR_CTRL,DDR memory controller unable to communicate with memory ICs,DDR_CTRL DDR memory controller unable to communicate with memory ICs,1
WARNING,POWER_CTRL,Power domain transition initiated but not completed,POWER_CTRL Power domain transition initiated but not completed,4
WARNING,DMA_ENGINE,DMA access to protected memory region attempted,DMA_ENGINE DMA access to protected memory region attempted,3
INFO,DMA_ENGINE,DMA transfer completed successfully for channel 6.,DMA_ENGINE DMA transfer completed successfully for channel 6.,3
WARNING,PCIE_CTRL,PCIe link state transitions too frequent,PCIE_CTRL PCIe link state transitions too frequent,6
WARNING,DMA_ENGINE,DMA channel bandwidth saturation,DMA_ENGINE DMA channel bandwidth saturation,3
ERROR,DDR_CTRL,DDR command queue buffer underflow detected,DDR_CTRL DDR command queue buffer underflow detected,1
INFO,DMA_ENGINE,DMA descriptor list fetched and processed,DMA_ENGINE DMA descriptor list fetched and processed,3
WARNING,INTERRUPT_CTRL,Too many spurious interrupts from source B.,INTERRUPT_CTRL Too many spurious interrupts from source B.,1
WARNING,INTERRUPT_CTRL,Unacknowledged interrupt pending for too long,INTERRUPT_CTRL Unacknowledged interrupt pending for too long,1
INFO,CLOCK_MANAGER,Clock buffer reset completed.,CLOCK_MANAGER Clock buffer reset completed.,0
WARNING,CLOCK_MANAGER,Clock 'USB_CLK' frequency deviation detected,CLOCK_MANAGER Clock 'USB_CLK' frequency deviation detected,0
CRITICAL,MEM_CTRL,Memory controller internal FSM reached unknown state,MEM_CTRL Memory controller internal FSM reached unknown state,1
ERROR,FIFO_BUF,"Write access attempted on full FIFO, blocked.","FIFO_BUF Write access attempted on full FIFO, blocked.",5
ERROR,MEM_CTRL,Memory request address out of bounds,MEM_CTRL Memory request address out of bounds,1
INFO,CACHE_CTRL,Cache write-through policy active,CACHE_CTRL Cache write-through policy active,1
WARNING,FIFO_BUF,FIFO write after read operation timing margin tight,FIFO_BUF FIFO write after read operation timing margin tight,5
ERROR,AXI_CTRL,AXI address phase violation.,AXI_CTRL AXI address phase violation.,2
ERROR,AXI_CTRL,AXI read burst length mismatch detected,AXI_CTRL AXI read burst length mismatch detected,2
WARNING,DDR_CTRL,DDR refresh rate deviation from specification,DDR_CTRL DDR refresh rate deviation from specification,1
CRITICAL,AXI_CTRL,AXI interconnect fabric detected a deadlock condition.,AXI_CTRL AXI interconnect fabric detected a deadlock condition.,2
INFO,INTERRUPT_CTRL,All pending interrupts cleared,INTERRUPT_CTRL All pending interrupts cleared,1
CRITICAL,DDR_CTRL,DDR memory chip returned fatal error code,DDR_CTRL DDR memory chip returned fatal error code,1
ERROR,CACHE_CTRL,Cache directory lookup timeout,CACHE_CTRL Cache directory lookup timeout,1
ERROR,CACHE_CTRL,Cache coherence protocol violation detected,CACHE_CTRL Cache coherence protocol violation detected,1
CRITICAL,POWER_CTRL,System power management unit unresponsive,POWER_CTRL System power management unit unresponsive,4
INFO,PCIE_CTRL,"PCIe link up, negotiated x16 Gen4","PCIE_CTRL PCIe link up, negotiated x16 Gen4",6
WARNING,DMA_ENGINE,"DMA buffer pointer corruption detected, software intervention","DMA_ENGINE DMA buffer pointer corruption detected, software intervention",3
CRITICAL,PCIE_CTRL,"PCIe link CRC error rate exceeding maximum threshold, link unstable","PCIE_CTRL PCIe link CRC error rate exceeding maximum threshold, link unstable",6
ERROR,CACHE_CTRL,Cache fill buffer overflow,CACHE_CTRL Cache fill buffer overflow,1
WARNING,FIFO_BUF,FIFO full status signal observed unstable,FIFO_BUF FIFO full status signal observed unstable,5
CRITICAL,POWER_CTRL,Power management unit (PMU) entered an invalid state,POWER_CTRL Power management unit (PMU) entered an invalid state,4
INFO,DMA_ENGINE,Channel 0 transfer setup completed.,DMA_ENGINE Channel 0 transfer setup completed.,3
INFO,MEM_CTRL,Memory page table updated,MEM_CTRL Memory page table updated,1
WARNING,PCIE_CTRL,PCIe device driver reported unexpected configuration space access,PCIE_CTRL PCIe device driver reported unexpected configuration space access,6
INFO,PCIE_CTRL,PCIe Link Width and Speed negotiated,PCIE_CTRL PCIe Link Width and Speed negotiated,6
ERROR,CLOCK_MANAGER,Asynchronous reset signal assertion detected,CLOCK_MANAGER Asynchronous reset signal assertion detected,0
ERROR,AXI_CTRL,AXI response channel slave error on write,AXI_CTRL AXI response channel slave error on write,2
INFO,FIFO_BUF,FIFO written with 16 bytes,FIFO_BUF FIFO written with 16 bytes,5
INFO,INTERRUPT_CTRL,Interrupt handler for IRQ 2 completed,INTERRUPT_CTRL Interrupt handler for IRQ 2 completed,1
CRITICAL,DDR_CTRL,DDR training eye scan failed catastrophically,DDR_CTRL DDR training eye scan failed catastrophically,-1
INFO,CLOCK_MANAGER,Core clock domain transition completed.,CLOCK_MANAGER Core clock domain transition completed.,-1
INFO,DMA_ENGINE,DMA scatter-gather list processing initiated.,DMA_ENGINE DMA scatter-gather list processing initiated.,3
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range,CLOCK_MANAGER Clock skew approaching unsafe range,0
WARNING,INTERRUPT_CTRL,"Multiple pending interrupts from same source, potential storm.","INTERRUPT_CTRL Multiple pending interrupts from same source, potential storm.",1
INFO,CACHE_CTRL,CACHE_CTRL module initialized.,CACHE_CTRL CACHE_CTRL module initialized.,1
ERROR,CACHE_CTRL,Cache L2 data corrupted on eviction,CACHE_CTRL Cache L2 data corrupted on eviction,1
WARNING,FIFO_BUF,FIFO underflow condition imminent,FIFO_BUF FIFO underflow condition imminent,5
CRITICAL,INTERRUPT_CTRL,Interrupt controller state machine deadlock,INTERRUPT_CTRL Interrupt controller state machine deadlock,1
WARNING,DMA_ENGINE,DMA engine internal buffer utilization above 70%,DMA_ENGINE DMA engine internal buffer utilization above 70%,3
WARNING,AXI_CTRL,AXI bus utilization consistently high (85%),AXI_CTRL AXI bus utilization consistently high (85%),2
INFO,POWER_CTRL,Core power rail stable at nominal voltage,POWER_CTRL Core power rail stable at nominal voltage,4
ERROR,AXI_CTRL,AXI burst size larger than requested,AXI_CTRL AXI burst size larger than requested,2
ERROR,CACHE_CTRL,Cache tag parity error detected in L1 data cache,CACHE_CTRL Cache tag parity error detected in L1 data cache,1
WARNING,CACHE_CTRL,Cache coherence protocol overhead increasing,CACHE_CTRL Cache coherence protocol overhead increasing,1
WARNING,POWER_CTRL,Power management unit attempting unauthorized state transition,POWER_CTRL Power management unit attempting unauthorized state transition,4
INFO,MEM_CTRL,Memory read operation successful,MEM_CTRL Memory read operation successful,1
WARNING,FIFO_BUF,FIFO_JTAG_OUT buffer nearing full,FIFO_BUF FIFO_JTAG_OUT buffer nearing full,5
INFO,CACHE_CTRL,Cache miss rate observed at 5%,CACHE_CTRL Cache miss rate observed at 5%,1
ERROR,CACHE_CTRL,Cache data array read disturbance error,CACHE_CTRL Cache data array read disturbance error,1
INFO,FIFO_BUF,FIFO status checked: empty,FIFO_BUF FIFO status checked: empty,5
INFO,DMA_ENGINE,DMA channel 4 transfer request queued,DMA_ENGINE DMA channel 4 transfer request queued,3
ERROR,INTERRUPT_CTRL,Priority inversion detected in interrupt service routine,INTERRUPT_CTRL Priority inversion detected in interrupt service routine,1
INFO,DMA_ENGINE,DMA descriptor fetched successfully from system memory,DMA_ENGINE DMA descriptor fetched successfully from system memory,3
ERROR,INTERRUPT_CTRL,Interrupt source 12 not clearing its pending status,INTERRUPT_CTRL Interrupt source 12 not clearing its pending status,1
INFO,DDR_CTRL,"DDR memory training complete, latency optimized","DDR_CTRL DDR memory training complete, latency optimized",1
INFO,CLOCK_MANAGER,Clock domain crossing handshake successful,CLOCK_MANAGER Clock domain crossing handshake successful,0
INFO,PCIE_CTRL,PCIe device 0x3A configured successfully.,PCIE_CTRL PCIe device 0x3A configured successfully.,6
INFO,CLOCK_MANAGER,Clock synchronization bridge reset successful,CLOCK_MANAGER Clock synchronization bridge reset successful,0
INFO,AXI_CTRL,AXI read request completed,AXI_CTRL AXI read request completed,2
CRITICAL,POWER_CTRL,Power domain isolation fault,POWER_CTRL Power domain isolation fault,4
ERROR,POWER_CTRL,Voltage regulator output ripple out of spec,POWER_CTRL Voltage regulator output ripple out of spec,4
CRITICAL,MEM_CTRL,Memory controller state machine entered an invalid FSM state,MEM_CTRL Memory controller state machine entered an invalid FSM state,1
ERROR,FIFO_BUF,FIFO write-after-full detected,FIFO_BUF FIFO write-after-full detected,5
ERROR,POWER_CTRL,Voltage regulator feedback loop unstable,POWER_CTRL Voltage regulator feedback loop unstable,4
INFO,PCIE_CTRL,PCIe link initialization sequence finished,PCIE_CTRL PCIe link initialization sequence finished,6
INFO,POWER_CTRL,Power gating successfully applied to peripheral block,POWER_CTRL Power gating successfully applied to peripheral block,4
INFO,PCIE_CTRL,PCIe link re-establishment successful,PCIE_CTRL PCIe link re-establishment successful,6
WARNING,FIFO_BUF,FIFO read pointer approaching write pointer,FIFO_BUF FIFO read pointer approaching write pointer,5
WARNING,POWER_CTRL,"Voltage regulator output ripple detected, within spec","POWER_CTRL Voltage regulator output ripple detected, within spec",4
CRITICAL,DMA_ENGINE,DMA engine initiated a transaction with invalid master ID,DMA_ENGINE DMA engine initiated a transaction with invalid master ID,-1
ERROR,PCIE_CTRL,PCIe uncorrectable error detected,PCIE_CTRL PCIe uncorrectable error detected,6
ERROR,FIFO_BUF,FIFO synchronization error detected.,FIFO_BUF FIFO synchronization error detected.,5
ERROR,MEM_CTRL,Memory address alignment fault on write,MEM_CTRL Memory address alignment fault on write,1
ERROR,MEM_CTRL,Memory page table entry corruption,MEM_CTRL Memory page table entry corruption,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge latency exceeding critical limit,INTERRUPT_CTRL Interrupt acknowledge latency exceeding critical limit,1
WARNING,FIFO_BUF,FIFO read data output glitch detected,FIFO_BUF FIFO read data output glitch detected,5
CRITICAL,AXI_CTRL,AXI transaction timeout detected for critical system access,AXI_CTRL AXI transaction timeout detected for critical system access,2
WARNING,FIFO_BUF,FIFO throughput rate below minimum specification,FIFO_BUF FIFO throughput rate below minimum specification,5
INFO,AXI_CTRL,AXI master 'GPU' completed a 4KB block transfer,AXI_CTRL AXI master 'GPU' completed a 4KB block transfer,-1
WARNING,DMA_ENGINE,DMA channel 11 bandwidth saturation,DMA_ENGINE DMA channel 11 bandwidth saturation,3
ERROR,DDR_CTRL,DDR memory address alignment fault at 0x6ef7e0ea.,DDR_CTRL DDR memory address alignment fault at 0x6ef7e0ea.,1
INFO,MEM_CTRL,Memory controller prefetch buffer enabled,MEM_CTRL Memory controller prefetch buffer enabled,1
WARNING,MEM_CTRL,Memory bank access conflict detected,MEM_CTRL Memory bank access conflict detected,1
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, high watermark","FIFO_BUF FIFO read pointer approaching write pointer, high watermark",5
WARNING,AXI_CTRL,AXI read channel response latency spike detected,AXI_CTRL AXI read channel response latency spike detected,2
ERROR,FIFO_BUF,FIFO reset deassertion timing violation,FIFO_BUF FIFO reset deassertion timing violation,5
INFO,FIFO_BUF,FIFO 'RX_HEADER' data consumed,FIFO_BUF FIFO 'RX_HEADER' data consumed,-1
INFO,CLOCK_MANAGER,Clock frequency configuration applied to 1GHz,CLOCK_MANAGER Clock frequency configuration applied to 1GHz,0
INFO,AXI_CTRL,AXI slave register read successful,AXI_CTRL AXI slave register read successful,2
ERROR,PCIE_CTRL,PCIe egress buffer overflow detected,PCIE_CTRL PCIe egress buffer overflow detected,6
INFO,POWER_CTRL,Power state S0 entered successfully,POWER_CTRL Power state S0 entered successfully,4
ERROR,CLOCK_MANAGER,"Main PLL lock lost, transient unlock detected, clock unstable","CLOCK_MANAGER Main PLL lock lost, transient unlock detected, clock unstable",0
ERROR,FIFO_BUF,FIFO 'debug_events' write operation attempted on full FIFO,FIFO_BUF FIFO 'debug_events' write operation attempted on full FIFO,5
ERROR,POWER_CTRL,Power domain sequence dependency violated,POWER_CTRL Power domain sequence dependency violated,4
INFO,PCIE_CTRL,"PCIe link training completed, speed negotiated to Gen4 x4","PCIE_CTRL PCIe link training completed, speed negotiated to Gen4 x4",6
INFO,MEM_CTRL,Memory scrub operation completed.,MEM_CTRL Memory scrub operation completed.,1
WARNING,CLOCK_MANAGER,Clock synthesizer phase noise exceeding specification,CLOCK_MANAGER Clock synthesizer phase noise exceeding specification,0
CRITICAL,FIFO_BUF,FIFO critical path timing violation at max frequency.,FIFO_BUF FIFO critical path timing violation at max frequency.,5
CRITICAL,MEM_CTRL,Memory controller experienced a fatal state machine error,MEM_CTRL Memory controller experienced a fatal state machine error,1
INFO,DMA_ENGINE,DMA transfer request acknowledged by slave,DMA_ENGINE DMA transfer request acknowledged by slave,3
ERROR,FIFO_BUF,FIFO read latency exceeded maximum threshold,FIFO_BUF FIFO read latency exceeded maximum threshold,5
INFO,DMA_ENGINE,DMA channel setup complete,DMA_ENGINE DMA channel setup complete,3
INFO,PCIE_CTRL,PCIe BAR configuration completed,PCIE_CTRL PCIe BAR configuration completed,6
CRITICAL,FIFO_BUF,"FIFO control logic entered invalid state, data path compromised. (invalid state transition)","FIFO_BUF FIFO control logic entered invalid state, data path compromised. (invalid state transition)",5
INFO,AXI_CTRL,AXI default slave accessed,AXI_CTRL AXI default slave accessed,2
WARNING,AXI_CTRL,AXI read data channel backpressure detected,AXI_CTRL AXI read data channel backpressure detected,2
INFO,CACHE_CTRL,Cache 'L1D' successfully cleared all dirty lines,CACHE_CTRL Cache 'L1D' successfully cleared all dirty lines,1
ERROR,CLOCK_MANAGER,PLL output frequency drift detected,CLOCK_MANAGER PLL output frequency drift detected,0
INFO,POWER_CTRL,System entered low power state,POWER_CTRL System entered low power state,4
INFO,FIFO_BUF,FIFO 'tx_queue' reported 0 entries available for write,FIFO_BUF FIFO 'tx_queue' reported 0 entries available for write,5
ERROR,MEM_CTRL,"MEM_CTRL: memory alignment fault - boundary violation detected. (Faulting Address: 0x936E7, Req Size: 2 Bytes)","MEM_CTRL MEM_CTRL: memory alignment fault - boundary violation detected. (Faulting Address: 0x936E7, Req Size: 2 Bytes)",1
CRITICAL,CACHE_CTRL,Cache line replacement policy logic deadlock,CACHE_CTRL Cache line replacement policy logic deadlock,1
WARNING,CACHE_CTRL,"Cache prefetcher buffer full, prefetch disabled","CACHE_CTRL Cache prefetcher buffer full, prefetch disabled",1
INFO,AXI_CTRL,AXI burst length configuration applied,AXI_CTRL AXI burst length configuration applied,2
INFO,DMA_ENGINE,DMA scatter-gather list processed,DMA_ENGINE DMA scatter-gather list processed,3
WARNING,DDR_CTRL,DDR command queue depth exceeding optimal,DDR_CTRL DDR command queue depth exceeding optimal,1
INFO,MEM_CTRL,Memory controller configuration reloaded,MEM_CTRL Memory controller configuration reloaded,1
CRITICAL,CLOCK_MANAGER,"Core clock signal loss detected, system halted","CLOCK_MANAGER Core clock signal loss detected, system halted",0
ERROR,FIFO_BUF,FIFO read without valid data,FIFO_BUF FIFO read without valid data,5
WARNING,AXI_CTRL,AXI exclusive access request denied,AXI_CTRL AXI exclusive access request denied,2
INFO,MEM_CTRL,Memory allocation successful,MEM_CTRL Memory allocation successful,1
WARNING,MEM_CTRL,Memory precharge timing marginal,MEM_CTRL Memory precharge timing marginal,-1
WARNING,DDR_CTRL,DDR initialization time exceeding specification,DDR_CTRL DDR initialization time exceeding specification,1
INFO,CACHE_CTRL,Cache line written back to main memory,CACHE_CTRL Cache line written back to main memory,1
WARNING,PCIE_CTRL,PCIe device link training attempts failed repeatedly,PCIE_CTRL PCIe device link training attempts failed repeatedly,6
WARNING,PCIE_CTRL,PCIe uncorrectable error reported by device GPU.,PCIE_CTRL PCIe uncorrectable error reported by device GPU.,6
INFO,FIFO_BUF,Read operation initiated from entry 12,FIFO_BUF Read operation initiated from entry 12,5
CRITICAL,PCIE_CTRL,PCIe endpoint response timeout during configuration write.,PCIE_CTRL PCIe endpoint response timeout during configuration write.,6
ERROR,DMA_ENGINE,Functional failure in DMA_ENGINE due to arbitration conflict (multiple requests granted simultaneously).,DMA_ENGINE Functional failure in DMA_ENGINE due to arbitration conflict (multiple requests granted simultaneously).,3
WARNING,PCIE_CTRL,PCIe posted writes pending for extended period,PCIE_CTRL PCIe posted writes pending for extended period,6
CRITICAL,POWER_CTRL,System power loss detected.,POWER_CTRL System power loss detected.,4
CRITICAL,AXI_CTRL,AXI deadlock detected in crossbar switch,AXI_CTRL AXI deadlock detected in crossbar switch,2
WARNING,PCIE_CTRL,PCIe up-stream queue latency increasing.,PCIE_CTRL PCIe up-stream queue latency increasing.,6
ERROR,DDR_CTRL,DDR command bus transaction timeout,DDR_CTRL DDR command bus transaction timeout,1
INFO,DMA_ENGINE,DMA loopback test passed,DMA_ENGINE DMA loopback test passed,3
WARNING,DDR_CTRL,DDR command issue queue stalled,DDR_CTRL DDR command issue queue stalled,1
ERROR,MEM_CTRL,Memory controller internal state mismatch,MEM_CTRL Memory controller internal state mismatch,1
CRITICAL,AXI_CTRL,Unrecoverable AXI response error (DECERR) from critical peripheral.,AXI_CTRL Unrecoverable AXI response error (DECERR) from critical peripheral.,2
INFO,INTERRUPT_CTRL,Interrupt controller internal self-test passed,INTERRUPT_CTRL Interrupt controller internal self-test passed,-1
INFO,DDR_CTRL,DDR refresh rate optimized,DDR_CTRL DDR refresh rate optimized,1
ERROR,CLOCK_MANAGER,Clock tree power gating sequence failure.,CLOCK_MANAGER Clock tree power gating sequence failure.,0
INFO,AXI_CTRL,AXI master issued read address,AXI_CTRL AXI master issued read address,2
INFO,DMA_ENGINE,"DMA channel 7 transfer completed, interrupt asserted","DMA_ENGINE DMA channel 7 transfer completed, interrupt asserted",3
CRITICAL,INTERRUPT_CTRL,Interrupt controller failed to clear pending interrupt,INTERRUPT_CTRL Interrupt controller failed to clear pending interrupt,1
CRITICAL,PCIE_CTRL,PCIe lane synchronization lost on link 0.,PCIE_CTRL PCIe lane synchronization lost on link 0.,6
CRITICAL,DMA_ENGINE,System memory access disabled by DMA,DMA_ENGINE System memory access disabled by DMA,3
ERROR,AXI_CTRL,AXI write response 'OKAY' received but data phase incomplete,AXI_CTRL AXI write response 'OKAY' received but data phase incomplete,2
CRITICAL,MEM_CTRL,"Double bit ECC corruption detected, unrecoverable data loss at 0xDEADBEEF","MEM_CTRL Double bit ECC corruption detected, unrecoverable data loss at 0xDEADBEEF",1
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance (237ps peak-to-peak).,CLOCK_MANAGER Clock jitter exceeding tolerance (237ps peak-to-peak).,0
WARNING,DDR_CTRL,DDR command queue utilization exceeding 80%,DDR_CTRL DDR command queue utilization exceeding 80%,1
ERROR,PCIE_CTRL,PCIe DLLP protocol violation detected on upstream port,PCIE_CTRL PCIe DLLP protocol violation detected on upstream port,6
WARNING,PCIE_CTRL,PCIe flow control credits low,PCIE_CTRL PCIe flow control credits low,6
INFO,POWER_CTRL,Voltage regulator enabled for 2.5V rail.,POWER_CTRL Voltage regulator enabled for 2.5V rail.,4
INFO,PCIE_CTRL,PCIe link width negotiated to x16.,PCIE_CTRL PCIe link width negotiated to x16.,6
CRITICAL,INTERRUPT_CTRL,Interrupt controller hardware fault,INTERRUPT_CTRL Interrupt controller hardware fault,1
WARNING,FIFO_BUF,FIFO_FULL asserted for an extended duration,FIFO_BUF FIFO_FULL asserted for an extended duration,5
ERROR,CLOCK_MANAGER,PLL X experienced a temporary unlock condition.,CLOCK_MANAGER PLL X experienced a temporary unlock condition.,0
ERROR,PCIE_CTRL,PCIe unexpected completion (UC),PCIE_CTRL PCIe unexpected completion (UC),6
WARNING,PCIE_CTRL,PCIe link speed negotiation in progress.,PCIE_CTRL PCIe link speed negotiation in progress.,6
WARNING,FIFO_BUF,"FIFO read buffer empty, pending data request","FIFO_BUF FIFO read buffer empty, pending data request",5
WARNING,DDR_CTRL,DDR write data buffer nearing capacity,DDR_CTRL DDR write data buffer nearing capacity,1
ERROR,PCIE_CTRL,PCIe physical layer signal integrity issue,PCIE_CTRL PCIe physical layer signal integrity issue,6
ERROR,CLOCK_MANAGER,Clock gate enable signal for CLOCK_B is stuck active.,CLOCK_MANAGER Clock gate enable signal for CLOCK_B is stuck active.,0
ERROR,CLOCK_MANAGER,Jitter on main system clock exceeding tolerance,CLOCK_MANAGER Jitter on main system clock exceeding tolerance,0
INFO,AXI_CTRL,AXI transaction ID X completed.,AXI_CTRL AXI transaction ID X completed.,2
CRITICAL,DDR_CTRL,"DDR training sequence failed, unrecoverable.","DDR_CTRL DDR training sequence failed, unrecoverable.",1
INFO,DMA_ENGINE,"DMA channel 0 transfer completed, 1024 bytes","DMA_ENGINE DMA channel 0 transfer completed, 1024 bytes",3
ERROR,INTERRUPT_CTRL,Interrupt controller watchdog timeout,INTERRUPT_CTRL Interrupt controller watchdog timeout,1
ERROR,MEM_CTRL,Memory write data corruption detected after integrity check,MEM_CTRL Memory write data corruption detected after integrity check,1
INFO,CACHE_CTRL,Cache enabled for all regions.,CACHE_CTRL Cache enabled for all regions.,1
WARNING,PCIE_CTRL,PCIe upstream buffer backpressure detected,PCIE_CTRL PCIe upstream buffer backpressure detected,6
INFO,INTERRUPT_CTRL,Interrupt priority level 5 now active,INTERRUPT_CTRL Interrupt priority level 5 now active,1
CRITICAL,PCIE_CTRL,"PCIe link training failed, unable to establish connection","PCIE_CTRL PCIe link training failed, unable to establish connection",6
ERROR,DMA_ENGINE,DMA channel 0 bus master arbitration failure,DMA_ENGINE DMA channel 0 bus master arbitration failure,3
ERROR,INTERRUPT_CTRL,Interrupt service routine for 'CRITICAL_ALARM' not found,INTERRUPT_CTRL Interrupt service routine for 'CRITICAL_ALARM' not found,-1
INFO,CACHE_CTRL,Cache line size configured to 64 bytes,CACHE_CTRL Cache line size configured to 64 bytes,1
INFO,POWER_CTRL,Dynamic voltage and frequency scaling active,POWER_CTRL Dynamic voltage and frequency scaling active,9
CRITICAL,INTERRUPT_CTRL,Fatal interrupt storm detected,INTERRUPT_CTRL Fatal interrupt storm detected,1
ERROR,POWER_CTRL,Power rail sequencing fault,POWER_CTRL Power rail sequencing fault,4
CRITICAL,CLOCK_MANAGER,Primary clock source loss detected,CLOCK_MANAGER Primary clock source loss detected,0
WARNING,POWER_CTRL,Current consumption nearing maximum limit,POWER_CTRL Current consumption nearing maximum limit,4
ERROR,AXI_CTRL,AXI read address channel (AR) burst length exceeds AXI4 max,AXI_CTRL AXI read address channel (AR) burst length exceeds AXI4 max,2
CRITICAL,MEM_CTRL,Memory controller arbitration logic deadlock,MEM_CTRL Memory controller arbitration logic deadlock,1
ERROR,POWER_CTRL,Power management unit (PMU) responded with error code 0x3A,POWER_CTRL Power management unit (PMU) responded with error code 0x3A,4
ERROR,POWER_CTRL,Voltage regulator output voltage out of specification,POWER_CTRL Voltage regulator output voltage out of specification,4
ERROR,PCIE_CTRL,PCIe message signaled interrupt (MSI) error,PCIE_CTRL PCIe message signaled interrupt (MSI) error,6
WARNING,DDR_CTRL,DDR command queue reporting unexpected latency spikes,DDR_CTRL DDR command queue reporting unexpected latency spikes,1
INFO,PCIE_CTRL,PCIe TLP received and processed.,PCIE_CTRL PCIe TLP received and processed.,6
CRITICAL,POWER_CTRL,Power management IC (PMIC) reported critical fault,POWER_CTRL Power management IC (PMIC) reported critical fault,4
WARNING,FIFO_BUF,FIFO fullness level fluctuating rapidly,FIFO_BUF FIFO fullness level fluctuating rapidly,5
CRITICAL,FIFO_BUF,"FIFO core logic unresponsive, system hang imminent","FIFO_BUF FIFO core logic unresponsive, system hang imminent",5
CRITICAL,POWER_CTRL,Power sequencing logic failed during ramp-up,POWER_CTRL Power sequencing logic failed during ramp-up,4
CRITICAL,DMA_ENGINE,DMA engine deadlock detected on channel 5.,DMA_ENGINE DMA engine deadlock detected on channel 5.,3
INFO,MEM_CTRL,Memory read operation successful at 0x2000_0000,MEM_CTRL Memory read operation successful at 0x2000_0000,1
WARNING,CACHE_CTRL,"Cache data corruption detected during writeback, corrected","CACHE_CTRL Cache data corruption detected during writeback, corrected",1
ERROR,FIFO_BUF,FIFO read data integrity check failed,FIFO_BUF FIFO read data integrity check failed,5
WARNING,POWER_CTRL,POWER_CTRL pending operations queue in POWER_CTRL growing (count: 14).,POWER_CTRL POWER_CTRL pending operations queue in POWER_CTRL growing (count: 14).,-1
ERROR,MEM_CTRL,Single bit ECC error detected and corrected,MEM_CTRL Single bit ECC error detected and corrected,1
ERROR,MEM_CTRL,Memory write protection violation at address 0x1000_0000,MEM_CTRL Memory write protection violation at address 0x1000_0000,1
INFO,DMA_ENGINE,DMA channel 0 transfer size 2048 bytes,DMA_ENGINE DMA channel 0 transfer size 2048 bytes,3
INFO,DDR_CTRL,DRAM initialised and ready,DDR_CTRL DRAM initialised and ready,1
WARNING,MEM_CTRL,Memory bank 'BANK_C' access latency increased,MEM_CTRL Memory bank 'BANK_C' access latency increased,1
ERROR,POWER_CTRL,Standby power rail unstable,POWER_CTRL Standby power rail unstable,4
CRITICAL,CLOCK_MANAGER,Global clock enable lost,CLOCK_MANAGER Global clock enable lost,0
INFO,MEM_CTRL,Memory bank power-down entered,MEM_CTRL Memory bank power-down entered,1
ERROR,PCIE_CTRL,PCIe packet CRC mismatch,PCIE_CTRL PCIe packet CRC mismatch,6
ERROR,AXI_CTRL,AXI master detected unexpected slave error response (SLVERR),AXI_CTRL AXI master detected unexpected slave error response (SLVERR),2
INFO,PCIE_CTRL,PCIe endpoint BAR configuration successful,PCIE_CTRL PCIe endpoint BAR configuration successful,6
CRITICAL,CLOCK_MANAGER,"Clock tree integrity critical failure, system unclocked.","CLOCK_MANAGER Clock tree integrity critical failure, system unclocked.",0
ERROR,DMA_ENGINE,DMA channel 8 burst write length violation,DMA_ENGINE DMA channel 8 burst write length violation,3
WARNING,DMA_ENGINE,DMA channel 14 transfer size request exceeded maximum permissible.,DMA_ENGINE DMA channel 14 transfer size request exceeded maximum permissible.,3
INFO,INTERRUPT_CTRL,Interrupt aggregation logic enabled,INTERRUPT_CTRL Interrupt aggregation logic enabled,-1
WARNING,AXI_CTRL,AXI outstanding read transactions nearing capacity limit,AXI_CTRL AXI outstanding read transactions nearing capacity limit,2
WARNING,CACHE_CTRL,"Cache write-back buffer nearing capacity, potential stalls","CACHE_CTRL Cache write-back buffer nearing capacity, potential stalls",1
WARNING,PCIE_CTRL,PCIe internal debug FIFO nearing capacity,PCIE_CTRL PCIe internal debug FIFO nearing capacity,6
WARNING,AXI_CTRL,AXI response channel assertion of BRESP unsupported,AXI_CTRL AXI response channel assertion of BRESP unsupported,2
ERROR,DDR_CTRL,DDR initialization failure: Mode Register configuration error,DDR_CTRL DDR initialization failure: Mode Register configuration error,1
INFO,CACHE_CTRL,Cache invalidation complete,CACHE_CTRL Cache invalidation complete,1
WARNING,PCIE_CTRL,PCIe internal memory buffer nearing capacity,PCIE_CTRL PCIe internal memory buffer nearing capacity,6
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold (90%).,CACHE_CTRL Cache miss rate exceeding expected threshold (90%).,1
ERROR,CACHE_CTRL,Cache bypass logic fault,CACHE_CTRL Cache bypass logic fault,1
WARNING,DDR_CTRL,DDR precharge command delay out of spec,DDR_CTRL DDR precharge command delay out of spec,1
CRITICAL,CLOCK_MANAGER,"System clock halted due to internal fault, entire system stopped.","CLOCK_MANAGER System clock halted due to internal fault, entire system stopped.",0
ERROR,MEM_CTRL,Memory refresh cycle timing violation,MEM_CTRL Memory refresh cycle timing violation,1
CRITICAL,PCIE_CTRL,PCIe link configuration fault,PCIE_CTRL PCIe link configuration fault,6
INFO,FIFO_BUF,Backpressure relieved on FIFO input,FIFO_BUF Backpressure relieved on FIFO input,5
WARNING,AXI_CTRL,AXI read request queue depth at 85%,AXI_CTRL AXI read request queue depth at 85%,2
CRITICAL,MEM_CTRL,"Memory arbiter deadlock detected, no further accesses possible.","MEM_CTRL Memory arbiter deadlock detected, no further accesses possible.",1
ERROR,PCIE_CTRL,PCIe device hot-plug detection timeout,PCIE_CTRL PCIe device hot-plug detection timeout,6
INFO,PCIE_CTRL,PCIe Function Level Reset (FLR) completed,PCIE_CTRL PCIe Function Level Reset (FLR) completed,6
WARNING,PCIE_CTRL,PCIe TLP poisoning detected,PCIE_CTRL PCIe TLP poisoning detected,6
CRITICAL,DMA_ENGINE,DMA controller internal state machine entered invalid state,DMA_ENGINE DMA controller internal state machine entered invalid state,3
WARNING,INTERRUPT_CTRL,Interrupt controller detected an interrupt storm condition,INTERRUPT_CTRL Interrupt controller detected an interrupt storm condition,1
INFO,FIFO_BUF,FIFO empty state cleared,FIFO_BUF FIFO empty state cleared,5
WARNING,PCIE_CTRL,PCIe CRC errors increasing on Lane 1,PCIE_CTRL PCIe CRC errors increasing on Lane 1,6
INFO,FIFO_BUF,"FIFO reset successful, all pointers at initial state","FIFO_BUF FIFO reset successful, all pointers at initial state",5
CRITICAL,DMA_ENGINE,DMA engine internal deadlock detected,DMA_ENGINE DMA engine internal deadlock detected,3
WARNING,MEM_CTRL,Memory controller internal register parity error,MEM_CTRL Memory controller internal register parity error,1
INFO,DDR_CTRL,DDR controller configured for dual-rank memory,DDR_CTRL DDR controller configured for dual-rank memory,1
INFO,DMA_ENGINE,DMA channel 1 enabled and ready for transfers,DMA_ENGINE DMA channel 1 enabled and ready for transfers,3
WARNING,AXI_CTRL,AXI read burst length longer than recommended,AXI_CTRL AXI read burst length longer than recommended,2
ERROR,AXI_CTRL,AXI master asserts invalid read address,AXI_CTRL AXI master asserts invalid read address,2
ERROR,INTERRUPT_CTRL,Interrupt controller reset not propagating,INTERRUPT_CTRL Interrupt controller reset not propagating,1
INFO,POWER_CTRL,Core voltage rail stabilized at nominal,POWER_CTRL Core voltage rail stabilized at nominal,4
INFO,INTERRUPT_CTRL,Interrupt pending for device 7,INTERRUPT_CTRL Interrupt pending for device 7,1
ERROR,DMA_ENGINE,DMA channel state machine stuck in busy state,DMA_ENGINE DMA channel state machine stuck in busy state,3
INFO,FIFO_BUF,FIFO maximum depth reported,FIFO_BUF FIFO maximum depth reported,5
ERROR,MEM_CTRL,Memory address alignment violation,MEM_CTRL Memory address alignment violation,1
INFO,PCIE_CTRL,PCIe hot reset sequence completed,PCIE_CTRL PCIe hot reset sequence completed,6
CRITICAL,POWER_CTRL,Power-on reset (POR) held active for too long,POWER_CTRL Power-on reset (POR) held active for too long,4
INFO,FIFO_BUF,"Write operation successful, FIFO depth now Y","FIFO_BUF Write operation successful, FIFO depth now Y",5
INFO,MEM_CTRL,Memory read-after-write consistency checked,MEM_CTRL Memory read-after-write consistency checked,1
INFO,MEM_CTRL,Memory data compare operation successful,MEM_CTRL Memory data compare operation successful,1
ERROR,POWER_CTRL,Power-on reset sequence timing violation,POWER_CTRL Power-on reset sequence timing violation,4
WARNING,AXI_CTRL,AXI response channel (RVALID) assertion delayed,AXI_CTRL AXI response channel (RVALID) assertion delayed,2
INFO,MEM_CTRL,Memory bank interleaving enabled,MEM_CTRL Memory bank interleaving enabled,1
WARNING,FIFO_BUF,FIFO almost empty condition detected.,FIFO_BUF FIFO almost empty condition detected.,5
INFO,MEM_CTRL,Memory controller firmware updated,MEM_CTRL Memory controller firmware updated,1
INFO,AXI_CTRL,AXI bus utilization at 85%,AXI_CTRL AXI bus utilization at 85%,2
CRITICAL,CLOCK_MANAGER,System clock integrity compromised,CLOCK_MANAGER System clock integrity compromised,0
INFO,CLOCK_MANAGER,Spread spectrum clocking disabled,CLOCK_MANAGER Spread spectrum clocking disabled,-1
WARNING,PCIE_CTRL,PCIe maximum read request size limited,PCIE_CTRL PCIe maximum read request size limited,6
WARNING,FIFO_BUF,FIFO write pointer approaching overflow,FIFO_BUF FIFO write pointer approaching overflow,5
ERROR,CLOCK_MANAGER,Clock domain crossing synchronizer output instability,CLOCK_MANAGER Clock domain crossing synchronizer output instability,0
WARNING,INTERRUPT_CTRL,Spurious interrupt count rising,INTERRUPT_CTRL Spurious interrupt count rising,1
ERROR,DMA_ENGINE,DMA channel X configuration error,DMA_ENGINE DMA channel X configuration error,3
ERROR,FIFO_BUF,FIFO synchronization error detected on reset_async.,FIFO_BUF FIFO synchronization error detected on reset_async.,5
INFO,PCIE_CTRL,PCIe link speed negotiated to Gen3 x8,PCIE_CTRL PCIe link speed negotiated to Gen3 x8,6
WARNING,INTERRUPT_CTRL,Interrupt acknowledge signal delayed,INTERRUPT_CTRL Interrupt acknowledge signal delayed,1
INFO,DDR_CTRL,DDR memory power state changed to active,DDR_CTRL DDR memory power state changed to active,1
INFO,DDR_CTRL,DDR controller in low power state,DDR_CTRL DDR controller in low power state,1
ERROR,CACHE_CTRL,Cache tag comparison logic returned incorrect hit,CACHE_CTRL Cache tag comparison logic returned incorrect hit,1
ERROR,AXI_CTRL,AXI write data bus parity error,AXI_CTRL AXI write data bus parity error,2
INFO,POWER_CTRL,Core voltage rail stable at nominal,POWER_CTRL Core voltage rail stable at nominal,4
ERROR,DDR_CTRL,DDR command to address mapping error.,DDR_CTRL DDR command to address mapping error.,1
INFO,CLOCK_MANAGER,Clock manager reset sequence finished,CLOCK_MANAGER Clock manager reset sequence finished,0
WARNING,DDR_CTRL,"DDR low power entry initiated, monitoring exit.","DDR_CTRL DDR low power entry initiated, monitoring exit.",1
WARNING,INTERRUPT_CTRL,Interrupt controller performance degradation,INTERRUPT_CTRL Interrupt controller performance degradation,1
ERROR,FIFO_BUF,Write operation failed due to FIFO full condition,FIFO_BUF Write operation failed due to FIFO full condition,5
CRITICAL,CLOCK_MANAGER,Global clock buffer fault,CLOCK_MANAGER Global clock buffer fault,0
WARNING,PCIE_CTRL,PCIe L1/L2 entry delay detected,PCIE_CTRL PCIe L1/L2 entry delay detected,6
INFO,DMA_ENGINE,DMA scatter-gather list processed.,DMA_ENGINE DMA scatter-gather list processed.,3
WARNING,CACHE_CTRL,Cache prefetcher unit stalled waiting for memory response.,CACHE_CTRL Cache prefetcher unit stalled waiting for memory response.,1
WARNING,AXI_CTRL,AXI handshake delay approaching threshold on read channel for ID 0x2,AXI_CTRL AXI handshake delay approaching threshold on read channel for ID 0x2,2
INFO,PCIE_CTRL,"PCIe configuration read from device 0, function 0","PCIE_CTRL PCIe configuration read from device 0, function 0",6
INFO,AXI_CTRL,AXI burst size 4 successfully negotiated,AXI_CTRL AXI burst size 4 successfully negotiated,2
ERROR,POWER_CTRL,Voltage regulator 'VDD_ARM' response time out of spec,POWER_CTRL Voltage regulator 'VDD_ARM' response time out of spec,4
INFO,MEM_CTRL,Memory refresh cycle completed,MEM_CTRL Memory refresh cycle completed,1
ERROR,MEM_CTRL,Memory read data mismatch at address 0x3000_0000,MEM_CTRL Memory read data mismatch at address 0x3000_0000,1
CRITICAL,CLOCK_MANAGER,"Clock generation PLL permanently lost lock, system clock absent","CLOCK_MANAGER Clock generation PLL permanently lost lock, system clock absent",0
WARNING,POWER_CTRL,Voltage rail droop below minimum threshold,POWER_CTRL Voltage rail droop below minimum threshold,4
CRITICAL,MEM_CTRL,Memory controller state machine entered invalid state,MEM_CTRL Memory controller state machine entered invalid state,1
INFO,DDR_CTRL,DDR memory initialization sequence completed,DDR_CTRL DDR memory initialization sequence completed,1
WARNING,CLOCK_MANAGER,Reference clock input quality degraded,CLOCK_MANAGER Reference clock input quality degraded,0
INFO,FIFO_BUF,"FIFO reset completed, data cleared","FIFO_BUF FIFO reset completed, data cleared",5
CRITICAL,INTERRUPT_CTRL,"Interrupt controller entered unrecoverable state, system responsiveness lost","INTERRUPT_CTRL Interrupt controller entered unrecoverable state, system responsiveness lost",1
INFO,CACHE_CTRL,Cache way X locked for debug,CACHE_CTRL Cache way X locked for debug,-1
WARNING,MEM_CTRL,Single bit ECC error corrected by hardware (address 0x11223344),MEM_CTRL Single bit ECC error corrected by hardware (address 0x11223344),1
WARNING,DDR_CTRL,DDR read latency increased by 10 cycles,DDR_CTRL DDR read latency increased by 10 cycles,1
WARNING,CACHE_CTRL,Cache way replacement policy causing thrashing,CACHE_CTRL Cache way replacement policy causing thrashing,1
WARNING,POWER_CTRL,Voltage scaling transition taking longer than expected,POWER_CTRL Voltage scaling transition taking longer than expected,4
WARNING,CLOCK_MANAGER,Clock domain crossing asynchronous path detected,CLOCK_MANAGER Clock domain crossing asynchronous path detected,0
ERROR,FIFO_BUF,FIFO data lost during flush,FIFO_BUF FIFO data lost during flush,5
ERROR,PCIE_CTRL,PCIe transaction timeout,PCIE_CTRL PCIe transaction timeout,6
ERROR,DMA_ENGINE,DMA channel 0 descriptor chain pointer corrupted,DMA_ENGINE DMA channel 0 descriptor chain pointer corrupted,3
INFO,CLOCK_MANAGER,Clock domain crossing bridges synchronized,CLOCK_MANAGER Clock domain crossing bridges synchronized,0
WARNING,DDR_CTRL,DDR access latency increasing for bank 0,DDR_CTRL DDR access latency increasing for bank 0,1
CRITICAL,MEM_CTRL,"Double bit ECC corruption detected at address 0x7E2F6, uncorrectable","MEM_CTRL Double bit ECC corruption detected at address 0x7E2F6, uncorrectable",1
WARNING,AXI_CTRL,AXI response channel delayed,AXI_CTRL AXI response channel delayed,2
WARNING,DDR_CTRL,DDR data bus inversion (DBI) error detection active,DDR_CTRL DDR data bus inversion (DBI) error detection active,-1
CRITICAL,PCIE_CTRL,PCIe protocol layer fatal error detected,PCIE_CTRL PCIe protocol layer fatal error detected,6
ERROR,MEM_CTRL,Memory controller state machine entered invalid state 0xF0.,MEM_CTRL Memory controller state machine entered invalid state 0xF0.,1
WARNING,CACHE_CTRL,Cache miss count consistently high for data access,CACHE_CTRL Cache miss count consistently high for data access,1
ERROR,AXI_CTRL,AXI protocol violation on read channel,AXI_CTRL AXI protocol violation on read channel,2
CRITICAL,CACHE_CTRL,"Cache controller state machine fault, cache bypass engaged","CACHE_CTRL Cache controller state machine fault, cache bypass engaged",1
WARNING,AXI_CTRL,AXI bus arbitration latency increasing,AXI_CTRL AXI bus arbitration latency increasing,2
WARNING,DMA_ENGINE,DMA channel bandwidth utilization exceeding 90%,DMA_ENGINE DMA channel bandwidth utilization exceeding 90%,3
ERROR,CACHE_CTRL,Cache line data corruption,CACHE_CTRL Cache line data corruption,1
INFO,FIFO_BUF,FIFO_BUF configuration update applied.,FIFO_BUF FIFO_BUF configuration update applied.,5
WARNING,AXI_CTRL,AXI bus contention detected,AXI_CTRL AXI bus contention detected,2
WARNING,DDR_CTRL,DDR_CTRL internal buffer fill level in DDR_CTRL exceeding nominal range.,DDR_CTRL DDR_CTRL internal buffer fill level in DDR_CTRL exceeding nominal range.,1
INFO,POWER_CTRL,Power domain 'IO_VDD' switched to 'active',POWER_CTRL Power domain 'IO_VDD' switched to 'active',4
CRITICAL,DDR_CTRL,"Persistent DDR timing violations, cannot stabilize","DDR_CTRL Persistent DDR timing violations, cannot stabilize",1
WARNING,DDR_CTRL,DDR page close/open policy causing performance degradation,DDR_CTRL DDR page close/open policy causing performance degradation,1
WARNING,INTERRUPT_CTRL,Interrupt priority levels incorrectly configured.,INTERRUPT_CTRL Interrupt priority levels incorrectly configured.,1
INFO,FIFO_BUF,FIFO read operation completed with valid data,FIFO_BUF FIFO read operation completed with valid data,5
INFO,MEM_CTRL,Memory write operation successful for address.,MEM_CTRL Memory write operation successful for address.,1
INFO,CACHE_CTRL,Cache initialized,CACHE_CTRL Cache initialized,1
WARNING,AXI_CTRL,AXI read data received with delay,AXI_CTRL AXI read data received with delay,2
INFO,POWER_CTRL,Deep sleep power state entered successfully,POWER_CTRL Deep sleep power state entered successfully,4
INFO,PCIE_CTRL,PCIe link training initiated,PCIE_CTRL PCIe link training initiated,6
INFO,FIFO_BUF,FIFO_BUF_9 empty after read sequence,FIFO_BUF FIFO_BUF_9 empty after read sequence,5
ERROR,POWER_CTRL,Power domain isolation failure,POWER_CTRL Power domain isolation failure,4
CRITICAL,AXI_CTRL,AXI ID-tagging error resulting in out-of-order responses for same ID,AXI_CTRL AXI ID-tagging error resulting in out-of-order responses for same ID,2
CRITICAL,AXI_CTRL,AXI ID-tagging conflict resulted in master transaction corruption.,AXI_CTRL AXI ID-tagging conflict resulted in master transaction corruption.,2
ERROR,AXI_CTRL,AXI read response contains unexpected SLVERR,AXI_CTRL AXI read response contains unexpected SLVERR,2
INFO,INTERRUPT_CTRL,Interrupt handler registered for IRQ 12,INTERRUPT_CTRL Interrupt handler registered for IRQ 12,1
WARNING,PCIE_CTRL,PCIe egress buffer fill level high,PCIE_CTRL PCIe egress buffer fill level high,6
CRITICAL,CLOCK_MANAGER,Clock buffer bypass path error detected,CLOCK_MANAGER Clock buffer bypass path error detected,0
WARNING,MEM_CTRL,Potential memory bank conflict detected for address 0xDEADBEEF.,MEM_CTRL Potential memory bank conflict detected for address 0xDEADBEEF.,1
ERROR,DMA_ENGINE,DMA source/destination address invalid,DMA_ENGINE DMA source/destination address invalid,3
INFO,AXI_CTRL,AXI write channel idle timeout configured,AXI_CTRL AXI write channel idle timeout configured,2
INFO,DDR_CTRL,DDR memory burst length set to 8,DDR_CTRL DDR memory burst length set to 8,1
CRITICAL,AXI_CTRL,"AXI interconnect deadlock detected, system unresponsive","AXI_CTRL AXI interconnect deadlock detected, system unresponsive",2
ERROR,PCIE_CTRL,PCIe receiver equalization failed,PCIE_CTRL PCIe receiver equalization failed,6
INFO,DMA_ENGINE,"DMA channel 0 status cleared, ready for next transfer","DMA_ENGINE DMA channel 0 status cleared, ready for next transfer",3
INFO,MEM_CTRL,Memory address range configured,MEM_CTRL Memory address range configured,1
WARNING,AXI_CTRL,"AXI `WLAST` asserted too early, possible data truncation","AXI_CTRL AXI `WLAST` asserted too early, possible data truncation",-1
WARNING,PCIE_CTRL,PCIe transaction layer retry buffer approaching overflow,PCIE_CTRL PCIe transaction layer retry buffer approaching overflow,6
WARNING,PCIE_CTRL,PCIe completion timeout counter close to expiration,PCIE_CTRL PCIe completion timeout counter close to expiration,6
WARNING,CACHE_CTRL,Cache prefetcher disabled due to errors,CACHE_CTRL Cache prefetcher disabled due to errors,1
WARNING,AXI_CTRL,AXI slave indicating retry responses frequently,AXI_CTRL AXI slave indicating retry responses frequently,2
ERROR,MEM_CTRL,Memory write data parity error detected by controller.,MEM_CTRL Memory write data parity error detected by controller.,1
ERROR,INTERRUPT_CTRL,Interrupt vector resolution failure,INTERRUPT_CTRL Interrupt vector resolution failure,1
CRITICAL,PCIE_CTRL,PCIe lane synchronization lost on lane 0 and 1,PCIE_CTRL PCIe lane synchronization lost on lane 0 and 1,6
WARNING,DDR_CTRL,DDR memory rank calibration data mismatch,DDR_CTRL DDR memory rank calibration data mismatch,1
INFO,POWER_CTRL,Power domain D transition to OFF state,POWER_CTRL Power domain D transition to OFF state,4
WARNING,CACHE_CTRL,Cache fill buffer overflow,CACHE_CTRL Cache fill buffer overflow,1
ERROR,MEM_CTRL,Memory bank X access denied due to protection violation,MEM_CTRL Memory bank X access denied due to protection violation,1
WARNING,DDR_CTRL,"DDR read pointer stuck, potentially delaying data","DDR_CTRL DDR read pointer stuck, potentially delaying data",1
WARNING,INTERRUPT_CTRL,Interrupt debouncing circuit detecting excessive noise on IRQ_KEYPAD.,INTERRUPT_CTRL Interrupt debouncing circuit detecting excessive noise on IRQ_KEYPAD.,-1
WARNING,POWER_CTRL,Power rail voltage fluctuation outside nominal range,POWER_CTRL Power rail voltage fluctuation outside nominal range,4
CRITICAL,CLOCK_MANAGER,Clock domain crossing bridge asserted fatal error,CLOCK_MANAGER Clock domain crossing bridge asserted fatal error,0
WARNING,AXI_CTRL,AXI burst length violation detected on slave,AXI_CTRL AXI burst length violation detected on slave,2
ERROR,MEM_CTRL,Address bus contention detected,MEM_CTRL Address bus contention detected,1
CRITICAL,MEM_CTRL,"ECC parity mismatch detected, uncorrectable error at 0x2287f3e8.","MEM_CTRL ECC parity mismatch detected, uncorrectable error at 0x2287f3e8.",1
ERROR,FIFO_BUF,FIFO fill level counter erroneous,FIFO_BUF FIFO fill level counter erroneous,5
ERROR,FIFO_BUF,Asynchronous FIFO clock domain crossing metastability event,FIFO_BUF Asynchronous FIFO clock domain crossing metastability event,5
WARNING,MEM_CTRL,Memory self-test warning,MEM_CTRL Memory self-test warning,1
INFO,AXI_CTRL,AXI burst read completed on channel Y,AXI_CTRL AXI burst read completed on channel Y,2
WARNING,CLOCK_MANAGER,Secondary clock source activated due to primary instability,CLOCK_MANAGER Secondary clock source activated due to primary instability,0
WARNING,CLOCK_MANAGER,Secondary clock source showing phase instability,CLOCK_MANAGER Secondary clock source showing phase instability,0
CRITICAL,PCIE_CTRL,PCIe receiver equalization failed across multiple lanes,PCIE_CTRL PCIe receiver equalization failed across multiple lanes,6
WARNING,CLOCK_MANAGER,Clock gating logic detected a transient glitch,CLOCK_MANAGER Clock gating logic detected a transient glitch,0
INFO,MEM_CTRL,Memory prefetcher disabled,MEM_CTRL Memory prefetcher disabled,1
ERROR,INTERRUPT_CTRL,Interrupt source not cleared after acknowledgement,INTERRUPT_CTRL Interrupt source not cleared after acknowledgement,1
WARNING,PCIE_CTRL,PCIe configuration space access latency exceeding threshold,PCIE_CTRL PCIe configuration space access latency exceeding threshold,6
INFO,DDR_CTRL,DDR self-refresh mode entered.,DDR_CTRL DDR self-refresh mode entered.,1
CRITICAL,DMA_ENGINE,"DMA engine unresponsive, critical data path blocked","DMA_ENGINE DMA engine unresponsive, critical data path blocked",3
ERROR,AXI_CTRL,"AXI burst length violation detected (actual 256, expected 32).","AXI_CTRL AXI burst length violation detected (actual 256, expected 32).",2
INFO,INTERRUPT_CTRL,GIC (Generic Interrupt Controller) configuration validated,INTERRUPT_CTRL GIC (Generic Interrupt Controller) configuration validated,-1
INFO,POWER_CTRL,Voltage regulator fine-tuning completed,POWER_CTRL Voltage regulator fine-tuning completed,4
INFO,AXI_CTRL,AXI outstanding read limit reached,AXI_CTRL AXI outstanding read limit reached,2
ERROR,POWER_CTRL,Power-on sequence watchdog timeout,POWER_CTRL Power-on sequence watchdog timeout,4
CRITICAL,CACHE_CTRL,Cache line data parity error during critical operation,CACHE_CTRL Cache line data parity error during critical operation,1
INFO,FIFO_BUF,FIFO almost-empty threshold reached,FIFO_BUF FIFO almost-empty threshold reached,5
CRITICAL,CLOCK_MANAGER,"CRITICAL: Main system clock distribution network failure, module A affected.","CLOCK_MANAGER CRITICAL: Main system clock distribution network failure, module A affected.",0
ERROR,MEM_CTRL,Memory controller state machine transition timeout,MEM_CTRL Memory controller state machine transition timeout,1
INFO,INTERRUPT_CTRL,Interrupt handler for IRQ_05 successfully dispatched,INTERRUPT_CTRL Interrupt handler for IRQ_05 successfully dispatched,1
INFO,PCIE_CTRL,Configuration space read for device ID 0x1234 completed,PCIE_CTRL Configuration space read for device ID 0x1234 completed,6
CRITICAL,CACHE_CTRL,Cache coherence integrity failure,CACHE_CTRL Cache coherence integrity failure,1
ERROR,FIFO_BUF,"FIFO write operation to a full FIFO, data dropped","FIFO_BUF FIFO write operation to a full FIFO, data dropped",5
INFO,CLOCK_MANAGER,Clock frequency configuration applied to 'PERIPH_CLK',CLOCK_MANAGER Clock frequency configuration applied to 'PERIPH_CLK',0
ERROR,FIFO_BUF,FIFO_BUF detected a severe buffer overflow: buffer capacity exceeded. (FIFO 'FIFO_BUF' Depth: 139),FIFO_BUF FIFO_BUF detected a severe buffer overflow: buffer capacity exceeded. (FIFO 'FIFO_BUF' Depth: 139),5
CRITICAL,AXI_CTRL,"Multiple masters asserting same AXI ID, severe protocol violation.","AXI_CTRL Multiple masters asserting same AXI ID, severe protocol violation.",2
INFO,DMA_ENGINE,DMA configuration loaded successfully.,DMA_ENGINE DMA configuration loaded successfully.,3
ERROR,DMA_ENGINE,DMA completion interrupt not asserted after transfer,DMA_ENGINE DMA completion interrupt not asserted after transfer,3
INFO,AXI_CTRL,AXI master 0x1 asserted ARESETN,AXI_CTRL AXI master 0x1 asserted ARESETN,2
WARNING,PCIE_CTRL,PCIe device unable to enter D3hot state,PCIE_CTRL PCIe device unable to enter D3hot state,-1
INFO,MEM_CTRL,Memory bank 0 enabled and initialized,MEM_CTRL Memory bank 0 enabled and initialized,1
INFO,INTERRUPT_CTRL,Interrupt line IRQ_12 de-asserted,INTERRUPT_CTRL Interrupt line IRQ_12 de-asserted,1
WARNING,DDR_CTRL,DDR precharge power consumption elevated,DDR_CTRL DDR precharge power consumption elevated,1
WARNING,INTERRUPT_CTRL,Interrupt request line stuck high for IRQ 15,INTERRUPT_CTRL Interrupt request line stuck high for IRQ 15,1
INFO,POWER_CTRL,Power state C1 transition completed,POWER_CTRL Power state C1 transition completed,4
CRITICAL,DDR_CTRL,DDR memory controller command FIFO overflow,DDR_CTRL DDR memory controller command FIFO overflow,-1
ERROR,PCIE_CTRL,PCIe link training failure: negotiation timeout,PCIE_CTRL PCIe link training failure: negotiation timeout,6
WARNING,DDR_CTRL,"DDR refresh cycle delayed, potential data retention issue","DDR_CTRL DDR refresh cycle delayed, potential data retention issue",1
ERROR,CACHE_CTRL,Cache coherence violation detected for line 0x12345678.,CACHE_CTRL Cache coherence violation detected for line 0x12345678.,1
CRITICAL,MEM_CTRL,Memory address bus contention detected,MEM_CTRL Memory address bus contention detected,1
INFO,INTERRUPT_CTRL,Interrupt handler for CAN controller invoked,INTERRUPT_CTRL Interrupt handler for CAN controller invoked,-1
INFO,POWER_CTRL,Low-power mode entry sequence started,POWER_CTRL Low-power mode entry sequence started,4
ERROR,DDR_CTRL,DDR write data integrity check failed,DDR_CTRL DDR write data integrity check failed,1
INFO,AXI_CTRL,AXI burst write to 'flash_memory' completed,AXI_CTRL AXI burst write to 'flash_memory' completed,2
WARNING,DMA_ENGINE,DMA channel arbitration fairness issue observed,DMA_ENGINE DMA channel arbitration fairness issue observed,3
INFO,PCIE_CTRL,PCIe link width negotiated to x8,PCIE_CTRL PCIe link width negotiated to x8,6
ERROR,AXI_CTRL,AXI transaction ID 1 resulted in DECERR response,AXI_CTRL AXI transaction ID 1 resulted in DECERR response,2
WARNING,PCIE_CTRL,PCIe replay buffer nearing capacity due to link errors,PCIE_CTRL PCIe replay buffer nearing capacity due to link errors,6
ERROR,CLOCK_MANAGER,External clock buffer output degradation,CLOCK_MANAGER External clock buffer output degradation,0
INFO,MEM_CTRL,Memory region 0x1000-0x1FFF successfully accessed.,MEM_CTRL Memory region 0x1000-0x1FFF successfully accessed.,1
INFO,PCIE_CTRL,PCIe endpoint configuration space accessed,PCIE_CTRL PCIe endpoint configuration space accessed,6
ERROR,CLOCK_MANAGER,Clock frequency deviation critical: 450MHz instead of 500MHz,CLOCK_MANAGER Clock frequency deviation critical: 450MHz instead of 500MHz,0
WARNING,FIFO_BUF,FIFO_CMD_QUEUE average occupancy exceeding 70%.,FIFO_BUF FIFO_CMD_QUEUE average occupancy exceeding 70%.,-1
ERROR,CACHE_CTRL,Cache data array corruption at index 128.,CACHE_CTRL Cache data array corruption at index 128.,1
WARNING,MEM_CTRL,Memory controller arbitration conflict detected,MEM_CTRL Memory controller arbitration conflict detected,1
WARNING,DDR_CTRL,DDR refresh interval shortening due to temperature,DDR_CTRL DDR refresh interval shortening due to temperature,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal de-asserted prematurely,INTERRUPT_CTRL Interrupt acknowledge signal de-asserted prematurely,1
INFO,AXI_CTRL,AXI protocol checker reports all transactions compliant,AXI_CTRL AXI protocol checker reports all transactions compliant,-1
WARNING,DDR_CTRL,DDR read data eye margin decreased,DDR_CTRL DDR read data eye margin decreased,1
INFO,DMA_ENGINE,"DMA engine idle, ready for next transfer.","DMA_ENGINE DMA engine idle, ready for next transfer.",3
CRITICAL,POWER_CTRL,"Core power rail instability detected, auto-shutdown initiated","POWER_CTRL Core power rail instability detected, auto-shutdown initiated",4
CRITICAL,DMA_ENGINE,"DMA descriptor fetch deadlock, channel unresponsive","DMA_ENGINE DMA descriptor fetch deadlock, channel unresponsive",3
INFO,INTERRUPT_CTRL,Interrupt pending bit cleared,INTERRUPT_CTRL Interrupt pending bit cleared,1
WARNING,DMA_ENGINE,DMA channel X completion status poll timeout,DMA_ENGINE DMA channel X completion status poll timeout,3
INFO,INTERRUPT_CTRL,Interrupt controller register access verified,INTERRUPT_CTRL Interrupt controller register access verified,1
WARNING,DDR_CTRL,DDR refresh interval approaching limit,DDR_CTRL DDR refresh interval approaching limit,1
ERROR,FIFO_BUF,FIFO depth mismatch between design and configuration,FIFO_BUF FIFO depth mismatch between design and configuration,5
CRITICAL,DMA_ENGINE,"CRITICAL: DMA control logic detected critical failure, system stall.","DMA_ENGINE CRITICAL: DMA control logic detected critical failure, system stall.",3
ERROR,AXI_CTRL,AXI unaligned write access detected,AXI_CTRL AXI unaligned write access detected,2
CRITICAL,INTERRUPT_CTRL,"Interrupt controller FSM in deadlock, system unresponsive.","INTERRUPT_CTRL Interrupt controller FSM in deadlock, system unresponsive.",1
WARNING,DDR_CTRL,DDR read latency variation exceeding threshold,DDR_CTRL DDR read latency variation exceeding threshold,1
CRITICAL,AXI_CTRL,AXI bus arbiter entered a starvation condition for master X,AXI_CTRL AXI bus arbiter entered a starvation condition for master X,2
INFO,CACHE_CTRL,Cache way 0 invalidated due to external snoop,CACHE_CTRL Cache way 0 invalidated due to external snoop,1
INFO,POWER_CTRL,Thermal sensor readings within limits,POWER_CTRL Thermal sensor readings within limits,4
ERROR,FIFO_BUF,FIFO write latency exceeding specification,FIFO_BUF FIFO write latency exceeding specification,5
WARNING,FIFO_BUF,FIFO status flags inconsistent with actual state,FIFO_BUF FIFO status flags inconsistent with actual state,5
INFO,FIFO_BUF,FIFO watermarks configured successfully,FIFO_BUF FIFO watermarks configured successfully,5
CRITICAL,MEM_CTRL,Memory controller self-test failed,MEM_CTRL Memory controller self-test failed,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller configuration registers corrupted,INTERRUPT_CTRL Interrupt controller configuration registers corrupted,1
ERROR,CLOCK_MANAGER,Clock input signal quality degraded.,CLOCK_MANAGER Clock input signal quality degraded.,0
INFO,MEM_CTRL,Memory scrubbing operation completed,MEM_CTRL Memory scrubbing operation completed,1
CRITICAL,DDR_CTRL,DDR memory training loop exceeded maximum iterations,DDR_CTRL DDR memory training loop exceeded maximum iterations,1
WARNING,AXI_CTRL,AXI interconnect showing high contention,AXI_CTRL AXI interconnect showing high contention,2
INFO,FIFO_BUF,Write pointer updated after successful enqueue.,FIFO_BUF Write pointer updated after successful enqueue.,5
CRITICAL,MEM_CTRL,"Double bit ECC uncorrectable error detected (ECC failure), data loss probable","MEM_CTRL Double bit ECC uncorrectable error detected (ECC failure), data loss probable",1
INFO,POWER_CTRL,Voltage regulator enabled for 1.8V rail.,POWER_CTRL Voltage regulator enabled for 1.8V rail.,4
CRITICAL,DDR_CTRL,DDR command queue internal deadlock,DDR_CTRL DDR command queue internal deadlock,1
CRITICAL,PCIE_CTRL,"PCIe link width negotiation failed, operating at reduced lanes","PCIE_CTRL PCIe link width negotiation failed, operating at reduced lanes",6
ERROR,DMA_ENGINE,DMA channel configuration register corruption,DMA_ENGINE DMA channel configuration register corruption,3
ERROR,DMA_ENGINE,DMA scatter-gather list integrity check failed on channel 0x6,DMA_ENGINE DMA scatter-gather list integrity check failed on channel 0x6,3
INFO,CACHE_CTRL,Cache line invalidated for address 0x1234,CACHE_CTRL Cache line invalidated for address 0x1234,1
WARNING,CLOCK_MANAGER,Clock gate enable path detected a glitch,CLOCK_MANAGER Clock gate enable path detected a glitch,0
WARNING,CACHE_CTRL,Cache coherence protocol violation detected,CACHE_CTRL Cache coherence protocol violation detected,1
INFO,POWER_CTRL,Power domain I voltage stable,POWER_CTRL Power domain I voltage stable,4
INFO,CLOCK_MANAGER,Clock divider for 'TIMER' configured to /10.,CLOCK_MANAGER Clock divider for 'TIMER' configured to /10.,0
ERROR,POWER_CTRL,Core power domain voltage ramp-up too slow,POWER_CTRL Core power domain voltage ramp-up too slow,4
INFO,CACHE_CTRL,Cache line invalidated for address 0x1000_0000,CACHE_CTRL Cache line invalidated for address 0x1000_0000,1
WARNING,CLOCK_MANAGER,Clock source drift observed.,CLOCK_MANAGER Clock source drift observed.,0
CRITICAL,DDR_CTRL,"DDR initialization sequence failed, device unresponsive","DDR_CTRL DDR initialization sequence failed, device unresponsive",1
WARNING,POWER_CTRL,Current draw spiking,POWER_CTRL Current draw spiking,4
ERROR,DDR_CTRL,DDR write data not matching readback data for block 0x1000,DDR_CTRL DDR write data not matching readback data for block 0x1000,-1
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lock lost, system clock unstable/halted","CLOCK_MANAGER Clock generation PLL lock lost, system clock unstable/halted",0
ERROR,POWER_CTRL,Power domain X isolation request denied,POWER_CTRL Power domain X isolation request denied,4
INFO,POWER_CTRL,Power domain C entered active state,POWER_CTRL Power domain C entered active state,4
INFO,DDR_CTRL,DDR command reordering enabled,DDR_CTRL DDR command reordering enabled,1
INFO,INTERRUPT_CTRL,Interrupt controller priority scheme updated,INTERRUPT_CTRL Interrupt controller priority scheme updated,1
CRITICAL,MEM_CTRL,Memory access violation in secure boot region,MEM_CTRL Memory access violation in secure boot region,1
ERROR,DMA_ENGINE,DMA descriptor link list corruption,DMA_ENGINE DMA descriptor link list corruption,3
CRITICAL,DDR_CTRL,DDR PHY unrecoverable error during initialization,DDR_CTRL DDR PHY unrecoverable error during initialization,1
CRITICAL,MEM_CTRL,Uncorrectable ECC error in critical data block,MEM_CTRL Uncorrectable ECC error in critical data block,1
CRITICAL,DDR_CTRL,DDR memory interface signal integrity failure,DDR_CTRL DDR memory interface signal integrity failure,1
ERROR,DDR_CTRL,DDR read data bus parity error,DDR_CTRL DDR read data bus parity error,1
WARNING,PCIE_CTRL,PCIe link training speed downgraded from Gen4 to Gen3,PCIE_CTRL PCIe link training speed downgraded from Gen4 to Gen3,6
INFO,CLOCK_MANAGER,Clock frequency configuration verified,CLOCK_MANAGER Clock frequency configuration verified,0
INFO,DMA_ENGINE,DMA channel 10 transfer completed,DMA_ENGINE DMA channel 10 transfer completed,3
WARNING,CACHE_CTRL,Cache miss rate for L2 cache is high,CACHE_CTRL Cache miss rate for L2 cache is high,1
INFO,PCIE_CTRL,PCIe link established successfully at Gen3 speed.,PCIE_CTRL PCIe link established successfully at Gen3 speed.,6
ERROR,CACHE_CTRL,Cache line tag parity error detected,CACHE_CTRL Cache line tag parity error detected,1
INFO,DDR_CTRL,DDR memory page hit rate 95%,DDR_CTRL DDR memory page hit rate 95%,1
WARNING,FIFO_BUF,FIFO almost_empty signal asserted,FIFO_BUF FIFO almost_empty signal asserted,5
INFO,AXI_CTRL,AXI atomic operation completed,AXI_CTRL AXI atomic operation completed,2
CRITICAL,MEM_CTRL,Memory data bus stuck-at fault detected.,MEM_CTRL Memory data bus stuck-at fault detected.,1
CRITICAL,DMA_ENGINE,DMA engine unable to access system memory,DMA_ENGINE DMA engine unable to access system memory,3
ERROR,DDR_CTRL,DDR CKE signal glitch detected.,DDR_CTRL DDR CKE signal glitch detected.,8
INFO,POWER_CTRL,Power measurement unit reports normal consumption,POWER_CTRL Power measurement unit reports normal consumption,4
INFO,CLOCK_MANAGER,Clock domain crossing bridge reset,CLOCK_MANAGER Clock domain crossing bridge reset,0
ERROR,CACHE_CTRL,Cache line not marked dirty after write,CACHE_CTRL Cache line not marked dirty after write,1
ERROR,DMA_ENGINE,DMA descriptor chain completion error,DMA_ENGINE DMA descriptor chain completion error,3
CRITICAL,MEM_CTRL,Memory ECC logic reported a fatal fault,MEM_CTRL Memory ECC logic reported a fatal fault,1
INFO,AXI_CTRL,AXI slave 'gpio_controller' responded with OKAY,AXI_CTRL AXI slave 'gpio_controller' responded with OKAY,2
CRITICAL,PCIE_CTRL,PCIe lane de-skew training failed,PCIE_CTRL PCIe lane de-skew training failed,6
ERROR,AXI_CTRL,Bus transaction cancelled by master,AXI_CTRL Bus transaction cancelled by master,2
ERROR,MEM_CTRL,Single-bit ECC uncorrectable error at address 0x80000000.,MEM_CTRL Single-bit ECC uncorrectable error at address 0x80000000.,1
INFO,INTERRUPT_CTRL,All interrupts masked,INTERRUPT_CTRL All interrupts masked,1
ERROR,DMA_ENGINE,DMA transfer error: byte count mismatch (50 vs 8).,DMA_ENGINE DMA transfer error: byte count mismatch (50 vs 8).,3
ERROR,CLOCK_MANAGER,Clock domain crossing data path latency mismatch,CLOCK_MANAGER Clock domain crossing data path latency mismatch,0
INFO,DMA_ENGINE,DMA channel enabled,DMA_ENGINE DMA channel enabled,3
WARNING,FIFO_BUF,FIFO read enable asserted without valid data,FIFO_BUF FIFO read enable asserted without valid data,5
WARNING,MEM_CTRL,Address decode for 0xDEADBEEF seems unusual,MEM_CTRL Address decode for 0xDEADBEEF seems unusual,1
INFO,AXI_CTRL,AXI transaction acknowledged by slave,AXI_CTRL AXI transaction acknowledged by slave,2
ERROR,CACHE_CTRL,Cache tag RAM address decoder fault,CACHE_CTRL Cache tag RAM address decoder fault,1
INFO,FIFO_BUF,FIFO_BUF_17 current fill level: 10%,FIFO_BUF FIFO_BUF_17 current fill level: 10%,5
ERROR,FIFO_BUF,Bidirectional FIFO deadlock detected,FIFO_BUF Bidirectional FIFO deadlock detected,5
WARNING,PCIE_CTRL,"PCIe error statistics increasing, monitoring required","PCIE_CTRL PCIe error statistics increasing, monitoring required",6
WARNING,FIFO_BUF,FIFO read pointer approaching write pointer threshold,FIFO_BUF FIFO read pointer approaching write pointer threshold,5
INFO,CACHE_CTRL,Cache write-through policy confirmed,CACHE_CTRL Cache write-through policy confirmed,1
WARNING,CACHE_CTRL,Cache miss rate unexpectedly high,CACHE_CTRL Cache miss rate unexpectedly high,1
WARNING,PCIE_CTRL,PCIe link width degradation from x16 to x8,PCIE_CTRL PCIe link width degradation from x16 to x8,6
INFO,CACHE_CTRL,Cache miss handled successfully,CACHE_CTRL Cache miss handled successfully,1
WARNING,CACHE_CTRL,Cache instruction fetch miss rate exceeding threshold,CACHE_CTRL Cache instruction fetch miss rate exceeding threshold,1
ERROR,DMA_ENGINE,DMA address generation unit invalid state transition.,DMA_ENGINE DMA address generation unit invalid state transition.,3
WARNING,FIFO_BUF,FIFO input write rate significantly lower than output read rate,FIFO_BUF FIFO input write rate significantly lower than output read rate,5
ERROR,MEM_CTRL,Memory controller internal register parity error,MEM_CTRL Memory controller internal register parity error,1
INFO,FIFO_BUF,FIFO_KEYBOARD_RX read successful,FIFO_BUF FIFO_KEYBOARD_RX read successful,5
WARNING,PCIE_CTRL,"PCIe device hot-plug event detected, but enumeration failed","PCIE_CTRL PCIe device hot-plug event detected, but enumeration failed",6
CRITICAL,POWER_CTRL,"Power regulator failure detected, initiating shutdown","POWER_CTRL Power regulator failure detected, initiating shutdown",4
WARNING,AXI_CTRL,AXI slave 'Y' reports frequent `SLVERR`,AXI_CTRL AXI slave 'Y' reports frequent `SLVERR`,2
WARNING,AXI_CTRL,AXI slave responded with `SLVERR`,AXI_CTRL AXI slave responded with `SLVERR`,2
ERROR,CLOCK_MANAGER,Clock domain crossing path hold time violation,CLOCK_MANAGER Clock domain crossing path hold time violation,0
WARNING,AXI_CTRL,AXI response timeout on specific address range,AXI_CTRL AXI response timeout on specific address range,2
ERROR,FIFO_BUF,FIFO write pointer corruption detected,FIFO_BUF FIFO write pointer corruption detected,5
INFO,MEM_CTRL,Memory protection unit (MPU) configured,MEM_CTRL Memory protection unit (MPU) configured,1
INFO,MEM_CTRL,Memory ECC scrubbing started,MEM_CTRL Memory ECC scrubbing started,1
INFO,FIFO_BUF,"Read operation successful, data available.","FIFO_BUF Read operation successful, data available.",5
ERROR,CACHE_CTRL,CACHE_CTRL: timing violation - setup/hold time violation detected.,CACHE_CTRL CACHE_CTRL: timing violation - setup/hold time violation detected.,-1
CRITICAL,POWER_CTRL,Power rail VDD_CORE instability leading to CPU reset loop.,POWER_CTRL Power rail VDD_CORE instability leading to CPU reset loop.,-1
ERROR,PCIE_CTRL,PCIe link training failure: equalization stage timeout.,PCIE_CTRL PCIe link training failure: equalization stage timeout.,6
ERROR,CLOCK_MANAGER,Clock multiplexer output selected wrong source,CLOCK_MANAGER Clock multiplexer output selected wrong source,0
INFO,PCIE_CTRL,PCIe link width negotiated to x16,PCIE_CTRL PCIe link width negotiated to x16,6
ERROR,DMA_ENGINE,DMA buffer descriptor corruption detected,DMA_ENGINE DMA buffer descriptor corruption detected,3
WARNING,FIFO_BUF,FIFO read operation while almost_empty asserted,FIFO_BUF FIFO read operation while almost_empty asserted,5
INFO,POWER_CTRL,Power domain DSP reset completed,POWER_CTRL Power domain DSP reset completed,4
ERROR,MEM_CTRL,Memory data bus parity error,MEM_CTRL Memory data bus parity error,1
WARNING,AXI_CTRL,AXI response channel not asserting last signal,AXI_CTRL AXI response channel not asserting last signal,2
WARNING,INTERRUPT_CTRL,Interrupt controller internal FIFO nearing capacity,INTERRUPT_CTRL Interrupt controller internal FIFO nearing capacity,1
INFO,INTERRUPT_CTRL,Global interrupt enable asserted.,INTERRUPT_CTRL Global interrupt enable asserted.,1
CRITICAL,CLOCK_MANAGER,"PLL frequency lock lost, internal clock generator fallback","CLOCK_MANAGER PLL frequency lock lost, internal clock generator fallback",0
INFO,INTERRUPT_CTRL,Interrupt pending register shows no active interrupts,INTERRUPT_CTRL Interrupt pending register shows no active interrupts,1
INFO,POWER_CTRL,System power-on sequence completed without errors,POWER_CTRL System power-on sequence completed without errors,4
WARNING,AXI_CTRL,AXI write channel idle for extended period,AXI_CTRL AXI write channel idle for extended period,2
CRITICAL,MEM_CTRL,Data integrity check failed in memory controller,MEM_CTRL Data integrity check failed in memory controller,1
ERROR,DDR_CTRL,DDR precharge command timing violation at bank 2,DDR_CTRL DDR precharge command timing violation at bank 2,1
CRITICAL,POWER_CTRL,On-chip regulator failed to stabilize voltage,POWER_CTRL On-chip regulator failed to stabilize voltage,4
CRITICAL,DDR_CTRL,DDR rank 1 fails initialization sequence.,DDR_CTRL DDR rank 1 fails initialization sequence.,1
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance of 131 ps,CLOCK_MANAGER Clock jitter exceeding tolerance of 131 ps,0
INFO,FIFO_BUF,FIFO initialized successfully.,FIFO_BUF FIFO initialized successfully.,5
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold.,FIFO_BUF FIFO latency exceeding expected threshold.,5
CRITICAL,PCIE_CTRL,PCIe root complex configuration error,PCIE_CTRL PCIe root complex configuration error,6
ERROR,AXI_CTRL,AXI master 'security_engine' issued transaction to invalid address,AXI_CTRL AXI master 'security_engine' issued transaction to invalid address,2
INFO,FIFO_BUF,"Write operation successful, data enqueued (count 0x1)","FIFO_BUF Write operation successful, data enqueued (count 0x1)",5
WARNING,AXI_CTRL,AXI master attempting an unsupported burst length,AXI_CTRL AXI master attempting an unsupported burst length,2
INFO,MEM_CTRL,Memory region X access granted.,MEM_CTRL Memory region X access granted.,1
ERROR,POWER_CTRL,Power rail sequencing timeout during bringup,POWER_CTRL Power rail sequencing timeout during bringup,4
INFO,POWER_CTRL,Power domain E powered up,POWER_CTRL Power domain E powered up,4
CRITICAL,PCIE_CTRL,PCIe device BAR configuration failed,PCIE_CTRL PCIe device BAR configuration failed,6
CRITICAL,AXI_CTRL,AXI fabric internal routing table corruption detected.,AXI_CTRL AXI fabric internal routing table corruption detected.,-1
INFO,INTERRUPT_CTRL,Interrupt handler registered for vector 0x33B10,INTERRUPT_CTRL Interrupt handler registered for vector 0x33B10,1
ERROR,INTERRUPT_CTRL,"Non-maskable interrupt (NMI) received, but handler not registered","INTERRUPT_CTRL Non-maskable interrupt (NMI) received, but handler not registered",1
WARNING,AXI_CTRL,AXI outstanding read transactions exceeding 75% capacity,AXI_CTRL AXI outstanding read transactions exceeding 75% capacity,2
ERROR,PCIE_CTRL,PCIe packet framing error detected on receive.,PCIE_CTRL PCIe packet framing error detected on receive.,6
INFO,FIFO_BUF,Write operation committed to buffer,FIFO_BUF Write operation committed to buffer,5
ERROR,FIFO_BUF,FIFO internal state corruption,FIFO_BUF FIFO internal state corruption,5
WARNING,AXI_CTRL,AXI write data channel stall detected.,AXI_CTRL AXI write data channel stall detected.,2
WARNING,FIFO_BUF,FIFO 'rx_queue' read pointer stuck,FIFO_BUF FIFO 'rx_queue' read pointer stuck,5
WARNING,FIFO_BUF,"FIFO read latency increasing, potential bottleneck","FIFO_BUF FIFO read latency increasing, potential bottleneck",5
WARNING,CACHE_CTRL,L2 cache fill buffer approaching full.,CACHE_CTRL L2 cache fill buffer approaching full.,1
WARNING,DDR_CTRL,DDR temperature sensor reporting elevated values,DDR_CTRL DDR temperature sensor reporting elevated values,1
ERROR,DMA_ENGINE,DMA channel 3 invalid descriptor address,DMA_ENGINE DMA channel 3 invalid descriptor address,3
INFO,FIFO_BUF,FIFO_MESSAGE_QUEUE reset and ready.,FIFO_BUF FIFO_MESSAGE_QUEUE reset and ready.,5
INFO,POWER_CTRL,Power sequencing initiated for peripheral block.,POWER_CTRL Power sequencing initiated for peripheral block.,4
CRITICAL,DDR_CTRL,"CRITICAL: Multi-bit ECC detected during memory scrub, system integrity compromised at 0xDEADBEEF.","DDR_CTRL CRITICAL: Multi-bit ECC detected during memory scrub, system integrity compromised at 0xDEADBEEF.",1
WARNING,AXI_CTRL,AXI slave S0 responding slowly to read requests,AXI_CTRL AXI slave S0 responding slowly to read requests,2
ERROR,PCIE_CTRL,PCIe received malformed header for MRd.,PCIE_CTRL PCIe received malformed header for MRd.,6
INFO,INTERRUPT_CTRL,Interrupt 9 (Software) dispatched,INTERRUPT_CTRL Interrupt 9 (Software) dispatched,1
CRITICAL,CLOCK_MANAGER,Clock input signal to PLL became intermittent,CLOCK_MANAGER Clock input signal to PLL became intermittent,0
WARNING,DDR_CTRL,DDR memory voltage deviating from nominal,DDR_CTRL DDR memory voltage deviating from nominal,-1
INFO,DDR_CTRL,DDR memory initialized for 4GB.,DDR_CTRL DDR memory initialized for 4GB.,1
ERROR,MEM_CTRL,Memory ECC logic self-test failed,MEM_CTRL Memory ECC logic self-test failed,1
WARNING,PCIE_CTRL,PCIe internal clock jitter detected,PCIE_CTRL PCIe internal clock jitter detected,-1
ERROR,POWER_CTRL,Power gate control signal stuck high,POWER_CTRL Power gate control signal stuck high,-1
WARNING,CLOCK_MANAGER,Clock enable signal Main exhibiting abnormal pulse width.,CLOCK_MANAGER Clock enable signal Main exhibiting abnormal pulse width.,-1
CRITICAL,POWER_CTRL,Voltage regulator reports critical output impedance,POWER_CTRL Voltage regulator reports critical output impedance,4
ERROR,MEM_CTRL,Memory double bit ECC error (uncorrectable),MEM_CTRL Memory double bit ECC error (uncorrectable),1
CRITICAL,MEM_CTRL,Memory system self-test failed critical checks,MEM_CTRL Memory system self-test failed critical checks,1
INFO,FIFO_BUF,"FIFO almost empty, read operation safe","FIFO_BUF FIFO almost empty, read operation safe",5
WARNING,DDR_CTRL,DDR burst length set dynamically,DDR_CTRL DDR burst length set dynamically,1
WARNING,PCIE_CTRL,PCIe completion with unexpected status,PCIE_CTRL PCIe completion with unexpected status,6
ERROR,DDR_CTRL,Self-refresh exit sequence failure,DDR_CTRL Self-refresh exit sequence failure,1
WARNING,AXI_CTRL,AXI `ARVALID` asserted but target slave not responding,AXI_CTRL AXI `ARVALID` asserted but target slave not responding,2
INFO,INTERRUPT_CTRL,Interrupt priority level 3 processed,INTERRUPT_CTRL Interrupt priority level 3 processed,1
INFO,POWER_CTRL,Voltage rail enabled,POWER_CTRL Voltage rail enabled,4
INFO,CACHE_CTRL,Cache directory flushed on system reset,CACHE_CTRL Cache directory flushed on system reset,1
INFO,PCIE_CTRL,PCIe device 0x5C driver loaded successfully.,PCIE_CTRL PCIe device 0x5C driver loaded successfully.,6
INFO,MEM_CTRL,Memory scrubbing completed successfully,MEM_CTRL Memory scrubbing completed successfully,1
ERROR,FIFO_BUF,"Attempted read from empty FIFO, underflow condition","FIFO_BUF Attempted read from empty FIFO, underflow condition",5
WARNING,PCIE_CTRL,"TLP buffer fill level significant, approaching warning limit","PCIE_CTRL TLP buffer fill level significant, approaching warning limit",6
INFO,PCIE_CTRL,PCIe link trained to full bandwidth,PCIE_CTRL PCIe link trained to full bandwidth,6
ERROR,MEM_CTRL,Memory controller detected invalid request from CPU,MEM_CTRL Memory controller detected invalid request from CPU,1
WARNING,POWER_CTRL,Voltage rail 'VCC_AUX' showing minor ripple,POWER_CTRL Voltage rail 'VCC_AUX' showing minor ripple,4
WARNING,FIFO_BUF,FIFO empty condition detected prematurely,FIFO_BUF FIFO empty condition detected prematurely,5
WARNING,FIFO_BUF,FIFO data integrity check warning,FIFO_BUF FIFO data integrity check warning,5
WARNING,INTERRUPT_CTRL,ISR latency increasing,INTERRUPT_CTRL ISR latency increasing,1
ERROR,AXI_CTRL,AXI bus contention detected on shared resource.,AXI_CTRL AXI bus contention detected on shared resource.,2
INFO,AXI_CTRL,AXI master 0x05 requested a read burst,AXI_CTRL AXI master 0x05 requested a read burst,2
CRITICAL,POWER_CTRL,Power management unit unrecoverable bus contention.,POWER_CTRL Power management unit unrecoverable bus contention.,4
WARNING,CACHE_CTRL,Cache line eviction count unusually high,CACHE_CTRL Cache line eviction count unusually high,1
ERROR,CLOCK_MANAGER,CDC metastability detected on control path SYNC_REG,CLOCK_MANAGER CDC metastability detected on control path SYNC_REG,0
WARNING,PCIE_CTRL,PCIe receiver detection failure on unused lanes,PCIE_CTRL PCIe receiver detection failure on unused lanes,6
WARNING,FIFO_BUF,FIFO_AUDIO_OUT nearing full capacity,FIFO_BUF FIFO_AUDIO_OUT nearing full capacity,5
INFO,POWER_CTRL,Voltage regulator in stable state.,POWER_CTRL Voltage regulator in stable state.,4
WARNING,DDR_CTRL,Controller detected marginal voltage level on VDDQ.,DDR_CTRL Controller detected marginal voltage level on VDDQ.,-1
CRITICAL,DDR_CTRL,DDR memory refresh controller state machine fault,DDR_CTRL DDR memory refresh controller state machine fault,1
CRITICAL,MEM_CTRL,"Double bit ECC error on address 0x40000000, unrecoverable.","MEM_CTRL Double bit ECC error on address 0x40000000, unrecoverable.",1
WARNING,DDR_CTRL,DDR precharge command pending.,DDR_CTRL DDR precharge command pending.,1
CRITICAL,CACHE_CTRL,"Multi-level cache coherence failure, data integrity compromised","CACHE_CTRL Multi-level cache coherence failure, data integrity compromised",1
WARNING,PCIE_CTRL,PCIe bridge configuration register CRC error,PCIE_CTRL PCIe bridge configuration register CRC error,6
ERROR,POWER_CTRL,"Voltage regulator response timeout detected, transaction timeout.","POWER_CTRL Voltage regulator response timeout detected, transaction timeout.",4
WARNING,PCIE_CTRL,PCIe CRC error count increasing.,PCIE_CTRL PCIe CRC error count increasing.,6
ERROR,PCIE_CTRL,PCIe received malformed TLP header.,PCIE_CTRL PCIe received malformed TLP header.,6
CRITICAL,DMA_ENGINE,"DMA engine internal controller error, restart required","DMA_ENGINE DMA engine internal controller error, restart required",3
WARNING,CACHE_CTRL,Cache directory lookup performance degradation,CACHE_CTRL Cache directory lookup performance degradation,1
WARNING,CLOCK_MANAGER,Clock domain crossing bridge experiencing high latency,CLOCK_MANAGER Clock domain crossing bridge experiencing high latency,0
ERROR,FIFO_BUF,"FIFO almost empty, but read failed","FIFO_BUF FIFO almost empty, but read failed",5
WARNING,PCIE_CTRL,PCIe PME (Power Management Event) assertion unexpected,PCIE_CTRL PCIe PME (Power Management Event) assertion unexpected,6
WARNING,CLOCK_MANAGER,Clock source selection logic meta-stability,CLOCK_MANAGER Clock source selection logic meta-stability,0
WARNING,PCIE_CTRL,PCIe data link layer CRC error rate increasing,PCIE_CTRL PCIe data link layer CRC error rate increasing,6
CRITICAL,CLOCK_MANAGER,Critical clock source failure,CLOCK_MANAGER Critical clock source failure,0
INFO,DMA_ENGINE,DMA transfer completed with `OKAY` status,DMA_ENGINE DMA transfer completed with `OKAY` status,3
INFO,AXI_CTRL,AXI read burst alignment violation,AXI_CTRL AXI read burst alignment violation,2
ERROR,MEM_CTRL,Read-after-write data inconsistency,MEM_CTRL Read-after-write data inconsistency,1
INFO,CLOCK_MANAGER,Clock domain crossing bridge 'cfg_sync' verified stable,CLOCK_MANAGER Clock domain crossing bridge 'cfg_sync' verified stable,0
CRITICAL,PCIE_CTRL,PCIe physical layer (PHY) unrecoverable error,PCIE_CTRL PCIe physical layer (PHY) unrecoverable error,6
ERROR,PCIE_CTRL,"PCIe data link layer protocol error, unexpected TLP sequence","PCIE_CTRL PCIe data link layer protocol error, unexpected TLP sequence",6
INFO,CACHE_CTRL,Cache line eviction policy updated,CACHE_CTRL Cache line eviction policy updated,1
WARNING,POWER_CTRL,Voltage sensor reading slightly out of calibration,POWER_CTRL Voltage sensor reading slightly out of calibration,7
ERROR,AXI_CTRL,AXI read burst alignment violation (addr=0xa01375d0).,AXI_CTRL AXI read burst alignment violation (addr=0xa01375d0).,2
WARNING,FIFO_BUF,FIFO read after write latency increased,FIFO_BUF FIFO read after write latency increased,5
ERROR,AXI_CTRL,AXI master ID collision detected,AXI_CTRL AXI master ID collision detected,2
INFO,PCIE_CTRL,PCIe device ID recognized,PCIE_CTRL PCIe device ID recognized,6
INFO,INTERRUPT_CTRL,Software interrupt triggered successfully,INTERRUPT_CTRL Software interrupt triggered successfully,1
CRITICAL,FIFO_BUF,FIFO physical storage corruption detected,FIFO_BUF FIFO physical storage corruption detected,5
ERROR,PCIE_CTRL,"PCIe link degradation, reduced width","PCIE_CTRL PCIe link degradation, reduced width",6
ERROR,DMA_ENGINE,DMA scatter-gather list corruption detected,DMA_ENGINE DMA scatter-gather list corruption detected,3
INFO,DMA_ENGINE,DMA channel 23 configuration complete,DMA_ENGINE DMA channel 23 configuration complete,3
ERROR,PCIE_CTRL,PCIe Root Complex response timeout for configuration read,PCIE_CTRL PCIe Root Complex response timeout for configuration read,6
INFO,POWER_CTRL,Voltage regulator for VDD_USB confirmed stable.,POWER_CTRL Voltage regulator for VDD_USB confirmed stable.,-1
ERROR,MEM_CTRL,Data poisoning detected in memory region 0x1000-0x1FFF.,MEM_CTRL Data poisoning detected in memory region 0x1000-0x1FFF.,1
WARNING,MEM_CTRL,Memory refresh arbitration delay,MEM_CTRL Memory refresh arbitration delay,1
CRITICAL,DMA_ENGINE,"DMA channel 7 buffer pointer corrupted, writing to OS kernel memory","DMA_ENGINE DMA channel 7 buffer pointer corrupted, writing to OS kernel memory",3
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal timer overflow leading to deadlock,INTERRUPT_CTRL Interrupt controller internal timer overflow leading to deadlock,1
ERROR,INTERRUPT_CTRL,Interrupt vector table access error,INTERRUPT_CTRL Interrupt vector table access error,1
INFO,AXI_CTRL,AXI master USB initiated burst read.,AXI_CTRL AXI master USB initiated burst read.,2
WARNING,CLOCK_MANAGER,Reset de-assertion timing marginal (9ns remaining).,CLOCK_MANAGER Reset de-assertion timing marginal (9ns remaining).,0
WARNING,MEM_CTRL,"Memory controller busy, deferring request","MEM_CTRL Memory controller busy, deferring request",1
INFO,PCIE_CTRL,PCIe device 0x1001 initialized successfully.,PCIE_CTRL PCIe device 0x1001 initialized successfully.,6
CRITICAL,MEM_CTRL,"Fatal memory controller logic error, system reset required","MEM_CTRL Fatal memory controller logic error, system reset required",1
ERROR,FIFO_BUF,FIFO empty status unexpectedly asserted,FIFO_BUF FIFO empty status unexpectedly asserted,5
INFO,INTERRUPT_CTRL,Interrupt controller in masked state,INTERRUPT_CTRL Interrupt controller in masked state,1
INFO,PCIE_CTRL,PCIe upstream link bandwidth utilized,PCIE_CTRL PCIe upstream link bandwidth utilized,6
INFO,MEM_CTRL,Memory status: all banks nominal,MEM_CTRL Memory status: all banks nominal,1
ERROR,AXI_CTRL,AXI read burst alignment violation at address 0xDEADBEEF.,AXI_CTRL AXI read burst alignment violation at address 0xDEADBEEF.,2
INFO,MEM_CTRL,Memory BIST passed,MEM_CTRL Memory BIST passed,1
CRITICAL,FIFO_BUF,"FIFO hardware error detected, unrecoverable","FIFO_BUF FIFO hardware error detected, unrecoverable",5
WARNING,FIFO_BUF,FIFO_SDCARD_TX buffer 95% full,FIFO_BUF FIFO_SDCARD_TX buffer 95% full,5
CRITICAL,POWER_CTRL,System power-on reset failure,POWER_CTRL System power-on reset failure,4
WARNING,PCIE_CTRL,PCIe PTM (Precision Time Measurement) capability disabled,PCIE_CTRL PCIe PTM (Precision Time Measurement) capability disabled,-1
WARNING,POWER_CTRL,"Power domain X transition taking too long, potential issue","POWER_CTRL Power domain X transition taking too long, potential issue",4
INFO,FIFO_BUF,"FIFO reset completed, ready for operations","FIFO_BUF FIFO reset completed, ready for operations",5
INFO,MEM_CTRL,Memory controller bank 0 initialization complete,MEM_CTRL Memory controller bank 0 initialization complete,1
ERROR,FIFO_BUF,"FIFO data parity error on read, index 32.","FIFO_BUF FIFO data parity error on read, index 32.",5
INFO,DDR_CTRL,DDR memory initialization sequence complete,DDR_CTRL DDR memory initialization sequence complete,1
INFO,AXI_CTRL,AXI master initiated a streaming burst read,AXI_CTRL AXI master initiated a streaming burst read,2
WARNING,POWER_CTRL,Core voltage rail sags below nominal,POWER_CTRL Core voltage rail sags below nominal,4
INFO,POWER_CTRL,Thermal sensor data read,POWER_CTRL Thermal sensor data read,4
WARNING,AXI_CTRL,"AXI write response delayed, pending for 500 cycles","AXI_CTRL AXI write response delayed, pending for 500 cycles",2
ERROR,MEM_CTRL,Memory write protection violation detected.,MEM_CTRL Memory write protection violation detected.,1
INFO,INTERRUPT_CTRL,Interrupt pending register polled clear,INTERRUPT_CTRL Interrupt pending register polled clear,1
INFO,PCIE_CTRL,TLP transaction initiated successfully,PCIE_CTRL TLP transaction initiated successfully,6
INFO,POWER_CTRL,Power domain VDD_GPU powered up,POWER_CTRL Power domain VDD_GPU powered up,4
INFO,MEM_CTRL,Memory read operation initiated at 0x200000,MEM_CTRL Memory read operation initiated at 0x200000,1
CRITICAL,FIFO_BUF,FIFO internal control path deadlock,FIFO_BUF FIFO internal control path deadlock,5
WARNING,CACHE_CTRL,Cache line writebacks delayed due to bus congestion,CACHE_CTRL Cache line writebacks delayed due to bus congestion,1
INFO,DMA_ENGINE,Descriptor queue processed,DMA_ENGINE Descriptor queue processed,3
ERROR,POWER_CTRL,Power sequencing error,POWER_CTRL Power sequencing error,4
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lost lock, system in emergency shutdown","CLOCK_MANAGER Clock generation PLL lost lock, system in emergency shutdown",0
CRITICAL,PCIE_CTRL,"PCIe TLP (Transaction Layer Packet) framing error, unrecoverable","PCIE_CTRL PCIe TLP (Transaction Layer Packet) framing error, unrecoverable",6
ERROR,AXI_CTRL,AXI master 0 write address channel deadlock detected,AXI_CTRL AXI master 0 write address channel deadlock detected,2
WARNING,CLOCK_MANAGER,Clock source output jitter increasing,CLOCK_MANAGER Clock source output jitter increasing,0
CRITICAL,MEM_CTRL,Memory arbitration logic entered hung state,MEM_CTRL Memory arbitration logic entered hung state,1
CRITICAL,PCIE_CTRL,"PCIe Physical Layer (PHY) link training failure, unable to establish connection","PCIE_CTRL PCIe Physical Layer (PHY) link training failure, unable to establish connection",6
ERROR,CLOCK_MANAGER,Clock period violation detected,CLOCK_MANAGER Clock period violation detected,0
CRITICAL,POWER_CTRL,Voltage detector reported critical low voltage on system rail,POWER_CTRL Voltage detector reported critical low voltage on system rail,4
ERROR,DDR_CTRL,DDR memory array read data mismatch at 0x123400,DDR_CTRL DDR memory array read data mismatch at 0x123400,1
WARNING,DMA_ENGINE,DMA bandwidth utilization high.,DMA_ENGINE DMA bandwidth utilization high.,3
WARNING,POWER_CTRL,Brown-out detection triggered temporarily,POWER_CTRL Brown-out detection triggered temporarily,4
ERROR,INTERRUPT_CTRL,Interrupt vector mismatch detected for IRQ_ID 5,INTERRUPT_CTRL Interrupt vector mismatch detected for IRQ_ID 5,1
INFO,DMA_ENGINE,DMA transfer complete for channel 1,DMA_ENGINE DMA transfer complete for channel 1,3
ERROR,DDR_CTRL,Data bus inversion (DBI) error detected on DDR interface,DDR_CTRL Data bus inversion (DBI) error detected on DDR interface,-1
WARNING,FIFO_BUF,FIFO read access from empty buffer stalled,FIFO_BUF FIFO read access from empty buffer stalled,5
WARNING,INTERRUPT_CTRL,Interrupt queue depth exceeding average,INTERRUPT_CTRL Interrupt queue depth exceeding average,1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller stuck in unrecoverable state, IRQs disabled","INTERRUPT_CTRL Interrupt controller stuck in unrecoverable state, IRQs disabled",1
CRITICAL,CLOCK_MANAGER,Global clock distribution error,CLOCK_MANAGER Global clock distribution error,0
WARNING,FIFO_BUF,FIFO high watermark approaching,FIFO_BUF FIFO high watermark approaching,5
INFO,FIFO_BUF,"FIFO reset completed, all pointers initialized","FIFO_BUF FIFO reset completed, all pointers initialized",5
CRITICAL,MEM_CTRL,Double-bit ECC error detected in crucial boot ROM region,MEM_CTRL Double-bit ECC error detected in crucial boot ROM region,1
ERROR,DMA_ENGINE,DMA completion status register read failed,DMA_ENGINE DMA completion status register read failed,3
ERROR,DMA_ENGINE,DMA Scatter-Gather list processing error,DMA_ENGINE DMA Scatter-Gather list processing error,3
CRITICAL,MEM_CTRL,Memory controller state machine stuck in refresh pending.,MEM_CTRL Memory controller state machine stuck in refresh pending.,1
INFO,FIFO_BUF,FIFO almost full condition cleared,FIFO_BUF FIFO almost full condition cleared,5
CRITICAL,CACHE_CTRL,Cache controller state machine unrecoverable error,CACHE_CTRL Cache controller state machine unrecoverable error,1
WARNING,MEM_CTRL,Memory controller read buffer nearing capacity,MEM_CTRL Memory controller read buffer nearing capacity,1
WARNING,PCIE_CTRL,PCIe link state transition taking longer than expected,PCIE_CTRL PCIe link state transition taking longer than expected,6
ERROR,AXI_CTRL,AXI write data bus width mismatch,AXI_CTRL AXI write data bus width mismatch,2
ERROR,FIFO_BUF,Read pointer advanced past write pointer (underflow condition),FIFO_BUF Read pointer advanced past write pointer (underflow condition),5
INFO,POWER_CTRL,Dynamic voltage scaling applied,POWER_CTRL Dynamic voltage scaling applied,9
CRITICAL,CACHE_CTRL,Cache controller state machine locked up,CACHE_CTRL Cache controller state machine locked up,1
INFO,PCIE_CTRL,PCIe Root Complex received completion with unsupported status.,PCIE_CTRL PCIe Root Complex received completion with unsupported status.,6
WARNING,DMA_ENGINE,"DMA descriptor fetch delayed, potential latency impact","DMA_ENGINE DMA descriptor fetch delayed, potential latency impact",3
WARNING,CLOCK_MANAGER,Clock jitter on PLL_SYS output approaching specification limit,CLOCK_MANAGER Clock jitter on PLL_SYS output approaching specification limit,0
WARNING,POWER_CTRL,Power domain transition delay detected for domain CORE.,POWER_CTRL Power domain transition delay detected for domain CORE.,4
WARNING,CACHE_CTRL,Cache coherency probe latency exceeding limit.,CACHE_CTRL Cache coherency probe latency exceeding limit.,1
CRITICAL,MEM_CTRL,Uncorrectable ECC error on critical boot memory region,MEM_CTRL Uncorrectable ECC error on critical boot memory region,1
INFO,DDR_CTRL,DDR calibration completed with optimal settings,DDR_CTRL DDR calibration completed with optimal settings,1
ERROR,POWER_CTRL,Power supply voltage outside acceptable limits,POWER_CTRL Power supply voltage outside acceptable limits,4
ERROR,PCIE_CTRL,PCIe upstream port error detected,PCIE_CTRL PCIe upstream port error detected,6
ERROR,DMA_ENGINE,DMA channel 1 burst length violation detected.,DMA_ENGINE DMA channel 1 burst length violation detected.,3
INFO,FIFO_BUF,Handshake mechanism reset in FIFO_BUF.,FIFO_BUF Handshake mechanism reset in FIFO_BUF.,5
WARNING,POWER_CTRL,Current draw on rail VDD_CORE increasing rapidly,POWER_CTRL Current draw on rail VDD_CORE increasing rapidly,4
WARNING,CACHE_CTRL,Cache line ownership conflict detected,CACHE_CTRL Cache line ownership conflict detected,1
ERROR,AXI_CTRL,AXI write address channel timeout,AXI_CTRL AXI write address channel timeout,2
INFO,MEM_CTRL,Memory controller configured for ECC.,MEM_CTRL Memory controller configured for ECC.,1
WARNING,PCIE_CTRL,PCIe endpoint not responding to PME,PCIE_CTRL PCIe endpoint not responding to PME,6
WARNING,CLOCK_MANAGER,Clock source stability marginal.,CLOCK_MANAGER Clock source stability marginal.,0
ERROR,INTERRUPT_CTRL,Interrupt controller not responding to acknowledge,INTERRUPT_CTRL Interrupt controller not responding to acknowledge,1
WARNING,AXI_CTRL,AXI read outstanding transactions approaching limit,AXI_CTRL AXI read outstanding transactions approaching limit,2
INFO,PCIE_CTRL,Configuration space read,PCIE_CTRL Configuration space read,6
WARNING,INTERRUPT_CTRL,Interrupt pending register shows unmasked IRQ,INTERRUPT_CTRL Interrupt pending register shows unmasked IRQ,1
INFO,POWER_CTRL,Voltage rail VCC_CORE enabled successfully,POWER_CTRL Voltage rail VCC_CORE enabled successfully,4
INFO,DDR_CTRL,DDR controller operating in half-rate mode,DDR_CTRL DDR controller operating in half-rate mode,1
WARNING,FIFO_BUF,FIFO write pointer reaching end of buffer,FIFO_BUF FIFO write pointer reaching end of buffer,5
WARNING,INTERRUPT_CTRL,INTERRUPT_CTRL power domain transition taking longer than nominal.,INTERRUPT_CTRL INTERRUPT_CTRL power domain transition taking longer than nominal.,-1
ERROR,CACHE_CTRL,Cache coherence protocol violation on write-back,CACHE_CTRL Cache coherence protocol violation on write-back,1
INFO,POWER_CTRL,Core power domain successfully entered low-power state,POWER_CTRL Core power domain successfully entered low-power state,4
ERROR,FIFO_BUF,FIFO read attempt on empty buffer (underflow),FIFO_BUF FIFO read attempt on empty buffer (underflow),5
ERROR,CACHE_CTRL,Cache invalidate-all command failed,CACHE_CTRL Cache invalidate-all command failed,1
ERROR,DDR_CTRL,DDR memory device internal error,DDR_CTRL DDR memory device internal error,1
ERROR,PCIE_CTRL,PCIe Completer Abort (CA) received,PCIE_CTRL PCIe Completer Abort (CA) received,6
ERROR,POWER_CTRL,Voltage trip point exceeded,POWER_CTRL Voltage trip point exceeded,-1
ERROR,CLOCK_MANAGER,Clock gating logic detected a glitch on critical path,CLOCK_MANAGER Clock gating logic detected a glitch on critical path,0
WARNING,CLOCK_MANAGER,Clock gate activity factor unusually high,CLOCK_MANAGER Clock gate activity factor unusually high,-1
ERROR,DMA_ENGINE,DMA burst size exceeds configured maximum,DMA_ENGINE DMA burst size exceeds configured maximum,3
WARNING,DMA_ENGINE,DMA channel 9 burst transaction count unexpectedly low.,DMA_ENGINE DMA channel 9 burst transaction count unexpectedly low.,3
WARNING,AXI_CTRL,AXI write channel experiencing unexpected delays,AXI_CTRL AXI write channel experiencing unexpected delays,2
ERROR,CLOCK_MANAGER,Clock generation circuitry output voltage out of spec,CLOCK_MANAGER Clock generation circuitry output voltage out of spec,-1
INFO,MEM_CTRL,Memory scrubbing cycle initiated,MEM_CTRL Memory scrubbing cycle initiated,1
ERROR,MEM_CTRL,Memory controller state machine fault,MEM_CTRL Memory controller state machine fault,1
WARNING,INTERRUPT_CTRL,Interrupt controller processing backlog,INTERRUPT_CTRL Interrupt controller processing backlog,-1
INFO,PCIE_CTRL,Flow control credits exchanged,PCIE_CTRL Flow control credits exchanged,6
ERROR,AXI_CTRL,AXI read transaction timeout,AXI_CTRL AXI read transaction timeout,2
ERROR,FIFO_BUF,FIFO 'data_in_buffer' read after empty assertion failure,FIFO_BUF FIFO 'data_in_buffer' read after empty assertion failure,5
ERROR,INTERRUPT_CTRL,Interrupt controller asserted an unrequested interrupt,INTERRUPT_CTRL Interrupt controller asserted an unrequested interrupt,1
ERROR,AXI_CTRL,AXI write address channel transaction timeout detected.,AXI_CTRL AXI write address channel transaction timeout detected.,2
CRITICAL,POWER_CTRL,Power supply unit (PSU) failure,POWER_CTRL Power supply unit (PSU) failure,4
INFO,FIFO_BUF,FIFO reconfigured for wider data path,FIFO_BUF FIFO reconfigured for wider data path,5
ERROR,CLOCK_MANAGER,Clock recovery loop failed to stabilize,CLOCK_MANAGER Clock recovery loop failed to stabilize,0
INFO,FIFO_BUF,Data written to FIFO at address 0x1A,FIFO_BUF Data written to FIFO at address 0x1A,5
WARNING,FIFO_BUF,FIFO backpressure asserted due to downstream congestion,FIFO_BUF FIFO backpressure asserted due to downstream congestion,5
INFO,CLOCK_MANAGER,Secondary clock source enabled,CLOCK_MANAGER Secondary clock source enabled,0
ERROR,CLOCK_MANAGER,"PLL feedback path broken, frequency drifting","CLOCK_MANAGER PLL feedback path broken, frequency drifting",0
WARNING,AXI_CTRL,AXI outstanding read transactions nearing limit.,AXI_CTRL AXI outstanding read transactions nearing limit.,2
ERROR,PCIE_CTRL,PCIe unexpected completion with status 'Unsupported Request',PCIE_CTRL PCIe unexpected completion with status 'Unsupported Request',6
INFO,MEM_CTRL,Memory block accessed by CPU successfully,MEM_CTRL Memory block accessed by CPU successfully,1
INFO,CLOCK_MANAGER,Frequency measurement unit online,CLOCK_MANAGER Frequency measurement unit online,0
INFO,MEM_CTRL,Memory read from 0x7000_0000 returned expected data,MEM_CTRL Memory read from 0x7000_0000 returned expected data,1
CRITICAL,CACHE_CTRL,"Cache directory corrupted, unrecoverable data loss.","CACHE_CTRL Cache directory corrupted, unrecoverable data loss.",1
ERROR,PCIE_CTRL,PCIe configuration write failed for device 1:0:0,PCIE_CTRL PCIe configuration write failed for device 1:0:0,6
INFO,DDR_CTRL,DDR refresh cycle initiated,DDR_CTRL DDR refresh cycle initiated,1
INFO,POWER_CTRL,Standby power domain activated,POWER_CTRL Standby power domain activated,4
INFO,PCIE_CTRL,PCIe link speed switch to lower rate due to errors,PCIE_CTRL PCIe link speed switch to lower rate due to errors,6
INFO,DMA_ENGINE,DMA channel 2 pause request completed,DMA_ENGINE DMA channel 2 pause request completed,3
INFO,MEM_CTRL,Memory access error due to address alignment violation,MEM_CTRL Memory access error due to address alignment violation,1
INFO,FIFO_BUF,"FIFO write operation complete, 1 entry added","FIFO_BUF FIFO write operation complete, 1 entry added",5
ERROR,DMA_ENGINE,DMA transfer completion deadlock detected.,DMA_ENGINE DMA transfer completion deadlock detected.,3
CRITICAL,INTERRUPT_CTRL,Interrupt controller entered unrecoverable lockout state.,INTERRUPT_CTRL Interrupt controller entered unrecoverable lockout state.,1
ERROR,DDR_CTRL,DDR read data strobe timing violation,DDR_CTRL DDR read data strobe timing violation,1
ERROR,MEM_CTRL,Parity error detected on memory data bus,MEM_CTRL Parity error detected on memory data bus,1
INFO,DDR_CTRL,DDR memory bank 0 entered active state,DDR_CTRL DDR memory bank 0 entered active state,1
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lost lock, system unstable","CLOCK_MANAGER Clock generation PLL lost lock, system unstable",0
ERROR,MEM_CTRL,Memory address alignment violation for access type 'read',MEM_CTRL Memory address alignment violation for access type 'read',1
INFO,POWER_CTRL,Power domain isolation completed,POWER_CTRL Power domain isolation completed,4
CRITICAL,PCIE_CTRL,PCIe device hot-plug detection failure,PCIE_CTRL PCIe device hot-plug detection failure,6
WARNING,DDR_CTRL,DDR controller refresh counter out of sync,DDR_CTRL DDR controller refresh counter out of sync,1
WARNING,DDR_CTRL,DDR training sequence marginal results,DDR_CTRL DDR training sequence marginal results,1
WARNING,CLOCK_MANAGER,System reset output pulse width out of specification,CLOCK_MANAGER System reset output pulse width out of specification,-1
ERROR,POWER_CTRL,Core voltage rail current spike detected,POWER_CTRL Core voltage rail current spike detected,4
CRITICAL,CLOCK_MANAGER,Fatal clock synchronization failure,CLOCK_MANAGER Fatal clock synchronization failure,0
INFO,DMA_ENGINE,DMA channel 4 successfully paused,DMA_ENGINE DMA channel 4 successfully paused,3
INFO,MEM_CTRL,Memory region marked as cacheable,MEM_CTRL Memory region marked as cacheable,1
WARNING,CACHE_CTRL,Cache eviction policy causing thrashing.,CACHE_CTRL Cache eviction policy causing thrashing.,1
CRITICAL,DDR_CTRL,"DRAM device unresponsive to initialization commands, fatal error","DDR_CTRL DRAM device unresponsive to initialization commands, fatal error",1
ERROR,POWER_CTRL,Power sequence controller entered undefined state,POWER_CTRL Power sequence controller entered undefined state,4
INFO,POWER_CTRL,Power domain peripheral reset released,POWER_CTRL Power domain peripheral reset released,4
ERROR,POWER_CTRL,Voltage scaling down sequence stuck,POWER_CTRL Voltage scaling down sequence stuck,-1
WARNING,MEM_CTRL,Memory page table entry approaching limit,MEM_CTRL Memory page table entry approaching limit,1
WARNING,INTERRUPT_CTRL,Multiple interrupts pending for same priority level,INTERRUPT_CTRL Multiple interrupts pending for same priority level,1
ERROR,DDR_CTRL,DDR training sequence failed to establish stable write leveling,DDR_CTRL DDR training sequence failed to establish stable write leveling,1
ERROR,DMA_ENGINE,"DMA channel 2 arbitration failure, cannot gain bus access","DMA_ENGINE DMA channel 2 arbitration failure, cannot gain bus access",3
ERROR,CACHE_CTRL,Cache dirty bit inconsistency detected,CACHE_CTRL Cache dirty bit inconsistency detected,1
INFO,MEM_CTRL,Memory controller initialized in normal operation mode,MEM_CTRL Memory controller initialized in normal operation mode,1
CRITICAL,CLOCK_MANAGER,"Critical clock domain crossing bridge failed, data path broken","CLOCK_MANAGER Critical clock domain crossing bridge failed, data path broken",0
WARNING,FIFO_BUF,FIFO_read_data_ready assertion delayed,FIFO_BUF FIFO_read_data_ready assertion delayed,5
INFO,CACHE_CTRL,Cache statistics reset,CACHE_CTRL Cache statistics reset,1
INFO,DDR_CTRL,DDR VREF calibration updated,DDR_CTRL DDR VREF calibration updated,1
ERROR,CLOCK_MANAGER,"Clock generation PLL lock lost, frequency unstable","CLOCK_MANAGER Clock generation PLL lock lost, frequency unstable",0
WARNING,FIFO_BUF,FIFO read buffer nearing underflow condition,FIFO_BUF FIFO read buffer nearing underflow condition,5
WARNING,CLOCK_MANAGER,Clock signal quality degradation detected,CLOCK_MANAGER Clock signal quality degradation detected,0
INFO,POWER_CTRL,Power state transition to D1 completed,POWER_CTRL Power state transition to D1 completed,4
WARNING,CACHE_CTRL,Dirty cache lines writeback queue full,CACHE_CTRL Dirty cache lines writeback queue full,1
INFO,CLOCK_MANAGER,System clock frequency switched to 200MHz.,CLOCK_MANAGER System clock frequency switched to 200MHz.,0
WARNING,DMA_ENGINE,"DMA source address invalid, potential error","DMA_ENGINE DMA source address invalid, potential error",3
WARNING,DDR_CTRL,DDR training sequence marginal for certain parameters,DDR_CTRL DDR training sequence marginal for certain parameters,1
ERROR,FIFO_BUF,FIFO 'diagnostic_output' reported write pointer out of bounds,FIFO_BUF FIFO 'diagnostic_output' reported write pointer out of bounds,5
ERROR,AXI_CTRL,AXI response channel (RRESP) received SLVERR.,AXI_CTRL AXI response channel (RRESP) received SLVERR.,2
ERROR,AXI_CTRL,AXI write burst alignment violation,AXI_CTRL AXI write burst alignment violation,2
WARNING,CACHE_CTRL,Cache eviction rate is unusually high,CACHE_CTRL Cache eviction rate is unusually high,1
ERROR,DDR_CTRL,DDR memory controller's internal timer experienced overflow,DDR_CTRL DDR memory controller's internal timer experienced overflow,-1
WARNING,AXI_CTRL,AXI master 1 bus utilization exceeding threshold,AXI_CTRL AXI master 1 bus utilization exceeding threshold,2
ERROR,POWER_CTRL,Power-on sequence stalled on PGOOD assertion,POWER_CTRL Power-on sequence stalled on PGOOD assertion,4
CRITICAL,PCIE_CTRL,"PCIe lane synchronization lost, physical link down on lane 0x3","PCIE_CTRL PCIe lane synchronization lost, physical link down on lane 0x3",6
ERROR,CACHE_CTRL,Cache way selection error,CACHE_CTRL Cache way selection error,1
ERROR,INTERRUPT_CTRL,"Interrupt storm detected, rate 10k interrupts/sec.","INTERRUPT_CTRL Interrupt storm detected, rate 10k interrupts/sec.",1
WARNING,AXI_CTRL,AXI handshake delay approaching threshold for AWREADY,AXI_CTRL AXI handshake delay approaching threshold for AWREADY,2
INFO,FIFO_BUF,"FIFO overflow detected, but producer handled by backpressure","FIFO_BUF FIFO overflow detected, but producer handled by backpressure",5
INFO,CLOCK_MANAGER,Clock 'SYS_CLK' frequency set to 200MHz,CLOCK_MANAGER Clock 'SYS_CLK' frequency set to 200MHz,0
ERROR,POWER_CTRL,Voltage regulator VDD_DDR over-current protection tripped,POWER_CTRL Voltage regulator VDD_DDR over-current protection tripped,-1
ERROR,DMA_ENGINE,DMA_ENGINE: arbitration conflict - multiple requests granted simultaneously detected.,DMA_ENGINE DMA_ENGINE: arbitration conflict - multiple requests granted simultaneously detected.,3
ERROR,FIFO_BUF,FIFO read past valid data boundary (address 0x3),FIFO_BUF FIFO read past valid data boundary (address 0x3),5
WARNING,AXI_CTRL,AXI write channel idle for extended period (5000 cycles),AXI_CTRL AXI write channel idle for extended period (5000 cycles),2
ERROR,INTERRUPT_CTRL,INTERRUPT_CTRL: deadlock detected - circular dependency stall detected. (Conflicting IRQ IDs: 19 and 22),INTERRUPT_CTRL INTERRUPT_CTRL: deadlock detected - circular dependency stall detected. (Conflicting IRQ IDs: 19 and 22),-1
INFO,DDR_CTRL,DDR command issued,DDR_CTRL DDR command issued,1
WARNING,CLOCK_MANAGER,Clock signal integrity degradation on internal trace,CLOCK_MANAGER Clock signal integrity degradation on internal trace,0
INFO,POWER_CTRL,Power domain DDR activated,POWER_CTRL Power domain DDR activated,1
WARNING,AXI_CTRL,AXI response timeout on specific write ID,AXI_CTRL AXI response timeout on specific write ID,2
WARNING,AXI_CTRL,AXI write burst with unaligned address detected,AXI_CTRL AXI write burst with unaligned address detected,2
ERROR,PCIE_CTRL,PCIe Data Link Layer Packet (DLLP) error,PCIE_CTRL PCIe Data Link Layer Packet (DLLP) error,6
WARNING,DDR_CTRL,DDR command address parity error on read,DDR_CTRL DDR command address parity error on read,1
INFO,MEM_CTRL,ECC scrubber enabled,MEM_CTRL ECC scrubber enabled,1
CRITICAL,FIFO_BUF,"FIFO internal pointer desynchronization, leading to data loss.","FIFO_BUF FIFO internal pointer desynchronization, leading to data loss.",5
INFO,CACHE_CTRL,Cache line locked by processor,CACHE_CTRL Cache line locked by processor,1
CRITICAL,FIFO_BUF,FIFO state machine entered invalid state.,FIFO_BUF FIFO state machine entered invalid state.,5
ERROR,INTERRUPT_CTRL,Unhandled interrupt vector received,INTERRUPT_CTRL Unhandled interrupt vector received,1
ERROR,DDR_CTRL,DDR data bus inversion (DBI) error detected,DDR_CTRL DDR data bus inversion (DBI) error detected,-1
CRITICAL,CACHE_CTRL,Cache coherence protocol violation leading to data inconsistency,CACHE_CTRL Cache coherence protocol violation leading to data inconsistency,1
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on 'data_valid' signal,CLOCK_MANAGER Clock domain crossing synchronization failure on 'data_valid' signal,0
WARNING,MEM_CTRL,Single bit ECC error corrected by hardware,MEM_CTRL Single bit ECC error corrected by hardware,1
CRITICAL,MEM_CTRL,Memory protection unit (MPU) configuration corrupted during runtime,MEM_CTRL Memory protection unit (MPU) configuration corrupted during runtime,1
CRITICAL,PCIE_CTRL,PCIe link width negotiation failure,PCIE_CTRL PCIe link width negotiation failure,6
WARNING,FIFO_BUF,Read pointer approaching overflow condition due to slow consumer,FIFO_BUF Read pointer approaching overflow condition due to slow consumer,5
ERROR,FIFO_BUF,FIFO_BUF: buffer overflow - data loss due to overflow detected. (FIFO 'FIFO_BUF' Depth: 167),FIFO_BUF FIFO_BUF: buffer overflow - data loss due to overflow detected. (FIFO 'FIFO_BUF' Depth: 167),5
CRITICAL,POWER_CTRL,On-board power supply health monitor failure,POWER_CTRL On-board power supply health monitor failure,-1
INFO,MEM_CTRL,Memory page fault detected and handled,MEM_CTRL Memory page fault detected and handled,1
CRITICAL,FIFO_BUF,FIFO pointer logic entered illegal state,FIFO_BUF FIFO pointer logic entered illegal state,5
INFO,DMA_ENGINE,Scatter-gather DMA transfer completed for channel 3,DMA_ENGINE Scatter-gather DMA transfer completed for channel 3,3
ERROR,CLOCK_MANAGER,Asynchronous reset propagation failure across domain,CLOCK_MANAGER Asynchronous reset propagation failure across domain,0
ERROR,DDR_CTRL,DDR command timing violation: tRC_min not met,DDR_CTRL DDR command timing violation: tRC_min not met,1
CRITICAL,INTERRUPT_CTRL,"Interrupt storm detected, overwhelming CPU and causing system freeze","INTERRUPT_CTRL Interrupt storm detected, overwhelming CPU and causing system freeze",1
INFO,FIFO_BUF,"FIFO underflow detected, but consumer already handled empty state","FIFO_BUF FIFO underflow detected, but consumer already handled empty state",5
INFO,PCIE_CTRL,PCIe configuration space read initiated.,PCIE_CTRL PCIe configuration space read initiated.,6
INFO,DMA_ENGINE,Debug registers read for DMA_ENGINE.,DMA_ENGINE Debug registers read for DMA_ENGINE.,3
WARNING,FIFO_BUF,FIFO almost full,FIFO_BUF FIFO almost full,5
CRITICAL,MEM_CTRL,Multi-bit ECC error detected on memory bank 3,MEM_CTRL Multi-bit ECC error detected on memory bank 3,1
WARNING,CLOCK_MANAGER,Clock domain X frequency drift detected,CLOCK_MANAGER Clock domain X frequency drift detected,0
WARNING,DMA_ENGINE,DMA channel 6 pending request count high,DMA_ENGINE DMA channel 6 pending request count high,3
ERROR,AXI_CTRL,AXI protocol violation: multiple write responses,AXI_CTRL AXI protocol violation: multiple write responses,2
WARNING,DDR_CTRL,DDR refresh cycle delayed by high priority access,DDR_CTRL DDR refresh cycle delayed by high priority access,1
CRITICAL,CACHE_CTRL,System-wide data inconsistency due to cache failure,CACHE_CTRL System-wide data inconsistency due to cache failure,1
ERROR,DMA_ENGINE,DMA channel 3 descriptor chain corruption,DMA_ENGINE DMA channel 3 descriptor chain corruption,3
ERROR,POWER_CTRL,Voltage rail VDD_CORE current spike detected,POWER_CTRL Voltage rail VDD_CORE current spike detected,4
ERROR,MEM_CTRL,Memory read data mismatch after ECC correction,MEM_CTRL Memory read data mismatch after ECC correction,1
ERROR,DMA_ENGINE,DMA engine received malformed descriptor from software.,DMA_ENGINE DMA engine received malformed descriptor from software.,3
INFO,CACHE_CTRL,Cache prefetcher enabled,CACHE_CTRL Cache prefetcher enabled,1
WARNING,MEM_CTRL,Memory refresh interval misconfigured,MEM_CTRL Memory refresh interval misconfigured,1
INFO,CACHE_CTRL,Cache line write-back for 0xABCDE000 completed,CACHE_CTRL Cache line write-back for 0xABCDE000 completed,1
CRITICAL,DDR_CTRL,DDR memory bank conflict resulting in data loss,DDR_CTRL DDR memory bank conflict resulting in data loss,1
ERROR,AXI_CTRL,AXI bus matrix arbitration failure detected,AXI_CTRL AXI bus matrix arbitration failure detected,2
WARNING,AXI_CTRL,AXI transaction burst size mismatch,AXI_CTRL AXI transaction burst size mismatch,2
ERROR,CLOCK_MANAGER,Clock enable signal asserted asynchronously across clock domains.,CLOCK_MANAGER Clock enable signal asserted asynchronously across clock domains.,0
ERROR,INTERRUPT_CTRL,"Interrupt priority inversion detected, critical task delayed","INTERRUPT_CTRL Interrupt priority inversion detected, critical task delayed",1
WARNING,DDR_CTRL,DDR read latency exceeding expected value,DDR_CTRL DDR read latency exceeding expected value,1
WARNING,AXI_CTRL,AXI slave responded with `SLVERR` on valid request,AXI_CTRL AXI slave responded with `SLVERR` on valid request,2
CRITICAL,POWER_CTRL,Brown-out condition leading to reset loop,POWER_CTRL Brown-out condition leading to reset loop,4
CRITICAL,FIFO_BUF,Hard reset failed to clear FIFO errors,FIFO_BUF Hard reset failed to clear FIFO errors,5
ERROR,PCIE_CTRL,PCIe uncorrectable internal error detected by ECC logic,PCIE_CTRL PCIe uncorrectable internal error detected by ECC logic,6
CRITICAL,AXI_CTRL,AXI fatal bus error detected,AXI_CTRL AXI fatal bus error detected,2
CRITICAL,POWER_CTRL,Power rail sequencing failure during shutdown,POWER_CTRL Power rail sequencing failure during shutdown,4
INFO,DMA_ENGINE,DMA transfer completed without error,DMA_ENGINE DMA transfer completed without error,3
WARNING,FIFO_BUF,FIFO_NETWORK_RX buffer 90% full,FIFO_BUF FIFO_NETWORK_RX buffer 90% full,5
WARNING,POWER_CTRL,Power state transition sequence partially stalled,POWER_CTRL Power state transition sequence partially stalled,4
ERROR,FIFO_BUF,FIFO data mismatch after write/read cycle,FIFO_BUF FIFO data mismatch after write/read cycle,5
INFO,FIFO_BUF,FIFO initialized to default state,FIFO_BUF FIFO initialized to default state,5
WARNING,AXI_CTRL,AXI master `ARLEN` exceeding 16 beats for burst,AXI_CTRL AXI master `ARLEN` exceeding 16 beats for burst,2
WARNING,CLOCK_MANAGER,PLL lock time extended during recent reset sequence,CLOCK_MANAGER PLL lock time extended during recent reset sequence,0
WARNING,DMA_ENGINE,DMA burst size exceeds channel maximum recommended,DMA_ENGINE DMA burst size exceeds channel maximum recommended,3
WARNING,DMA_ENGINE,DMA channel X re-arbitrated,DMA_ENGINE DMA channel X re-arbitrated,3
WARNING,CACHE_CTRL,Number of dirty cache lines increasing rapidly,CACHE_CTRL Number of dirty cache lines increasing rapidly,1
CRITICAL,INTERRUPT_CTRL,"CRITICAL: Interrupt controller entered a non-maskable, unrecoverable state.","INTERRUPT_CTRL CRITICAL: Interrupt controller entered a non-maskable, unrecoverable state.",1
INFO,CACHE_CTRL,Cache hit detected for address 0xDEADBEEF.,CACHE_CTRL Cache hit detected for address 0xDEADBEEF.,1
CRITICAL,DMA_ENGINE,DMA channel 0 bus master interface permanently stuck,DMA_ENGINE DMA channel 0 bus master interface permanently stuck,3
CRITICAL,AXI_CTRL,AXI bus monitor detected permanent address phase stall,AXI_CTRL AXI bus monitor detected permanent address phase stall,2
CRITICAL,DDR_CTRL,DDR chip select line stuck in invalid state,DDR_CTRL DDR chip select line stuck in invalid state,-1
WARNING,DMA_ENGINE,Channel arbitration latency increasing,DMA_ENGINE Channel arbitration latency increasing,3
ERROR,POWER_CTRL,Voltage regulator thermal shutdown detected,POWER_CTRL Voltage regulator thermal shutdown detected,4
WARNING,DDR_CTRL,DDR write data eye margin decreasing.,DDR_CTRL DDR write data eye margin decreasing.,1
ERROR,CLOCK_MANAGER,PLL Y experienced a temporary unlock condition.,CLOCK_MANAGER PLL Y experienced a temporary unlock condition.,0
CRITICAL,AXI_CTRL,"AXI interconnect deadlock detected, system freeze","AXI_CTRL AXI interconnect deadlock detected, system freeze",2
WARNING,DMA_ENGINE,DMA queue latency increasing,DMA_ENGINE DMA queue latency increasing,3
ERROR,CLOCK_MANAGER,Clock domain crossing bridge experiencing data loss,CLOCK_MANAGER Clock domain crossing bridge experiencing data loss,0
CRITICAL,POWER_CTRL,Main power supply voltage deviation beyond tolerance,POWER_CTRL Main power supply voltage deviation beyond tolerance,-1
WARNING,POWER_CTRL,Power domain reset signal held active too long,POWER_CTRL Power domain reset signal held active too long,4
ERROR,DMA_ENGINE,DMA transfer timeout for channel 3,DMA_ENGINE DMA transfer timeout for channel 3,3
WARNING,CLOCK_MANAGER,Clock jitter detected on peripheral clock output,CLOCK_MANAGER Clock jitter detected on peripheral clock output,0
WARNING,CACHE_CTRL,Pre-fetch request pending,CACHE_CTRL Pre-fetch request pending,1
WARNING,DDR_CTRL,DDR memory ECC correctable errors increasing,DDR_CTRL DDR memory ECC correctable errors increasing,1
INFO,CACHE_CTRL,Cache dirty bit cleared,CACHE_CTRL Cache dirty bit cleared,1
ERROR,INTERRUPT_CTRL,Interrupt controller internal state register corrupted,INTERRUPT_CTRL Interrupt controller internal state register corrupted,1
INFO,MEM_CTRL,Memory access with byte enable violation,MEM_CTRL Memory access with byte enable violation,1
WARNING,CLOCK_MANAGER,Local clock frequency drifting from reference,CLOCK_MANAGER Local clock frequency drifting from reference,0
ERROR,MEM_CTRL,Memory controller internal bus arbitration deadlock,MEM_CTRL Memory controller internal bus arbitration deadlock,1
ERROR,DDR_CTRL,DDR command pipeline stall detected,DDR_CTRL DDR command pipeline stall detected,1
ERROR,CLOCK_MANAGER,Clock multiplexer output selected invalid source,CLOCK_MANAGER Clock multiplexer output selected invalid source,0
CRITICAL,PCIE_CTRL,"PCIe lane synchronization lost, link down (lane 6).","PCIE_CTRL PCIe lane synchronization lost, link down (lane 6).",6
CRITICAL,INTERRUPT_CTRL,"Interrupt cascade logic failure, unrecoverable state machine fault.","INTERRUPT_CTRL Interrupt cascade logic failure, unrecoverable state machine fault.",1
WARNING,FIFO_BUF,FIFO read data integrity check failed marginal,FIFO_BUF FIFO read data integrity check failed marginal,5
INFO,AXI_CTRL,AXI bus idle detected.,AXI_CTRL AXI bus idle detected.,2
INFO,DMA_ENGINE,DMA channel 6 configured for burst transfer,DMA_ENGINE DMA channel 6 configured for burst transfer,3
ERROR,DDR_CTRL,DDR memory training calibration sequence failed at step 7,DDR_CTRL DDR memory training calibration sequence failed at step 7,1
ERROR,PCIE_CTRL,PCIe unexpected completion without corresponding request,PCIE_CTRL PCIe unexpected completion without corresponding request,6
WARNING,DDR_CTRL,DDR memory temperature rising,DDR_CTRL DDR memory temperature rising,1
ERROR,INTERRUPT_CTRL,INTERRUPT_CTRL reported an unrecoverable internal arbitration conflict (Code: 0x8).,INTERRUPT_CTRL INTERRUPT_CTRL reported an unrecoverable internal arbitration conflict (Code: 0x8).,1
INFO,POWER_CTRL,Power domain VDD_GPU entered high performance state,POWER_CTRL Power domain VDD_GPU entered high performance state,4
INFO,FIFO_BUF,Write operation successful,FIFO_BUF Write operation successful,5
WARNING,AXI_CTRL,"AXI bus busy for extended period, potential bus contention.","AXI_CTRL AXI bus busy for extended period, potential bus contention.",2
ERROR,POWER_CTRL,Brownout detection triggered on periphery rail,POWER_CTRL Brownout detection triggered on periphery rail,4
WARNING,AXI_CTRL,AXI response channel latency exceeding soft limit,AXI_CTRL AXI response channel latency exceeding soft limit,2
INFO,CACHE_CTRL,Cache flush completed successfully,CACHE_CTRL Cache flush completed successfully,1
ERROR,DDR_CTRL,"DDR command queue depth exceeded, discarding requests","DDR_CTRL DDR command queue depth exceeded, discarding requests",1
WARNING,INTERRUPT_CTRL,Interrupt service routine latency exceeding expected value,INTERRUPT_CTRL Interrupt service routine latency exceeding expected value,1
WARNING,DMA_ENGINE,DMA transfer size approaching maximum supported,DMA_ENGINE DMA transfer size approaching maximum supported,3
INFO,AXI_CTRL,Command accepted,AXI_CTRL Command accepted,2
ERROR,MEM_CTRL,Memory write data parity error detected by external agent,MEM_CTRL Memory write data parity error detected by external agent,1
INFO,DDR_CTRL,DDR memory initialized,DDR_CTRL DDR memory initialized,1
WARNING,DMA_ENGINE,DMA channel request signal stuck high,DMA_ENGINE DMA channel request signal stuck high,3
WARNING,PCIE_CTRL,PCIe error reporting mechanism detected an internal error,PCIE_CTRL PCIe error reporting mechanism detected an internal error,6
ERROR,DMA_ENGINE,DMA channel data path parity error detected,DMA_ENGINE DMA channel data path parity error detected,3
WARNING,AXI_CTRL,AXI outstanding read transactions nearing limit of 16,AXI_CTRL AXI outstanding read transactions nearing limit of 16,2
INFO,PCIE_CTRL,PCIe PME event successfully asserted,PCIE_CTRL PCIe PME event successfully asserted,6
ERROR,PCIE_CTRL,"PCIe retry buffer nearing capacity, performance degradation","PCIE_CTRL PCIe retry buffer nearing capacity, performance degradation",6
ERROR,PCIE_CTRL,PCIe Hot Plug Controller state machine fault,PCIE_CTRL PCIe Hot Plug Controller state machine fault,6
INFO,PCIE_CTRL,PCIe link established successfully at Gen5 x8,PCIE_CTRL PCIe link established successfully at Gen5 x8,6
CRITICAL,POWER_CTRL,Power regulator short circuit detected,POWER_CTRL Power regulator short circuit detected,-1
INFO,INTERRUPT_CTRL,Interrupt controller configuration loaded from EEPROM,INTERRUPT_CTRL Interrupt controller configuration loaded from EEPROM,-1
ERROR,DDR_CTRL,DDR write data group timing violation on DQS to DQ,DDR_CTRL DDR write data group timing violation on DQS to DQ,1
WARNING,PCIE_CTRL,PCIe link state transitions occurring frequently,PCIE_CTRL PCIe link state transitions occurring frequently,6
CRITICAL,DDR_CTRL,DDR controller internal state machine hung,DDR_CTRL DDR controller internal state machine hung,1
WARNING,INTERRUPT_CTRL,Interrupt request from disabled source.,INTERRUPT_CTRL Interrupt request from disabled source.,1
WARNING,FIFO_BUF,FIFO almost_full assertion de-asserted,FIFO_BUF FIFO almost_full assertion de-asserted,5
INFO,DMA_ENGINE,DMA transfer on channel 13 completed successfully,DMA_ENGINE DMA transfer on channel 13 completed successfully,3
CRITICAL,POWER_CTRL,"Power rail overcurrent detected, system shutdown","POWER_CTRL Power rail overcurrent detected, system shutdown",4
ERROR,AXI_CTRL,AXI slave port stuck in busy state,AXI_CTRL AXI slave port stuck in busy state,2
CRITICAL,AXI_CTRL,"AXI master 1 hung indefinitely, no transactions possible","AXI_CTRL AXI master 1 hung indefinitely, no transactions possible",2
ERROR,CLOCK_MANAGER,Clock generation PLL phase error exceeding tolerance,CLOCK_MANAGER Clock generation PLL phase error exceeding tolerance,0
CRITICAL,FIFO_BUF,FIFO internal state machine reset failure,FIFO_BUF FIFO internal state machine reset failure,5
WARNING,DDR_CTRL,DDR memory controller command queue depth above 90%,DDR_CTRL DDR memory controller command queue depth above 90%,1
WARNING,MEM_CTRL,Memory access patterns causing high page-miss rate,MEM_CTRL Memory access patterns causing high page-miss rate,1
CRITICAL,POWER_CTRL,System power grid instability detected by on-chip monitor,POWER_CTRL System power grid instability detected by on-chip monitor,4
ERROR,MEM_CTRL,Memory controller arbitration conflict detected,MEM_CTRL Memory controller arbitration conflict detected,1
WARNING,DDR_CTRL,DDR command reordering delay exceeding expected,DDR_CTRL DDR command reordering delay exceeding expected,1
CRITICAL,PCIE_CTRL,PCIe physical layer link equalization failure,PCIE_CTRL PCIe physical layer link equalization failure,6
WARNING,FIFO_BUF,Read latency increased.,FIFO_BUF Read latency increased.,5
WARNING,POWER_CTRL,"Voltage rail X fluctuation detected, minor instability.","POWER_CTRL Voltage rail X fluctuation detected, minor instability.",4
ERROR,MEM_CTRL,"Single bit ECC corruption detected, corrected","MEM_CTRL Single bit ECC corruption detected, corrected",1
WARNING,AXI_CTRL,"AXI slave response slow, wait states inserted.","AXI_CTRL AXI slave response slow, wait states inserted.",2
INFO,MEM_CTRL,Memory controller entering idle state.,MEM_CTRL Memory controller entering idle state.,1
CRITICAL,DMA_ENGINE,DMA engine halted due to unrecoverable internal state,DMA_ENGINE DMA engine halted due to unrecoverable internal state,3
INFO,PCIE_CTRL,PCIe transaction acknowledged,PCIE_CTRL PCIe transaction acknowledged,6
WARNING,AXI_CTRL,AXI response channel congestion detected,AXI_CTRL AXI response channel congestion detected,2
ERROR,PCIE_CTRL,PCIe packet framing error detected,PCIE_CTRL PCIe packet framing error detected,6
ERROR,CLOCK_MANAGER,Clock distribution network power rail instability,CLOCK_MANAGER Clock distribution network power rail instability,0
INFO,INTERRUPT_CTRL,Interrupt request line IRQ_ETH asserted,INTERRUPT_CTRL Interrupt request line IRQ_ETH asserted,1
INFO,POWER_CTRL,Voltage regulator output stable at 1.1V,POWER_CTRL Voltage regulator output stable at 1.1V,4
INFO,INTERRUPT_CTRL,Interrupt controller in low-power sleep mode,INTERRUPT_CTRL Interrupt controller in low-power sleep mode,-1
INFO,MEM_CTRL,Memory write protection enabled for region 0x0-0xFFF,MEM_CTRL Memory write protection enabled for region 0x0-0xFFF,1
WARNING,AXI_CTRL,AXI slave response delay exceeding expected threshold,AXI_CTRL AXI slave response delay exceeding expected threshold,2
WARNING,POWER_CTRL,Temperature sensor reading high,POWER_CTRL Temperature sensor reading high,4
ERROR,DMA_ENGINE,DMA engine unable to acquire bus mastership,DMA_ENGINE DMA engine unable to acquire bus mastership,3
INFO,CACHE_CTRL,Cache line write-back completed to main memory,CACHE_CTRL Cache line write-back completed to main memory,1
WARNING,DMA_ENGINE,DMA channel 0 paused due to external memory contention.,DMA_ENGINE DMA channel 0 paused due to external memory contention.,3
CRITICAL,FIFO_BUF,FIFO bypass path corruption leading to critical data loss,FIFO_BUF FIFO bypass path corruption leading to critical data loss,5
WARNING,AXI_CTRL,AXI read channel backpressure asserted by slave,AXI_CTRL AXI read channel backpressure asserted by slave,2
ERROR,POWER_CTRL,Voltage regulator over-current protection tripped on VDD_GPU.,POWER_CTRL Voltage regulator over-current protection tripped on VDD_GPU.,-1
INFO,FIFO_BUF,FIFO reset operation completed,FIFO_BUF FIFO reset operation completed,5
INFO,CACHE_CTRL,Cache line for address 0xDEADBEEF flushed,CACHE_CTRL Cache line for address 0xDEADBEEF flushed,1
ERROR,POWER_CTRL,Power sequence state machine entered invalid state,POWER_CTRL Power sequence state machine entered invalid state,4
WARNING,DDR_CTRL,DDR write queue depth consistently high,DDR_CTRL DDR write queue depth consistently high,1
CRITICAL,MEM_CTRL,Memory integrity check failed during boot sequence,MEM_CTRL Memory integrity check failed during boot sequence,1
CRITICAL,MEM_CTRL,Memory ECC multi-bit uncorrectable error detected,MEM_CTRL Memory ECC multi-bit uncorrectable error detected,1
INFO,AXI_CTRL,Burst read of 32 bytes from 0x1000 completed,AXI_CTRL Burst read of 32 bytes from 0x1000 completed,2
WARNING,AXI_CTRL,AXI read address channel stall detected,AXI_CTRL AXI read address channel stall detected,2
INFO,CACHE_CTRL,Cache line invalidated and written back,CACHE_CTRL Cache line invalidated and written back,1
INFO,MEM_CTRL,Memory controller pipeline flushed,MEM_CTRL Memory controller pipeline flushed,1
INFO,MEM_CTRL,Memory region protected,MEM_CTRL Memory region protected,1
WARNING,CACHE_CTRL,Cache line invalidation delay,CACHE_CTRL Cache line invalidation delay,1
ERROR,CACHE_CTRL,Cache data integrity check failed on block X,CACHE_CTRL Cache data integrity check failed on block X,1
ERROR,MEM_CTRL,Memory access violation from master 12 to 0x18ed179b.,MEM_CTRL Memory access violation from master 12 to 0x18ed179b.,1
INFO,FIFO_BUF,FIFO depth reconfigured to 2048,FIFO_BUF FIFO depth reconfigured to 2048,5
CRITICAL,POWER_CTRL,Voltage supply to critical analog block failed,POWER_CTRL Voltage supply to critical analog block failed,-1
INFO,PCIE_CTRL,PCIE_CTRL self-test passed.,PCIE_CTRL PCIE_CTRL self-test passed.,6
ERROR,AXI_CTRL,"AXI_CTRL: bus contention - multiple masters asserting bus ownership detected. (Master ID: 0, AXI ID: 15)","AXI_CTRL AXI_CTRL: bus contention - multiple masters asserting bus ownership detected. (Master ID: 0, AXI ID: 15)",2
CRITICAL,MEM_CTRL,Data bus stuck-at fault identified,MEM_CTRL Data bus stuck-at fault identified,1
ERROR,CACHE_CTRL,Cache write buffer entry lost due to eviction policy error,CACHE_CTRL Cache write buffer entry lost due to eviction policy error,1
ERROR,PCIE_CTRL,PCIe completion timeout on outbound transaction,PCIE_CTRL PCIe completion timeout on outbound transaction,6
INFO,PCIE_CTRL,PCIe ASPM L1 state entered,PCIE_CTRL PCIe ASPM L1 state entered,6
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance on peripheral clock.,CLOCK_MANAGER Clock jitter exceeding tolerance on peripheral clock.,0
ERROR,PCIE_CTRL,PCIe device enumeration failed,PCIE_CTRL PCIe device enumeration failed,6
WARNING,POWER_CTRL,Voltage regulator response time close to threshold.,POWER_CTRL Voltage regulator response time close to threshold.,4
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal data corruption detected,INTERRUPT_CTRL Interrupt controller internal data corruption detected,1
ERROR,CLOCK_MANAGER,Clock source switch resulted in a transient glitch,CLOCK_MANAGER Clock source switch resulted in a transient glitch,0
WARNING,AXI_CTRL,AXI write response channel `BVALID` asserted without `BREADY`,AXI_CTRL AXI write response channel `BVALID` asserted without `BREADY`,2
WARNING,DDR_CTRL,DDR calibration retry limit reached,DDR_CTRL DDR calibration retry limit reached,1
INFO,INTERRUPT_CTRL,Interrupt affinity set for core 1,INTERRUPT_CTRL Interrupt affinity set for core 1,-1
ERROR,DMA_ENGINE,DMA target address beyond memory boundary,DMA_ENGINE DMA target address beyond memory boundary,3
ERROR,DMA_ENGINE,DMA write channel data corruption,DMA_ENGINE DMA write channel data corruption,3
ERROR,INTERRUPT_CTRL,Spurious interrupt detected on IRQ line 7.,INTERRUPT_CTRL Spurious interrupt detected on IRQ line 7.,1
ERROR,FIFO_BUF,FIFO pointer race condition detected during simultaneous access,FIFO_BUF FIFO pointer race condition detected during simultaneous access,5
ERROR,FIFO_BUF,FIFO read pointer overflow,FIFO_BUF FIFO read pointer overflow,5
CRITICAL,MEM_CTRL,Uncorrectable error in memory mapped I/O region,MEM_CTRL Uncorrectable error in memory mapped I/O region,1
INFO,POWER_CTRL,System powered up from standby,POWER_CTRL System powered up from standby,4
ERROR,POWER_CTRL,Voltage regulator output out of specification,POWER_CTRL Voltage regulator output out of specification,4
ERROR,CACHE_CTRL,Cache tag parity error detected for set 79.,CACHE_CTRL Cache tag parity error detected for set 79.,1
ERROR,AXI_CTRL,AXI read data bus error detected,AXI_CTRL AXI read data bus error detected,2
CRITICAL,INTERRUPT_CTRL,Interrupt controller state machine entered an invalid state.,INTERRUPT_CTRL Interrupt controller state machine entered an invalid state.,1
CRITICAL,DMA_ENGINE,"DMA clock domain crossing failure, data loss expected.","DMA_ENGINE DMA clock domain crossing failure, data loss expected.",-1
INFO,POWER_CTRL,Power domain isolation active,POWER_CTRL Power domain isolation active,4
WARNING,CACHE_CTRL,"Cache eviction queue size critical, nearing capacity.","CACHE_CTRL Cache eviction queue size critical, nearing capacity.",1
ERROR,DDR_CTRL,"Memory address decoding fault, accessed address outside of valid range.","DDR_CTRL Memory address decoding fault, accessed address outside of valid range.",1
ERROR,DDR_CTRL,DDR training sequence failed for bank 0,DDR_CTRL DDR training sequence failed for bank 0,1
INFO,CACHE_CTRL,Cache line filled from main memory,CACHE_CTRL Cache line filled from main memory,1
INFO,AXI_CTRL,AXI transaction acknowledged by slave 0x1A,AXI_CTRL AXI transaction acknowledged by slave 0x1A,2
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on path RST_async,CLOCK_MANAGER Clock domain crossing synchronization failure on path RST_async,0
WARNING,PCIE_CTRL,PCIe retry buffer nearing capacity for endpoint 0x01:0x00.,PCIE_CTRL PCIe retry buffer nearing capacity for endpoint 0x01:0x00.,6
WARNING,CLOCK_MANAGER,PLL lock time exceeding specification during warm reset,CLOCK_MANAGER PLL lock time exceeding specification during warm reset,0
WARNING,DDR_CTRL,DDR access latency jitter detected,DDR_CTRL DDR access latency jitter detected,1
WARNING,DMA_ENGINE,DMA read channel high latency,DMA_ENGINE DMA read channel high latency,3
CRITICAL,MEM_CTRL,Uncorrectable double-bit error on memory address 0x30000000,MEM_CTRL Uncorrectable double-bit error on memory address 0x30000000,1
CRITICAL,POWER_CTRL,Power rail sequencing interlock failure,POWER_CTRL Power rail sequencing interlock failure,4
WARNING,DMA_ENGINE,DMA controller arbitration conflict detected between channels.,DMA_ENGINE DMA controller arbitration conflict detected between channels.,3
INFO,DMA_ENGINE,DMA channel 3 descriptor fetch initiated,DMA_ENGINE DMA channel 3 descriptor fetch initiated,3
ERROR,MEM_CTRL,Memory controller data path error,MEM_CTRL Memory controller data path error,1
ERROR,AXI_CTRL,AXI burst length violation detected on master 2,AXI_CTRL AXI burst length violation detected on master 2,2
CRITICAL,PCIE_CTRL,PCIe link training sequence stalled,PCIE_CTRL PCIe link training sequence stalled,6
CRITICAL,POWER_CTRL,"CRITICAL: System power supply failure detected, system shutdown.","POWER_CTRL CRITICAL: System power supply failure detected, system shutdown.",4
ERROR,AXI_CTRL,AXI write data channel WSTRB signal asserted incorrectly,AXI_CTRL AXI write data channel WSTRB signal asserted incorrectly,-1
ERROR,FIFO_BUF,FIFO almost full condition persistent for too long.,FIFO_BUF FIFO almost full condition persistent for too long.,5
INFO,DMA_ENGINE,DMA channel 12 transfer ongoing,DMA_ENGINE DMA channel 12 transfer ongoing,3
INFO,CACHE_CTRL,Cache invalidate operation completed,CACHE_CTRL Cache invalidate operation completed,1
CRITICAL,INTERRUPT_CTRL,"Critical interrupt pending for too long, watchdog triggered","INTERRUPT_CTRL Critical interrupt pending for too long, watchdog triggered",1
WARNING,AXI_CTRL,AXI response channel (BRESP) indicating a slave error,AXI_CTRL AXI response channel (BRESP) indicating a slave error,2
INFO,DMA_ENGINE,DMA channel X activated.,DMA_ENGINE DMA channel X activated.,3
ERROR,CACHE_CTRL,Cache directory lookup failure,CACHE_CTRL Cache directory lookup failure,1
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for IRQ 0x0,INTERRUPT_CTRL Interrupt dispatch completed for IRQ 0x0,1
WARNING,INTERRUPT_CTRL,Interrupt handler execution time exceeding threshold for IRQ 8,INTERRUPT_CTRL Interrupt handler execution time exceeding threshold for IRQ 8,1
INFO,PCIE_CTRL,PCIe endpoint successfully configured,PCIE_CTRL PCIe endpoint successfully configured,6
INFO,CACHE_CTRL,Cache Line Way-selection successful,CACHE_CTRL Cache Line Way-selection successful,1
WARNING,INTERRUPT_CTRL,Interrupt coalescing queue approaching overflow,INTERRUPT_CTRL Interrupt coalescing queue approaching overflow,1
ERROR,DMA_ENGINE,DMA block transfer misaligned address access,DMA_ENGINE DMA block transfer misaligned address access,3
ERROR,CLOCK_MANAGER,Clock phase error detected on output PLL,CLOCK_MANAGER Clock phase error detected on output PLL,0
ERROR,MEM_CTRL,Read-modify-write operation on protected memory failed,MEM_CTRL Read-modify-write operation on protected memory failed,1
INFO,FIFO_BUF,Read pointer advanced successfully,FIFO_BUF Read pointer advanced successfully,5
INFO,CACHE_CTRL,Cache way partitioning enabled,CACHE_CTRL Cache way partitioning enabled,-1
WARNING,INTERRUPT_CTRL,"Stale interrupt pending after acknowledgement, checking for race condition for IRQ 0x2","INTERRUPT_CTRL Stale interrupt pending after acknowledgement, checking for race condition for IRQ 0x2",1
WARNING,DDR_CTRL,DDR calibration parameter drift observed,DDR_CTRL DDR calibration parameter drift observed,1
INFO,PCIE_CTRL,PCIe power management event PME_Turn_Off detected,PCIE_CTRL PCIe power management event PME_Turn_Off detected,6
INFO,CACHE_CTRL,Cache miss rate within acceptable bounds,CACHE_CTRL Cache miss rate within acceptable bounds,1
ERROR,FIFO_BUF,FIFO full status not deasserting after read,FIFO_BUF FIFO full status not deasserting after read,5
ERROR,FIFO_BUF,FIFO full status asserted unexpectedly,FIFO_BUF FIFO full status asserted unexpectedly,5
CRITICAL,DMA_ENGINE,DMA engine unable to release bus due to internal error,DMA_ENGINE DMA engine unable to release bus due to internal error,3
ERROR,PCIE_CTRL,PCIe hotplug event detection failure,PCIE_CTRL PCIe hotplug event detection failure,6
INFO,CACHE_CTRL,Instruction cache prefetcher enabled,CACHE_CTRL Instruction cache prefetcher enabled,1
CRITICAL,MEM_CTRL,Memory controller state machine entered an unrecoverable error state.,MEM_CTRL Memory controller state machine entered an unrecoverable error state.,1
ERROR,CACHE_CTRL,"Cache miss rate too high, thrashing detected","CACHE_CTRL Cache miss rate too high, thrashing detected",1
ERROR,FIFO_BUF,"FIFO synchronization error detected, CDC failure.","FIFO_BUF FIFO synchronization error detected, CDC failure.",5
INFO,FIFO_BUF,Data burst pushed to FIFO,FIFO_BUF Data burst pushed to FIFO,5
CRITICAL,CACHE_CTRL,Cache tag array hardware failure,CACHE_CTRL Cache tag array hardware failure,1
ERROR,CACHE_CTRL,Cache state machine entered illegal state,CACHE_CTRL Cache state machine entered illegal state,1
ERROR,DMA_ENGINE,DMA controller arbitration conflict,DMA_ENGINE DMA controller arbitration conflict,3
CRITICAL,FIFO_BUF,Unrecoverable FIFO state machine error,FIFO_BUF Unrecoverable FIFO state machine error,5
WARNING,PCIE_CTRL,PCIe link state oscillating between L0 and L1,PCIE_CTRL PCIe link state oscillating between L0 and L1,6
ERROR,FIFO_BUF,FIFO_BUF: buffer underflow - read from empty buffer detected. (FIFO 'FIFO_BUF' Depth: 18),FIFO_BUF FIFO_BUF: buffer underflow - read from empty buffer detected. (FIFO 'FIFO_BUF' Depth: 18),5
ERROR,PCIE_CTRL,"PCIe flow control credits exhausted, transaction stalled","PCIE_CTRL PCIe flow control credits exhausted, transaction stalled",6
WARNING,CACHE_CTRL,Cache replacement policy thrashing,CACHE_CTRL Cache replacement policy thrashing,1
WARNING,POWER_CTRL,Power domain X transition delay detected,POWER_CTRL Power domain X transition delay detected,4
WARNING,MEM_CTRL,Memory controller arbitration contention observed,MEM_CTRL Memory controller arbitration contention observed,1
CRITICAL,DMA_ENGINE,"DMA buffer descriptor list corrupted, unrecoverable transfer","DMA_ENGINE DMA buffer descriptor list corrupted, unrecoverable transfer",3
ERROR,INTERRUPT_CTRL,Interrupt routing table invalid entry detected.,INTERRUPT_CTRL Interrupt routing table invalid entry detected.,1
ERROR,DDR_CTRL,DDR refresh sequence abort,DDR_CTRL DDR refresh sequence abort,1
CRITICAL,POWER_CTRL,Power domain isolation logic failed during transition,POWER_CTRL Power domain isolation logic failed during transition,4
WARNING,PCIE_CTRL,PCIe transaction latency exceeding expected range,PCIE_CTRL PCIe transaction latency exceeding expected range,6
CRITICAL,POWER_CTRL,Voltage regulator output failed to reach target voltage,POWER_CTRL Voltage regulator output failed to reach target voltage,4
ERROR,FIFO_BUF,FIFO control logic state machine fault.,FIFO_BUF FIFO control logic state machine fault.,5
ERROR,PCIE_CTRL,PCIe device hot-reset failed to complete,PCIE_CTRL PCIe device hot-reset failed to complete,6
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe limits on core clock,CLOCK_MANAGER Clock skew approaching unsafe limits on core clock,0
WARNING,INTERRUPT_CTRL,Interrupt 15 asserted for an extended duration.,INTERRUPT_CTRL Interrupt 15 asserted for an extended duration.,-1
WARNING,POWER_CTRL,Current consumption nearing limit.,POWER_CTRL Current consumption nearing limit.,4
INFO,PCIE_CTRL,PCIe TLP posted completion received,PCIE_CTRL PCIe TLP posted completion received,6
CRITICAL,PCIE_CTRL,CRITICAL: PCIe link layer re-training initiated due to catastrophic failure.,PCIE_CTRL CRITICAL: PCIe link layer re-training initiated due to catastrophic failure.,6
WARNING,PCIE_CTRL,PCIe TLP retry count for failed transactions is high,PCIE_CTRL PCIe TLP retry count for failed transactions is high,6
INFO,DMA_ENGINE,"DMA channel 18 idle, waiting for descriptors","DMA_ENGINE DMA channel 18 idle, waiting for descriptors",3
WARNING,DMA_ENGINE,DMA channel 2 high priority request denied,DMA_ENGINE DMA channel 2 high priority request denied,3
CRITICAL,PCIE_CTRL,PCIe fatal error detected on downstream port,PCIE_CTRL PCIe fatal error detected on downstream port,6
CRITICAL,FIFO_BUF,"FIFO control logic deadlock, cannot enqueue or dequeue data","FIFO_BUF FIFO control logic deadlock, cannot enqueue or dequeue data",5
WARNING,DDR_CTRL,DDR temperature sensor above normal operating range,DDR_CTRL DDR temperature sensor above normal operating range,1
ERROR,DDR_CTRL,DRAM bank conflict detected,DDR_CTRL DRAM bank conflict detected,1
WARNING,DMA_ENGINE,"DMA transfer progress slower than expected, potential bottleneck","DMA_ENGINE DMA transfer progress slower than expected, potential bottleneck",3
CRITICAL,POWER_CTRL,System power rail overcurrent protection disabled unintentionally,POWER_CTRL System power rail overcurrent protection disabled unintentionally,4
CRITICAL,CLOCK_MANAGER,System clock frequency deviation detected,CLOCK_MANAGER System clock frequency deviation detected,0
ERROR,CACHE_CTRL,Cache dirty line count mismatch after flush,CACHE_CTRL Cache dirty line count mismatch after flush,1
WARNING,INTERRUPT_CTRL,Edge-triggered interrupt spurious assertion,INTERRUPT_CTRL Edge-triggered interrupt spurious assertion,1
INFO,INTERRUPT_CTRL,Interrupt handler registered,INTERRUPT_CTRL Interrupt handler registered,1
INFO,DDR_CTRL,DDR memory training phase 3 completed.,DDR_CTRL DDR memory training phase 3 completed.,1
ERROR,DMA_ENGINE,DMA buffer descriptor chain end marker missing,DMA_ENGINE DMA buffer descriptor chain end marker missing,3
CRITICAL,CLOCK_MANAGER,Primary clock signal absent,CLOCK_MANAGER Primary clock signal absent,0
INFO,FIFO_BUF,"FIFO status register polled: not empty, not full.","FIFO_BUF FIFO status register polled: not empty, not full.",5
INFO,FIFO_BUF,"Write operation successful, FIFO not yet full.","FIFO_BUF Write operation successful, FIFO not yet full.",5
WARNING,INTERRUPT_CTRL,Interrupt controller software configuration mismatch with hardware mask Z.,INTERRUPT_CTRL Interrupt controller software configuration mismatch with hardware mask Z.,1
ERROR,CACHE_CTRL,Cache tag ECC uncorrectable error,CACHE_CTRL Cache tag ECC uncorrectable error,1
WARNING,AXI_CTRL,AXI interconnect arbitration conflict detected on AW channel,AXI_CTRL AXI interconnect arbitration conflict detected on AW channel,2
ERROR,POWER_CTRL,Power good signal asserted incorrectly,POWER_CTRL Power good signal asserted incorrectly,4
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL clock gate enabled.,INTERRUPT_CTRL INTERRUPT_CTRL clock gate enabled.,1
ERROR,DMA_ENGINE,DMA channel arbitration failure detected for channel 0.,DMA_ENGINE DMA channel arbitration failure detected for channel 0.,3
CRITICAL,DMA_ENGINE,DMA engine unable to complete descriptor fetch,DMA_ENGINE DMA engine unable to complete descriptor fetch,3
INFO,MEM_CTRL,Memory controller idle state entered,MEM_CTRL Memory controller idle state entered,1
INFO,CACHE_CTRL,Cache 'data_cache_0' flush operation completed,CACHE_CTRL Cache 'data_cache_0' flush operation completed,1
WARNING,PCIE_CTRL,PCIe device re-enumeration in progress,PCIE_CTRL PCIe device re-enumeration in progress,6
CRITICAL,CACHE_CTRL,L1 cache critical path timing violation,CACHE_CTRL L1 cache critical path timing violation,1
CRITICAL,POWER_CTRL,Power rail sequencing failure,POWER_CTRL Power rail sequencing failure,4
ERROR,CACHE_CTRL,Cache fill operation data integrity check failed,CACHE_CTRL Cache fill operation data integrity check failed,1
WARNING,DDR_CTRL,DDR read data bus contention detected,DDR_CTRL DDR read data bus contention detected,1
INFO,CLOCK_MANAGER,Clock manager status nominal,CLOCK_MANAGER Clock manager status nominal,-1
ERROR,FIFO_BUF,FIFO read past valid data boundary,FIFO_BUF FIFO read past valid data boundary,5
WARNING,AXI_CTRL,AXI bus contention detected on shared interconnect,AXI_CTRL AXI bus contention detected on shared interconnect,2
ERROR,INTERRUPT_CTRL,Interrupt pending status conflicting with active status,INTERRUPT_CTRL Interrupt pending status conflicting with active status,1
WARNING,CACHE_CTRL,CACHE_CTRL power domain transition taking longer than nominal.,CACHE_CTRL CACHE_CTRL power domain transition taking longer than nominal.,-1
INFO,POWER_CTRL,Power regulator output voltage checked,POWER_CTRL Power regulator output voltage checked,4
CRITICAL,FIFO_BUF,"FIFO synchronization logic entered illegal state, data lost","FIFO_BUF FIFO synchronization logic entered illegal state, data lost",5
WARNING,PCIE_CTRL,PCIe link retraining initiated due to signal integrity issues,PCIE_CTRL PCIe link retraining initiated due to signal integrity issues,6
WARNING,AXI_CTRL,AXI read address channel latency high,AXI_CTRL AXI read address channel latency high,2
WARNING,CACHE_CTRL,Cache line invalidation queue backlog,CACHE_CTRL Cache line invalidation queue backlog,1
ERROR,INTERRUPT_CTRL,Interrupt controller configuration error,INTERRUPT_CTRL Interrupt controller configuration error,1
ERROR,DMA_ENGINE,DMA channel address translation fault,DMA_ENGINE DMA channel address translation fault,3
INFO,CLOCK_MANAGER,Secondary clock generator enabled,CLOCK_MANAGER Secondary clock generator enabled,0
INFO,POWER_CTRL,Power-on reset deasserted,POWER_CTRL Power-on reset deasserted,4
INFO,FIFO_BUF,FIFO pass-through mode enabled,FIFO_BUF FIFO pass-through mode enabled,-1
INFO,FIFO_BUF,FIFO buffer flushed,FIFO_BUF FIFO buffer flushed,5
ERROR,MEM_CTRL,Memory controller read data CRC error detected,MEM_CTRL Memory controller read data CRC error detected,1
INFO,DMA_ENGINE,DMA transfer to peripheral completed,DMA_ENGINE DMA transfer to peripheral completed,3
WARNING,DMA_ENGINE,DMA channel 5 data buffer nearly full,DMA_ENGINE DMA channel 5 data buffer nearly full,3
WARNING,DMA_ENGINE,DMA channel 1 burst size configuration non-optimal.,DMA_ENGINE DMA channel 1 burst size configuration non-optimal.,3
WARNING,CLOCK_MANAGER,"Clock skew approaching unsafe range, timing violation detected.","CLOCK_MANAGER Clock skew approaching unsafe range, timing violation detected.",0
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding expected limits,INTERRUPT_CTRL Interrupt latency exceeding expected limits,1
CRITICAL,MEM_CTRL,Read/Write access to protected memory region,MEM_CTRL Read/Write access to protected memory region,1
ERROR,POWER_CTRL,Power supply monitoring unit reports failure,POWER_CTRL Power supply monitoring unit reports failure,4
INFO,CLOCK_MANAGER,JTAG clock bypass enabled,CLOCK_MANAGER JTAG clock bypass enabled,-1
ERROR,MEM_CTRL,Memory array data bit flip detected,MEM_CTRL Memory array data bit flip detected,1
WARNING,AXI_CTRL,AXI master 0x02 is holding the bus for extended periods,AXI_CTRL AXI master 0x02 is holding the bus for extended periods,2
ERROR,MEM_CTRL,Memory write protection violation for address 0xDEADBEEF,MEM_CTRL Memory write protection violation for address 0xDEADBEEF,1
INFO,FIFO_BUF,"Write operation successful, 16 bytes added","FIFO_BUF Write operation successful, 16 bytes added",5
ERROR,CLOCK_MANAGER,Clock domain crossing FIFO overflow,CLOCK_MANAGER Clock domain crossing FIFO overflow,0
CRITICAL,CACHE_CTRL,Cache way protection bits corrupted,CACHE_CTRL Cache way protection bits corrupted,1
CRITICAL,MEM_CTRL,"Unrecoverable memory access failure, system halt required","MEM_CTRL Unrecoverable memory access failure, system halt required",1
ERROR,CLOCK_MANAGER,Clock generator output frequency drift exceeding tolerance.,CLOCK_MANAGER Clock generator output frequency drift exceeding tolerance.,0
CRITICAL,DMA_ENGINE,DMA engine control register access resulted in bus error,DMA_ENGINE DMA engine control register access resulted in bus error,3
WARNING,AXI_CTRL,"AXI transaction ID collision detected, resolved","AXI_CTRL AXI transaction ID collision detected, resolved",2
WARNING,INTERRUPT_CTRL,"Interrupt vector mismatch detected, re-initialization","INTERRUPT_CTRL Interrupt vector mismatch detected, re-initialization",1
CRITICAL,MEM_CTRL,Data bus integrity check failure,MEM_CTRL Data bus integrity check failure,1
WARNING,POWER_CTRL,Core voltage rail experienced transient drop below minimum.,POWER_CTRL Core voltage rail experienced transient drop below minimum.,4
WARNING,AXI_CTRL,AXI outstanding write transactions nearing capacity,AXI_CTRL AXI outstanding write transactions nearing capacity,2
CRITICAL,POWER_CTRL,Core voltage rail out of spec,POWER_CTRL Core voltage rail out of spec,4
ERROR,DDR_CTRL,"DDR command queue experienced overflow, dropping commands.","DDR_CTRL DDR command queue experienced overflow, dropping commands.",1
ERROR,PCIE_CTRL,PCIe link width negotiation failed,PCIE_CTRL PCIe link width negotiation failed,6
CRITICAL,CACHE_CTRL,Cache system deadlock detected on coherency protocol.,CACHE_CTRL Cache system deadlock detected on coherency protocol.,1
WARNING,DMA_ENGINE,DMA queue nearing saturation on channel 3 (60%).,DMA_ENGINE DMA queue nearing saturation on channel 3 (60%).,3
CRITICAL,POWER_CTRL,Voltage regulator for internal logic unresponsive,POWER_CTRL Voltage regulator for internal logic unresponsive,4
INFO,POWER_CTRL,System power consumption within specification.,POWER_CTRL System power consumption within specification.,4
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding expected threshold for ISR 7,INTERRUPT_CTRL Interrupt latency exceeding expected threshold for ISR 7,1
CRITICAL,FIFO_BUF,FIFO 'critical_log' experienced continuous overflow,FIFO_BUF FIFO 'critical_log' experienced continuous overflow,5
ERROR,CACHE_CTRL,Cache invalidate-all command unresponsive,CACHE_CTRL Cache invalidate-all command unresponsive,1
ERROR,CLOCK_MANAGER,Clock synchronizer for module A detected metastability,CLOCK_MANAGER Clock synchronizer for module A detected metastability,0
CRITICAL,AXI_CTRL,AXI critical timing violation on write channel.,AXI_CTRL AXI critical timing violation on write channel.,2
ERROR,POWER_CTRL,On-chip voltage sensor reporting out of range value,POWER_CTRL On-chip voltage sensor reporting out of range value,7
INFO,FIFO_BUF,Data written to FIFO buffer,FIFO_BUF Data written to FIFO buffer,5
ERROR,PCIE_CTRL,PCIE_CTRL reported an unrecoverable internal arbitration conflict (Code: 0xF).,PCIE_CTRL PCIE_CTRL reported an unrecoverable internal arbitration conflict (Code: 0xF).,-1
ERROR,CACHE_CTRL,Cache line state machine fault,CACHE_CTRL Cache line state machine fault,1
INFO,PCIE_CTRL,PCIe root complex initialized,PCIE_CTRL PCIe root complex initialized,6
CRITICAL,AXI_CTRL,AXI interconnect deadlock detected,AXI_CTRL AXI interconnect deadlock detected,2
ERROR,DMA_ENGINE,DMA transfer timeout,DMA_ENGINE DMA transfer timeout,3
INFO,CACHE_CTRL,Cache hit rate for L1 instruction cache at 95%,CACHE_CTRL Cache hit rate for L1 instruction cache at 95%,1
ERROR,MEM_CTRL,Memory address decoding logic output mismatch,MEM_CTRL Memory address decoding logic output mismatch,1
INFO,AXI_CTRL,AXI write data channel ready asserted,AXI_CTRL AXI write data channel ready asserted,2
CRITICAL,CLOCK_MANAGER,Clock distribution network critical fault,CLOCK_MANAGER Clock distribution network critical fault,0
WARNING,DDR_CTRL,DDR read latency variation exceeding acceptable limits,DDR_CTRL DDR read latency variation exceeding acceptable limits,1
ERROR,CLOCK_MANAGER,"Clock tree integrity check failed, potential clock loss","CLOCK_MANAGER Clock tree integrity check failed, potential clock loss",0
ERROR,PCIE_CTRL,"PCIe link training failure, unable to achieve L0 state.","PCIE_CTRL PCIe link training failure, unable to achieve L0 state.",6
WARNING,CLOCK_MANAGER,Global reset deassertion timing skew observed,CLOCK_MANAGER Global reset deassertion timing skew observed,0
INFO,INTERRUPT_CTRL,IRQ 3 acknowledged by CPU,INTERRUPT_CTRL IRQ 3 acknowledged by CPU,1
CRITICAL,CACHE_CTRL,Cache tag RAM unrecoverable error,CACHE_CTRL Cache tag RAM unrecoverable error,1
ERROR,AXI_CTRL,AXI response channel assertion failure,AXI_CTRL AXI response channel assertion failure,2
INFO,DMA_ENGINE,DMA channel 0 paused by external request,DMA_ENGINE DMA channel 0 paused by external request,3
ERROR,DDR_CTRL,DDR read latency variation detected,DDR_CTRL DDR read latency variation detected,1
ERROR,CACHE_CTRL,"Cache flush operation failed to complete, remaining dirty lines 10.","CACHE_CTRL Cache flush operation failed to complete, remaining dirty lines 10.",1
CRITICAL,MEM_CTRL,Memory controller initialization sequence failed,MEM_CTRL Memory controller initialization sequence failed,1
ERROR,CACHE_CTRL,Cache way prediction logic failed,CACHE_CTRL Cache way prediction logic failed,1
INFO,DMA_ENGINE,DMA channel 2 status: idle,DMA_ENGINE DMA channel 2 status: idle,3
WARNING,CLOCK_MANAGER,Clock period deviation exceeding tolerance on local clock,CLOCK_MANAGER Clock period deviation exceeding tolerance on local clock,0
WARNING,FIFO_BUF,"FIFO almost empty, but expected data flow is high.","FIFO_BUF FIFO almost empty, but expected data flow is high.",5
ERROR,INTERRUPT_CTRL,Interrupt controller internal arbitration failure,INTERRUPT_CTRL Interrupt controller internal arbitration failure,1
INFO,MEM_CTRL,Read queue cleared,MEM_CTRL Read queue cleared,1
INFO,CACHE_CTRL,Cache line invalidated.,CACHE_CTRL Cache line invalidated.,1
ERROR,INTERRUPT_CTRL,Unexpected interrupt vector received,INTERRUPT_CTRL Unexpected interrupt vector received,1
INFO,POWER_CTRL,Deep sleep entered,POWER_CTRL Deep sleep entered,4
CRITICAL,POWER_CTRL,System reset caused by power rail instability,POWER_CTRL System reset caused by power rail instability,4
CRITICAL,CLOCK_MANAGER,System clock source switching failed,CLOCK_MANAGER System clock source switching failed,0
INFO,CACHE_CTRL,Directory synchronized,CACHE_CTRL Directory synchronized,1
ERROR,INTERRUPT_CTRL,Interrupt priority inversion detected for IRQ 7 and IRQ 1,INTERRUPT_CTRL Interrupt priority inversion detected for IRQ 7 and IRQ 1,1
ERROR,POWER_CTRL,Voltage drop detected on periphery rail,POWER_CTRL Voltage drop detected on periphery rail,4
INFO,CACHE_CTRL,Cacheable memory region defined,CACHE_CTRL Cacheable memory region defined,1
WARNING,INTERRUPT_CTRL,Masked interrupt request received for critical event,INTERRUPT_CTRL Masked interrupt request received for critical event,1
WARNING,CLOCK_MANAGER,External clock input signal quality degraded,CLOCK_MANAGER External clock input signal quality degraded,0
ERROR,CLOCK_MANAGER,Clock domain crossing metastability detected on control signal,CLOCK_MANAGER Clock domain crossing metastability detected on control signal,0
INFO,CACHE_CTRL,"Cache line writeback completed, data committed to memory","CACHE_CTRL Cache line writeback completed, data committed to memory",1
ERROR,FIFO_BUF,FIFO empty status asserted unexpectedly during read,FIFO_BUF FIFO empty status asserted unexpectedly during read,5
WARNING,INTERRUPT_CTRL,Interrupt priority level inversion warning,INTERRUPT_CTRL Interrupt priority level inversion warning,1
CRITICAL,DMA_ENGINE,DMA channel 0 descriptor chain corruption,DMA_ENGINE DMA channel 0 descriptor chain corruption,3
ERROR,MEM_CTRL,Memory controller arbitration logic stalled indefinitely.,MEM_CTRL Memory controller arbitration logic stalled indefinitely.,1
ERROR,MEM_CTRL,Memory access permission violation,MEM_CTRL Memory access permission violation,1
WARNING,CLOCK_MANAGER,Clock enable glitch detected,CLOCK_MANAGER Clock enable glitch detected,0
WARNING,DDR_CTRL,DDR memory controller reports potential row hammer access pattern,DDR_CTRL DDR memory controller reports potential row hammer access pattern,-1
WARNING,PCIE_CTRL,PCIe upstream link bandwidth utilization exceeding 90%,PCIE_CTRL PCIe upstream link bandwidth utilization exceeding 90%,6
ERROR,POWER_CTRL,Power domain VDD_AUX failed to transition to ON state,POWER_CTRL Power domain VDD_AUX failed to transition to ON state,4
ERROR,CLOCK_MANAGER,Global reset assertion failure,CLOCK_MANAGER Global reset assertion failure,0
INFO,AXI_CTRL,AXI read channel idle.,AXI_CTRL AXI read channel idle.,2
WARNING,AXI_CTRL,AXI write channel backpressure detected,AXI_CTRL AXI write channel backpressure detected,2
CRITICAL,DDR_CTRL,DDR controller logic unresponsive to commands,DDR_CTRL DDR controller logic unresponsive to commands,1
WARNING,POWER_CTRL,Core voltage rail showing minor fluctuations,POWER_CTRL Core voltage rail showing minor fluctuations,4
WARNING,CLOCK_MANAGER,Clock gate enable signal delay detected,CLOCK_MANAGER Clock gate enable signal delay detected,0
WARNING,POWER_CTRL,Power consumption spike detected,POWER_CTRL Power consumption spike detected,4
WARNING,DDR_CTRL,DDR command bus utilization exceeding recommended levels,DDR_CTRL DDR command bus utilization exceeding recommended levels,1
ERROR,AXI_CTRL,AXI write address channel response timeout,AXI_CTRL AXI write address channel response timeout,2
CRITICAL,FIFO_BUF,"FIFO data path corruption detected, unrecoverable data loss.","FIFO_BUF FIFO data path corruption detected, unrecoverable data loss.",5
WARNING,AXI_CTRL,AXI data strobe timing violation,AXI_CTRL AXI data strobe timing violation,2
INFO,AXI_CTRL,AXI transaction initiated by master,AXI_CTRL AXI transaction initiated by master,2
WARNING,FIFO_BUF,FIFO 'command_queue' read pointer nearing write pointer,FIFO_BUF FIFO 'command_queue' read pointer nearing write pointer,5
WARNING,MEM_CTRL,Memory access latency for 'CPU' exceeding average.,MEM_CTRL Memory access latency for 'CPU' exceeding average.,1
ERROR,MEM_CTRL,Memory write protection violation at 0x93cf258d.,MEM_CTRL Memory write protection violation at 0x93cf258d.,1
ERROR,MEM_CTRL,Memory read data mismatch detected,MEM_CTRL Memory read data mismatch detected,1
ERROR,DDR_CTRL,DDR memory rank X failed initialization,DDR_CTRL DDR memory rank X failed initialization,1
INFO,AXI_CTRL,AXI transaction ID assigned.,AXI_CTRL AXI transaction ID assigned.,2
INFO,CLOCK_MANAGER,Clock frequency changed to default.,CLOCK_MANAGER Clock frequency changed to default.,0
ERROR,PCIE_CTRL,PCIe TLP header CRC mismatch,PCIE_CTRL PCIe TLP header CRC mismatch,6
CRITICAL,CLOCK_MANAGER,"System primary clock source failed, unable to switch to backup.","CLOCK_MANAGER System primary clock source failed, unable to switch to backup.",0
ERROR,PCIE_CTRL,PCIe device error reporting disabled,PCIE_CTRL PCIe device error reporting disabled,6
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal FIFO overflow causing IRQ loss,INTERRUPT_CTRL Interrupt controller internal FIFO overflow causing IRQ loss,1
INFO,PCIE_CTRL,"PCIe hot-plug event detected, device enumerating","PCIE_CTRL PCIe hot-plug event detected, device enumerating",6
INFO,DMA_ENGINE,DMA transfer completion for channel 0,DMA_ENGINE DMA transfer completion for channel 0,3
INFO,POWER_CTRL,System power monitor active,POWER_CTRL System power monitor active,4
ERROR,DMA_ENGINE,DMA channel 5 transfer aborted due to bus error,DMA_ENGINE DMA channel 5 transfer aborted due to bus error,3
CRITICAL,DMA_ENGINE,"DMA descriptor ring buffer corrupted, all channels halted (channel 0x5)","DMA_ENGINE DMA descriptor ring buffer corrupted, all channels halted (channel 0x5)",3
ERROR,DDR_CTRL,"DDR training sequence failed, protocol mismatch.","DDR_CTRL DDR training sequence failed, protocol mismatch.",1
ERROR,CACHE_CTRL,Cache coherence protocol mismatch for address 0xDEADBEEF,CACHE_CTRL Cache coherence protocol mismatch for address 0xDEADBEEF,1
INFO,POWER_CTRL,Power domain reset de-asserted,POWER_CTRL Power domain reset de-asserted,4
WARNING,DDR_CTRL,DDR memory temperature above nominal range,DDR_CTRL DDR memory temperature above nominal range,1
WARNING,AXI_CTRL,Pending AXI requests high,AXI_CTRL Pending AXI requests high,2
ERROR,FIFO_BUF,"FIFO 'command_in' overflow detected, commands lost","FIFO_BUF FIFO 'command_in' overflow detected, commands lost",5
INFO,DMA_ENGINE,DMA channel 5 configured for loopback test,DMA_ENGINE DMA channel 5 configured for loopback test,3
ERROR,CLOCK_MANAGER,Clock division error detected.,CLOCK_MANAGER Clock division error detected.,0
INFO,CLOCK_MANAGER,Clock domain crossing buffer underrun detected,CLOCK_MANAGER Clock domain crossing buffer underrun detected,0
ERROR,MEM_CTRL,Memory controller internal register corrupted,MEM_CTRL Memory controller internal register corrupted,1
INFO,POWER_CTRL,New power state engaged for POWER_CTRL.,POWER_CTRL New power state engaged for POWER_CTRL.,4
INFO,CLOCK_MANAGER,Clock frequency configuration applied.,CLOCK_MANAGER Clock frequency configuration applied.,0
INFO,DDR_CTRL,DDR calibration completed successfully (mode manual).,DDR_CTRL DDR calibration completed successfully (mode manual).,1
INFO,CACHE_CTRL,Cache prefetcher successfully fetched next line,CACHE_CTRL Cache prefetcher successfully fetched next line,1
ERROR,MEM_CTRL,"Memory read data mismatch detected, expected 0x54238543 got 0x98765432 at address 0x12345678","MEM_CTRL Memory read data mismatch detected, expected 0x54238543 got 0x98765432 at address 0x12345678",1
WARNING,DDR_CTRL,"DDR refresh rate deviation detected, margin decreasing","DDR_CTRL DDR refresh rate deviation detected, margin decreasing",1
ERROR,FIFO_BUF,"FIFO overflow detected, data loss occurred (buffer overflow)","FIFO_BUF FIFO overflow detected, data loss occurred (buffer overflow)",5
WARNING,POWER_CTRL,Voltage regulator output ripple exceeding specification,POWER_CTRL Voltage regulator output ripple exceeding specification,4
WARNING,DDR_CTRL,DDR calibration parameter out of range,DDR_CTRL DDR calibration parameter out of range,1
ERROR,AXI_CTRL,"AXI_CTRL: protocol mismatch - invalid handshake sequence detected. (Master ID: 3, AXI ID: 15)","AXI_CTRL AXI_CTRL: protocol mismatch - invalid handshake sequence detected. (Master ID: 3, AXI ID: 15)",2
WARNING,POWER_CTRL,Power consumption spike detected during workload burst,POWER_CTRL Power consumption spike detected during workload burst,4
ERROR,AXI_CTRL,AXI transaction timeout detected on read burst,AXI_CTRL AXI transaction timeout detected on read burst,2
WARNING,DMA_ENGINE,DMA transfer size exceeding available buffer,DMA_ENGINE DMA transfer size exceeding available buffer,3
INFO,POWER_CTRL,Power sequencing step 2 completed,POWER_CTRL Power sequencing step 2 completed,4
WARNING,CLOCK_MANAGER,Gated clock output glitch detected.,CLOCK_MANAGER Gated clock output glitch detected.,0
ERROR,PCIE_CTRL,PCIe transaction layer CRC error detected on TLP,PCIE_CTRL PCIe transaction layer CRC error detected on TLP,6
ERROR,INTERRUPT_CTRL,Interrupt controller detected a non-maskable interrupt (NMI) on line 1.,INTERRUPT_CTRL Interrupt controller detected a non-maskable interrupt (NMI) on line 1.,1
ERROR,CACHE_CTRL,Cache way selection logic fault,CACHE_CTRL Cache way selection logic fault,1
ERROR,CACHE_CTRL,Cache coherence protocol violation during store operation,CACHE_CTRL Cache coherence protocol violation during store operation,1
INFO,FIFO_BUF,FIFO almost-full condition deasserted,FIFO_BUF FIFO almost-full condition deasserted,5
CRITICAL,DMA_ENGINE,"DMA engine internal FSM entered an illegal state, unrecoverable","DMA_ENGINE DMA engine internal FSM entered an illegal state, unrecoverable",3
ERROR,DMA_ENGINE,DMA channel 7 address incrementer malfunction,DMA_ENGINE DMA channel 7 address incrementer malfunction,3
ERROR,POWER_CTRL,"Power sequence incorrect, component failed to initialize","POWER_CTRL Power sequence incorrect, component failed to initialize",4
ERROR,POWER_CTRL,Thermal shutdown initiated due to 67C.,POWER_CTRL Thermal shutdown initiated due to 67C.,4
ERROR,PCIE_CTRL,"PCIe lane deskew failure, symbol lock lost.","PCIE_CTRL PCIe lane deskew failure, symbol lock lost.",-1
WARNING,CACHE_CTRL,Cache write-back buffer backlog,CACHE_CTRL Cache write-back buffer backlog,1
ERROR,DMA_ENGINE,DMA target address out of bounds,DMA_ENGINE DMA target address out of bounds,3
CRITICAL,MEM_CTRL,Memory bank access conflict deadlock,MEM_CTRL Memory bank access conflict deadlock,1
CRITICAL,POWER_CTRL,"CRITICAL: Core power domain X failed to reach target voltage 1.2V, system halt.","POWER_CTRL CRITICAL: Core power domain X failed to reach target voltage 1.2V, system halt.",4
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal not received within timeout period.,INTERRUPT_CTRL Interrupt acknowledge signal not received within timeout period.,1
WARNING,MEM_CTRL,Memory refresh command queued,MEM_CTRL Memory refresh command queued,1
ERROR,FIFO_BUF,FIFO read attempt on empty buffer,FIFO_BUF FIFO read attempt on empty buffer,5
CRITICAL,INTERRUPT_CTRL,Interrupt controller global enable stuck low.,INTERRUPT_CTRL Interrupt controller global enable stuck low.,1
ERROR,MEM_CTRL,ECC parity mismatch detected on boot block,MEM_CTRL ECC parity mismatch detected on boot block,1
INFO,AXI_CTRL,AXI transaction completed successfully,AXI_CTRL AXI transaction completed successfully,2
INFO,PCIE_CTRL,PCIe link speed negotiated to Gen4,PCIE_CTRL PCIe link speed negotiated to Gen4,6
INFO,INTERRUPT_CTRL,Interrupt line 3 asserted by timer peripheral,INTERRUPT_CTRL Interrupt line 3 asserted by timer peripheral,1
ERROR,CLOCK_MANAGER,Clock jitter exceeding tolerance on system clock,CLOCK_MANAGER Clock jitter exceeding tolerance on system clock,0
ERROR,DMA_ENGINE,DMA transfer timeout waiting for peripheral response,DMA_ENGINE DMA transfer timeout waiting for peripheral response,3
CRITICAL,AXI_CTRL,AXI transaction deadlock on multiple masters,AXI_CTRL AXI transaction deadlock on multiple masters,2
INFO,FIFO_BUF,Data popped from FIFO,FIFO_BUF Data popped from FIFO,5
ERROR,PCIE_CTRL,PCIe TLP header error detected,PCIE_CTRL PCIe TLP header error detected,6
WARNING,POWER_CTRL,Power domain transition delay detected for VDDPST (exceeded 10ms),POWER_CTRL Power domain transition delay detected for VDDPST (exceeded 10ms),4
WARNING,DDR_CTRL,DDR power consumption spiking during heavy load,DDR_CTRL DDR power consumption spiking during heavy load,1
INFO,CLOCK_MANAGER,Clock generator output enabled,CLOCK_MANAGER Clock generator output enabled,0
INFO,PCIE_CTRL,PCIe device 0x4B received valid configuration request.,PCIE_CTRL PCIe device 0x4B received valid configuration request.,6
INFO,FIFO_BUF,FIFO empty condition detected.,FIFO_BUF FIFO empty condition detected.,5
CRITICAL,POWER_CTRL,Power-on-reset (POR) signal failed to de-assert,POWER_CTRL Power-on-reset (POR) signal failed to de-assert,4
WARNING,FIFO_BUF,FIFO almost empty threshold reached,FIFO_BUF FIFO almost empty threshold reached,5
ERROR,DMA_ENGINE,DMA control register readback mismatch,DMA_ENGINE DMA control register readback mismatch,3
INFO,PCIE_CTRL,Data path reset for PCIE_CTRL completed.,PCIE_CTRL Data path reset for PCIE_CTRL completed.,6
WARNING,PCIE_CTRL,PCIe flow control credits approaching zero for outbound traffic,PCIE_CTRL PCIe flow control credits approaching zero for outbound traffic,6
INFO,INTERRUPT_CTRL,Interrupt vector for ID 10 mapped,INTERRUPT_CTRL Interrupt vector for ID 10 mapped,1
WARNING,FIFO_BUF,"FIFO read operation stalled, empty signal asserted","FIFO_BUF FIFO read operation stalled, empty signal asserted",5
ERROR,DMA_ENGINE,DMA channel 1 bus error on write,DMA_ENGINE DMA channel 1 bus error on write,3
ERROR,DMA_ENGINE,DMA channel 6 descriptor read bus error,DMA_ENGINE DMA channel 6 descriptor read bus error,3
CRITICAL,DDR_CTRL,DDR interface logic failure,DDR_CTRL DDR interface logic failure,1
INFO,DMA_ENGINE,DMA channel 1 burst transfer initiated,DMA_ENGINE DMA channel 1 burst transfer initiated,3
WARNING,POWER_CTRL,Supply voltage droop detected during heavy load,POWER_CTRL Supply voltage droop detected during heavy load,4
ERROR,MEM_CTRL,Memory controller unable to complete burst write,MEM_CTRL Memory controller unable to complete burst write,1
WARNING,INTERRUPT_CTRL,Interrupt %d masked for extended duration,INTERRUPT_CTRL Interrupt %d masked for extended duration,1
WARNING,FIFO_BUF,"Read pointer approaching write pointer, potential empty stall.","FIFO_BUF Read pointer approaching write pointer, potential empty stall.",5
ERROR,FIFO_BUF,FIFO_TX_CMD underflow detected on channel 0.,FIFO_BUF FIFO_TX_CMD underflow detected on channel 0.,5
WARNING,DMA_ENGINE,DMA channel completion backlog growing,DMA_ENGINE DMA channel completion backlog growing,3
CRITICAL,DMA_ENGINE,DMA controller state machine entered illegal state,DMA_ENGINE DMA controller state machine entered illegal state,3
CRITICAL,PCIE_CTRL,"Unrecoverable PCIe TLP CRC error, continuous link reset.","PCIE_CTRL Unrecoverable PCIe TLP CRC error, continuous link reset.",6
CRITICAL,CLOCK_MANAGER,Clock output buffer failure,CLOCK_MANAGER Clock output buffer failure,0
WARNING,POWER_CTRL,Power domain transition latency exceeded,POWER_CTRL Power domain transition latency exceeded,4
CRITICAL,POWER_CTRL,"CRITICAL: Power rail instability detected (rail System), potential hardware damage.","POWER_CTRL CRITICAL: Power rail instability detected (rail System), potential hardware damage.",4
CRITICAL,DDR_CTRL,DDR memory initialization loop detected,DDR_CTRL DDR memory initialization loop detected,1
INFO,INTERRUPT_CTRL,Interrupt acknowledged for IRQ_SPI,INTERRUPT_CTRL Interrupt acknowledged for IRQ_SPI,1
WARNING,PCIE_CTRL,PCIe CRC error rate elevated.,PCIE_CTRL PCIe CRC error rate elevated.,6
WARNING,CLOCK_MANAGER,Clock domain crossing FIFO nearing capacity,CLOCK_MANAGER Clock domain crossing FIFO nearing capacity,0
CRITICAL,POWER_CTRL,Power management unit asserted critical system error,POWER_CTRL Power management unit asserted critical system error,4
CRITICAL,PCIE_CTRL,"PCIe TLP layer protocol violation, system instability","PCIE_CTRL PCIe TLP layer protocol violation, system instability",6
CRITICAL,CACHE_CTRL,"Cache data corruption detected, unrecoverable","CACHE_CTRL Cache data corruption detected, unrecoverable",1
ERROR,CLOCK_MANAGER,External clock source lost,CLOCK_MANAGER External clock source lost,0
WARNING,AXI_CTRL,AXI bus arbitration fairness issue observed,AXI_CTRL AXI bus arbitration fairness issue observed,2
INFO,CLOCK_MANAGER,Clock frequency configuration applied to 500MHz.,CLOCK_MANAGER Clock frequency configuration applied to 500MHz.,0
CRITICAL,DMA_ENGINE,DMA engine microcode corruption detected,DMA_ENGINE DMA engine microcode corruption detected,3
CRITICAL,POWER_CTRL,Power controller detected unrecoverable power supply fault.,POWER_CTRL Power controller detected unrecoverable power supply fault.,4
CRITICAL,DMA_ENGINE,DMA engine initiated system reset due to unrecoverable error,DMA_ENGINE DMA engine initiated system reset due to unrecoverable error,3
INFO,DMA_ENGINE,DMA transfer completion for channel 1 reported,DMA_ENGINE DMA transfer completion for channel 1 reported,3
WARNING,DDR_CTRL,DDR read/write bus contention detected,DDR_CTRL DDR read/write bus contention detected,1
INFO,POWER_CTRL,Voltage regulator enabled,POWER_CTRL Voltage regulator enabled,4
ERROR,POWER_CTRL,Power monitor unit reports over-voltage,POWER_CTRL Power monitor unit reports over-voltage,4
ERROR,MEM_CTRL,Data bus parity error detected on memory read,MEM_CTRL Data bus parity error detected on memory read,1
INFO,FIFO_BUF,FIFO depth reported: 64,FIFO_BUF FIFO depth reported: 64,5
INFO,DDR_CTRL,DDR memory array initialized to 0s,DDR_CTRL DDR memory array initialized to 0s,1
CRITICAL,DDR_CTRL,DDR training sequence failed,DDR_CTRL DDR training sequence failed,1
INFO,CLOCK_MANAGER,Clock frequency configured to 500 MHz.,CLOCK_MANAGER Clock frequency configured to 500 MHz.,0
ERROR,AXI_CTRL,AXI write burst count violation,AXI_CTRL AXI write burst count violation,2
ERROR,DDR_CTRL,DDR write data strobe (DQS) calibration failure,DDR_CTRL DDR write data strobe (DQS) calibration failure,1
CRITICAL,MEM_CTRL,Memory controller unrecoverable state machine error,MEM_CTRL Memory controller unrecoverable state machine error,1
WARNING,INTERRUPT_CTRL,"Interrupt queue approaching limit, potential buffer overflow.","INTERRUPT_CTRL Interrupt queue approaching limit, potential buffer overflow.",1
ERROR,CLOCK_MANAGER,Clock reference input loss detected,CLOCK_MANAGER Clock reference input loss detected,0
ERROR,CLOCK_MANAGER,Clock recovery circuit failure,CLOCK_MANAGER Clock recovery circuit failure,0
WARNING,DDR_CTRL,DDR controller busy cycles exceeding threshold,DDR_CTRL DDR controller busy cycles exceeding threshold,1
CRITICAL,MEM_CTRL,Memory controller register file corruption,MEM_CTRL Memory controller register file corruption,1
CRITICAL,DMA_ENGINE,DMA engine internal bus deadlock detected,DMA_ENGINE DMA engine internal bus deadlock detected,3
CRITICAL,CLOCK_MANAGER,Clock monitor detected a complete clock cessation.,CLOCK_MANAGER Clock monitor detected a complete clock cessation.,0
CRITICAL,PCIE_CTRL,PCIe root complex unresponsive.,PCIE_CTRL PCIe root complex unresponsive.,6
INFO,AXI_CTRL,AXI interconnect configured.,AXI_CTRL AXI interconnect configured.,2
WARNING,DMA_ENGINE,"DMA descriptor fetch latency high, average 23 cycles","DMA_ENGINE DMA descriptor fetch latency high, average 23 cycles",3
INFO,POWER_CTRL,Dynamic voltage and frequency scaling (DVFS) level updated,POWER_CTRL Dynamic voltage and frequency scaling (DVFS) level updated,9
WARNING,MEM_CTRL,Memory controller write buffer nearly full,MEM_CTRL Memory controller write buffer nearly full,1
WARNING,AXI_CTRL,AXI outstanding read transactions nearing limit (16/32),AXI_CTRL AXI outstanding read transactions nearing limit (16/32),2
WARNING,POWER_CTRL,"Battery level low (15%), considering shutdown","POWER_CTRL Battery level low (15%), considering shutdown",-1
ERROR,POWER_CTRL,Power domain VDD_PCIE failed to respond to shutdown request,POWER_CTRL Power domain VDD_PCIE failed to respond to shutdown request,4
CRITICAL,CLOCK_MANAGER,Global reset issued due to clock instability,CLOCK_MANAGER Global reset issued due to clock instability,0
INFO,DDR_CTRL,DDR_CTRL activity detected on interface.,DDR_CTRL DDR_CTRL activity detected on interface.,-1
WARNING,DDR_CTRL,DDR access patterns indicate potential row hammer effect at 0xDEADBEEF.,DDR_CTRL DDR access patterns indicate potential row hammer effect at 0xDEADBEEF.,-1
ERROR,MEM_CTRL,Uninitialized memory region accessed,MEM_CTRL Uninitialized memory region accessed,1
ERROR,POWER_CTRL,Power domain 'DSP' failed to power up completely,POWER_CTRL Power domain 'DSP' failed to power up completely,4
WARNING,DMA_ENGINE,DMA queue nearing saturation for channel 1.,DMA_ENGINE DMA queue nearing saturation for channel 1.,3
WARNING,AXI_CTRL,AXI write data channel backpressure duration exceeding threshold,AXI_CTRL AXI write data channel backpressure duration exceeding threshold,2
ERROR,AXI_CTRL,AXI ID mismatch error,AXI_CTRL AXI ID mismatch error,2
CRITICAL,DMA_ENGINE,DMA engine configuration corruption detected,DMA_ENGINE DMA engine configuration corruption detected,3
CRITICAL,CACHE_CTRL,"Cache data array integrity compromised, all cached data untrustworthy","CACHE_CTRL Cache data array integrity compromised, all cached data untrustworthy",1
INFO,INTERRUPT_CTRL,Interrupt controller initialized with default masks,INTERRUPT_CTRL Interrupt controller initialized with default masks,1
WARNING,CACHE_CTRL,Cache eviction rate oscillating,CACHE_CTRL Cache eviction rate oscillating,1
INFO,AXI_CTRL,AXI write data channel (WDATA) received.,AXI_CTRL AXI write data channel (WDATA) received.,2
ERROR,MEM_CTRL,Memory controller write data buffer overflow,MEM_CTRL Memory controller write data buffer overflow,1
INFO,CLOCK_MANAGER,Jitter measurement within tolerance limits.,CLOCK_MANAGER Jitter measurement within tolerance limits.,0
WARNING,AXI_CTRL,AXI outstanding transaction limit nearing capacity for master 0x07,AXI_CTRL AXI outstanding transaction limit nearing capacity for master 0x07,2
ERROR,INTERRUPT_CTRL,Interrupt controller internal state machine hung,INTERRUPT_CTRL Interrupt controller internal state machine hung,1
INFO,AXI_CTRL,AXI handshake sequence completed.,AXI_CTRL AXI handshake sequence completed.,2
WARNING,MEM_CTRL,Memory ECC event counter nearing overflow.,MEM_CTRL Memory ECC event counter nearing overflow.,1
WARNING,CACHE_CTRL,Cache snoop filter misses exceeding threshold,CACHE_CTRL Cache snoop filter misses exceeding threshold,1
INFO,MEM_CTRL,Memory read from 0xFF00_0000 successful,MEM_CTRL Memory read from 0xFF00_0000 successful,1
INFO,CACHE_CTRL,Cache line writeback completed for address 0xb8e37e90.,CACHE_CTRL Cache line writeback completed for address 0xb8e37e90.,1
WARNING,DMA_ENGINE,DMA channel transfer retransmission count increasing,DMA_ENGINE DMA channel transfer retransmission count increasing,3
ERROR,INTERRUPT_CTRL,Interrupt priority level inversion observed,INTERRUPT_CTRL Interrupt priority level inversion observed,1
WARNING,DMA_ENGINE,DMA transfer pending for extended period.,DMA_ENGINE DMA transfer pending for extended period.,3
ERROR,CLOCK_MANAGER,Clock fanout exceeded maximum permissible limit,CLOCK_MANAGER Clock fanout exceeded maximum permissible limit,0
INFO,CLOCK_MANAGER,Internal oscillator trimmed,CLOCK_MANAGER Internal oscillator trimmed,-1
ERROR,DMA_ENGINE,DMA engine internal bus error,DMA_ENGINE DMA engine internal bus error,3
ERROR,PCIE_CTRL,PCIe configuration space access timeout,PCIE_CTRL PCIe configuration space access timeout,6
WARNING,CACHE_CTRL,Cache write-through buffer nearing capacity,CACHE_CTRL Cache write-through buffer nearing capacity,1
WARNING,AXI_CTRL,AXI address decoding conflict detected,AXI_CTRL AXI address decoding conflict detected,2
CRITICAL,DDR_CTRL,DDR Memory initialization sequence failed,DDR_CTRL DDR Memory initialization sequence failed,1
ERROR,DDR_CTRL,DDR auto-refresh command sequence failed,DDR_CTRL DDR auto-refresh command sequence failed,1
ERROR,INTERRUPT_CTRL,Interrupt controller unable to clear pending interrupt,INTERRUPT_CTRL Interrupt controller unable to clear pending interrupt,1
ERROR,DMA_ENGINE,DMA transaction timeout detected on channel 2,DMA_ENGINE DMA transaction timeout detected on channel 2,3
INFO,AXI_CTRL,AXI burst type changed to INCR,AXI_CTRL AXI burst type changed to INCR,2
WARNING,AXI_CTRL,AXI bus master 0x01 backpressure asserted on read channel,AXI_CTRL AXI bus master 0x01 backpressure asserted on read channel,2
INFO,FIFO_BUF,FIFO 'rx_packet' read successful,FIFO_BUF FIFO 'rx_packet' read successful,-1
INFO,DMA_ENGINE,DMA channel 10 transfer initiation successful,DMA_ENGINE DMA channel 10 transfer initiation successful,3
INFO,CLOCK_MANAGER,Reference clock detected,CLOCK_MANAGER Reference clock detected,0
INFO,PCIE_CTRL,PCIe root complex configured.,PCIE_CTRL PCIe root complex configured.,6
CRITICAL,DMA_ENGINE,DMA engine detected hardware deadlock on channel 4,DMA_ENGINE DMA engine detected hardware deadlock on channel 4,3
CRITICAL,CACHE_CTRL,"L1 cache parity error detected on tag RAM, data integrity compromised","CACHE_CTRL L1 cache parity error detected on tag RAM, data integrity compromised",1
CRITICAL,CACHE_CTRL,Cache controller logic detected a self-test failure.,CACHE_CTRL Cache controller logic detected a self-test failure.,-1
CRITICAL,MEM_CTRL,Memory controller internal bus parity error,MEM_CTRL Memory controller internal bus parity error,1
ERROR,POWER_CTRL,"Voltage drop detected on core rail, power supply issue.","POWER_CTRL Voltage drop detected on core rail, power supply issue.",4
ERROR,MEM_CTRL,Memory read-modify-write operation failed verification,MEM_CTRL Memory read-modify-write operation failed verification,1
INFO,MEM_CTRL,Memory controller idle state achieved,MEM_CTRL Memory controller idle state achieved,1
WARNING,MEM_CTRL,Page table entry invalidation storm observed,MEM_CTRL Page table entry invalidation storm observed,1
WARNING,POWER_CTRL,Low power mode entry stalled,POWER_CTRL Low power mode entry stalled,4
INFO,DMA_ENGINE,DMA channel 3 configured for scatter-gather transfer,DMA_ENGINE DMA channel 3 configured for scatter-gather transfer,3
INFO,CACHE_CTRL,Cache line prefetched successfully,CACHE_CTRL Cache line prefetched successfully,1
CRITICAL,AXI_CTRL,AXI fabric deadlock detected on main interconnect (deadlock detected),AXI_CTRL AXI fabric deadlock detected on main interconnect (deadlock detected),2
ERROR,FIFO_BUF,FIFO 'response_buffer' suffered an unexpected overflow,FIFO_BUF FIFO 'response_buffer' suffered an unexpected overflow,5
CRITICAL,POWER_CTRL,"Thermal sensor critical alert, system shutdown initiated","POWER_CTRL Thermal sensor critical alert, system shutdown initiated",4
CRITICAL,CLOCK_MANAGER,Clock domain X source has failed,CLOCK_MANAGER Clock domain X source has failed,0
ERROR,AXI_CTRL,AXI write response (BRESP) received DECERR.,AXI_CTRL AXI write response (BRESP) received DECERR.,2
WARNING,DDR_CTRL,DDR data mask pin stuck,DDR_CTRL DDR data mask pin stuck,-1
ERROR,MEM_CTRL,Memory controller received unaligned write address with misaligned byte enable,MEM_CTRL Memory controller received unaligned write address with misaligned byte enable,1
ERROR,AXI_CTRL,AXI write data (W) channel protocol violation (WLAST mismatch),AXI_CTRL AXI write data (W) channel protocol violation (WLAST mismatch),2
INFO,INTERRUPT_CTRL,Interrupt priority level updated,INTERRUPT_CTRL Interrupt priority level updated,1
WARNING,DDR_CTRL,DDR precharge timing parameter out of spec,DDR_CTRL DDR precharge timing parameter out of spec,1
INFO,PCIE_CTRL,PCIe Completion with Requester ID mismatch,PCIE_CTRL PCIe Completion with Requester ID mismatch,6
WARNING,CLOCK_MANAGER,Clock gate enable sequence interrupted,CLOCK_MANAGER Clock gate enable sequence interrupted,0
INFO,AXI_CTRL,AXI master 0 completed transaction with OKAY response,AXI_CTRL AXI master 0 completed transaction with OKAY response,2
ERROR,AXI_CTRL,AXI write address channel transaction timeout,AXI_CTRL AXI write address channel transaction timeout,2
CRITICAL,INTERRUPT_CTRL,"Critical system interrupt unacknowledged, potential watchdog reset","INTERRUPT_CTRL Critical system interrupt unacknowledged, potential watchdog reset",1
WARNING,AXI_CTRL,AXI slave read response taking too long,AXI_CTRL AXI slave read response taking too long,2
WARNING,AXI_CTRL,AXI slave 'S2' asserting constant backpressure,AXI_CTRL AXI slave 'S2' asserting constant backpressure,2
WARNING,CACHE_CTRL,Cache write-through policy causing high bus traffic,CACHE_CTRL Cache write-through policy causing high bus traffic,1
WARNING,DMA_ENGINE,Descriptor fetch latency increasing,DMA_ENGINE Descriptor fetch latency increasing,3
CRITICAL,CLOCK_MANAGER,Multiple clock domains reporting deadlocks,CLOCK_MANAGER Multiple clock domains reporting deadlocks,-1
WARNING,PCIE_CTRL,PCIe link error rate increasing over time,PCIE_CTRL PCIe link error rate increasing over time,6
CRITICAL,MEM_CTRL,Address translation unit (ATU) reported invalid mapping,MEM_CTRL Address translation unit (ATU) reported invalid mapping,1
WARNING,FIFO_BUF,FIFO fill level fluctuating widely,FIFO_BUF FIFO fill level fluctuating widely,5
INFO,FIFO_BUF,"FIFO_BUF_6 almost empty, ready for more writes","FIFO_BUF FIFO_BUF_6 almost empty, ready for more writes",5
WARNING,INTERRUPT_CTRL,Interrupt mask configuration allows low priority interrupts to starve high priority ones.,INTERRUPT_CTRL Interrupt mask configuration allows low priority interrupts to starve high priority ones.,1
WARNING,AXI_CTRL,AXI read latency spike detected for burst transactions,AXI_CTRL AXI read latency spike detected for burst transactions,2
CRITICAL,PCIE_CTRL,PCIe bridge fatal error,PCIE_CTRL PCIe bridge fatal error,6
INFO,AXI_CTRL,AXI master `cpu_0` initiated a locked transaction,AXI_CTRL AXI master `cpu_0` initiated a locked transaction,-1
WARNING,CLOCK_MANAGER,Clock source selection switch glitch detected,CLOCK_MANAGER Clock source selection switch glitch detected,0
ERROR,DDR_CTRL,DDR memory rank 1 failed row activation,DDR_CTRL DDR memory rank 1 failed row activation,1
CRITICAL,POWER_CTRL,Core power supply voltage instability detected,POWER_CTRL Core power supply voltage instability detected,4
INFO,FIFO_BUF,FIFO_BUF_10 write operation successful,FIFO_BUF FIFO_BUF_10 write operation successful,5
WARNING,DMA_ENGINE,DMA channel 1 transfer rate below expected,DMA_ENGINE DMA channel 1 transfer rate below expected,3
CRITICAL,POWER_CTRL,"Critical power rail VDD_CORE failure, system shut down","POWER_CTRL Critical power rail VDD_CORE failure, system shut down",4
WARNING,PCIE_CTRL,PCIe device power state transition error,PCIE_CTRL PCIe device power state transition error,6
ERROR,DDR_CTRL,DDR write data mask (DM) signal timing violation,DDR_CTRL DDR write data mask (DM) signal timing violation,1
INFO,FIFO_BUF,Low power entry requested by FIFO_BUF.,FIFO_BUF Low power entry requested by FIFO_BUF.,-1
ERROR,MEM_CTRL,Memory scrub operation reported uncorrectable errors,MEM_CTRL Memory scrub operation reported uncorrectable errors,1
INFO,MEM_CTRL,Read request granted for address 0xFEED,MEM_CTRL Read request granted for address 0xFEED,1
WARNING,AXI_CTRL,AXI read channel starvation detected for low-priority master.,AXI_CTRL AXI read channel starvation detected for low-priority master.,2
ERROR,INTERRUPT_CTRL,"Interrupt vector mismatch detected (expected 29, got 14).","INTERRUPT_CTRL Interrupt vector mismatch detected (expected 29, got 14).",1
ERROR,CLOCK_MANAGER,Clock source output impedance mismatch,CLOCK_MANAGER Clock source output impedance mismatch,-1
CRITICAL,MEM_CTRL,ECC scrubber detected uncorrectable multi-bit error,MEM_CTRL ECC scrubber detected uncorrectable multi-bit error,1
CRITICAL,CACHE_CTRL,CRITICAL: Cache coherence protocol violation leading to system-wide data inconsistency.,CACHE_CTRL CRITICAL: Cache coherence protocol violation leading to system-wide data inconsistency.,1
WARNING,FIFO_BUF,FIFO write pointer nearing full condition.,FIFO_BUF FIFO write pointer nearing full condition.,5
ERROR,DMA_ENGINE,"DMA descriptor fetch failed, invalid descriptor address at 0x7","DMA_ENGINE DMA descriptor fetch failed, invalid descriptor address at 0x7",3
WARNING,AXI_CTRL,AXI back-pressure asserted on write channel for 34 cycles,AXI_CTRL AXI back-pressure asserted on write channel for 34 cycles,2
ERROR,PCIE_CTRL,PCIe completion timeout for requester ID A.,PCIE_CTRL PCIe completion timeout for requester ID A.,6
ERROR,FIFO_BUF,FIFO write pointer overrun detected,FIFO_BUF FIFO write pointer overrun detected,5
WARNING,DDR_CTRL,DDR command reordering buffer near capacity,DDR_CTRL DDR command reordering buffer near capacity,-1
ERROR,PCIE_CTRL,PCIe bridge configuration register corruption,PCIE_CTRL PCIe bridge configuration register corruption,6
CRITICAL,POWER_CTRL,Power sequence controller stuck in boot state,POWER_CTRL Power sequence controller stuck in boot state,4
ERROR,AXI_CTRL,AXI read burst completion not received,AXI_CTRL AXI read burst completion not received,2
CRITICAL,CLOCK_MANAGER,Asynchronous reset propagation failure across domains,CLOCK_MANAGER Asynchronous reset propagation failure across domains,0
CRITICAL,POWER_CTRL,"Power controller FSM in illegal state, permanent deadlock.","POWER_CTRL Power controller FSM in illegal state, permanent deadlock.",-1
INFO,AXI_CTRL,Operation on AXI_CTRL completed successfully.,AXI_CTRL Operation on AXI_CTRL completed successfully.,2
INFO,FIFO_BUF,FIFO occupancy checked,FIFO_BUF FIFO occupancy checked,5
INFO,FIFO_BUF,FIFO configuration loaded,FIFO_BUF FIFO configuration loaded,5
INFO,POWER_CTRL,Core voltage rail within nominal operating range,POWER_CTRL Core voltage rail within nominal operating range,4
CRITICAL,AXI_CTRL,AXI bus master 0x01 detected in a permanent deadlock state,AXI_CTRL AXI bus master 0x01 detected in a permanent deadlock state,2
WARNING,FIFO_BUF,FIFO_RX_PACKET_BUFFER has inconsistent read and write pointers.,FIFO_BUF FIFO_RX_PACKET_BUFFER has inconsistent read and write pointers.,-1
ERROR,MEM_CTRL,Memory initialization pattern mismatch detected,MEM_CTRL Memory initialization pattern mismatch detected,1
ERROR,FIFO_BUF,FIFO data read while not valid,FIFO_BUF FIFO data read while not valid,5
CRITICAL,INTERRUPT_CTRL,Persistent interrupt priority inversion leading to system deadlock,INTERRUPT_CTRL Persistent interrupt priority inversion leading to system deadlock,1
INFO,PCIE_CTRL,PCIe link re-training initiated by remote endpoint.,PCIE_CTRL PCIe link re-training initiated by remote endpoint.,6
ERROR,AXI_CTRL,AXI slave 0x18 provided an unexpected RRESP value of DECERR.,AXI_CTRL AXI slave 0x18 provided an unexpected RRESP value of DECERR.,2
INFO,CLOCK_MANAGER,Clock domain reset deasserted,CLOCK_MANAGER Clock domain reset deasserted,0
ERROR,AXI_CTRL,AXI write data channel byte lane error,AXI_CTRL AXI write data channel byte lane error,2
ERROR,CACHE_CTRL,Cache access to invalid physical address 0xAAAAAAAA.,CACHE_CTRL Cache access to invalid physical address 0xAAAAAAAA.,1
WARNING,DMA_ENGINE,DMA channel 8 pending transfers queue growing,DMA_ENGINE DMA channel 8 pending transfers queue growing,3
INFO,CLOCK_MANAGER,Auxiliary clock source activated,CLOCK_MANAGER Auxiliary clock source activated,0
ERROR,CLOCK_MANAGER,PLL re-lock sequence failed for CPU clock,CLOCK_MANAGER PLL re-lock sequence failed for CPU clock,0
CRITICAL,DMA_ENGINE,DMA engine unresponsive,DMA_ENGINE DMA engine unresponsive,3
INFO,CACHE_CTRL,CACHE_CTRL self-test passed.,CACHE_CTRL CACHE_CTRL self-test passed.,1
CRITICAL,PCIE_CTRL,PCIe Hot-Plug event failed,PCIE_CTRL PCIe Hot-Plug event failed,6
WARNING,CLOCK_MANAGER,Clock switching logic detected glitches,CLOCK_MANAGER Clock switching logic detected glitches,0
INFO,PCIE_CTRL,PCIe MSI-X table updated,PCIE_CTRL PCIe MSI-X table updated,-1
INFO,DDR_CTRL,DDR clock frequency set to 1600MHz,DDR_CTRL DDR clock frequency set to 1600MHz,1
INFO,DMA_ENGINE,DMA channel 2 completed with partial transfer,DMA_ENGINE DMA channel 2 completed with partial transfer,3
INFO,POWER_CTRL,Power sequence initiation acknowledged.,POWER_CTRL Power sequence initiation acknowledged.,4
WARNING,AXI_CTRL,AXI transaction outstanding count reached max for specific master,AXI_CTRL AXI transaction outstanding count reached max for specific master,2
ERROR,DDR_CTRL,DDR auto-refresh cycle skipped,DDR_CTRL DDR auto-refresh cycle skipped,1
WARNING,DMA_ENGINE,DMA transfer size exceeds maximum allowed,DMA_ENGINE DMA transfer size exceeds maximum allowed,3
WARNING,FIFO_BUF,FIFO write latency exceeding specification,FIFO_BUF FIFO write latency exceeding specification,5
WARNING,INTERRUPT_CTRL,"Interrupt acknowledge latency high, timing violation performance impact.","INTERRUPT_CTRL Interrupt acknowledge latency high, timing violation performance impact.",1
WARNING,DDR_CTRL,DDR memory refresh pending too long,DDR_CTRL DDR memory refresh pending too long,1
INFO,CACHE_CTRL,Cache 'L1I' hit rate maintained above 95%,CACHE_CTRL Cache 'L1I' hit rate maintained above 95%,1
CRITICAL,CLOCK_MANAGER,"Main clock source failed, system halted","CLOCK_MANAGER Main clock source failed, system halted",0
ERROR,CLOCK_MANAGER,Clock switching logic generated a runt pulse,CLOCK_MANAGER Clock switching logic generated a runt pulse,-1
CRITICAL,MEM_CTRL,Double-bit ECC error detected on critical data block,MEM_CTRL Double-bit ECC error detected on critical data block,1
WARNING,AXI_CTRL,AXI bridge FIFO nearing capacity on write path,AXI_CTRL AXI bridge FIFO nearing capacity on write path,2
INFO,DMA_ENGINE,DMA transfer for image processing completed,DMA_ENGINE DMA transfer for image processing completed,3
INFO,CACHE_CTRL,Data successfully fetched from cache (cache hit).,CACHE_CTRL Data successfully fetched from cache (cache hit).,1
WARNING,AXI_CTRL,AXI address phase latency increasing.,AXI_CTRL AXI address phase latency increasing.,2
INFO,CACHE_CTRL,Cache line evicted using LRU policy,CACHE_CTRL Cache line evicted using LRU policy,1
ERROR,DDR_CTRL,DDR memory training sequence failed to lock,DDR_CTRL DDR memory training sequence failed to lock,1
ERROR,MEM_CTRL,Memory page table entry translation fault,MEM_CTRL Memory page table entry translation fault,1
WARNING,DMA_ENGINE,DMA transfer completion interrupt delayed,DMA_ENGINE DMA transfer completion interrupt delayed,3
ERROR,DDR_CTRL,DDR read data mismatch after burst,DDR_CTRL DDR read data mismatch after burst,1
INFO,PCIE_CTRL,"PCIe link up, negotiation complete","PCIE_CTRL PCIe link up, negotiation complete",6
WARNING,AXI_CTRL,AXI outstanding transaction limit nearing capacity (12 of 21).,AXI_CTRL AXI outstanding transaction limit nearing capacity (12 of 21).,2
INFO,CLOCK_MANAGER,Clock frequency reduced to 100MHz for debug.,CLOCK_MANAGER Clock frequency reduced to 100MHz for debug.,0
ERROR,DDR_CTRL,DDR command bus drive strength calibration issue.,DDR_CTRL DDR command bus drive strength calibration issue.,-1
INFO,CACHE_CTRL,Cache coherency check completed without errors,CACHE_CTRL Cache coherency check completed without errors,1
WARNING,INTERRUPT_CTRL,Interrupt mask register configuration anomaly.,INTERRUPT_CTRL Interrupt mask register configuration anomaly.,1
INFO,MEM_CTRL,Memory block allocation successful,MEM_CTRL Memory block allocation successful,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal deadlock detected,INTERRUPT_CTRL Interrupt controller internal deadlock detected,1
INFO,AXI_CTRL,AXI write response OK received,AXI_CTRL AXI write response OK received,2
INFO,DMA_ENGINE,"DMA descriptor queue depth is 0, idle","DMA_ENGINE DMA descriptor queue depth is 0, idle",3
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range between domains,CLOCK_MANAGER Clock skew approaching unsafe range between domains,0
INFO,CACHE_CTRL,Cache line invalidated due to external stimulus,CACHE_CTRL Cache line invalidated due to external stimulus,1
INFO,DMA_ENGINE,DMA descriptor queue flushed,DMA_ENGINE DMA descriptor queue flushed,3
ERROR,PCIE_CTRL,PCIe link integrity check failed,PCIE_CTRL PCIe link integrity check failed,6
INFO,POWER_CTRL,Power state transition to RUN mode,POWER_CTRL Power state transition to RUN mode,4
CRITICAL,PCIE_CTRL,PCIe Root Complex fatal error reported,PCIE_CTRL PCIe Root Complex fatal error reported,6
ERROR,CLOCK_MANAGER,Clock monitor detected frequency outside limits.,CLOCK_MANAGER Clock monitor detected frequency outside limits.,0
ERROR,INTERRUPT_CTRL,"Interrupt priority inversion detected, lower priority IRQ serviced first","INTERRUPT_CTRL Interrupt priority inversion detected, lower priority IRQ serviced first",1
WARNING,PCIE_CTRL,PCIe device power consumption above specification,PCIE_CTRL PCIe device power consumption above specification,-1
CRITICAL,DDR_CTRL,DDR memory controller asserted critical error during calibration,DDR_CTRL DDR memory controller asserted critical error during calibration,1
INFO,FIFO_BUF,"Data written to FIFO, fill level updated.","FIFO_BUF Data written to FIFO, fill level updated.",5
ERROR,DDR_CTRL,Command queue depth exceeded allowed limit,DDR_CTRL Command queue depth exceeded allowed limit,1
CRITICAL,POWER_CTRL,Power sequence controller entered undefined state,POWER_CTRL Power sequence controller entered undefined state,4
INFO,POWER_CTRL,Power rail VDD_CORE enabled and stable,POWER_CTRL Power rail VDD_CORE enabled and stable,4
INFO,POWER_CTRL,Power domain for USB controller enabled,POWER_CTRL Power domain for USB controller enabled,4
INFO,AXI_CTRL,AXI interconnect channel M0 is idle,AXI_CTRL AXI interconnect channel M0 is idle,-1
ERROR,AXI_CTRL,"AXI_CTRL: bus contention - drive conflict on bus detected. (Master ID: 7, AXI ID: 9)","AXI_CTRL AXI_CTRL: bus contention - drive conflict on bus detected. (Master ID: 7, AXI ID: 9)",2
ERROR,CLOCK_MANAGER,Clock generation PLL output phase error,CLOCK_MANAGER Clock generation PLL output phase error,0
CRITICAL,CACHE_CTRL,Persistent cache coherence failure.,CACHE_CTRL Persistent cache coherence failure.,1
ERROR,POWER_CTRL,Power sequencing controller stuck state,POWER_CTRL Power sequencing controller stuck state,4
ERROR,MEM_CTRL,Memory access permissions violation detected,MEM_CTRL Memory access permissions violation detected,1
INFO,AXI_CTRL,AXI outstanding write limit not exceeded,AXI_CTRL AXI outstanding write limit not exceeded,2
ERROR,AXI_CTRL,AXI write address channel setup time violation detected,AXI_CTRL AXI write address channel setup time violation detected,2
WARNING,INTERRUPT_CTRL,INTERRUPT_CTRL resource allocation nearing limit (87% utilized).,INTERRUPT_CTRL INTERRUPT_CTRL resource allocation nearing limit (87% utilized).,1
WARNING,CLOCK_MANAGER,Clock input signal quality degradation detected,CLOCK_MANAGER Clock input signal quality degradation detected,0
ERROR,CLOCK_MANAGER,Clock domain crossing handshaking failure on 'event_sync',CLOCK_MANAGER Clock domain crossing handshaking failure on 'event_sync',0
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on data path.,CLOCK_MANAGER Clock domain crossing synchronization failure on data path.,0
CRITICAL,POWER_CTRL,Voltage regulator critical response timeout,POWER_CTRL Voltage regulator critical response timeout,4
WARNING,FIFO_BUF,FIFO data corruption detected during read,FIFO_BUF FIFO data corruption detected during read,5
ERROR,AXI_CTRL,AXI transaction address decoding error,AXI_CTRL AXI transaction address decoding error,2
INFO,CLOCK_MANAGER,Clock gate enabled for peripheral block A,CLOCK_MANAGER Clock gate enabled for peripheral block A,-1
WARNING,CLOCK_MANAGER,Gated clock output glitch detected,CLOCK_MANAGER Gated clock output glitch detected,0
ERROR,INTERRUPT_CTRL,Interrupt controller read-modify-write error,INTERRUPT_CTRL Interrupt controller read-modify-write error,1
INFO,PCIE_CTRL,TLP transmitted successfully,PCIE_CTRL TLP transmitted successfully,6
ERROR,PCIE_CTRL,PCIe link training failure detected during LTSSM Polling.,PCIE_CTRL PCIe link training failure detected during LTSSM Polling.,6
INFO,CLOCK_MANAGER,Clock frequency configuration applied to system PLL.,CLOCK_MANAGER Clock frequency configuration applied to system PLL.,0
INFO,MEM_CTRL,Write operation acknowledged by memory controller,MEM_CTRL Write operation acknowledged by memory controller,1
WARNING,CLOCK_MANAGER,Clock recovery circuit reporting phase offset,CLOCK_MANAGER Clock recovery circuit reporting phase offset,0
INFO,CACHE_CTRL,Cache way prediction accuracy logged,CACHE_CTRL Cache way prediction accuracy logged,1
INFO,INTERRUPT_CTRL,Interrupt dispatcher enabled,INTERRUPT_CTRL Interrupt dispatcher enabled,1
WARNING,INTERRUPT_CTRL,Interrupt storm detected from peripheral,INTERRUPT_CTRL Interrupt storm detected from peripheral,1
ERROR,AXI_CTRL,Illegal address access detected,AXI_CTRL Illegal address access detected,2
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold (28.7%).,CACHE_CTRL Cache miss rate exceeding expected threshold (28.7%).,1
ERROR,DDR_CTRL,Memory controller responded with an unexpected error code for MRS command.,DDR_CTRL Memory controller responded with an unexpected error code for MRS command.,1
INFO,MEM_CTRL,Memory controller initialized and ready,MEM_CTRL Memory controller initialized and ready,1
ERROR,POWER_CTRL,Power sequence controller detected an unexpected power rail glitch,POWER_CTRL Power sequence controller detected an unexpected power rail glitch,4
WARNING,INTERRUPT_CTRL,Software interrupt queue growing,INTERRUPT_CTRL Software interrupt queue growing,1
INFO,DMA_ENGINE,DMA engine reset done,DMA_ENGINE DMA engine reset done,3
INFO,CACHE_CTRL,L1 cache initialized successfully,CACHE_CTRL L1 cache initialized successfully,1
INFO,FIFO_BUF,FIFO depth reported as 128,FIFO_BUF FIFO depth reported as 128,5
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout detected for IRQ 7.,INTERRUPT_CTRL Interrupt acknowledge timeout detected for IRQ 7.,1
INFO,POWER_CTRL,Power state transition to RUN mode completed,POWER_CTRL Power state transition to RUN mode completed,4
WARNING,DDR_CTRL,DDR controller reports high power consumption,DDR_CTRL DDR controller reports high power consumption,1
INFO,CLOCK_MANAGER,Clock source switched to high-frequency PLL,CLOCK_MANAGER Clock source switched to high-frequency PLL,0
CRITICAL,PCIE_CTRL,PCIe endpoint entered unrecognized reset state,PCIE_CTRL PCIe endpoint entered unrecognized reset state,6
CRITICAL,INTERRUPT_CTRL,Fatal error in interrupt vector table access.,INTERRUPT_CTRL Fatal error in interrupt vector table access.,1
INFO,AXI_CTRL,AXI read burst length set to 16,AXI_CTRL AXI read burst length set to 16,2
WARNING,DDR_CTRL,"DDR refresh cycle delayed, potential data loss risk","DDR_CTRL DDR refresh cycle delayed, potential data loss risk",1
WARNING,FIFO_BUF,"FIFO overflow prevented by backpressure, but imminent.","FIFO_BUF FIFO overflow prevented by backpressure, but imminent.",5
CRITICAL,PCIE_CTRL,"PCIe device configuration space corrupted, device unusable.","PCIE_CTRL PCIe device configuration space corrupted, device unusable.",6
ERROR,POWER_CTRL,Power sequencing controller stuck in intermediate state,POWER_CTRL Power sequencing controller stuck in intermediate state,4
INFO,FIFO_BUF,FIFO 'cmd_resp' has 5 entries written,FIFO_BUF FIFO 'cmd_resp' has 5 entries written,-1
INFO,AXI_CTRL,Read burst completed successfully for master 0,AXI_CTRL Read burst completed successfully for master 0,2
WARNING,PCIE_CTRL,PCIe TLP retry limit reached for multiple packets,PCIE_CTRL PCIe TLP retry limit reached for multiple packets,6
ERROR,AXI_CTRL,AXI read data channel backpressure detected,AXI_CTRL AXI read data channel backpressure detected,2
WARNING,AXI_CTRL,AXI write response received after extended delay from slave B.,AXI_CTRL AXI write response received after extended delay from slave B.,2
INFO,INTERRUPT_CTRL,Interrupt vector for IRQ23 dispatched,INTERRUPT_CTRL Interrupt vector for IRQ23 dispatched,1
INFO,AXI_CTRL,AXI interconnect health check passed,AXI_CTRL AXI interconnect health check passed,2
CRITICAL,CLOCK_MANAGER,Clock distribution fault detected on branch Z,CLOCK_MANAGER Clock distribution fault detected on branch Z,0
CRITICAL,MEM_CTRL,Multi-bit soft ECC error detected,MEM_CTRL Multi-bit soft ECC error detected,1
ERROR,DDR_CTRL,DDR memory rank calibration data corrupted,DDR_CTRL DDR memory rank calibration data corrupted,1
WARNING,POWER_CTRL,Voltage regulator output current exceeding design limits,POWER_CTRL Voltage regulator output current exceeding design limits,4
WARNING,AXI_CTRL,AXI response channel `RVALID` asserted without `RREADY`,AXI_CTRL AXI response channel `RVALID` asserted without `RREADY`,2
INFO,MEM_CTRL,Memory bank 0 activity increased,MEM_CTRL Memory bank 0 activity increased,1
CRITICAL,POWER_CTRL,"PMIC communication failure, system power critical","POWER_CTRL PMIC communication failure, system power critical",4
WARNING,PCIE_CTRL,PCIe TX buffer nearing capacity.,PCIE_CTRL PCIe TX buffer nearing capacity.,6
CRITICAL,PCIE_CTRL,"PCIe lane synchronization lost, link down (lane 0).","PCIE_CTRL PCIe lane synchronization lost, link down (lane 0).",6
ERROR,INTERRUPT_CTRL,Interrupt source not cleared after acknowledge,INTERRUPT_CTRL Interrupt source not cleared after acknowledge,1
WARNING,PCIE_CTRL,PCIe device ID register read incorrect value,PCIE_CTRL PCIe device ID register read incorrect value,6
ERROR,DDR_CTRL,DDR initialization failure,DDR_CTRL DDR initialization failure,1
ERROR,CLOCK_MANAGER,Clock domain crossing FIFO for 'video_stream' overflowed,CLOCK_MANAGER Clock domain crossing FIFO for 'video_stream' overflowed,0
ERROR,CACHE_CTRL,Cache dirty bit corruption detected on multiple lines.,CACHE_CTRL Cache dirty bit corruption detected on multiple lines.,1
INFO,MEM_CTRL,Memory prefetcher enabled,MEM_CTRL Memory prefetcher enabled,1
ERROR,MEM_CTRL,Memory controller write transaction rejected,MEM_CTRL Memory controller write transaction rejected,1
INFO,DMA_ENGINE,DMA channel 0 paused,DMA_ENGINE DMA channel 0 paused,3
WARNING,CLOCK_MANAGER,Clock domain crossing (CDC) synchronizer output jitter,CLOCK_MANAGER Clock domain crossing (CDC) synchronizer output jitter,0
INFO,PCIE_CTRL,PCIe link speed negotiated to X GT/s.,PCIE_CTRL PCIe link speed negotiated to X GT/s.,6
WARNING,FIFO_BUF,Input FIFO fill level at 85% capacity,FIFO_BUF Input FIFO fill level at 85% capacity,5
ERROR,AXI_CTRL,AXI write response channel incorrect ID,AXI_CTRL AXI write response channel incorrect ID,2
CRITICAL,POWER_CTRL,"Power rail VDD_MAIN detected instability, system power-off initiated","POWER_CTRL Power rail VDD_MAIN detected instability, system power-off initiated",4
INFO,MEM_CTRL,Memory controller performing background scrub,MEM_CTRL Memory controller performing background scrub,1
ERROR,INTERRUPT_CTRL,Interrupt pending signal stuck high,INTERRUPT_CTRL Interrupt pending signal stuck high,1
ERROR,CACHE_CTRL,Cache M-state writeback failure,CACHE_CTRL Cache M-state writeback failure,1
WARNING,INTERRUPT_CTRL,Interrupt handler registration pending for module,INTERRUPT_CTRL Interrupt handler registration pending for module,1
WARNING,PCIE_CTRL,PCIe transmit buffer approaching full capacity,PCIE_CTRL PCIe transmit buffer approaching full capacity,6
ERROR,DDR_CTRL,DDR ZQ calibration timeout,DDR_CTRL DDR ZQ calibration timeout,1
CRITICAL,POWER_CTRL,VCORE voltage rail critically unstable,POWER_CTRL VCORE voltage rail critically unstable,4
ERROR,PCIE_CTRL,PCIe flow control credits exhausted,PCIE_CTRL PCIe flow control credits exhausted,6
ERROR,AXI_CTRL,AXI write response channel RRESP/BRESP mismatch,AXI_CTRL AXI write response channel RRESP/BRESP mismatch,2
INFO,DMA_ENGINE,DMA channel reset completed,DMA_ENGINE DMA channel reset completed,3
INFO,DDR_CTRL,DDR memory access frequency stable,DDR_CTRL DDR memory access frequency stable,1
WARNING,DMA_ENGINE,DMA channel 5 busy for extended period,DMA_ENGINE DMA channel 5 busy for extended period,3
CRITICAL,DDR_CTRL,DDR VREF calibration failed during power-up,DDR_CTRL DDR VREF calibration failed during power-up,1
WARNING,PCIE_CTRL,PCIe receiver detects excessive bit errors,PCIE_CTRL PCIe receiver detects excessive bit errors,6
ERROR,POWER_CTRL,Voltage regulator response timeout detected for VDD_CORE,POWER_CTRL Voltage regulator response timeout detected for VDD_CORE,4
ERROR,CACHE_CTRL,Cache line 'dirty' bit unexpectedly cleared,CACHE_CTRL Cache line 'dirty' bit unexpectedly cleared,1
ERROR,PCIE_CTRL,TLPs dropped due to internal buffer overflow in PCIe controller.,PCIE_CTRL TLPs dropped due to internal buffer overflow in PCIe controller.,6
WARNING,DDR_CTRL,DDR command queue exceeding normal limits,DDR_CTRL DDR command queue exceeding normal limits,1
CRITICAL,MEM_CTRL,Memory controller configuration error at boot,MEM_CTRL Memory controller configuration error at boot,1
WARNING,POWER_CTRL,Standby power domain current draw elevated,POWER_CTRL Standby power domain current draw elevated,4
INFO,FIFO_BUF,FIFO 'data_out' successfully flushed,FIFO_BUF FIFO 'data_out' successfully flushed,5
CRITICAL,PCIE_CTRL,"PCIe lane synchronization lost, link permanently down. (link failure)","PCIE_CTRL PCIe lane synchronization lost, link permanently down. (link failure)",6
INFO,CACHE_CTRL,Cache hit on data line at 0x1234,CACHE_CTRL Cache hit on data line at 0x1234,1
CRITICAL,PCIE_CTRL,PCIe link down: unrecoverable loss of synchronization (PCIe lane synchronization lost),PCIE_CTRL PCIe link down: unrecoverable loss of synchronization (PCIe lane synchronization lost),6
INFO,FIFO_BUF,FIFO push operation completed,FIFO_BUF FIFO push operation completed,5
ERROR,CACHE_CTRL,Cache data RAM ECC error detected,CACHE_CTRL Cache data RAM ECC error detected,1
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding expected threshold of 200 cycles,INTERRUPT_CTRL Interrupt latency exceeding expected threshold of 200 cycles,1
CRITICAL,POWER_CTRL,Entire system power shutdown due to critical rail failure,POWER_CTRL Entire system power shutdown due to critical rail failure,4
INFO,DDR_CTRL,Memory controller entering low power state,DDR_CTRL Memory controller entering low power state,1
WARNING,PCIE_CTRL,PCIe TLP poisoning detected on receive path,PCIE_CTRL PCIe TLP poisoning detected on receive path,6
ERROR,DMA_ENGINE,DMA destination address 0x97805d76 out of bounds.,DMA_ENGINE DMA destination address 0x97805d76 out of bounds.,3
WARNING,POWER_CTRL,Power management unit self-test detected minor anomaly,POWER_CTRL Power management unit self-test detected minor anomaly,4
CRITICAL,AXI_CTRL,AXI protocol assertion failure: exclusive access violation,AXI_CTRL AXI protocol assertion failure: exclusive access violation,2
ERROR,AXI_CTRL,AXI write address alignment violation detected for 64-bit access,AXI_CTRL AXI write address alignment violation detected for 64-bit access,2
ERROR,INTERRUPT_CTRL,"Interrupt storm detected, rate 50k interrupts/sec.","INTERRUPT_CTRL Interrupt storm detected, rate 50k interrupts/sec.",1
ERROR,CACHE_CTRL,Cache way allocation logic produced an illegal index.,CACHE_CTRL Cache way allocation logic produced an illegal index.,-1
INFO,DDR_CTRL,DDR bank activated,DDR_CTRL DDR bank activated,1
CRITICAL,MEM_CTRL,Memory BIST (Built-In Self Test) failed,MEM_CTRL Memory BIST (Built-In Self Test) failed,1
INFO,CACHE_CTRL,Cache line invalidated due to snoop hit,CACHE_CTRL Cache line invalidated due to snoop hit,1
INFO,CACHE_CTRL,Cache line replaced,CACHE_CTRL Cache line replaced,1
INFO,POWER_CTRL,POWER_CTRL debug status collected.,POWER_CTRL POWER_CTRL debug status collected.,-1
INFO,INTERRUPT_CTRL,Interrupt queue cleared,INTERRUPT_CTRL Interrupt queue cleared,1
ERROR,DDR_CTRL,DDR PHY training error on DQS lane,DDR_CTRL DDR PHY training error on DQS lane,1
WARNING,AXI_CTRL,AXI burst length variance high,AXI_CTRL AXI burst length variance high,2
ERROR,AXI_CTRL,AXI write address setup time violation,AXI_CTRL AXI write address setup time violation,2
ERROR,CACHE_CTRL,Cache line replacement algorithm error,CACHE_CTRL Cache line replacement algorithm error,1
WARNING,INTERRUPT_CTRL,Interrupt controller internal queue nearing capacity.,INTERRUPT_CTRL Interrupt controller internal queue nearing capacity.,1
ERROR,CACHE_CTRL,Cache invalidation protocol failure,CACHE_CTRL Cache invalidation protocol failure,1
CRITICAL,DMA_ENGINE,"DMA engine FSM in permanent halt state, invalid state transition.","DMA_ENGINE DMA engine FSM in permanent halt state, invalid state transition.",3
ERROR,PCIE_CTRL,PCIe TLP egress queue overflow,PCIE_CTRL PCIe TLP egress queue overflow,6
INFO,PCIE_CTRL,PCIe endpoint enabled,PCIE_CTRL PCIe endpoint enabled,6
WARNING,POWER_CTRL,POWER_CTRL observed higher than expected transaction latency (TxID: 153).,POWER_CTRL POWER_CTRL observed higher than expected transaction latency (TxID: 153).,-1
ERROR,AXI_CTRL,AXI write burst length mismatch with master request,AXI_CTRL AXI write burst length mismatch with master request,2
INFO,FIFO_BUF,Read pointer advanced,FIFO_BUF Read pointer advanced,5
CRITICAL,INTERRUPT_CTRL,"Non-maskable interrupt not serviced, watchdog triggered","INTERRUPT_CTRL Non-maskable interrupt not serviced, watchdog triggered",-1
CRITICAL,DDR_CTRL,DDR memory module returned unexpected device ID,DDR_CTRL DDR memory module returned unexpected device ID,1
WARNING,PCIE_CTRL,PCIe flow control credits nearing exhaustion,PCIE_CTRL PCIe flow control credits nearing exhaustion,6
WARNING,DDR_CTRL,DDR access latency exceeding spec,DDR_CTRL DDR access latency exceeding spec,1
CRITICAL,FIFO_BUF,Persistent FIFO overflow causing data loss,FIFO_BUF Persistent FIFO overflow causing data loss,5
ERROR,DDR_CTRL,DDR command scheduler deadlock,DDR_CTRL DDR command scheduler deadlock,1
ERROR,AXI_CTRL,AXI write response mismatch detected.,AXI_CTRL AXI write response mismatch detected.,2
ERROR,DDR_CTRL,DDR MR register write failed verification.,DDR_CTRL DDR MR register write failed verification.,1
ERROR,PCIE_CTRL,PCIe surprise link down detected,PCIE_CTRL PCIe surprise link down detected,6
ERROR,MEM_CTRL,Double bit ECC corruption detected at 0xFF00FF00,MEM_CTRL Double bit ECC corruption detected at 0xFF00FF00,1
WARNING,POWER_CTRL,External power supply unstable,POWER_CTRL External power supply unstable,4
INFO,CLOCK_MANAGER,Clock buffer bypass path activated,CLOCK_MANAGER Clock buffer bypass path activated,0
INFO,POWER_CTRL,Power rail current monitoring reset,POWER_CTRL Power rail current monitoring reset,4
ERROR,DMA_ENGINE,DMA channel 8 configuration timeout,DMA_ENGINE DMA channel 8 configuration timeout,3
INFO,FIFO_BUF,FIFO depth utilization 80%,FIFO_BUF FIFO depth utilization 80%,5
ERROR,FIFO_BUF,"FIFO underflow detected, read from empty FIFO buffer for channel 0x2","FIFO_BUF FIFO underflow detected, read from empty FIFO buffer for channel 0x2",5
ERROR,FIFO_BUF,FIFO write after full attempt,FIFO_BUF FIFO write after full attempt,5
CRITICAL,DDR_CTRL,DDR memory data path integrity compromised,DDR_CTRL DDR memory data path integrity compromised,1
CRITICAL,DDR_CTRL,DDR memory device not responding to any commands,DDR_CTRL DDR memory device not responding to any commands,1
INFO,PCIE_CTRL,PCIe message signaled interrupt posted,PCIE_CTRL PCIe message signaled interrupt posted,6
ERROR,DDR_CTRL,Memory address range violation detected during write,DDR_CTRL Memory address range violation detected during write,1
INFO,INTERRUPT_CTRL,Interrupt handler for 'ETH' module dispatched,INTERRUPT_CTRL Interrupt handler for 'ETH' module dispatched,-1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller internal watchdog timeout, system halt","INTERRUPT_CTRL Interrupt controller internal watchdog timeout, system halt",1
CRITICAL,PCIE_CTRL,PCIe physical layer lane de-synchronization,PCIE_CTRL PCIe physical layer lane de-synchronization,6
INFO,CLOCK_MANAGER,Clock monitor threshold updated,CLOCK_MANAGER Clock monitor threshold updated,-1
CRITICAL,MEM_CTRL,"ECC parity mismatch detected on memory at 0x0000FF00, uncorrectable.","MEM_CTRL ECC parity mismatch detected on memory at 0x0000FF00, uncorrectable.",1
WARNING,CLOCK_MANAGER,Frequency drift detected on CLK_AUDIO,CLOCK_MANAGER Frequency drift detected on CLK_AUDIO,0
ERROR,CACHE_CTRL,Cache tag parity error detected for entry 0.,CACHE_CTRL Cache tag parity error detected for entry 0.,1
INFO,CLOCK_MANAGER,Debug clock output enabled.,CLOCK_MANAGER Debug clock output enabled.,0
CRITICAL,INTERRUPT_CTRL,Interrupt controller logic reports self-test failure.,INTERRUPT_CTRL Interrupt controller logic reports self-test failure.,1
CRITICAL,DMA_ENGINE,DMA transfer stuck in pending state indefinitely,DMA_ENGINE DMA transfer stuck in pending state indefinitely,3
ERROR,AXI_CTRL,AXI read data channel handshake timeout,AXI_CTRL AXI read data channel handshake timeout,2
WARNING,FIFO_BUF,FIFO nearing capacity: 99/140 entries used,FIFO_BUF FIFO nearing capacity: 99/140 entries used,5
ERROR,PCIE_CTRL,"PCIe packet framing error, length mismatch","PCIE_CTRL PCIe packet framing error, length mismatch",6
INFO,CLOCK_MANAGER,Clock frequency monitoring enabled,CLOCK_MANAGER Clock frequency monitoring enabled,0
ERROR,INTERRUPT_CTRL,Interrupt controller responded with an invalid vector ID.,INTERRUPT_CTRL Interrupt controller responded with an invalid vector ID.,1
INFO,MEM_CTRL,Address translation unit configured,MEM_CTRL Address translation unit configured,1
INFO,POWER_CTRL,Core voltage boosted for performance,POWER_CTRL Core voltage boosted for performance,-1
WARNING,FIFO_BUF,FIFO nearing empty: 11/30 entries remaining,FIFO_BUF FIFO nearing empty: 11/30 entries remaining,5
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, potential underflow","FIFO_BUF FIFO read pointer approaching write pointer, potential underflow",5
ERROR,CACHE_CTRL,Dirty bit corruption detected in cache line,CACHE_CTRL Dirty bit corruption detected in cache line,1
INFO,PCIE_CTRL,PCIe device function enabled,PCIE_CTRL PCIe device function enabled,6
WARNING,AXI_CTRL,AXI `BREADY` asserted without `BVALID` being asserted first,AXI_CTRL AXI `BREADY` asserted without `BVALID` being asserted first,2
ERROR,CLOCK_MANAGER,Clock tree synthesis reported max delay violation,CLOCK_MANAGER Clock tree synthesis reported max delay violation,0
INFO,CLOCK_MANAGER,Clock 'ETH_TX_CLK' enabled,CLOCK_MANAGER Clock 'ETH_TX_CLK' enabled,-1
WARNING,DDR_CTRL,DDR memory page hit rate decreasing,DDR_CTRL DDR memory page hit rate decreasing,1
WARNING,POWER_CTRL,Temperature sensor reporting high value,POWER_CTRL Temperature sensor reporting high value,4
WARNING,POWER_CTRL,Power domain transition delay detected for domain 'GPU'.,POWER_CTRL Power domain transition delay detected for domain 'GPU'.,4
INFO,FIFO_BUF,Read pointer reset to start of buffer,FIFO_BUF Read pointer reset to start of buffer,5
ERROR,POWER_CTRL,Power-on sequence stalled,POWER_CTRL Power-on sequence stalled,4
CRITICAL,MEM_CTRL,Memory controller internal bus arbitration failure,MEM_CTRL Memory controller internal bus arbitration failure,1
WARNING,DMA_ENGINE,DMA channel 2 completion queue nearing capacity,DMA_ENGINE DMA channel 2 completion queue nearing capacity,3
WARNING,CLOCK_MANAGER,Clock tree static timing violation margin below 50ps,CLOCK_MANAGER Clock tree static timing violation margin below 50ps,-1
INFO,MEM_CTRL,Memory protection unit enabled,MEM_CTRL Memory protection unit enabled,1
WARNING,DMA_ENGINE,DMA_ENGINE resource allocation nearing limit (91% utilized).,DMA_ENGINE DMA_ENGINE resource allocation nearing limit (91% utilized).,3
ERROR,CLOCK_MANAGER,Clock frequency configuration applied with warnings,CLOCK_MANAGER Clock frequency configuration applied with warnings,0
CRITICAL,CLOCK_MANAGER,Critical clock line stuck at logic 0,CLOCK_MANAGER Critical clock line stuck at logic 0,-1
INFO,FIFO_BUF,FIFO 'debug_data' is empty,FIFO_BUF FIFO 'debug_data' is empty,5
ERROR,CLOCK_MANAGER,Clock domain crossing FIFO overflow on data path,CLOCK_MANAGER Clock domain crossing FIFO overflow on data path,0
INFO,AXI_CTRL,AXI outstanding transaction count within limits,AXI_CTRL AXI outstanding transaction count within limits,2
ERROR,PCIE_CTRL,PCIe unsupported request type received,PCIE_CTRL PCIe unsupported request type received,6
INFO,INTERRUPT_CTRL,Interrupt controller hardware version read,INTERRUPT_CTRL Interrupt controller hardware version read,1
CRITICAL,POWER_CTRL,Power domain 'VDD_CORE' voltage droop beyond critical threshold,POWER_CTRL Power domain 'VDD_CORE' voltage droop beyond critical threshold,4
WARNING,CACHE_CTRL,L2 cache eviction rate elevated,CACHE_CTRL L2 cache eviction rate elevated,1
INFO,FIFO_BUF,FIFO read data outputting,FIFO_BUF FIFO read data outputting,5
WARNING,PCIE_CTRL,"PCIe TLP header CRC errors detected, non-fatal","PCIE_CTRL PCIe TLP header CRC errors detected, non-fatal",6
CRITICAL,MEM_CTRL,Double bit ECC error on system RAM,MEM_CTRL Double bit ECC error on system RAM,1
INFO,MEM_CTRL,Memory controller entered low-power state,MEM_CTRL Memory controller entered low-power state,1
WARNING,FIFO_BUF,FIFO_CONTROL_REGISTERS average latency increasing.,FIFO_BUF FIFO_CONTROL_REGISTERS average latency increasing.,5
CRITICAL,INTERRUPT_CTRL,Interrupt vector table access protection violation,INTERRUPT_CTRL Interrupt vector table access protection violation,1
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range for high-speed I/O,CLOCK_MANAGER Clock skew approaching unsafe range for high-speed I/O,0
CRITICAL,DMA_ENGINE,"DMA internal data path corruption, unrecoverable parity error.","DMA_ENGINE DMA internal data path corruption, unrecoverable parity error.",3
INFO,MEM_CTRL,Memory bank Z enabled for access,MEM_CTRL Memory bank Z enabled for access,1
ERROR,AXI_CTRL,AXI slave 0x08 responded with SLVERR,AXI_CTRL AXI slave 0x08 responded with SLVERR,2
ERROR,PCIE_CTRL,PCIe transaction layer protocol error,PCIE_CTRL PCIe transaction layer protocol error,6
INFO,DDR_CTRL,Memory refresh scheduling updated,DDR_CTRL Memory refresh scheduling updated,1
INFO,PCIE_CTRL,PCIe M.2 SSD enumerated successfully,PCIE_CTRL PCIe M.2 SSD enumerated successfully,-1
ERROR,AXI_CTRL,AXI ID tag mismatch on response.,AXI_CTRL AXI ID tag mismatch on response.,2
ERROR,CACHE_CTRL,Cache tag comparison mismatch.,CACHE_CTRL Cache tag comparison mismatch.,1
CRITICAL,DMA_ENGINE,DMA engine detected internal bus error during descriptor processing.,DMA_ENGINE DMA engine detected internal bus error during descriptor processing.,3
CRITICAL,MEM_CTRL,"Memory controller command queue starvation, no requests processed.","MEM_CTRL Memory controller command queue starvation, no requests processed.",1
INFO,AXI_CTRL,AXI manager connected to all subordinates,AXI_CTRL AXI manager connected to all subordinates,-1
INFO,PCIE_CTRL,PCIe link trained successfully to Gen3 speed,PCIE_CTRL PCIe link trained successfully to Gen3 speed,6
INFO,DDR_CTRL,DDR controller switching to low power mode.,DDR_CTRL DDR controller switching to low power mode.,1
INFO,POWER_CTRL,Voltage regulator enabled for 3.3V rail.,POWER_CTRL Voltage regulator enabled for 3.3V rail.,4
INFO,INTERRUPT_CTRL,Interrupt dispatch latency measured,INTERRUPT_CTRL Interrupt dispatch latency measured,1
WARNING,INTERRUPT_CTRL,Interrupt queue depth at 75% capacity,INTERRUPT_CTRL Interrupt queue depth at 75% capacity,1
WARNING,PCIE_CTRL,PCIe link stability degraded due to high error rate,PCIE_CTRL PCIe link stability degraded due to high error rate,6
WARNING,DMA_ENGINE,DMA queue depth approaching critical,DMA_ENGINE DMA queue depth approaching critical,3
ERROR,PCIE_CTRL,PCIe header parsing error,PCIE_CTRL PCIe header parsing error,6
CRITICAL,POWER_CTRL,"CRITICAL: Core power domain Z failed to reach target voltage 0.9V, system halt.","POWER_CTRL CRITICAL: Core power domain Z failed to reach target voltage 0.9V, system halt.",-1
ERROR,CACHE_CTRL,Cache write buffer full,CACHE_CTRL Cache write buffer full,1
INFO,AXI_CTRL,AXI transaction completed successfully.,AXI_CTRL AXI transaction completed successfully.,2
INFO,CACHE_CTRL,Cache data invalidation successful.,CACHE_CTRL Cache data invalidation successful.,1
ERROR,FIFO_BUF,FIFO control logic state machine error,FIFO_BUF FIFO control logic state machine error,5
INFO,CLOCK_MANAGER,Clock tree reconfigured for low power mode,CLOCK_MANAGER Clock tree reconfigured for low power mode,-1
CRITICAL,DDR_CTRL,DDR chip select signal permanently asserted,DDR_CTRL DDR chip select signal permanently asserted,8
WARNING,DMA_ENGINE,"DMA transfer pending for extended period, timing violation suspected.","DMA_ENGINE DMA transfer pending for extended period, timing violation suspected.",3
INFO,INTERRUPT_CTRL,Interrupt controller in master mode,INTERRUPT_CTRL Interrupt controller in master mode,-1
INFO,INTERRUPT_CTRL,Interrupt masking enabled for non-critical IRQs,INTERRUPT_CTRL Interrupt masking enabled for non-critical IRQs,1
WARNING,DDR_CTRL,DDR memory refresh cycle skipped,DDR_CTRL DDR memory refresh cycle skipped,1
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold for L1,CACHE_CTRL Cache miss rate exceeding expected threshold for L1,1
WARNING,AXI_CTRL,AXI write burst outstanding transactions high,AXI_CTRL AXI write burst outstanding transactions high,2
INFO,MEM_CTRL,Memory ECC scrub completed with corrections,MEM_CTRL Memory ECC scrub completed with corrections,1
ERROR,MEM_CTRL,Page fault detected,MEM_CTRL Page fault detected,1
INFO,FIFO_BUF,Write operation successful for 32-bit data.,FIFO_BUF Write operation successful for 32-bit data.,5
WARNING,POWER_CTRL,Voltage rail droop detected during heavy load burst,POWER_CTRL Voltage rail droop detected during heavy load burst,4
WARNING,CACHE_CTRL,Cache miss rate for L1 data cache exceeding 5%,CACHE_CTRL Cache miss rate for L1 data cache exceeding 5%,1
WARNING,INTERRUPT_CTRL,Interrupt pending register shows stale data,INTERRUPT_CTRL Interrupt pending register shows stale data,1
WARNING,AXI_CTRL,AXI master 'M1' observing excessive wait states,AXI_CTRL AXI master 'M1' observing excessive wait states,2
ERROR,DMA_ENGINE,DMA transfer completion interrupt not generated,DMA_ENGINE DMA transfer completion interrupt not generated,3
ERROR,PCIE_CTRL,PCIe TLP header corruption detected.,PCIE_CTRL PCIe TLP header corruption detected.,6
ERROR,POWER_CTRL,Power rail sequencing timeout detected,POWER_CTRL Power rail sequencing timeout detected,4
ERROR,INTERRUPT_CTRL,Interrupt controller internal register access error,INTERRUPT_CTRL Interrupt controller internal register access error,1
WARNING,DMA_ENGINE,DMA channel arbitration contention,DMA_ENGINE DMA channel arbitration contention,3
ERROR,DMA_ENGINE,DMA channel 0 transfer error,DMA_ENGINE DMA channel 0 transfer error,3
ERROR,MEM_CTRL,Memory controller detected an internal bus timeout,MEM_CTRL Memory controller detected an internal bus timeout,1
ERROR,CACHE_CTRL,Cache tag parity error detected.,CACHE_CTRL Cache tag parity error detected.,1
CRITICAL,POWER_CTRL,"Thermal shutdown initiated, hardware protection mode","POWER_CTRL Thermal shutdown initiated, hardware protection mode",4
CRITICAL,INTERRUPT_CTRL,"Interrupt controller power domain failure, interrupts inoperable.","INTERRUPT_CTRL Interrupt controller power domain failure, interrupts inoperable.",-1
ERROR,MEM_CTRL,Memory controller responded with an invalid read data.,MEM_CTRL Memory controller responded with an invalid read data.,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller hard reset sequence failed,INTERRUPT_CTRL Interrupt controller hard reset sequence failed,1
CRITICAL,MEM_CTRL,"CRITICAL: Memory controller state machine entered invalid state 0x3C, system unusable.","MEM_CTRL CRITICAL: Memory controller state machine entered invalid state 0x3C, system unusable.",1
WARNING,DDR_CTRL,DDR write leveling adjustment ongoing,DDR_CTRL DDR write leveling adjustment ongoing,1
INFO,MEM_CTRL,Memory page 0x100000 marked as dirty,MEM_CTRL Memory page 0x100000 marked as dirty,1
ERROR,PCIE_CTRL,PCIe link state transition failure,PCIE_CTRL PCIe link state transition failure,6
WARNING,CLOCK_MANAGER,Clock skew in region R exceeding threshold,CLOCK_MANAGER Clock skew in region R exceeding threshold,-1
WARNING,AXI_CTRL,AXI bus contention detected on shared resource,AXI_CTRL AXI bus contention detected on shared resource,2
WARNING,DDR_CTRL,DDR memory controller reports frequent ECC corrections,DDR_CTRL DDR memory controller reports frequent ECC corrections,1
WARNING,AXI_CTRL,AXI outstanding write transactions high,AXI_CTRL AXI outstanding write transactions high,2
ERROR,DDR_CTRL,DDR write operation failed at address 0x12345678.,DDR_CTRL DDR write operation failed at address 0x12345678.,1
CRITICAL,DDR_CTRL,"DDR PHY PLL lock lost, memory unaccessible.","DDR_CTRL DDR PHY PLL lock lost, memory unaccessible.",1
INFO,POWER_CTRL,Power state transition to standby completed,POWER_CTRL Power state transition to standby completed,4
INFO,DMA_ENGINE,DMA transfer completion interrupt asserted,DMA_ENGINE DMA transfer completion interrupt asserted,3
INFO,CACHE_CTRL,Cache line state transition completed,CACHE_CTRL Cache line state transition completed,1
ERROR,INTERRUPT_CTRL,Interrupt priority encoder fault,INTERRUPT_CTRL Interrupt priority encoder fault,1
WARNING,CLOCK_MANAGER,Clock domain crossing bridge experiencing data drops,CLOCK_MANAGER Clock domain crossing bridge experiencing data drops,0
WARNING,DMA_ENGINE,DMA channel 1 pending requests queue nearing capacity.,DMA_ENGINE DMA channel 1 pending requests queue nearing capacity.,3
WARNING,INTERRUPT_CTRL,Spurious interrupt detected on IRQ line 3,INTERRUPT_CTRL Spurious interrupt detected on IRQ line 3,1
CRITICAL,MEM_CTRL,Memory controller entered illegal arbitration state,MEM_CTRL Memory controller entered illegal arbitration state,1
WARNING,INTERRUPT_CTRL,"Multiple interrupts pending, processing delay.","INTERRUPT_CTRL Multiple interrupts pending, processing delay.",1
ERROR,CACHE_CTRL,Cache tag RAM parity error,CACHE_CTRL Cache tag RAM parity error,1
CRITICAL,CLOCK_MANAGER,"Uncontrolled clock domain crossing metastability, data path corrupted.","CLOCK_MANAGER Uncontrolled clock domain crossing metastability, data path corrupted.",0
WARNING,PCIE_CTRL,PCIe replay buffer approaching overflow,PCIE_CTRL PCIe replay buffer approaching overflow,6
WARNING,POWER_CTRL,Auxiliary rail voltage fluctuation observed,POWER_CTRL Auxiliary rail voltage fluctuation observed,4
WARNING,AXI_CTRL,AXI transaction completion delayed on specific ID,AXI_CTRL AXI transaction completion delayed on specific ID,2
INFO,POWER_CTRL,Power rail enabled.,POWER_CTRL Power rail enabled.,4
CRITICAL,MEM_CTRL,Memory controller entered unexpected power-gated state,MEM_CTRL Memory controller entered unexpected power-gated state,1
ERROR,PCIE_CTRL,PCIe AER (Advanced Error Reporting) protocol violation,PCIE_CTRL PCIe AER (Advanced Error Reporting) protocol violation,6
INFO,FIFO_BUF,FIFO reset initiated.,FIFO_BUF FIFO reset initiated.,5
ERROR,DDR_CTRL,DDR command timing violation: RAS to CAS delay exceeded,DDR_CTRL DDR command timing violation: RAS to CAS delay exceeded,1
ERROR,MEM_CTRL,Memory controller state machine entered an unexpected state.,MEM_CTRL Memory controller state machine entered an unexpected state.,1
CRITICAL,POWER_CTRL,"Power rail instability detected on 1.7V, system shutdown.","POWER_CTRL Power rail instability detected on 1.7V, system shutdown.",4
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for IRQ 5,INTERRUPT_CTRL Interrupt dispatch completed for IRQ 5,1
CRITICAL,MEM_CTRL,Memory controller internal FSM stuck in fatal state,MEM_CTRL Memory controller internal FSM stuck in fatal state,1
ERROR,CACHE_CTRL,Cache line writeback timeout,CACHE_CTRL Cache line writeback timeout,1
CRITICAL,PCIE_CTRL,PCIe Root Complex reported fatal error,PCIE_CTRL PCIe Root Complex reported fatal error,6
INFO,DMA_ENGINE,DMA descriptor fetch initiated.,DMA_ENGINE DMA descriptor fetch initiated.,3
WARNING,DDR_CTRL,DDR timing closure marginal,DDR_CTRL DDR timing closure marginal,-1
ERROR,FIFO_BUF,FIFO 'COMMAND_IN' overflow detected during stress test,FIFO_BUF FIFO 'COMMAND_IN' overflow detected during stress test,5
INFO,CLOCK_MANAGER,Clock domain crossing FIFO depth 0,CLOCK_MANAGER Clock domain crossing FIFO depth 0,0
CRITICAL,AXI_CTRL,AXI interconnect deadlock detected on master 3,AXI_CTRL AXI interconnect deadlock detected on master 3,2
INFO,FIFO_BUF,FIFO pop operation successful,FIFO_BUF FIFO pop operation successful,5
ERROR,CACHE_CTRL,Cache store buffer overflow,CACHE_CTRL Cache store buffer overflow,1
WARNING,AXI_CTRL,AXI master bus arbitration delay,AXI_CTRL AXI master bus arbitration delay,2
INFO,MEM_CTRL,Memory initialization sequence completed successfully.,MEM_CTRL Memory initialization sequence completed successfully.,1
CRITICAL,CACHE_CTRL,Cache way selector logic fault,CACHE_CTRL Cache way selector logic fault,1
WARNING,MEM_CTRL,Memory page access latency showing variance,MEM_CTRL Memory page access latency showing variance,1
INFO,DMA_ENGINE,DMA descriptor processed for channel 3.,DMA_ENGINE DMA descriptor processed for channel 3.,3
INFO,PCIE_CTRL,PCIe AER fatal error reported by device,PCIE_CTRL PCIe AER fatal error reported by device,6
INFO,MEM_CTRL,Memory diagnostic scan completed,MEM_CTRL Memory diagnostic scan completed,1
INFO,PCIE_CTRL,PCIe transaction layer packet (TLP) generated,PCIE_CTRL PCIe transaction layer packet (TLP) generated,6
INFO,AXI_CTRL,AXI read channel granted access,AXI_CTRL AXI read channel granted access,2
WARNING,CLOCK_MANAGER,PLL output phase noise detected.,CLOCK_MANAGER PLL output phase noise detected.,0
INFO,AXI_CTRL,AXI transaction latency report generated,AXI_CTRL AXI transaction latency report generated,2
CRITICAL,MEM_CTRL,Memory data bus stuck-at-0 fault detected,MEM_CTRL Memory data bus stuck-at-0 fault detected,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller unresponsive,INTERRUPT_CTRL Interrupt controller unresponsive,1
INFO,DMA_ENGINE,DMA channel status registered,DMA_ENGINE DMA channel status registered,3
CRITICAL,MEM_CTRL,Memory controller state machine entered an unrecoverable error state,MEM_CTRL Memory controller state machine entered an unrecoverable error state,1
INFO,POWER_CTRL,Power management handshake successful,POWER_CTRL Power management handshake successful,4
CRITICAL,POWER_CTRL,"CRITICAL: Power rail instability detected (rail Main), potential hardware damage.","POWER_CTRL CRITICAL: Power rail instability detected (rail Main), potential hardware damage.",4
ERROR,POWER_CTRL,Power sequencing controller failed to transition to next state,POWER_CTRL Power sequencing controller failed to transition to next state,4
WARNING,CACHE_CTRL,Cache coherence protocol overhead increased,CACHE_CTRL Cache coherence protocol overhead increased,1
ERROR,MEM_CTRL,Memory parity error detected on read data,MEM_CTRL Memory parity error detected on read data,1
WARNING,CLOCK_MANAGER,Jitter exceeding limits for critical path,CLOCK_MANAGER Jitter exceeding limits for critical path,0
INFO,PCIE_CTRL,PCIe Gen4 link width negotiated to x16,PCIE_CTRL PCIe Gen4 link width negotiated to x16,6
WARNING,FIFO_BUF,FIFO_ETH_TX data starvation detected,FIFO_BUF FIFO_ETH_TX data starvation detected,-1
INFO,FIFO_BUF,FIFO empty status confirmed,FIFO_BUF FIFO empty status confirmed,5
CRITICAL,AXI_CTRL,AXI bus arbiter entered a livelock state,AXI_CTRL AXI bus arbiter entered a livelock state,2
ERROR,DMA_ENGINE,DMA transfer size register corrupted during operation,DMA_ENGINE DMA transfer size register corrupted during operation,3
ERROR,AXI_CTRL,AXI interconnect bus contention.,AXI_CTRL AXI interconnect bus contention.,2
WARNING,POWER_CTRL,Temperature sensor 3 approaching critical limit (100C).,POWER_CTRL Temperature sensor 3 approaching critical limit (100C).,4
CRITICAL,MEM_CTRL,Uncorrectable ECC error detected on memory address 0xDEADBEEF,MEM_CTRL Uncorrectable ECC error detected on memory address 0xDEADBEEF,1
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range between domain A and B,CLOCK_MANAGER Clock skew approaching unsafe range between domain A and B,0
CRITICAL,CACHE_CTRL,"CACHE_CTRL: Catastrophic timing violation, requiring system reset. (unmet timing constraint)","CACHE_CTRL CACHE_CTRL: Catastrophic timing violation, requiring system reset. (unmet timing constraint)",1
ERROR,CLOCK_MANAGER,Asynchronous reset de-assertion in CDC path Z.,CLOCK_MANAGER Asynchronous reset de-assertion in CDC path Z.,-1
INFO,MEM_CTRL,Memory controller read buffer occupancy optimal,MEM_CTRL Memory controller read buffer occupancy optimal,1
WARNING,POWER_CTRL,Power domain 'GPU' voltage droop exceeding 5%,POWER_CTRL Power domain 'GPU' voltage droop exceeding 5%,4
INFO,FIFO_BUF,"Single entry read from FIFO, 7 entries remaining","FIFO_BUF Single entry read from FIFO, 7 entries remaining",5
WARNING,DMA_ENGINE,"DMA channel 0 stalled, waiting for bus access.","DMA_ENGINE DMA channel 0 stalled, waiting for bus access.",3
INFO,FIFO_BUF,FIFO 'usb_rx' status: 25% full,FIFO_BUF FIFO 'usb_rx' status: 25% full,-1
ERROR,POWER_CTRL,Power domain X failed to power down,POWER_CTRL Power domain X failed to power down,4
CRITICAL,POWER_CTRL,Unrecoverable power-on reset failure,POWER_CTRL Unrecoverable power-on reset failure,4
ERROR,CLOCK_MANAGER,CLOCK_MANAGER: state machine fault - control logic sequence error detected.,CLOCK_MANAGER CLOCK_MANAGER: state machine fault - control logic sequence error detected.,0
ERROR,MEM_CTRL,Unaligned memory access fault detected on write,MEM_CTRL Unaligned memory access fault detected on write,1
INFO,AXI_CTRL,Read address '0xABCD' issued by master 1,AXI_CTRL Read address '0xABCD' issued by master 1,2
CRITICAL,DDR_CTRL,DDR memory training sequence failed to converge,DDR_CTRL DDR memory training sequence failed to converge,1
CRITICAL,AXI_CTRL,AXI system master arbitration logic permanently stalled,AXI_CTRL AXI system master arbitration logic permanently stalled,2
INFO,DMA_ENGINE,DMA transfer aborted by software,DMA_ENGINE DMA transfer aborted by software,3
INFO,POWER_CTRL,Thermal sensor 0 reports 55C,POWER_CTRL Thermal sensor 0 reports 55C,4
INFO,MEM_CTRL,Data path idle,MEM_CTRL Data path idle,-1
ERROR,PCIE_CTRL,PCIe upstream bridge arbitration conflict.,PCIE_CTRL PCIe upstream bridge arbitration conflict.,-1
INFO,CLOCK_MANAGER,Secondary clock source selected,CLOCK_MANAGER Secondary clock source selected,0
INFO,INTERRUPT_CTRL,Edge-triggered interrupt detected,INTERRUPT_CTRL Edge-triggered interrupt detected,1
INFO,POWER_CTRL,Thermal sensor reporting optimal temperature,POWER_CTRL Thermal sensor reporting optimal temperature,4
INFO,FIFO_BUF,FIFO 'status_log' initialized to empty,FIFO_BUF FIFO 'status_log' initialized to empty,5
WARNING,AXI_CTRL,AXI write channel backlog,AXI_CTRL AXI write channel backlog,2
WARNING,CLOCK_MANAGER,Clock domain crossing FIFO nearing critical levels,CLOCK_MANAGER Clock domain crossing FIFO nearing critical levels,0
INFO,INTERRUPT_CTRL,Interrupt masking applied for non-critical sources,INTERRUPT_CTRL Interrupt masking applied for non-critical sources,1
WARNING,INTERRUPT_CTRL,"Multiple interrupts pending, processing delayed.","INTERRUPT_CTRL Multiple interrupts pending, processing delayed.",1
WARNING,INTERRUPT_CTRL,Interrupt acknowledge latency increasing,INTERRUPT_CTRL Interrupt acknowledge latency increasing,1
WARNING,AXI_CTRL,AXI bus utilization over 90%,AXI_CTRL AXI bus utilization over 90%,2
CRITICAL,CLOCK_MANAGER,"PLL failed to lock after reset, unrecoverable timing violation.","CLOCK_MANAGER PLL failed to lock after reset, unrecoverable timing violation.",0
WARNING,CACHE_CTRL,L1 instruction cache miss rate exceeding 15%,CACHE_CTRL L1 instruction cache miss rate exceeding 15%,1
ERROR,AXI_CTRL,AXI write data strobe count mismatch,AXI_CTRL AXI write data strobe count mismatch,-1
CRITICAL,FIFO_BUF,FIFO control logic entered undefined state,FIFO_BUF FIFO control logic entered undefined state,5
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout for critical IRQ 0,INTERRUPT_CTRL Interrupt acknowledge timeout for critical IRQ 0,1
ERROR,PCIE_CTRL,PCIe Endpoint Configuration Space write error,PCIE_CTRL PCIe Endpoint Configuration Space write error,6
ERROR,DDR_CTRL,DDR write data integrity error on bank 1,DDR_CTRL DDR write data integrity error on bank 1,1
ERROR,PCIE_CTRL,PCIE_CTRL: timing violation - unmet timing constraint detected.,PCIE_CTRL PCIE_CTRL: timing violation - unmet timing constraint detected.,-1
WARNING,DDR_CTRL,DDR write data group latency variation,DDR_CTRL DDR write data group latency variation,1
WARNING,AXI_CTRL,AXI transaction ID contention,AXI_CTRL AXI transaction ID contention,2
WARNING,INTERRUPT_CTRL,Interrupt line 10 in INTERRUPT_CTRL showing intermittent backpressure.,INTERRUPT_CTRL Interrupt line 10 in INTERRUPT_CTRL showing intermittent backpressure.,-1
ERROR,CACHE_CTRL,L1 cache tag RAM parity error detected,CACHE_CTRL L1 cache tag RAM parity error detected,1
INFO,FIFO_BUF,FIFO almost-empty signal deasserted,FIFO_BUF FIFO almost-empty signal deasserted,5
WARNING,CACHE_CTRL,Cache line replacement policy under stress.,CACHE_CTRL Cache line replacement policy under stress.,1
ERROR,PCIE_CTRL,PCIe link layer flow control deadlock,PCIE_CTRL PCIe link layer flow control deadlock,6
CRITICAL,DMA_ENGINE,"DMA engine unresponsive, system halt imminent","DMA_ENGINE DMA engine unresponsive, system halt imminent",3
WARNING,DDR_CTRL,DDR memory bus utilization at peak levels,DDR_CTRL DDR memory bus utilization at peak levels,1
CRITICAL,AXI_CTRL,CRITICAL: AXI bridge control logic entered unrecoverable state 0x3C.,AXI_CTRL CRITICAL: AXI bridge control logic entered unrecoverable state 0x3C.,2
ERROR,PCIE_CTRL,PCIe unmaskable error reported,PCIE_CTRL PCIe unmaskable error reported,6
WARNING,CLOCK_MANAGER,Expected CLOCK_MANAGER response delay exceeding threshold (current: 40 cycles).,CLOCK_MANAGER Expected CLOCK_MANAGER response delay exceeding threshold (current: 40 cycles).,-1
WARNING,POWER_CTRL,Voltage rail PHY_V ripple exceeding tolerance (48.4mV).,POWER_CTRL Voltage rail PHY_V ripple exceeding tolerance (48.4mV).,4
WARNING,DDR_CTRL,DDR refresh timer expiring soon,DDR_CTRL DDR refresh timer expiring soon,1
INFO,PCIE_CTRL,"PCIe link up, negotiated 16 GT/s","PCIE_CTRL PCIe link up, negotiated 16 GT/s",6
INFO,FIFO_BUF,FIFO read count incremented,FIFO_BUF FIFO read count incremented,5
INFO,CLOCK_MANAGER,PLL frequency re-locked to target,CLOCK_MANAGER PLL frequency re-locked to target,0
INFO,FIFO_BUF,FIFO 'status_log' reset successfully,FIFO_BUF FIFO 'status_log' reset successfully,5
INFO,DMA_ENGINE,DMA descriptor processed for channel 7.,DMA_ENGINE DMA descriptor processed for channel 7.,3
CRITICAL,AXI_CTRL,AXI bus deadlock between two high-priority masters,AXI_CTRL AXI bus deadlock between two high-priority masters,2
INFO,INTERRUPT_CTRL,Interrupt mask updated in INTERRUPT_CTRL.,INTERRUPT_CTRL Interrupt mask updated in INTERRUPT_CTRL.,1
ERROR,CLOCK_MANAGER,"PLL unlock detected, frequency deviation","CLOCK_MANAGER PLL unlock detected, frequency deviation",0
CRITICAL,CLOCK_MANAGER,Clock generator output stuck high,CLOCK_MANAGER Clock generator output stuck high,0
ERROR,MEM_CTRL,Memory controller state machine entered illegal state (state ID 0x5),MEM_CTRL Memory controller state machine entered illegal state (state ID 0x5),1
INFO,DDR_CTRL,DDR self-refresh mode entered,DDR_CTRL DDR self-refresh mode entered,1
ERROR,AXI_CTRL,"AXI_CTRL: deadlock detected - inter-module deadlock detected. (Master ID: 3, AXI ID: 15)","AXI_CTRL AXI_CTRL: deadlock detected - inter-module deadlock detected. (Master ID: 3, AXI ID: 15)",2
ERROR,CACHE_CTRL,Cache tag comparison mismatch detected,CACHE_CTRL Cache tag comparison mismatch detected,1
INFO,MEM_CTRL,Memory region 0x1000-0x2000 protected,MEM_CTRL Memory region 0x1000-0x2000 protected,1
WARNING,POWER_CTRL,Low power mode entry delayed,POWER_CTRL Low power mode entry delayed,4
ERROR,DMA_ENGINE,DMA address generation unit timing violation.,DMA_ENGINE DMA address generation unit timing violation.,3
INFO,CACHE_CTRL,Cache hit rate analysis initiated,CACHE_CTRL Cache hit rate analysis initiated,1
WARNING,DDR_CTRL,DDR write data buffer nearing overflow,DDR_CTRL DDR write data buffer nearing overflow,1
WARNING,PCIE_CTRL,DL_UP state entered due to error recovery,PCIE_CTRL DL_UP state entered due to error recovery,6
INFO,FIFO_BUF,FIFO_BUF module initialized.,FIFO_BUF FIFO_BUF module initialized.,5
ERROR,CACHE_CTRL,"Cache line invalidation error, inconsistent state for address 0x99887766","CACHE_CTRL Cache line invalidation error, inconsistent state for address 0x99887766",1
WARNING,DDR_CTRL,DDR controller internal FSM taking too long to settle,DDR_CTRL DDR controller internal FSM taking too long to settle,-1
INFO,FIFO_BUF,FIFO occupancy is 50%,FIFO_BUF FIFO occupancy is 50%,5
INFO,POWER_CTRL,Voltage monitoring enabled,POWER_CTRL Voltage monitoring enabled,4
ERROR,POWER_CTRL,Power gate isolation failed to activate on unused domain,POWER_CTRL Power gate isolation failed to activate on unused domain,4
WARNING,CLOCK_MANAGER,System clock output phase shift detected,CLOCK_MANAGER System clock output phase shift detected,0
ERROR,FIFO_BUF,FIFO pointer wrap-around error,FIFO_BUF FIFO pointer wrap-around error,5
CRITICAL,MEM_CTRL,Memory controller internal state mismatch with external interface,MEM_CTRL Memory controller internal state mismatch with external interface,1
CRITICAL,CLOCK_MANAGER,"Clock switch-over failure, unstable clock detected","CLOCK_MANAGER Clock switch-over failure, unstable clock detected",0
ERROR,CACHE_CTRL,Cache tag RAM read data parity error,CACHE_CTRL Cache tag RAM read data parity error,1
ERROR,AXI_CTRL,AXI protection bits protocol mismatch.,AXI_CTRL AXI protection bits protocol mismatch.,2
INFO,DMA_ENGINE,DMA channel 0 configured for scatter-gather transfer,DMA_ENGINE DMA channel 0 configured for scatter-gather transfer,3
INFO,DMA_ENGINE,DMA transfer to I/O device successful,DMA_ENGINE DMA transfer to I/O device successful,3
ERROR,FIFO_BUF,FIFO write pointer corruption due to clock glitch,FIFO_BUF FIFO write pointer corruption due to clock glitch,5
ERROR,CACHE_CTRL,Cache dirty line eviction failed due to write-back buffer full.,CACHE_CTRL Cache dirty line eviction failed due to write-back buffer full.,1
CRITICAL,DDR_CTRL,DDR voltage level out of specification,DDR_CTRL DDR voltage level out of specification,-1
INFO,INTERRUPT_CTRL,Software interrupt triggered for test,INTERRUPT_CTRL Software interrupt triggered for test,1
CRITICAL,CACHE_CTRL,Cache directory entry invalidation failure,CACHE_CTRL Cache directory entry invalidation failure,1
INFO,INTERRUPT_CTRL,New interrupt source enabled,INTERRUPT_CTRL New interrupt source enabled,1
WARNING,AXI_CTRL,AXI write data channel bandwidth contention,AXI_CTRL AXI write data channel bandwidth contention,2
WARNING,MEM_CTRL,Memory access contention detected for shared region,MEM_CTRL Memory access contention detected for shared region,1
CRITICAL,CACHE_CTRL,"Cache miss rate reached critical threshold, performance impact","CACHE_CTRL Cache miss rate reached critical threshold, performance impact",1
ERROR,INTERRUPT_CTRL,Unexpected interrupt assertion from GPIO controller,INTERRUPT_CTRL Unexpected interrupt assertion from GPIO controller,1
INFO,DMA_ENGINE,DMA channel idle,DMA_ENGINE DMA channel idle,3
WARNING,FIFO_BUF,FIFO almost empty flag asserted,FIFO_BUF FIFO almost empty flag asserted,5
INFO,DMA_ENGINE,DMA transfer completion interrupt generated,DMA_ENGINE DMA transfer completion interrupt generated,3
INFO,POWER_CTRL,Voltage regulator enabled for rail Y.,POWER_CTRL Voltage regulator enabled for rail Y.,4
WARNING,FIFO_BUF,FIFO watermarks approaching critical levels,FIFO_BUF FIFO watermarks approaching critical levels,5
WARNING,AXI_CTRL,AXI `WREADY` asserted prematurely before `WVALID`,AXI_CTRL AXI `WREADY` asserted prematurely before `WVALID`,2
WARNING,PCIE_CTRL,PCIe flow control credit approaching zero.,PCIE_CTRL PCIe flow control credit approaching zero.,6
INFO,FIFO_BUF,"Write operation successful, 16 bytes committed","FIFO_BUF Write operation successful, 16 bytes committed",5
CRITICAL,MEM_CTRL,Persistent memory access failures,MEM_CTRL Persistent memory access failures,1
WARNING,MEM_CTRL,Memory refresh command issued with incorrect bank address,MEM_CTRL Memory refresh command issued with incorrect bank address,1
INFO,PCIE_CTRL,MSI-X interrupt configured,PCIE_CTRL MSI-X interrupt configured,6
INFO,FIFO_BUF,FIFO flush operation completed successfully,FIFO_BUF FIFO flush operation completed successfully,5
CRITICAL,MEM_CTRL,Memory controller entered fatal error state,MEM_CTRL Memory controller entered fatal error state,1
WARNING,DMA_ENGINE,DMA completion interrupt pending,DMA_ENGINE DMA completion interrupt pending,3
INFO,PCIE_CTRL,PCIe ASPM L1 entry successful,PCIE_CTRL PCIe ASPM L1 entry successful,-1
WARNING,AXI_CTRL,AXI master ID conflict detected,AXI_CTRL AXI master ID conflict detected,2
INFO,INTERRUPT_CTRL,Interrupt controller initialized.,INTERRUPT_CTRL Interrupt controller initialized.,1
WARNING,CLOCK_MANAGER,Frequency deviation detected on auxiliary clock,CLOCK_MANAGER Frequency deviation detected on auxiliary clock,0
WARNING,INTERRUPT_CTRL,Pending interrupt duration high for IRQ 10,INTERRUPT_CTRL Pending interrupt duration high for IRQ 10,1
WARNING,CACHE_CTRL,Cache line eviction pressure increasing,CACHE_CTRL Cache line eviction pressure increasing,1
ERROR,MEM_CTRL,Memory data bus stuck-at-zero,MEM_CTRL Memory data bus stuck-at-zero,1
INFO,CACHE_CTRL,Cache line writeback completed.,CACHE_CTRL Cache line writeback completed.,1
CRITICAL,POWER_CTRL,Critical voltage drop on critical peripheral rail,POWER_CTRL Critical voltage drop on critical peripheral rail,4
INFO,PCIE_CTRL,TLP received and processed,PCIE_CTRL TLP received and processed,6
CRITICAL,POWER_CTRL,Power sequence controller asserted system reset due to failure,POWER_CTRL Power sequence controller asserted system reset due to failure,4
CRITICAL,PCIE_CTRL,PCIe root complex received uncorrectable error from endpoint,PCIE_CTRL PCIe root complex received uncorrectable error from endpoint,6
INFO,CLOCK_MANAGER,CLOCK_MANAGER resource allocation successful.,CLOCK_MANAGER CLOCK_MANAGER resource allocation successful.,-1
WARNING,PCIE_CTRL,PCIe hot-plug controller reporting unexpected status,PCIE_CTRL PCIe hot-plug controller reporting unexpected status,6
INFO,PCIE_CTRL,PCIe endpoint successfully responded to MSI-X interrupt,PCIE_CTRL PCIe endpoint successfully responded to MSI-X interrupt,6
ERROR,AXI_CTRL,AXI read transaction timeout detected,AXI_CTRL AXI read transaction timeout detected,2
CRITICAL,POWER_CTRL,Voltage regulator thermal shutdown activated,POWER_CTRL Voltage regulator thermal shutdown activated,4
ERROR,PCIE_CTRL,PCIe TLP header CRC error detected,PCIE_CTRL PCIe TLP header CRC error detected,6
ERROR,POWER_CTRL,Core voltage rail sags below threshold,POWER_CTRL Core voltage rail sags below threshold,4
CRITICAL,AXI_CTRL,AXI address decoding logic produced conflicting targets.,AXI_CTRL AXI address decoding logic produced conflicting targets.,2
ERROR,FIFO_BUF,FIFO almost full condition asserted prematurely,FIFO_BUF FIFO almost full condition asserted prematurely,5
WARNING,MEM_CTRL,Memory access latency increasing for region 0xDEADBEEF.,MEM_CTRL Memory access latency increasing for region 0xDEADBEEF.,1
ERROR,DMA_ENGINE,Scatter-gather list corruption,DMA_ENGINE Scatter-gather list corruption,3
WARNING,FIFO_BUF,FIFO_RX_CMD read pointer nearing write pointer.,FIFO_BUF FIFO_RX_CMD read pointer nearing write pointer.,5
INFO,MEM_CTRL,Memory controller in idle state,MEM_CTRL Memory controller in idle state,1
WARNING,CLOCK_MANAGER,Clock 'GPU_CLK' frequency deviation detected,CLOCK_MANAGER Clock 'GPU_CLK' frequency deviation detected,0
INFO,AXI_CTRL,AXI master ID 0x07 initiated new transaction.,AXI_CTRL AXI master ID 0x07 initiated new transaction.,2
WARNING,FIFO_BUF,FIFO_RX_DATA buffer fill level at 85% capacity.,FIFO_BUF FIFO_RX_DATA buffer fill level at 85% capacity.,5
ERROR,PCIE_CTRL,PCIe Gen4 link training failed to achieve target speed,PCIE_CTRL PCIe Gen4 link training failed to achieve target speed,6
WARNING,PCIE_CTRL,DLLP processing delay,PCIE_CTRL DLLP processing delay,6
WARNING,DMA_ENGINE,DMA channel 2 transfer rate below expected,DMA_ENGINE DMA channel 2 transfer rate below expected,3
CRITICAL,AXI_CTRL,AXI protocol analyzer detected fatal sequencing error,AXI_CTRL AXI protocol analyzer detected fatal sequencing error,-1
INFO,INTERRUPT_CTRL,Interrupt pending bit cleared.,INTERRUPT_CTRL Interrupt pending bit cleared.,1
WARNING,DDR_CTRL,DDR access latency exceeding typical range (100ns vs 70ns),DDR_CTRL DDR access latency exceeding typical range (100ns vs 70ns),1
INFO,INTERRUPT_CTRL,Interrupts successfully masked,INTERRUPT_CTRL Interrupts successfully masked,1
CRITICAL,MEM_CTRL,Uncorrectable ECC error detected at memory address 0xDEADBEEF in boot region.,MEM_CTRL Uncorrectable ECC error detected at memory address 0xDEADBEEF in boot region.,1
WARNING,CACHE_CTRL,L1 data cache eviction rate significantly elevated,CACHE_CTRL L1 data cache eviction rate significantly elevated,1
CRITICAL,AXI_CTRL,AXI master 0x0E issued transaction resulting in unrecoverable interconnect error.,AXI_CTRL AXI master 0x0E issued transaction resulting in unrecoverable interconnect error.,2
WARNING,DDR_CTRL,DDR memory temperature sensor exceeding warning threshold.,DDR_CTRL DDR memory temperature sensor exceeding warning threshold.,1
ERROR,DMA_ENGINE,DMA channel burst transfer size mismatch,DMA_ENGINE DMA channel burst transfer size mismatch,3
ERROR,DDR_CTRL,DDR read latency calibration failed,DDR_CTRL DDR read latency calibration failed,1
CRITICAL,POWER_CTRL,"Power regulator fault, main system voltage unstable.","POWER_CTRL Power regulator fault, main system voltage unstable.",4
ERROR,FIFO_BUF,Read pointer advanced into unwritten data area (phantom read),FIFO_BUF Read pointer advanced into unwritten data area (phantom read),5
WARNING,INTERRUPT_CTRL,Software interrupt triggered excessively,INTERRUPT_CTRL Software interrupt triggered excessively,1
INFO,MEM_CTRL,Memory controller in IDLE state,MEM_CTRL Memory controller in IDLE state,1
WARNING,INTERRUPT_CTRL,Interrupt queue for pending IRQs is 80% full.,INTERRUPT_CTRL Interrupt queue for pending IRQs is 80% full.,1
INFO,CLOCK_MANAGER,CLOCK_MANAGER entered idle state.,CLOCK_MANAGER CLOCK_MANAGER entered idle state.,0
CRITICAL,PCIE_CTRL,PCIe hot-reset failed to clear device errors,PCIE_CTRL PCIe hot-reset failed to clear device errors,6
WARNING,AXI_CTRL,AXI interconnect data path integrity check failed,AXI_CTRL AXI interconnect data path integrity check failed,2
ERROR,DDR_CTRL,DDR DQS synchronization failed to lock onto clock.,DDR_CTRL DDR DQS synchronization failed to lock onto clock.,-1
ERROR,AXI_CTRL,AXI read data (R) channel width mismatch detected,AXI_CTRL AXI read data (R) channel width mismatch detected,2
WARNING,DMA_ENGINE,DMA channel arbitration failure detected due to high traffic,DMA_ENGINE DMA channel arbitration failure detected due to high traffic,3
ERROR,FIFO_BUF,FIFO write-read pointer desynchronization,FIFO_BUF FIFO write-read pointer desynchronization,5
INFO,DDR_CTRL,DDR memory training completed for all ranks,DDR_CTRL DDR memory training completed for all ranks,1
WARNING,DDR_CTRL,DDR command bus integrity check failure,DDR_CTRL DDR command bus integrity check failure,1
WARNING,CLOCK_MANAGER,Clock phase shift detected between synchronous domains,CLOCK_MANAGER Clock phase shift detected between synchronous domains,0
WARNING,CLOCK_MANAGER,Clock domain crossing synchronization failure detected (minor),CLOCK_MANAGER Clock domain crossing synchronization failure detected (minor),0
ERROR,MEM_CTRL,MEM_CTRL reported an unrecoverable internal parity error (Code: 0x9).,MEM_CTRL MEM_CTRL reported an unrecoverable internal parity error (Code: 0x9).,1
WARNING,CACHE_CTRL,"Cache dirty line count increasing, potential write-back storms.","CACHE_CTRL Cache dirty line count increasing, potential write-back storms.",1
INFO,DDR_CTRL,DDR memory initialization routine finished,DDR_CTRL DDR memory initialization routine finished,1
CRITICAL,POWER_CTRL,Power rail voltage dropped below minimum operational threshold,POWER_CTRL Power rail voltage dropped below minimum operational threshold,4
CRITICAL,DMA_ENGINE,Critical DMA descriptor chain corruption,DMA_ENGINE Critical DMA descriptor chain corruption,3
CRITICAL,MEM_CTRL,Memory controller ECC scrubbing halted due to uncorrectable error,MEM_CTRL Memory controller ECC scrubbing halted due to uncorrectable error,1
INFO,MEM_CTRL,Memory integrity check completed successfully,MEM_CTRL Memory integrity check completed successfully,1
INFO,PCIE_CTRL,PCIe hot-reset sequence initiated,PCIE_CTRL PCIe hot-reset sequence initiated,6
ERROR,AXI_CTRL,"AXI read response mismatch, expected 0xDEADBEEF, got 0xC0FFEE","AXI_CTRL AXI read response mismatch, expected 0xDEADBEEF, got 0xC0FFEE",2
INFO,DDR_CTRL,DDR controller operating frequency set,DDR_CTRL DDR controller operating frequency set,1
ERROR,MEM_CTRL,Uncorrectable ECC error detected on memory address 0xDEADBEEF.,MEM_CTRL Uncorrectable ECC error detected on memory address 0xDEADBEEF.,1
WARNING,FIFO_BUF,FIFO almost full flag asserted for extended duration,FIFO_BUF FIFO almost full flag asserted for extended duration,5
CRITICAL,MEM_CTRL,"Double bit ECC corruption detected on memory read, unrecoverable. (ECC failure)","MEM_CTRL Double bit ECC corruption detected on memory read, unrecoverable. (ECC failure)",1
ERROR,AXI_CTRL,"AXI_CTRL: bus contention - drive conflict on bus detected. (Master ID: 3, AXI ID: 1)","AXI_CTRL AXI_CTRL: bus contention - drive conflict on bus detected. (Master ID: 3, AXI ID: 1)",2
WARNING,INTERRUPT_CTRL,Pending interrupt aging,INTERRUPT_CTRL Pending interrupt aging,1
WARNING,POWER_CTRL,Core voltage rail minor droop detected,POWER_CTRL Core voltage rail minor droop detected,4
CRITICAL,MEM_CTRL,Memory controller internal register file corruption.,MEM_CTRL Memory controller internal register file corruption.,1
CRITICAL,CLOCK_MANAGER,System reset generated due to clock instability,CLOCK_MANAGER System reset generated due to clock instability,0
INFO,PCIE_CTRL,Configuration space read successful,PCIE_CTRL Configuration space read successful,6
INFO,DDR_CTRL,DDR power-down entry successful,DDR_CTRL DDR power-down entry successful,1
WARNING,CACHE_CTRL,Cache line writeback initiated due to eviction pressure.,CACHE_CTRL Cache line writeback initiated due to eviction pressure.,1
INFO,DMA_ENGINE,DMA channel 0 enabled,DMA_ENGINE DMA channel 0 enabled,3
CRITICAL,CACHE_CTRL,Cache hardware detected a fatal tag array ECC error,CACHE_CTRL Cache hardware detected a fatal tag array ECC error,1
ERROR,FIFO_BUF,FIFO read clock domain not synchronized,FIFO_BUF FIFO read clock domain not synchronized,5
CRITICAL,CLOCK_MANAGER,Global clock buffer output stuck low,CLOCK_MANAGER Global clock buffer output stuck low,0
WARNING,AXI_CTRL,AXI master ID collision detected,AXI_CTRL AXI master ID collision detected,2
ERROR,FIFO_BUF,Input synchronization logic detected metastability.,FIFO_BUF Input synchronization logic detected metastability.,5
INFO,CACHE_CTRL,Cache way selection logic optimized,CACHE_CTRL Cache way selection logic optimized,1
ERROR,DDR_CTRL,DDR controller internal parity error,DDR_CTRL DDR controller internal parity error,1
CRITICAL,MEM_CTRL,"Double bit ECC corruption detected at address 0x933FE, uncorrectable","MEM_CTRL Double bit ECC corruption detected at address 0x933FE, uncorrectable",1
INFO,CLOCK_MANAGER,Clock domain 'CORE' now active.,CLOCK_MANAGER Clock domain 'CORE' now active.,0
WARNING,CACHE_CTRL,Cache coherency protocol transaction pending.,CACHE_CTRL Cache coherency protocol transaction pending.,1
ERROR,CACHE_CTRL,"Cache line invalidation error, inconsistent state","CACHE_CTRL Cache line invalidation error, inconsistent state",1
CRITICAL,CACHE_CTRL,Cache line state machine entered invalid state,CACHE_CTRL Cache line state machine entered invalid state,1
ERROR,DDR_CTRL,DDR write data integrity error detected,DDR_CTRL DDR write data integrity error detected,1
WARNING,PCIE_CTRL,"PCIe link width negotiation failed, downgraded to x1","PCIE_CTRL PCIe link width negotiation failed, downgraded to x1",6
INFO,DDR_CTRL,DDR memory access efficiency calculated,DDR_CTRL DDR memory access efficiency calculated,1
WARNING,DMA_ENGINE,DMA channel 3 status register indicates potential error,DMA_ENGINE DMA channel 3 status register indicates potential error,3
WARNING,AXI_CTRL,AXI interconnect observed excessive transaction reordering,AXI_CTRL AXI interconnect observed excessive transaction reordering,-1
WARNING,POWER_CTRL,Low power mode entry aborted due to active transactions,POWER_CTRL Low power mode entry aborted due to active transactions,4
WARNING,FIFO_BUF,Read-after-write hazard potential detected.,FIFO_BUF Read-after-write hazard potential detected.,5
INFO,AXI_CTRL,AXI protocol monitor reports clean transactions,AXI_CTRL AXI protocol monitor reports clean transactions,2
INFO,CLOCK_MANAGER,Clock tree delay measurement successful,CLOCK_MANAGER Clock tree delay measurement successful,-1
WARNING,DDR_CTRL,DDR chip select signal showing glitches,DDR_CTRL DDR chip select signal showing glitches,8
INFO,MEM_CTRL,Memory page table entry updated for virtual address 0xDEADBEEF.,MEM_CTRL Memory page table entry updated for virtual address 0xDEADBEEF.,1
WARNING,DDR_CTRL,DDR access latency elevated,DDR_CTRL DDR access latency elevated,1
WARNING,CACHE_CTRL,Cache line modified bit inconsistent with dirty state,CACHE_CTRL Cache line modified bit inconsistent with dirty state,1
WARNING,CACHE_CTRL,Cache miss rate exceeding acceptable threshold for L1-D,CACHE_CTRL Cache miss rate exceeding acceptable threshold for L1-D,1
CRITICAL,PCIE_CTRL,PCIe endpoint configuration space corruption,PCIE_CTRL PCIe endpoint configuration space corruption,6
CRITICAL,MEM_CTRL,Data corruption detected during memory scrubbing,MEM_CTRL Data corruption detected during memory scrubbing,1
ERROR,CACHE_CTRL,Cache way miss for critical memory region,CACHE_CTRL Cache way miss for critical memory region,1
WARNING,INTERRUPT_CTRL,Interrupt queue approaching limit (100 pending).,INTERRUPT_CTRL Interrupt queue approaching limit (100 pending).,1
CRITICAL,FIFO_BUF,FIFO control logic state machine corruption,FIFO_BUF FIFO control logic state machine corruption,5
INFO,POWER_CTRL,Power domain entered standby mode,POWER_CTRL Power domain entered standby mode,4
CRITICAL,DDR_CTRL,DDR memory calibration data corruption,DDR_CTRL DDR memory calibration data corruption,1
ERROR,FIFO_BUF,Bidirectional FIFO read-after-write data corruption,FIFO_BUF Bidirectional FIFO read-after-write data corruption,5
ERROR,POWER_CTRL,Voltage brownout detected on auxiliary rail,POWER_CTRL Voltage brownout detected on auxiliary rail,4
INFO,FIFO_BUF,FIFO_BUF status query successful.,FIFO_BUF FIFO_BUF status query successful.,5
ERROR,CACHE_CTRL,Cache fill operation timeout from main memory,CACHE_CTRL Cache fill operation timeout from main memory,1
WARNING,FIFO_BUF,"FIFO write pointer nearing read pointer, potential overflow","FIFO_BUF FIFO write pointer nearing read pointer, potential overflow",5
INFO,MEM_CTRL,Memory bank 2 access granted,MEM_CTRL Memory bank 2 access granted,1
INFO,DMA_ENGINE,DMA channel de-allocated,DMA_ENGINE DMA channel de-allocated,3
WARNING,INTERRUPT_CTRL,Interrupt queue depth approaching high watermark,INTERRUPT_CTRL Interrupt queue depth approaching high watermark,-1
WARNING,CACHE_CTRL,Cache way invalidation pending for a long time,CACHE_CTRL Cache way invalidation pending for a long time,1
INFO,CLOCK_MANAGER,Frequency adjustment completed for debugging,CLOCK_MANAGER Frequency adjustment completed for debugging,0
INFO,DDR_CTRL,DDR training sequence passed all stages,DDR_CTRL DDR training sequence passed all stages,1
ERROR,CLOCK_MANAGER,Clock source selected is unstable,CLOCK_MANAGER Clock source selected is unstable,0
INFO,PCIE_CTRL,PCIe BAR configuration successfully applied,PCIE_CTRL PCIe BAR configuration successfully applied,6
ERROR,AXI_CTRL,AXI master GPU issued unaligned access to 0x00000000.,AXI_CTRL AXI master GPU issued unaligned access to 0x00000000.,-1
CRITICAL,MEM_CTRL,Uncorrectable multi-bit ECC error on memory bank 1,MEM_CTRL Uncorrectable multi-bit ECC error on memory bank 1,1
INFO,DDR_CTRL,DDR read training sequence passed,DDR_CTRL DDR read training sequence passed,1
INFO,INTERRUPT_CTRL,New ISR registered for device ID 0x5.,INTERRUPT_CTRL New ISR registered for device ID 0x5.,1
CRITICAL,FIFO_BUF,"FIFO pointers corrupted, potentially losing data","FIFO_BUF FIFO pointers corrupted, potentially losing data",5
INFO,INTERRUPT_CTRL,Interrupt dispatch completed.,INTERRUPT_CTRL Interrupt dispatch completed.,1
INFO,DDR_CTRL,DDR ZQ calibration completed successfully,DDR_CTRL DDR ZQ calibration completed successfully,1
INFO,MEM_CTRL,Memory region 'DMA_BUFFER' freed successfully,MEM_CTRL Memory region 'DMA_BUFFER' freed successfully,1
ERROR,FIFO_BUF,FIFO 'sensor_data' read pointer corruption,FIFO_BUF FIFO 'sensor_data' read pointer corruption,5
CRITICAL,PCIE_CTRL,PCIe device link training timeout,PCIE_CTRL PCIe device link training timeout,6
ERROR,POWER_CTRL,Power manager unit internal error,POWER_CTRL Power manager unit internal error,4
WARNING,DMA_ENGINE,DMA scatter-gather list parsing exceeding typical execution time.,DMA_ENGINE DMA scatter-gather list parsing exceeding typical execution time.,3
CRITICAL,PCIE_CTRL,PCIe link width negotiation failed,PCIE_CTRL PCIe link width negotiation failed,6
INFO,FIFO_BUF,FIFO initialized with default depth,FIFO_BUF FIFO initialized with default depth,5
CRITICAL,PCIE_CTRL,"PCIe fatal link error, hardware reset required","PCIE_CTRL PCIe fatal link error, hardware reset required",6
INFO,AXI_CTRL,AXI write burst to 'network_adapter' completed successfully,AXI_CTRL AXI write burst to 'network_adapter' completed successfully,2
CRITICAL,MEM_CTRL,Memory controller arbitration logic stuck,MEM_CTRL Memory controller arbitration logic stuck,1
ERROR,DDR_CTRL,DDR rank initialization failed,DDR_CTRL DDR rank initialization failed,1
INFO,MEM_CTRL,MEM_CTRL monitoring initiated.,MEM_CTRL MEM_CTRL monitoring initiated.,-1
ERROR,CLOCK_MANAGER,Watchdog timer reset asserted due to clock instability,CLOCK_MANAGER Watchdog timer reset asserted due to clock instability,0
CRITICAL,POWER_CTRL,"Power rail instability detected, critical system shutdown","POWER_CTRL Power rail instability detected, critical system shutdown",4
WARNING,CACHE_CTRL,Cache dirty line count high,CACHE_CTRL Cache dirty line count high,1
INFO,FIFO_BUF,FIFO occupancy reporting current level,FIFO_BUF FIFO occupancy reporting current level,5
INFO,MEM_CTRL,Memory write protection enabled for kernel space,MEM_CTRL Memory write protection enabled for kernel space,1
ERROR,DDR_CTRL,DDR write leveling calibration failed,DDR_CTRL DDR write leveling calibration failed,1
INFO,CLOCK_MANAGER,Clock frequency configured to 2.4 GHz,CLOCK_MANAGER Clock frequency configured to 2.4 GHz,0
WARNING,DDR_CTRL,DDR memory data path experiencing increased noise,DDR_CTRL DDR memory data path experiencing increased noise,1
INFO,FIFO_BUF,"Read operation successful, FIFO now 10 entries full","FIFO_BUF Read operation successful, FIFO now 10 entries full",5
INFO,AXI_CTRL,AXI write completion acknowledged,AXI_CTRL AXI write completion acknowledged,2
CRITICAL,DDR_CTRL,DDR controller command FSM in illegal state,DDR_CTRL DDR controller command FSM in illegal state,-1
INFO,POWER_CTRL,Power management unit diagnostic complete,POWER_CTRL Power management unit diagnostic complete,4
WARNING,AXI_CTRL,AXI response channel with unexpected error code,AXI_CTRL AXI response channel with unexpected error code,2
INFO,CACHE_CTRL,Cache line 0xABC000 moved to modified state,CACHE_CTRL Cache line 0xABC000 moved to modified state,1
ERROR,MEM_CTRL,Memory ECC parity mismatch detected on read data,MEM_CTRL Memory ECC parity mismatch detected on read data,1
INFO,DMA_ENGINE,DMA channel 6 transfer request dequeued,DMA_ENGINE DMA channel 6 transfer request dequeued,3
CRITICAL,CACHE_CTRL,"Cache controller entered unrecoverable state, system crash imminent","CACHE_CTRL Cache controller entered unrecoverable state, system crash imminent",1
WARNING,FIFO_BUF,"FIFO read operation stalled, waiting for more data","FIFO_BUF FIFO read operation stalled, waiting for more data",5
INFO,DMA_ENGINE,DMA channel disabled,DMA_ENGINE DMA channel disabled,3
INFO,DMA_ENGINE,DMA engine software reset performed,DMA_ENGINE DMA engine software reset performed,3
INFO,DMA_ENGINE,"DMA channel 2 transfer completed successfully, 1024 bytes moved.","DMA_ENGINE DMA channel 2 transfer completed successfully, 1024 bytes moved.",3
CRITICAL,CLOCK_MANAGER,"Clock generation PLL permanently lost lock, system halt","CLOCK_MANAGER Clock generation PLL permanently lost lock, system halt",0
ERROR,CACHE_CTRL,"Cache line dirty status incorrect, potential data loss.","CACHE_CTRL Cache line dirty status incorrect, potential data loss.",1
INFO,INTERRUPT_CTRL,Interrupt acknowledged: PCIe_INT,INTERRUPT_CTRL Interrupt acknowledged: PCIe_INT,6
INFO,POWER_CTRL,Power domain 'IO' successfully powered up,POWER_CTRL Power domain 'IO' successfully powered up,4
CRITICAL,PCIE_CTRL,PCIe SERDES clock recovery failure,PCIE_CTRL PCIe SERDES clock recovery failure,-1
ERROR,CACHE_CTRL,Cache coherence protocol violation on 'Write-Back',CACHE_CTRL Cache coherence protocol violation on 'Write-Back',1
WARNING,PCIE_CTRL,Flow control credit low,PCIE_CTRL Flow control credit low,6
ERROR,CLOCK_MANAGER,Asynchronous reset de-assertion glitch detected,CLOCK_MANAGER Asynchronous reset de-assertion glitch detected,0
WARNING,PCIE_CTRL,PCIe flow control credits running low on egress,PCIE_CTRL PCIe flow control credits running low on egress,6
INFO,CACHE_CTRL,Cache line invalidation completed,CACHE_CTRL Cache line invalidation completed,1
WARNING,AXI_CTRL,AXI retry count elevated on master interface,AXI_CTRL AXI retry count elevated on master interface,-1
ERROR,FIFO_BUF,FIFO synchronization error detected across clock domains between CLK_A and CLK_B,FIFO_BUF FIFO synchronization error detected across clock domains between CLK_A and CLK_B,5
WARNING,INTERRUPT_CTRL,Interrupt latency elevated.,INTERRUPT_CTRL Interrupt latency elevated.,1
ERROR,INTERRUPT_CTRL,Interrupt source register read value mismatch,INTERRUPT_CTRL Interrupt source register read value mismatch,1
WARNING,PCIE_CTRL,PCIe retry buffer nearing capacity,PCIE_CTRL PCIe retry buffer nearing capacity,6
INFO,POWER_CTRL,Low power mode entered successfully,POWER_CTRL Low power mode entered successfully,4
ERROR,INTERRUPT_CTRL,Interrupt source unidentifiable,INTERRUPT_CTRL Interrupt source unidentifiable,1
WARNING,PCIE_CTRL,PCIe configuration write to read-only register,PCIE_CTRL PCIe configuration write to read-only register,6
ERROR,AXI_CTRL,AXI write burst with WLAST asserted incorrectly by master 0x0B.,AXI_CTRL AXI write burst with WLAST asserted incorrectly by master 0x0B.,2
INFO,DDR_CTRL,DDR controller self-refresh mode entered.,DDR_CTRL DDR controller self-refresh mode entered.,1
INFO,MEM_CTRL,Memory address range 0x8000-0x8FFF unaccessible,MEM_CTRL Memory address range 0x8000-0x8FFF unaccessible,1
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure between CPU and DSP,CLOCK_MANAGER Clock domain crossing synchronization failure between CPU and DSP,0
INFO,POWER_CTRL,System suspend to RAM initiated.,POWER_CTRL System suspend to RAM initiated.,-1
INFO,DDR_CTRL,ZQ calibration performed,DDR_CTRL ZQ calibration performed,1
ERROR,AXI_CTRL,AXI read burst alignment violation on address 0x10000001,AXI_CTRL AXI read burst alignment violation on address 0x10000001,2
ERROR,FIFO_BUF,FIFO 'instruction_fetch' detected read pointer corruption,FIFO_BUF FIFO 'instruction_fetch' detected read pointer corruption,5
ERROR,POWER_CTRL,Power rail VDD_AUX current exceeded maximum operating point,POWER_CTRL Power rail VDD_AUX current exceeded maximum operating point,-1
CRITICAL,FIFO_BUF,FIFO internal data path corruption,FIFO_BUF FIFO internal data path corruption,5
INFO,MEM_CTRL,Memory controller read-write turnaround optimized,MEM_CTRL Memory controller read-write turnaround optimized,1
WARNING,AXI_CTRL,AXI response latency increasing,AXI_CTRL AXI response latency increasing,2
WARNING,DMA_ENGINE,DMA descriptor memory region nearing full capacity.,DMA_ENGINE DMA descriptor memory region nearing full capacity.,3
INFO,POWER_CTRL,Voltage regulator output within 1% tolerance,POWER_CTRL Voltage regulator output within 1% tolerance,4
CRITICAL,FIFO_BUF,"FIFO synchronization logic failed, unrecoverable","FIFO_BUF FIFO synchronization logic failed, unrecoverable",5
INFO,PCIE_CTRL,PCIe hotplug event: device removed,PCIE_CTRL PCIe hotplug event: device removed,6
WARNING,FIFO_BUF,FIFO almost empty condition asserted,FIFO_BUF FIFO almost empty condition asserted,5
INFO,FIFO_BUF,"FIFO reset successful, all pointers cleared","FIFO_BUF FIFO reset successful, all pointers cleared",5
INFO,PCIE_CTRL,PCIe endpoint successfully transitioned to D3hot state,PCIE_CTRL PCIe endpoint successfully transitioned to D3hot state,-1
WARNING,INTERRUPT_CTRL,"Interrupt controller experiencing increased load, latency might be affected.","INTERRUPT_CTRL Interrupt controller experiencing increased load, latency might be affected.",1
ERROR,POWER_CTRL,Power-on reset sequence stalled.,POWER_CTRL Power-on reset sequence stalled.,4
INFO,INTERRUPT_CTRL,Interrupt acknowledge handled,INTERRUPT_CTRL Interrupt acknowledge handled,1
ERROR,AXI_CTRL,AXI write data channel parity error,AXI_CTRL AXI write data channel parity error,2
WARNING,AXI_CTRL,AXI slave asserted error response for address X,AXI_CTRL AXI slave asserted error response for address X,2
ERROR,AXI_CTRL,"AXI write response mismatch detected (expected OKAY, got SLVERR).","AXI_CTRL AXI write response mismatch detected (expected OKAY, got SLVERR).",2
WARNING,PCIE_CTRL,PCIe device capability mismatch detected,PCIE_CTRL PCIe device capability mismatch detected,6
WARNING,DMA_ENGINE,"DMA channel 11 stall detected, potential data path blockage","DMA_ENGINE DMA channel 11 stall detected, potential data path blockage",3
ERROR,CLOCK_MANAGER,Clock synchronization handshake timeout,CLOCK_MANAGER Clock synchronization handshake timeout,0
INFO,MEM_CTRL,Memory write to 0x4000_0000 completed,MEM_CTRL Memory write to 0x4000_0000 completed,1
WARNING,CACHE_CTRL,L2 cache fill buffer saturation detected,CACHE_CTRL L2 cache fill buffer saturation detected,1
ERROR,CLOCK_MANAGER,"Clock gate enable failure for module Y, module stuck ON","CLOCK_MANAGER Clock gate enable failure for module Y, module stuck ON",0
ERROR,POWER_CTRL,Brownout detected on peripheral power rail,POWER_CTRL Brownout detected on peripheral power rail,4
INFO,MEM_CTRL,Memory controller entered active state.,MEM_CTRL Memory controller entered active state.,1
ERROR,DMA_ENGINE,DMA configuration error: invalid burst size for 0.,DMA_ENGINE DMA configuration error: invalid burst size for 0.,3
ERROR,CACHE_CTRL,Cache line eviction policy violation for shared data,CACHE_CTRL Cache line eviction policy violation for shared data,1
INFO,FIFO_BUF,FIFO clear operation successful,FIFO_BUF FIFO clear operation successful,5
CRITICAL,CLOCK_MANAGER,Clock synchronizer metastability event detected,CLOCK_MANAGER Clock synchronizer metastability event detected,0
INFO,MEM_CTRL,ECC scrubbing initiated for memory region,MEM_CTRL ECC scrubbing initiated for memory region,1
ERROR,POWER_CTRL,Power domain sequencing violation,POWER_CTRL Power domain sequencing violation,4
INFO,CLOCK_MANAGER,Clock gate for debug module disabled,CLOCK_MANAGER Clock gate for debug module disabled,0
ERROR,PCIE_CTRL,PCIe link training failure during L0 state transition,PCIE_CTRL PCIe link training failure during L0 state transition,6
ERROR,DMA_ENGINE,DMA internal FIFO overflow detected.,DMA_ENGINE DMA internal FIFO overflow detected.,3
ERROR,INTERRUPT_CTRL,Interrupt controller FSM entered unexpected state,INTERRUPT_CTRL Interrupt controller FSM entered unexpected state,1
WARNING,PCIE_CTRL,PCIe error logging FIFO nearing capacity,PCIE_CTRL PCIe error logging FIFO nearing capacity,6
ERROR,FIFO_BUF,Unexpected data in FIFO.,FIFO_BUF Unexpected data in FIFO.,5
INFO,CACHE_CTRL,Cache line writeback completed for modified data,CACHE_CTRL Cache line writeback completed for modified data,1
WARNING,FIFO_BUF,FIFO_GPIO_IN read pointer nearing write pointer,FIFO_BUF FIFO_GPIO_IN read pointer nearing write pointer,5
ERROR,MEM_CTRL,Write-through cache eviction policy resulted in data loss,MEM_CTRL Write-through cache eviction policy resulted in data loss,1
WARNING,PCIE_CTRL,PCIe inbound queue for completions nearing capacity,PCIE_CTRL PCIe inbound queue for completions nearing capacity,6
WARNING,DDR_CTRL,DDR command queue depth sustained above 80% for 1000 cycles.,DDR_CTRL DDR command queue depth sustained above 80% for 1000 cycles.,1
ERROR,INTERRUPT_CTRL,Interrupt controller reports unmasked interrupt from disabled source,INTERRUPT_CTRL Interrupt controller reports unmasked interrupt from disabled source,1
WARNING,INTERRUPT_CTRL,Software handler for 'GPIO' interrupt not yet registered.,INTERRUPT_CTRL Software handler for 'GPIO' interrupt not yet registered.,1
WARNING,CACHE_CTRL,"Cache write buffer nearly full, potentially stalling CPU","CACHE_CTRL Cache write buffer nearly full, potentially stalling CPU",1
ERROR,DMA_ENGINE,DMA descriptor chain processing aborted,DMA_ENGINE DMA descriptor chain processing aborted,3
INFO,FIFO_BUF,"FIFO data available, 10 entries","FIFO_BUF FIFO data available, 10 entries",5
ERROR,AXI_CTRL,AXI read data integrity error,AXI_CTRL AXI read data integrity error,2
INFO,AXI_CTRL,AXI read outstanding transactions count reset,AXI_CTRL AXI read outstanding transactions count reset,2
CRITICAL,DDR_CTRL,"Uncorrectable ECC on DDR memory, system halt","DDR_CTRL Uncorrectable ECC on DDR memory, system halt",1
INFO,PCIE_CTRL,PCIe link re-negotiation initiated,PCIE_CTRL PCIe link re-negotiation initiated,6
INFO,FIFO_BUF,FIFO read operation successful.,FIFO_BUF FIFO read operation successful.,5
CRITICAL,PCIE_CTRL,"PCIe link fatal error, retraining initiated","PCIE_CTRL PCIe link fatal error, retraining initiated",6
WARNING,FIFO_BUF,FIFO nearing empty,FIFO_BUF FIFO nearing empty,5
CRITICAL,FIFO_BUF,FIFO controller hardware failure,FIFO_BUF FIFO controller hardware failure,5
WARNING,INTERRUPT_CTRL,Interrupt controller internal buffer usage at 90%,INTERRUPT_CTRL Interrupt controller internal buffer usage at 90%,1
CRITICAL,CLOCK_MANAGER,JTAG clock loopback test failed,CLOCK_MANAGER JTAG clock loopback test failed,-1
ERROR,INTERRUPT_CTRL,Interrupt handler address fetch error,INTERRUPT_CTRL Interrupt handler address fetch error,1
WARNING,CACHE_CTRL,Cache miss rate slightly above expected for L1,CACHE_CTRL Cache miss rate slightly above expected for L1,1
INFO,CLOCK_MANAGER,PLL re-calibration sequence initiated,CLOCK_MANAGER PLL re-calibration sequence initiated,0
INFO,INTERRUPT_CTRL,Interrupt pending status register cleared,INTERRUPT_CTRL Interrupt pending status register cleared,1
ERROR,INTERRUPT_CTRL,Interrupt request line stuck low,INTERRUPT_CTRL Interrupt request line stuck low,1
ERROR,MEM_CTRL,Memory access protection register corruption,MEM_CTRL Memory access protection register corruption,1
INFO,CACHE_CTRL,Cache hit rate reported at 95%,CACHE_CTRL Cache hit rate reported at 95%,1
ERROR,PCIE_CTRL,PCIe transaction layer protocol error detected,PCIE_CTRL PCIe transaction layer protocol error detected,6
WARNING,DMA_ENGINE,DMA completion interrupt pending for too long,DMA_ENGINE DMA completion interrupt pending for too long,3
ERROR,MEM_CTRL,"Memory write buffer overflow, transactions lost","MEM_CTRL Memory write buffer overflow, transactions lost",1
WARNING,POWER_CTRL,Power sequence initiation delay observed,POWER_CTRL Power sequence initiation delay observed,4
CRITICAL,MEM_CTRL,Multi-bit ECC corruption detected in data at 0xABCDEF00,MEM_CTRL Multi-bit ECC corruption detected in data at 0xABCDEF00,1
ERROR,PCIE_CTRL,PCIe flow control credit violation,PCIE_CTRL PCIe flow control credit violation,6
INFO,AXI_CTRL,AXI write data (WDATA) sent,AXI_CTRL AXI write data (WDATA) sent,2
WARNING,AXI_CTRL,AXI address channel stall count increasing,AXI_CTRL AXI address channel stall count increasing,2
WARNING,DMA_ENGINE,DMA channel 0 completion pending for extended duration,DMA_ENGINE DMA channel 0 completion pending for extended duration,3
ERROR,CLOCK_MANAGER,Asynchronous reset assertion timing violation,CLOCK_MANAGER Asynchronous reset assertion timing violation,0
WARNING,CACHE_CTRL,Cache directory entry invalidation pending,CACHE_CTRL Cache directory entry invalidation pending,1
WARNING,DMA_ENGINE,DMA descriptor queue depth approaching limit,DMA_ENGINE DMA descriptor queue depth approaching limit,3
INFO,DDR_CTRL,DDR command issued to memory rank 0,DDR_CTRL DDR command issued to memory rank 0,1
CRITICAL,DMA_ENGINE,DMA descriptor chain corrupted,DMA_ENGINE DMA descriptor chain corrupted,3
WARNING,INTERRUPT_CTRL,Interrupt pending queue depth at critical level,INTERRUPT_CTRL Interrupt pending queue depth at critical level,1
WARNING,MEM_CTRL,"Memory access latency increasing, performance degradation risk","MEM_CTRL Memory access latency increasing, performance degradation risk",1
WARNING,FIFO_BUF,FIFO read data invalid after read operation,FIFO_BUF FIFO read data invalid after read operation,5
INFO,INTERRUPT_CTRL,Priority assigned,INTERRUPT_CTRL Priority assigned,1
ERROR,DMA_ENGINE,DMA descriptor fetch logic error,DMA_ENGINE DMA descriptor fetch logic error,3
CRITICAL,POWER_CTRL,"Overcurrent protection trip, critical hardware fault.","POWER_CTRL Overcurrent protection trip, critical hardware fault.",4
ERROR,INTERRUPT_CTRL,Interrupt mask register value corrupted,INTERRUPT_CTRL Interrupt mask register value corrupted,1
INFO,FIFO_BUF,FIFO empty flag asserted.,FIFO_BUF FIFO empty flag asserted.,5
INFO,DMA_ENGINE,DMA controller idle state confirmed,DMA_ENGINE DMA controller idle state confirmed,3
WARNING,DMA_ENGINE,DMA channel suspended due to error,DMA_ENGINE DMA channel suspended due to error,3
ERROR,MEM_CTRL,Memory access permission violation detected at 0xCAFEF00D,MEM_CTRL Memory access permission violation detected at 0xCAFEF00D,1
INFO,CLOCK_MANAGER,External crystal oscillator stable,CLOCK_MANAGER External crystal oscillator stable,0
CRITICAL,MEM_CTRL,Memory controller configuration registers corrupted,MEM_CTRL Memory controller configuration registers corrupted,1
ERROR,DMA_ENGINE,DMA channel 5 transfer timeout due to unresponsive peripheral,DMA_ENGINE DMA channel 5 transfer timeout due to unresponsive peripheral,3
CRITICAL,MEM_CTRL,Memory controller detected unrecoverable hardware fault,MEM_CTRL Memory controller detected unrecoverable hardware fault,1
WARNING,DMA_ENGINE,DMA channel arbitration queue congested,DMA_ENGINE DMA channel arbitration queue congested,3
CRITICAL,POWER_CTRL,System thermal shutdown initiated due to over-temperature,POWER_CTRL System thermal shutdown initiated due to over-temperature,4
INFO,POWER_CTRL,Voltage rail nominal,POWER_CTRL Voltage rail nominal,4
INFO,POWER_CTRL,Core voltage rail nominal,POWER_CTRL Core voltage rail nominal,4
ERROR,DDR_CTRL,DDR bank activate memory alignment fault.,DDR_CTRL DDR bank activate memory alignment fault.,1
CRITICAL,PCIE_CTRL,PCIe link state machine stuck in recovery,PCIE_CTRL PCIe link state machine stuck in recovery,6
INFO,CACHE_CTRL,Cache way 0 disabled due to ECC errors,CACHE_CTRL Cache way 0 disabled due to ECC errors,1
WARNING,MEM_CTRL,Memory write latency exceeding expected threshold.,MEM_CTRL Memory write latency exceeding expected threshold.,1
CRITICAL,MEM_CTRL,Fatal memory interface protocol violation detected.,MEM_CTRL Fatal memory interface protocol violation detected.,1
INFO,MEM_CTRL,Memory read from 0xABCDEF00 completed,MEM_CTRL Memory read from 0xABCDEF00 completed,1
WARNING,CACHE_CTRL,"Cache eviction queue nearing capacity, thrashing risk (95% full)","CACHE_CTRL Cache eviction queue nearing capacity, thrashing risk (95% full)",1
WARNING,CLOCK_MANAGER,CLOCK_MANAGER expected response delay exceeding threshold (current: 47 cycles).,CLOCK_MANAGER CLOCK_MANAGER expected response delay exceeding threshold (current: 47 cycles).,-1
INFO,FIFO_BUF,FIFO_RESPONSE_QUEUE is now empty.,FIFO_BUF FIFO_RESPONSE_QUEUE is now empty.,5
CRITICAL,POWER_CTRL,System shutdown due to overcurrent event,POWER_CTRL System shutdown due to overcurrent event,4
INFO,CACHE_CTRL,Cache flush operation completed.,CACHE_CTRL Cache flush operation completed.,1
WARNING,INTERRUPT_CTRL,Interrupt service routine (ISR) execution time exceeding expected duration,INTERRUPT_CTRL Interrupt service routine (ISR) execution time exceeding expected duration,1
INFO,PCIE_CTRL,Link state transitioned to L0,PCIE_CTRL Link state transitioned to L0,6
WARNING,PCIE_CTRL,PCIe hot-plug operation detected slow device response,PCIE_CTRL PCIe hot-plug operation detected slow device response,6
ERROR,POWER_CTRL,Power rail voltage droop detected,POWER_CTRL Power rail voltage droop detected,4
ERROR,DDR_CTRL,"DDR refresh command not issued on time, channel CH1.","DDR_CTRL DDR refresh command not issued on time, channel CH1.",1
INFO,DDR_CTRL,DDR memory initialized with pattern 0x5A,DDR_CTRL DDR memory initialized with pattern 0x5A,1
CRITICAL,CLOCK_MANAGER,Clock domain crossing failure leading to data loss,CLOCK_MANAGER Clock domain crossing failure leading to data loss,0
ERROR,MEM_CTRL,Memory read operation from invalid address,MEM_CTRL Memory read operation from invalid address,1
INFO,AXI_CTRL,AXI master 'CPU' successfully acquired bus.,AXI_CTRL AXI master 'CPU' successfully acquired bus.,2
INFO,AXI_CTRL,AXI address phase completed,AXI_CTRL AXI address phase completed,2
ERROR,FIFO_BUF,FIFO access violation: illegal address 0xABCDEF01.,FIFO_BUF FIFO access violation: illegal address 0xABCDEF01.,-1
CRITICAL,POWER_CTRL,Critical voltage drop detected on logic core rail,POWER_CTRL Critical voltage drop detected on logic core rail,4
WARNING,DMA_ENGINE,DMA descriptor queue depth exceeding 80%,DMA_ENGINE DMA descriptor queue depth exceeding 80%,3
INFO,FIFO_BUF,FIFO 'debug_info' successfully read 10 entries,FIFO_BUF FIFO 'debug_info' successfully read 10 entries,5
CRITICAL,MEM_CTRL,"Memory fatal read error, system halt.","MEM_CTRL Memory fatal read error, system halt.",1
WARNING,FIFO_BUF,FIFO 'data_out' occupancy at 90%,FIFO_BUF FIFO 'data_out' occupancy at 90%,5
WARNING,CLOCK_MANAGER,"Clock skew between modules A and B increasing, approaching unsafe range","CLOCK_MANAGER Clock skew between modules A and B increasing, approaching unsafe range",0
CRITICAL,POWER_CTRL,Power rail voltage completely missing,POWER_CTRL Power rail voltage completely missing,4
CRITICAL,MEM_CTRL,Entire memory subsystem unresponsive,MEM_CTRL Entire memory subsystem unresponsive,1
ERROR,FIFO_BUF,FIFO_CONTROL buffer underflow,FIFO_BUF FIFO_CONTROL buffer underflow,5
CRITICAL,POWER_CTRL,System PMIC rail 0 voltage collapse,POWER_CTRL System PMIC rail 0 voltage collapse,4
INFO,DMA_ENGINE,New DMA transfer started,DMA_ENGINE New DMA transfer started,3
ERROR,INTERRUPT_CTRL,INTERRUPT_CTRL control logic stalled due to arbitration conflict (arbitration logic malfunction). (Conflicting IRQ IDs: 29 and 22),INTERRUPT_CTRL INTERRUPT_CTRL control logic stalled due to arbitration conflict (arbitration logic malfunction). (Conflicting IRQ IDs: 29 and 22),1
ERROR,CACHE_CTRL,Cache line invalidation timeout,CACHE_CTRL Cache line invalidation timeout,1
ERROR,AXI_CTRL,AXI protection bits (APROT) violation detected by firewall.,AXI_CTRL AXI protection bits (APROT) violation detected by firewall.,2
WARNING,CACHE_CTRL,Cache write buffer full causing stalls,CACHE_CTRL Cache write buffer full causing stalls,1
ERROR,DMA_ENGINE,DMA data transfer CRC error detected during block transfer,DMA_ENGINE DMA data transfer CRC error detected during block transfer,3
ERROR,INTERRUPT_CTRL,Non-maskable interrupt (NMI) acknowledgment timeout,INTERRUPT_CTRL Non-maskable interrupt (NMI) acknowledgment timeout,1
WARNING,CACHE_CTRL,Write buffer fill level high,CACHE_CTRL Write buffer fill level high,1
WARNING,DMA_ENGINE,DMA channel error status register asserted,DMA_ENGINE DMA channel error status register asserted,3
ERROR,INTERRUPT_CTRL,Shared interrupt line contention,INTERRUPT_CTRL Shared interrupt line contention,1
WARNING,PCIE_CTRL,PCIe retry buffer occupancy nearing capacity,PCIE_CTRL PCIe retry buffer occupancy nearing capacity,6
WARNING,INTERRUPT_CTRL,"Interrupt queue approaching limit, potential drops","INTERRUPT_CTRL Interrupt queue approaching limit, potential drops",1
CRITICAL,DMA_ENGINE,DMA controller internal state machine entered unrecoverable state.,DMA_ENGINE DMA controller internal state machine entered unrecoverable state.,3
CRITICAL,MEM_CTRL,Parity error detected in memory address generation unit,MEM_CTRL Parity error detected in memory address generation unit,1
CRITICAL,MEM_CTRL,Memory controller arbiter entered invalid state,MEM_CTRL Memory controller arbiter entered invalid state,1
CRITICAL,MEM_CTRL,Memory protection unit (MPU) violation and system halt.,MEM_CTRL Memory protection unit (MPU) violation and system halt.,1
ERROR,POWER_CTRL,Power rail VDD_GPU dropped below minimum operating voltage,POWER_CTRL Power rail VDD_GPU dropped below minimum operating voltage,4
INFO,CLOCK_MANAGER,Clock gate enabled for peripheral bus,CLOCK_MANAGER Clock gate enabled for peripheral bus,0
CRITICAL,CLOCK_MANAGER,"Primary clock source failed, unable to recover, system halted","CLOCK_MANAGER Primary clock source failed, unable to recover, system halted",0
WARNING,INTERRUPT_CTRL,Interrupt source 5 masked for too long,INTERRUPT_CTRL Interrupt source 5 masked for too long,1
ERROR,DMA_ENGINE,DMA buffer descriptor invalidation error,DMA_ENGINE DMA buffer descriptor invalidation error,3
INFO,CLOCK_MANAGER,PLL frequency lock re-established,CLOCK_MANAGER PLL frequency lock re-established,0
WARNING,DDR_CTRL,DDR performance nearing degradation threshold,DDR_CTRL DDR performance nearing degradation threshold,1
WARNING,CACHE_CTRL,Cache way miss count rising,CACHE_CTRL Cache way miss count rising,1
INFO,DDR_CTRL,DDR controller self-refresh exit successful,DDR_CTRL DDR controller self-refresh exit successful,1
ERROR,CLOCK_MANAGER,Global reset de-assertion timing violation,CLOCK_MANAGER Global reset de-assertion timing violation,0
WARNING,DDR_CTRL,DDR write data eye margin at minimum,DDR_CTRL DDR write data eye margin at minimum,1
INFO,PCIE_CTRL,PCIe virtual channel 0 enabled.,PCIE_CTRL PCIe virtual channel 0 enabled.,6
CRITICAL,CACHE_CTRL,"Data cache coherence deadlock detected, requiring system reset","CACHE_CTRL Data cache coherence deadlock detected, requiring system reset",1
ERROR,INTERRUPT_CTRL,"Interrupt storm detected, excessive interrupts.","INTERRUPT_CTRL Interrupt storm detected, excessive interrupts.",1
ERROR,DMA_ENGINE,DMA transfer size configured to an unsupported value.,DMA_ENGINE DMA transfer size configured to an unsupported value.,3
WARNING,DMA_ENGINE,"DMA buffer descriptor list nearing end, refill required","DMA_ENGINE DMA buffer descriptor list nearing end, refill required",3
WARNING,AXI_CTRL,AXI response error (DECERR) count increasing,AXI_CTRL AXI response error (DECERR) count increasing,2
CRITICAL,DDR_CTRL,DDR command bus parity error during critical operation.,DDR_CTRL DDR command bus parity error during critical operation.,1
INFO,FIFO_BUF,Read operation returned valid data,FIFO_BUF Read operation returned valid data,5
WARNING,DDR_CTRL,DDR refresh cycles delayed due to high priority access,DDR_CTRL DDR refresh cycles delayed due to high priority access,1
INFO,INTERRUPT_CTRL,Interrupt controller software reset asserted,INTERRUPT_CTRL Interrupt controller software reset asserted,1
INFO,AXI_CTRL,AXI write burst to address 0x... completed,AXI_CTRL AXI write burst to address 0x... completed,2
CRITICAL,CLOCK_MANAGER,System PLL reference clock loss detected,CLOCK_MANAGER System PLL reference clock loss detected,0
INFO,DMA_ENGINE,DMA channel 4 resumed operation,DMA_ENGINE DMA channel 4 resumed operation,3
WARNING,CACHE_CTRL,Cache tag RAM read/write error.,CACHE_CTRL Cache tag RAM read/write error.,1
WARNING,DDR_CTRL,DDR memory temperature above nominal,DDR_CTRL DDR memory temperature above nominal,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout detected for IRQ 1.,INTERRUPT_CTRL Interrupt acknowledge timeout detected for IRQ 1.,1
ERROR,CLOCK_MANAGER,Reference clock frequency drift beyond spec,CLOCK_MANAGER Reference clock frequency drift beyond spec,0
CRITICAL,PCIE_CTRL,"PCIe fatal link error, hot reset required.","PCIE_CTRL PCIe fatal link error, hot reset required.",6
CRITICAL,DDR_CTRL,"CRITICAL: DDR training sequence failed, memory unusable (channel CH0).","DDR_CTRL CRITICAL: DDR training sequence failed, memory unusable (channel CH0).",1
WARNING,CACHE_CTRL,Cache replacement policy thrashing detected.,CACHE_CTRL Cache replacement policy thrashing detected.,1
WARNING,CLOCK_MANAGER,Frequency deviation detected,CLOCK_MANAGER Frequency deviation detected,0
INFO,FIFO_BUF,"FIFO fill level 0x3A, still room for more data","FIFO_BUF FIFO fill level 0x3A, still room for more data",5
INFO,MEM_CTRL,Read operation successful from 0xDEADBEEF,MEM_CTRL Read operation successful from 0xDEADBEEF,1
INFO,DDR_CTRL,DDR power-up sequence complete.,DDR_CTRL DDR power-up sequence complete.,1
CRITICAL,MEM_CTRL,Memory refresh FSM deadlock,MEM_CTRL Memory refresh FSM deadlock,1
CRITICAL,PCIE_CTRL,PCIe root port link training fatal error,PCIE_CTRL PCIe root port link training fatal error,6
WARNING,CACHE_CTRL,Cache refill operation took longer than expected.,CACHE_CTRL Cache refill operation took longer than expected.,1
WARNING,DDR_CTRL,DDR training sequence retry count incremented,DDR_CTRL DDR training sequence retry count incremented,1
WARNING,INTERRUPT_CTRL,Pending interrupt queue nearing saturation (13 entries).,INTERRUPT_CTRL Pending interrupt queue nearing saturation (13 entries).,1
ERROR,DDR_CTRL,DDR row hammer event detected,DDR_CTRL DDR row hammer event detected,-1
WARNING,INTERRUPT_CTRL,Interrupt acknowledge timeout approaching limit,INTERRUPT_CTRL Interrupt acknowledge timeout approaching limit,1
CRITICAL,DMA_ENGINE,"DMA channel 10 data path stuck, data not flowing","DMA_ENGINE DMA channel 10 data path stuck, data not flowing",3
INFO,PCIE_CTRL,PCIe link training completed,PCIE_CTRL PCIe link training completed,6
WARNING,CACHE_CTRL,"Cache data array bit flip detected, corrected by ECC","CACHE_CTRL Cache data array bit flip detected, corrected by ECC",1
INFO,AXI_CTRL,AXI burst read from address 0xFEEDDEAD completed,AXI_CTRL AXI burst read from address 0xFEEDDEAD completed,2
INFO,AXI_CTRL,AXI slave 3 registered for interrupts,AXI_CTRL AXI slave 3 registered for interrupts,2
WARNING,AXI_CTRL,AXI burst length mismatch between master request and slave capability,AXI_CTRL AXI burst length mismatch between master request and slave capability,2
ERROR,MEM_CTRL,"Memory read data mismatch, multiple error bits","MEM_CTRL Memory read data mismatch, multiple error bits",1
WARNING,DMA_ENGINE,"DMA arbitration conflict detected, minor delay (channel 0x3 vs 0x4)","DMA_ENGINE DMA arbitration conflict detected, minor delay (channel 0x3 vs 0x4)",3
WARNING,DDR_CTRL,DDR data bus inversion (DBI) error,DDR_CTRL DDR data bus inversion (DBI) error,1
CRITICAL,DMA_ENGINE,DMA channel 11 transfer halted due to unrecoverable error,DMA_ENGINE DMA channel 11 transfer halted due to unrecoverable error,3
WARNING,FIFO_BUF,FIFO read data is stale due to timing.,FIFO_BUF FIFO read data is stale due to timing.,5
CRITICAL,DDR_CTRL,DDR controller internal configuration corruption,DDR_CTRL DDR controller internal configuration corruption,1
WARNING,AXI_CTRL,Backpressure asserted on AXI write channel,AXI_CTRL Backpressure asserted on AXI write channel,2
WARNING,CLOCK_MANAGER,Asynchronous reset deassertion delay detected,CLOCK_MANAGER Asynchronous reset deassertion delay detected,0
ERROR,MEM_CTRL,Memory address mapping conflict detected,MEM_CTRL Memory address mapping conflict detected,1
INFO,FIFO_BUF,"Read operation successful, data consumed","FIFO_BUF Read operation successful, data consumed",5
WARNING,POWER_CTRL,Voltage regulator thermal sensor approaching warning limit,POWER_CTRL Voltage regulator thermal sensor approaching warning limit,4
CRITICAL,FIFO_BUF,Critical data FIFO permanently desynchronized,FIFO_BUF Critical data FIFO permanently desynchronized,5
INFO,AXI_CTRL,Master 2 granted bus access successfully,AXI_CTRL Master 2 granted bus access successfully,2
ERROR,POWER_CTRL,Power domain isolation fault,POWER_CTRL Power domain isolation fault,4
INFO,CLOCK_MANAGER,Secondary clock source engaged,CLOCK_MANAGER Secondary clock source engaged,0
WARNING,FIFO_BUF,FIFO output data valid not asserted promptly,FIFO_BUF FIFO output data valid not asserted promptly,5
INFO,CLOCK_MANAGER,Clock frequency changed to 250MHz for low power mode.,CLOCK_MANAGER Clock frequency changed to 250MHz for low power mode.,0
INFO,DDR_CTRL,Low power entry requested by DDR_CTRL.,DDR_CTRL Low power entry requested by DDR_CTRL.,1
INFO,AXI_CTRL,AXI transaction ID remapping successful,AXI_CTRL AXI transaction ID remapping successful,2
WARNING,POWER_CTRL,Current monitor detected peak current exceeding nominal,POWER_CTRL Current monitor detected peak current exceeding nominal,-1
ERROR,MEM_CTRL,"MEM_CTRL: memory alignment fault - unaligned memory access detected. (Faulting Address: 0x935B6, Req Size: 8 Bytes)","MEM_CTRL MEM_CTRL: memory alignment fault - unaligned memory access detected. (Faulting Address: 0x935B6, Req Size: 8 Bytes)",1
ERROR,MEM_CTRL,Memory data corruption due to write buffering issue,MEM_CTRL Memory data corruption due to write buffering issue,1
WARNING,AXI_CTRL,AXI read latency exceeding threshold,AXI_CTRL AXI read latency exceeding threshold,2
ERROR,DDR_CTRL,DDR address parity error detected,DDR_CTRL DDR address parity error detected,1
CRITICAL,CLOCK_MANAGER,PLL frequency drift beyond acceptable range,CLOCK_MANAGER PLL frequency drift beyond acceptable range,0
ERROR,MEM_CTRL,"Memory controller FSM in invalid state, unexpected behavior.","MEM_CTRL Memory controller FSM in invalid state, unexpected behavior.",1
ERROR,DDR_CTRL,DDR precharge command sequence violation,DDR_CTRL DDR precharge command sequence violation,1
CRITICAL,DDR_CTRL,DDR command bus integrity check failed,DDR_CTRL DDR command bus integrity check failed,1
CRITICAL,DMA_ENGINE,DMA engine configuration registers corrupted.,DMA_ENGINE DMA engine configuration registers corrupted.,3
ERROR,CACHE_CTRL,Cache write buffer overflow,CACHE_CTRL Cache write buffer overflow,1
WARNING,FIFO_BUF,"FIFO write pointer close to read pointer, potential underflow","FIFO_BUF FIFO write pointer close to read pointer, potential underflow",5
INFO,DMA_ENGINE,DMA transfer completed on channel 15,DMA_ENGINE DMA transfer completed on channel 15,3
CRITICAL,POWER_CTRL,Critical core voltage rail dropped below threshold,POWER_CTRL Critical core voltage rail dropped below threshold,4
ERROR,FIFO_BUF,Read/write pointer divergence beyond acceptable limits.,FIFO_BUF Read/write pointer divergence beyond acceptable limits.,5
WARNING,AXI_CTRL,AXI outstanding write transaction count elevated,AXI_CTRL AXI outstanding write transaction count elevated,2
ERROR,AXI_CTRL,"AXI burst length violation detected, illegal burst size of 17","AXI_CTRL AXI burst length violation detected, illegal burst size of 17",2
INFO,CLOCK_MANAGER,Clock gating enabled for module B.,CLOCK_MANAGER Clock gating enabled for module B.,0
ERROR,POWER_CTRL,Voltage regulator output out of spec,POWER_CTRL Voltage regulator output out of spec,4
ERROR,CACHE_CTRL,Cache line filled with data that has bad parity.,CACHE_CTRL Cache line filled with data that has bad parity.,1
ERROR,DDR_CTRL,DDR write data path integrity failure,DDR_CTRL DDR write data path integrity failure,1
ERROR,PCIE_CTRL,"PCIe TLP parsing error, malformed packet received","PCIE_CTRL PCIe TLP parsing error, malformed packet received",6
INFO,INTERRUPT_CTRL,Interrupt controller configured for edge triggered mode,INTERRUPT_CTRL Interrupt controller configured for edge triggered mode,-1
ERROR,INTERRUPT_CTRL,Unexpected interrupt assertion from unconfigured source.,INTERRUPT_CTRL Unexpected interrupt assertion from unconfigured source.,1
ERROR,AXI_CTRL,AXI response channel handshake violation,AXI_CTRL AXI response channel handshake violation,2
ERROR,CLOCK_MANAGER,PLL bypass mode entered unexpectedly,CLOCK_MANAGER PLL bypass mode entered unexpectedly,0
INFO,POWER_CTRL,Power-on reset sequence complete.,POWER_CTRL Power-on reset sequence complete.,4
ERROR,PCIE_CTRL,"PCIe link training failure detected, defaulting to Gen1 x1","PCIE_CTRL PCIe link training failure detected, defaulting to Gen1 x1",6
INFO,POWER_CTRL,Low-power idle state successfully entered,POWER_CTRL Low-power idle state successfully entered,4
WARNING,AXI_CTRL,AXI master 0x04 waiting for RREADY from slave 0x07 for too long,AXI_CTRL AXI master 0x04 waiting for RREADY from slave 0x07 for too long,2
WARNING,AXI_CTRL,AXI handshake delay approaching threshold for master 'ETH'.,AXI_CTRL AXI handshake delay approaching threshold for master 'ETH'.,2
CRITICAL,CACHE_CTRL,L1 data cache writeback buffer overflow,CACHE_CTRL L1 data cache writeback buffer overflow,1
ERROR,CLOCK_MANAGER,Clock gating cell for module 'UART' stuck open,CLOCK_MANAGER Clock gating cell for module 'UART' stuck open,-1
CRITICAL,DDR_CTRL,DDR PHY calibration values drifted out of tolerance,DDR_CTRL DDR PHY calibration values drifted out of tolerance,1
INFO,FIFO_BUF,FIFO flush completed.,FIFO_BUF FIFO flush completed.,5
CRITICAL,MEM_CTRL,ECC parity mismatch detected on memory read,MEM_CTRL ECC parity mismatch detected on memory read,1
CRITICAL,MEM_CTRL,Multi-bit ECC corruption detected in critical memory region,MEM_CTRL Multi-bit ECC corruption detected in critical memory region,1
CRITICAL,POWER_CTRL,Overvoltage protection tripped,POWER_CTRL Overvoltage protection tripped,4
INFO,AXI_CTRL,AXI master granted bus access,AXI_CTRL AXI master granted bus access,2
CRITICAL,CACHE_CTRL,"Cache data array uncorrectable error, ECC failure.","CACHE_CTRL Cache data array uncorrectable error, ECC failure.",1
WARNING,FIFO_BUF,Output FIFO buffer nearing underflow condition,FIFO_BUF Output FIFO buffer nearing underflow condition,5
INFO,FIFO_BUF,FIFO reset sequence verified,FIFO_BUF FIFO reset sequence verified,5
INFO,AXI_CTRL,AXI interconnect QoS level configured,AXI_CTRL AXI interconnect QoS level configured,2
INFO,POWER_CTRL,System power measurements recorded,POWER_CTRL System power measurements recorded,4
CRITICAL,POWER_CTRL,Power management controller reported fatal error,POWER_CTRL Power management controller reported fatal error,4
INFO,CLOCK_MANAGER,All clocks re-synchronized after reset.,CLOCK_MANAGER All clocks re-synchronized after reset.,0
INFO,DMA_ENGINE,DMA channel 15 configured for peripheral transfer,DMA_ENGINE DMA channel 15 configured for peripheral transfer,3
ERROR,INTERRUPT_CTRL,Non-maskable interrupt (NMI) triggered unexpectedly,INTERRUPT_CTRL Non-maskable interrupt (NMI) triggered unexpectedly,1
CRITICAL,DDR_CTRL,"DDR memory initialization sequence failed, system unbootable.","DDR_CTRL DDR memory initialization sequence failed, system unbootable.",1
INFO,FIFO_BUF,FIFO_BUF_11 read pointer advanced,FIFO_BUF FIFO_BUF_11 read pointer advanced,5
INFO,PCIE_CTRL,PCIe TLP transmitted.,PCIE_CTRL PCIe TLP transmitted.,6
INFO,CLOCK_MANAGER,System clock frequency reduced to save power,CLOCK_MANAGER System clock frequency reduced to save power,0
WARNING,PCIE_CTRL,"PCIe retry buffer nearing capacity, potential buffer overflow.","PCIE_CTRL PCIe retry buffer nearing capacity, potential buffer overflow.",6
CRITICAL,DDR_CTRL,DDR ECC multi-bit error detected,DDR_CTRL DDR ECC multi-bit error detected,1
CRITICAL,CACHE_CTRL,"Cache controller in invalid state, requiring reset","CACHE_CTRL Cache controller in invalid state, requiring reset",1
ERROR,DMA_ENGINE,DMA request arbitration fairness violation,DMA_ENGINE DMA request arbitration fairness violation,3
WARNING,MEM_CTRL,Uncorrectable ECC error predicted on memory bank 3,MEM_CTRL Uncorrectable ECC error predicted on memory bank 3,1
CRITICAL,PCIE_CTRL,PCIe device hot-plug controller failure,PCIE_CTRL PCIe device hot-plug controller failure,6
ERROR,PCIE_CTRL,PCIE_CTRL detected a severe state machine fault: FSM stuck in error state.,PCIE_CTRL PCIE_CTRL detected a severe state machine fault: FSM stuck in error state.,-1
CRITICAL,DDR_CTRL,DDR memory module 0 failed to initialize,DDR_CTRL DDR memory module 0 failed to initialize,1
WARNING,MEM_CTRL,Memory bus arbitration fairness issue,MEM_CTRL Memory bus arbitration fairness issue,1
INFO,PCIE_CTRL,PCIe device BAR configuration successful.,PCIE_CTRL PCIe device BAR configuration successful.,6
ERROR,DMA_ENGINE,Invalid DMA channel access attempt detected,DMA_ENGINE Invalid DMA channel access attempt detected,3
WARNING,AXI_CTRL,AXI protection fault warning: supervisor access denied,AXI_CTRL AXI protection fault warning: supervisor access denied,-1
INFO,MEM_CTRL,Memory self-test passed successfully,MEM_CTRL Memory self-test passed successfully,1
CRITICAL,PCIE_CTRL,PCIe endpoint initiated unexpected link down sequence,PCIE_CTRL PCIe endpoint initiated unexpected link down sequence,6
WARNING,AXI_CTRL,AXI read channel ID mismatch detected,AXI_CTRL AXI read channel ID mismatch detected,2
INFO,DMA_ENGINE,DMA channel 4 transfer paused for debug,DMA_ENGINE DMA channel 4 transfer paused for debug,3
WARNING,DMA_ENGINE,DMA channel 4 transfer rate degrading,DMA_ENGINE DMA channel 4 transfer rate degrading,3
INFO,DDR_CTRL,DDR memory block activated,DDR_CTRL DDR memory block activated,1
CRITICAL,POWER_CTRL,Power sequencing logic halted,POWER_CTRL Power sequencing logic halted,4
INFO,MEM_CTRL,Memory data initialization successful,MEM_CTRL Memory data initialization successful,1
WARNING,AXI_CTRL,Burst length inconsistent,AXI_CTRL Burst length inconsistent,2
INFO,CLOCK_MANAGER,Reference clock source verified,CLOCK_MANAGER Reference clock source verified,0
WARNING,MEM_CTRL,Memory controller refresh cycles becoming less frequent,MEM_CTRL Memory controller refresh cycles becoming less frequent,1
INFO,AXI_CTRL,AXI transaction to slave 0x0F completed without errors.,AXI_CTRL AXI transaction to slave 0x0F completed without errors.,2
WARNING,DMA_ENGINE,DMA channel 2 bandwidth utilization low,DMA_ENGINE DMA channel 2 bandwidth utilization low,3
WARNING,AXI_CTRL,Read address channel handshake delay approaching threshold,AXI_CTRL Read address channel handshake delay approaching threshold,2
ERROR,DMA_ENGINE,DMA channel configuration mismatch.,DMA_ENGINE DMA channel configuration mismatch.,3
ERROR,CLOCK_MANAGER,"Clock generator output stuck low, hardware fault.","CLOCK_MANAGER Clock generator output stuck low, hardware fault.",0
CRITICAL,POWER_CTRL,Critical system power rail VCC_DDR went offline,POWER_CTRL Critical system power rail VCC_DDR went offline,-1
INFO,DMA_ENGINE,DMA engine capabilities queried,DMA_ENGINE DMA engine capabilities queried,3
CRITICAL,CLOCK_MANAGER,System clock distribution network integrity compromised,CLOCK_MANAGER System clock distribution network integrity compromised,0
ERROR,PCIE_CTRL,PCIe TLP header corruption detected on inbound transaction,PCIE_CTRL PCIe TLP header corruption detected on inbound transaction,6
ERROR,INTERRUPT_CTRL,"Interrupt line Y stuck high, hardware issue.","INTERRUPT_CTRL Interrupt line Y stuck high, hardware issue.",1
INFO,CACHE_CTRL,L2 cache flush operation initiated,CACHE_CTRL L2 cache flush operation initiated,1
ERROR,MEM_CTRL,Single-bit ECC error corrected at address 0xDEADBEEF,MEM_CTRL Single-bit ECC error corrected at address 0xDEADBEEF,1
INFO,AXI_CTRL,AXI slave responding with OKAY status,AXI_CTRL AXI slave responding with OKAY status,2
CRITICAL,INTERRUPT_CTRL,"Interrupt logic unrecoverable error, system unresponsive.","INTERRUPT_CTRL Interrupt logic unrecoverable error, system unresponsive.",1
ERROR,MEM_CTRL,Command timing violation detected for consecutive memory accesses.,MEM_CTRL Command timing violation detected for consecutive memory accesses.,1
INFO,MEM_CTRL,Memory ECC enabled successfully,MEM_CTRL Memory ECC enabled successfully,1
CRITICAL,CACHE_CTRL,"Cache directory entry corruption detected, resulting in stale data access.","CACHE_CTRL Cache directory entry corruption detected, resulting in stale data access.",1
WARNING,DDR_CTRL,DDR power down entry/exit delay.,DDR_CTRL DDR power down entry/exit delay.,1
ERROR,POWER_CTRL,Power rail current limit exceeded on VDD_MEM,POWER_CTRL Power rail current limit exceeded on VDD_MEM,4
INFO,DDR_CTRL,DDR controller calibration data saved,DDR_CTRL DDR controller calibration data saved,1
ERROR,CACHE_CTRL,Cache prefetcher accessed an invalid memory region.,CACHE_CTRL Cache prefetcher accessed an invalid memory region.,1
INFO,CACHE_CTRL,L2 cache flush initiated,CACHE_CTRL L2 cache flush initiated,1
WARNING,INTERRUPT_CTRL,Interrupt source 10 unacknowledged for too long,INTERRUPT_CTRL Interrupt source 10 unacknowledged for too long,1
INFO,POWER_CTRL,Voltage rail Y within nominal range,POWER_CTRL Voltage rail Y within nominal range,4
CRITICAL,DDR_CTRL,DDR calibration sequence failed to converge,DDR_CTRL DDR calibration sequence failed to converge,1
WARNING,DDR_CTRL,DDR command queue depth exceeding target,DDR_CTRL DDR command queue depth exceeding target,1
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance on external clock input,CLOCK_MANAGER Clock jitter exceeding tolerance on external clock input,0
INFO,CLOCK_MANAGER,Phase-locked loop re-locked successfully,CLOCK_MANAGER Phase-locked loop re-locked successfully,0
CRITICAL,MEM_CTRL,System memory access disabled by controller,MEM_CTRL System memory access disabled by controller,1
ERROR,PCIE_CTRL,PCIe completer abort (CA) received from downstream device,PCIE_CTRL PCIe completer abort (CA) received from downstream device,6
ERROR,CLOCK_MANAGER,Clock domain crossing metastable event detected,CLOCK_MANAGER Clock domain crossing metastable event detected,0
INFO,PCIE_CTRL,PCIe device Function 1 disabled.,PCIE_CTRL PCIe device Function 1 disabled.,6
INFO,AXI_CTRL,AXI AW channel handshake detected.,AXI_CTRL AXI AW channel handshake detected.,2
WARNING,FIFO_BUF,FIFO synchronization logic asynchronous event detected,FIFO_BUF FIFO synchronization logic asynchronous event detected,5
ERROR,AXI_CTRL,AXI address decoding error detected,AXI_CTRL AXI address decoding error detected,2
CRITICAL,CLOCK_MANAGER,Primary system clock halted,CLOCK_MANAGER Primary system clock halted,0
ERROR,AXI_CTRL,AXI response error (SLVERR) from slave,AXI_CTRL AXI response error (SLVERR) from slave,2
ERROR,AXI_CTRL,AXI burst write completion timeout,AXI_CTRL AXI burst write completion timeout,2
CRITICAL,AXI_CTRL,AXI protocol violation causing unrecoverable bus error,AXI_CTRL AXI protocol violation causing unrecoverable bus error,2
INFO,CACHE_CTRL,Cache flush initiated for specific address range,CACHE_CTRL Cache flush initiated for specific address range,1
WARNING,DMA_ENGINE,DMA transfer rate below expected performance for channel 3.,DMA_ENGINE DMA transfer rate below expected performance for channel 3.,3
INFO,INTERRUPT_CTRL,Interrupt acknowledge completed successfully,INTERRUPT_CTRL Interrupt acknowledge completed successfully,1
ERROR,DDR_CTRL,"DDR training sequence failed, suboptimal memory settings (channel 0x1)","DDR_CTRL DDR training sequence failed, suboptimal memory settings (channel 0x1)",1
WARNING,DDR_CTRL,DDR memory temperature nearing thermal shutdown limit,DDR_CTRL DDR memory temperature nearing thermal shutdown limit,1
ERROR,POWER_CTRL,"Battery voltage low, initiating shutdown","POWER_CTRL Battery voltage low, initiating shutdown",-1
WARNING,DMA_ENGINE,DMA scatter-gather list parsing delay detected,DMA_ENGINE DMA scatter-gather list parsing delay detected,3
INFO,INTERRUPT_CTRL,Interrupt service routine for IRQ_DMA_COMPLETE invoked,INTERRUPT_CTRL Interrupt service routine for IRQ_DMA_COMPLETE invoked,1
ERROR,DDR_CTRL,DDR memory address alignment fault during write,DDR_CTRL DDR memory address alignment fault during write,1
ERROR,POWER_CTRL,Power fault detected on internal supply,POWER_CTRL Power fault detected on internal supply,4
WARNING,CLOCK_MANAGER,Global asynchronous reset assertion detected,CLOCK_MANAGER Global asynchronous reset assertion detected,0
CRITICAL,INTERRUPT_CTRL,System crash due to unmaskable interrupt storm,INTERRUPT_CTRL System crash due to unmaskable interrupt storm,1
CRITICAL,AXI_CTRL,AXI transaction integrity critical failure,AXI_CTRL AXI transaction integrity critical failure,2
ERROR,PCIE_CTRL,PCIe link layer state machine entered error recovery,PCIE_CTRL PCIe link layer state machine entered error recovery,6
CRITICAL,MEM_CTRL,"Memory power rail instability detected, potential data loss","MEM_CTRL Memory power rail instability detected, potential data loss",1
ERROR,FIFO_BUF,FIFO write data bus parity error,FIFO_BUF FIFO write data bus parity error,5
WARNING,PCIE_CTRL,PCIe receiver equalization failing to converge.,PCIE_CTRL PCIe receiver equalization failing to converge.,6
WARNING,PCIE_CTRL,PCIe Completion timeout (CTO) register value unexpected,PCIE_CTRL PCIe Completion timeout (CTO) register value unexpected,6
WARNING,PCIE_CTRL,PCIe link training duration exceeding expected time,PCIE_CTRL PCIe link training duration exceeding expected time,6
CRITICAL,INTERRUPT_CTRL,Unhandled critical system interrupt leading to crash. (system crash),INTERRUPT_CTRL Unhandled critical system interrupt leading to crash. (system crash),1
INFO,CACHE_CTRL,Cache hit detected for read request,CACHE_CTRL Cache hit detected for read request,1
INFO,PCIE_CTRL,PCIe link established successfully,PCIE_CTRL PCIe link established successfully,6
WARNING,CLOCK_MANAGER,CLOCK_MANAGER observed higher than expected transaction latency (TxID: 75).,CLOCK_MANAGER CLOCK_MANAGER observed higher than expected transaction latency (TxID: 75).,-1
ERROR,POWER_CTRL,Power management state machine hung,POWER_CTRL Power management state machine hung,4
ERROR,AXI_CTRL,AXI slave issued an unexpected error response (SLVERR),AXI_CTRL AXI slave issued an unexpected error response (SLVERR),2
ERROR,POWER_CTRL,Overcurrent condition detected on peripheral rail,POWER_CTRL Overcurrent condition detected on peripheral rail,4
ERROR,DMA_ENGINE,DMA channel 9 burst transaction resulted in AXI SLVERR,DMA_ENGINE DMA channel 9 burst transaction resulted in AXI SLVERR,-1
WARNING,CACHE_CTRL,Cache invalidate queue backing up,CACHE_CTRL Cache invalidate queue backing up,1
ERROR,PCIE_CTRL,PCIe AER fatal error reported by endpoint 0x1000.,PCIE_CTRL PCIe AER fatal error reported by endpoint 0x1000.,6
ERROR,CLOCK_MANAGER,Global reset signal asserted for too short a duration,CLOCK_MANAGER Global reset signal asserted for too short a duration,-1
INFO,CLOCK_MANAGER,Clock gate enable status verified,CLOCK_MANAGER Clock gate enable status verified,0
CRITICAL,POWER_CTRL,Overcurrent condition detected on 3.3V supply,POWER_CTRL Overcurrent condition detected on 3.3V supply,4
CRITICAL,AXI_CTRL,"AXI interconnect deadlock detected, system halt.","AXI_CTRL AXI interconnect deadlock detected, system halt.",2
WARNING,INTERRUPT_CTRL,Multiple interrupts pending from same source,INTERRUPT_CTRL Multiple interrupts pending from same source,1
WARNING,DDR_CTRL,DDR memory controller queue for reads consistently full,DDR_CTRL DDR memory controller queue for reads consistently full,1
CRITICAL,CACHE_CTRL,Cache controller detected a critical system deadlock.,CACHE_CTRL Cache controller detected a critical system deadlock.,1
ERROR,DMA_ENGINE,"DMA channel arbitration failure, channel hung","DMA_ENGINE DMA channel arbitration failure, channel hung",3
CRITICAL,DMA_ENGINE,DMA data corruption across multiple transfers,DMA_ENGINE DMA data corruption across multiple transfers,3
ERROR,CACHE_CTRL,Cache tag parity error detected for line 0x750A8,CACHE_CTRL Cache tag parity error detected for line 0x750A8,1
ERROR,DDR_CTRL,DDR command pipeline stalled due to timing violation,DDR_CTRL DDR command pipeline stalled due to timing violation,1
INFO,DMA_ENGINE,New DMA transfer started for device 1.,DMA_ENGINE New DMA transfer started for device 1.,3
ERROR,DMA_ENGINE,DMA channel 5 transfer aborted due to descriptor error,DMA_ENGINE DMA channel 5 transfer aborted due to descriptor error,3
ERROR,MEM_CTRL,"Memory address decoding error, access to reserved region.","MEM_CTRL Memory address decoding error, access to reserved region.",1
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected on channel 0.,DMA_ENGINE DMA buffer pointer corruption detected on channel 0.,3
WARNING,PCIE_CTRL,PCIe CRC error rate increasing,PCIE_CTRL PCIe CRC error rate increasing,6
INFO,CACHE_CTRL,Cache writeback completed for dirty line,CACHE_CTRL Cache writeback completed for dirty line,1
WARNING,PCIE_CTRL,PCIe retry buffer nearing capacity (90% full),PCIE_CTRL PCIe retry buffer nearing capacity (90% full),6
INFO,CACHE_CTRL,Cache line allocation successful,CACHE_CTRL Cache line allocation successful,1
ERROR,AXI_CTRL,AXI protocol error on write address channel,AXI_CTRL AXI protocol error on write address channel,2
INFO,CACHE_CTRL,Cache directory entry successfully updated,CACHE_CTRL Cache directory entry successfully updated,1
INFO,CACHE_CTRL,Cache line written back from dirty state,CACHE_CTRL Cache line written back from dirty state,1
ERROR,INTERRUPT_CTRL,Interrupt signal toggling too rapidly,INTERRUPT_CTRL Interrupt signal toggling too rapidly,1
ERROR,MEM_CTRL,Memory address alignment violation (address 0x12345678).,MEM_CTRL Memory address alignment violation (address 0x12345678).,1
INFO,POWER_CTRL,Voltage scaling successful,POWER_CTRL Voltage scaling successful,-1
INFO,INTERRUPT_CTRL,Interrupt X acknowledged.,INTERRUPT_CTRL Interrupt X acknowledged.,1
ERROR,CACHE_CTRL,Cache entry lock failure,CACHE_CTRL Cache entry lock failure,1
WARNING,PCIE_CTRL,PCIe replay buffer occupancy high,PCIE_CTRL PCIe replay buffer occupancy high,6
INFO,CLOCK_MANAGER,Clock buffer power consumption optimized,CLOCK_MANAGER Clock buffer power consumption optimized,-1
INFO,CLOCK_MANAGER,PLL locked successfully (3052MHz).,CLOCK_MANAGER PLL locked successfully (3052MHz).,0
ERROR,POWER_CTRL,Overcurrent protection tripped on auxiliary rail,POWER_CTRL Overcurrent protection tripped on auxiliary rail,4
ERROR,DDR_CTRL,DDR power-up sequence failed to meet timing,DDR_CTRL DDR power-up sequence failed to meet timing,1
ERROR,DDR_CTRL,DDR mode register write failed,DDR_CTRL DDR mode register write failed,1
ERROR,INTERRUPT_CTRL,Interrupt arbitration conflict detected for IRQ lines 3 and 4,INTERRUPT_CTRL Interrupt arbitration conflict detected for IRQ lines 3 and 4,1
CRITICAL,CLOCK_MANAGER,External clock source lost,CLOCK_MANAGER External clock source lost,0
ERROR,DDR_CTRL,DDR memory refresh command timing violation,DDR_CTRL DDR memory refresh command timing violation,1
CRITICAL,DMA_ENGINE,DMA engine initiated an uncommanded transfer to protected memory,DMA_ENGINE DMA engine initiated an uncommanded transfer to protected memory,3
WARNING,CACHE_CTRL,Cache invalidation backlog,CACHE_CTRL Cache invalidation backlog,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal configuration mismatch detected,INTERRUPT_CTRL Interrupt controller internal configuration mismatch detected,1
CRITICAL,MEM_CTRL,Memory bank 0 access failure,MEM_CTRL Memory bank 0 access failure,1
INFO,PCIE_CTRL,PCIe device BARs successfully mapped,PCIE_CTRL PCIe device BARs successfully mapped,6
INFO,DMA_ENGINE,DMA transfer completed successfully for channel 7.,DMA_ENGINE DMA transfer completed successfully for channel 7.,3
ERROR,AXI_CTRL,AXI bus contention detected between two masters,AXI_CTRL AXI bus contention detected between two masters,2
ERROR,AXI_CTRL,AXI write channel (AW) response timeout detected,AXI_CTRL AXI write channel (AW) response timeout detected,2
CRITICAL,MEM_CTRL,"DRAM device unresponsive to all commands, fatal memory error","MEM_CTRL DRAM device unresponsive to all commands, fatal memory error",1
CRITICAL,INTERRUPT_CTRL,Unrecoverable interrupt controller deadlock,INTERRUPT_CTRL Unrecoverable interrupt controller deadlock,1
INFO,DDR_CTRL,DDR memory status good,DDR_CTRL DDR memory status good,1
ERROR,AXI_CTRL,AXI master arbitration failure,AXI_CTRL AXI master arbitration failure,2
CRITICAL,DMA_ENGINE,"DMA engine internal bus deadlocked, requiring reset","DMA_ENGINE DMA engine internal bus deadlocked, requiring reset",3
WARNING,DMA_ENGINE,DMA descriptor fetch latency high.,DMA_ENGINE DMA descriptor fetch latency high.,3
ERROR,INTERRUPT_CTRL,Interrupt vector mismatch detected,INTERRUPT_CTRL Interrupt vector mismatch detected,1
WARNING,DDR_CTRL,DDR write data corruption on specific banks during high load,DDR_CTRL DDR write data corruption on specific banks during high load,1
WARNING,FIFO_BUF,"FIFO nearly empty, watch for underflow.","FIFO_BUF FIFO nearly empty, watch for underflow.",5
INFO,POWER_CTRL,Power domain J powered on successfully,POWER_CTRL Power domain J powered on successfully,4
WARNING,PCIE_CTRL,"Received TLP with bad CRC detected, replayed","PCIE_CTRL Received TLP with bad CRC detected, replayed",6
WARNING,CACHE_CTRL,Cache line eviction count exceeding average,CACHE_CTRL Cache line eviction count exceeding average,1
INFO,INTERRUPT_CTRL,Interrupt vector 0x20 acknowledged.,INTERRUPT_CTRL Interrupt vector 0x20 acknowledged.,1
CRITICAL,DMA_ENGINE,"DMA engine command queue deadlock, no further commands accepted","DMA_ENGINE DMA engine command queue deadlock, no further commands accepted",3
ERROR,PCIE_CTRL,PCIe flow control credit starvation detected,PCIE_CTRL PCIe flow control credit starvation detected,6
ERROR,CACHE_CTRL,L2 cache ways associativity violation detected during lookup.,CACHE_CTRL L2 cache ways associativity violation detected during lookup.,-1
CRITICAL,PCIE_CTRL,"PCIe Link protocol error, unrecoverable","PCIE_CTRL PCIe Link protocol error, unrecoverable",6
CRITICAL,DMA_ENGINE,DMA channel 9 burst data transfer halted indefinitely,DMA_ENGINE DMA channel 9 burst data transfer halted indefinitely,3
ERROR,PCIE_CTRL,PCIe Flow Control credit underflow detected,PCIE_CTRL PCIe Flow Control credit underflow detected,6
ERROR,INTERRUPT_CTRL,"Interrupt vector mismatch, unexpected IRQ source","INTERRUPT_CTRL Interrupt vector mismatch, unexpected IRQ source",1
ERROR,MEM_CTRL,Data bus parity error,MEM_CTRL Data bus parity error,1
INFO,FIFO_BUF,"Flush completed, FIFO is now empty.","FIFO_BUF Flush completed, FIFO is now empty.",5
CRITICAL,MEM_CTRL,Memory controller configuration register corruption,MEM_CTRL Memory controller configuration register corruption,1
INFO,POWER_CTRL,Voltage regulator output stable at nominal,POWER_CTRL Voltage regulator output stable at nominal,4
ERROR,FIFO_BUF,FIFO underflow due to premature read,FIFO_BUF FIFO underflow due to premature read,5
INFO,CLOCK_MANAGER,Clock frequency configuration applied to peripheral domain,CLOCK_MANAGER Clock frequency configuration applied to peripheral domain,0
INFO,CACHE_CTRL,Cache miss for instruction fetch at 0x12345678,CACHE_CTRL Cache miss for instruction fetch at 0x12345678,1
CRITICAL,CLOCK_MANAGER,"Global clock halt detected, system shutdown","CLOCK_MANAGER Global clock halt detected, system shutdown",0
WARNING,CACHE_CTRL,Cache line writeback delay,CACHE_CTRL Cache line writeback delay,1
WARNING,AXI_CTRL,AXI ID tag collision detected,AXI_CTRL AXI ID tag collision detected,2
INFO,POWER_CTRL,Power domain VDD_CPU transitioned to low power state.,POWER_CTRL Power domain VDD_CPU transitioned to low power state.,4
INFO,FIFO_BUF,FIFO data written successfully,FIFO_BUF FIFO data written successfully,5
ERROR,MEM_CTRL,Data bus contention detected during write,MEM_CTRL Data bus contention detected during write,1
INFO,PCIE_CTRL,PCIe enumeration complete,PCIE_CTRL PCIe enumeration complete,6
INFO,MEM_CTRL,Memory controller entered active state,MEM_CTRL Memory controller entered active state,1
INFO,POWER_CTRL,Power-on reset sequence initiated,POWER_CTRL Power-on reset sequence initiated,4
INFO,AXI_CTRL,AXI transaction successfully completed on slave interface,AXI_CTRL AXI transaction successfully completed on slave interface,2
ERROR,PCIE_CTRL,PCIe completion with unsupported completer ID,PCIE_CTRL PCIe completion with unsupported completer ID,6
CRITICAL,DDR_CTRL,DDR memory PHY PLL loss of lock,DDR_CTRL DDR memory PHY PLL loss of lock,1
INFO,POWER_CTRL,Power domain reset asserted,POWER_CTRL Power domain reset asserted,4
WARNING,INTERRUPT_CTRL,"Spurious interrupt detected, no known source","INTERRUPT_CTRL Spurious interrupt detected, no known source",1
INFO,CACHE_CTRL,Cache line evicted successfully,CACHE_CTRL Cache line evicted successfully,1
WARNING,DMA_ENGINE,DMA read channel backpressure asserted for extended duration,DMA_ENGINE DMA read channel backpressure asserted for extended duration,-1
WARNING,DMA_ENGINE,DMA channel 10 busy wait timeout,DMA_ENGINE DMA channel 10 busy wait timeout,3
INFO,CLOCK_MANAGER,Clock multiplexer switched to primary source,CLOCK_MANAGER Clock multiplexer switched to primary source,0
WARNING,AXI_CTRL,AXI outstanding transactions reaching critical limit,AXI_CTRL AXI outstanding transactions reaching critical limit,2
WARNING,DDR_CTRL,DDR memory access latency exceeding 200 cycles,DDR_CTRL DDR memory access latency exceeding 200 cycles,1
ERROR,AXI_CTRL,Slave response error (SLVERR) received,AXI_CTRL Slave response error (SLVERR) received,2
CRITICAL,MEM_CTRL,ECC parity mismatch detected,MEM_CTRL ECC parity mismatch detected,1
INFO,DMA_ENGINE,DMA transfer completed without AXI errors,DMA_ENGINE DMA transfer completed without AXI errors,3
WARNING,MEM_CTRL,Memory refresh interval approaching maximum allowed,MEM_CTRL Memory refresh interval approaching maximum allowed,1
CRITICAL,POWER_CTRL,"Power rail instability detected on critical core voltage rail (VCC_CORE), shutdown initiated.","POWER_CTRL Power rail instability detected on critical core voltage rail (VCC_CORE), shutdown initiated.",4
WARNING,POWER_CTRL,"Power cycle event detected, system recovering","POWER_CTRL Power cycle event detected, system recovering",4
INFO,MEM_CTRL,Memory block X initialized to zero,MEM_CTRL Memory block X initialized to zero,1
WARNING,FIFO_BUF,FIFO occupancy graph showing unexpected spikes,FIFO_BUF FIFO occupancy graph showing unexpected spikes,-1
INFO,DMA_ENGINE,DMA channel 0 configuration updated,DMA_ENGINE DMA channel 0 configuration updated,3
ERROR,POWER_CTRL,Power-gating isolation logic failed to engage,POWER_CTRL Power-gating isolation logic failed to engage,4
INFO,AXI_CTRL,AXI slave interface 0 connected,AXI_CTRL AXI slave interface 0 connected,2
CRITICAL,CACHE_CTRL,Cache data corruption leading to system instability,CACHE_CTRL Cache data corruption leading to system instability,1
INFO,DDR_CTRL,DDR self-refresh entered successfully,DDR_CTRL DDR self-refresh entered successfully,1
WARNING,POWER_CTRL,Temperature sensor reading high on PMIC,POWER_CTRL Temperature sensor reading high on PMIC,4
INFO,FIFO_BUF,"FIFO reset successful, pointers re-initialized","FIFO_BUF FIFO reset successful, pointers re-initialized",5
WARNING,PCIE_CTRL,PCIe flow control credits low for Tx buffer,PCIE_CTRL PCIe flow control credits low for Tx buffer,6
ERROR,MEM_CTRL,Memory access permission denied,MEM_CTRL Memory access permission denied,1
ERROR,POWER_CTRL,Power gating cell stuck-at-on,POWER_CTRL Power gating cell stuck-at-on,-1
INFO,POWER_CTRL,Voltage regulator output within specification,POWER_CTRL Voltage regulator output within specification,4
INFO,POWER_CTRL,Voltage regulator enabled for 1.6V rail.,POWER_CTRL Voltage regulator enabled for 1.6V rail.,4
WARNING,MEM_CTRL,Memory access contention detected between CPU and DMA,MEM_CTRL Memory access contention detected between CPU and DMA,1
CRITICAL,CLOCK_MANAGER,"Primary clock source failed, unable to recover","CLOCK_MANAGER Primary clock source failed, unable to recover",0
ERROR,MEM_CTRL,Write protection violation on memory page 0x10E659,MEM_CTRL Write protection violation on memory page 0x10E659,1
CRITICAL,AXI_CTRL,AXI interconnect asserted an unrecoverable error (SLVERR) to master,AXI_CTRL AXI interconnect asserted an unrecoverable error (SLVERR) to master,2
ERROR,INTERRUPT_CTRL,Interrupt source not registered with controller,INTERRUPT_CTRL Interrupt source not registered with controller,1
WARNING,FIFO_BUF,FIFO_STATUS_CHANNEL output rate significantly lower than input rate.,FIFO_BUF FIFO_STATUS_CHANNEL output rate significantly lower than input rate.,5
INFO,CACHE_CTRL,CACHE_CTRL resource allocation successful.,CACHE_CTRL CACHE_CTRL resource allocation successful.,1
WARNING,DMA_ENGINE,DMA channel descriptor completion timeout,DMA_ENGINE DMA channel descriptor completion timeout,3
ERROR,MEM_CTRL,Memory refresh timer failed to reset,MEM_CTRL Memory refresh timer failed to reset,1
ERROR,DDR_CTRL,DDR command channel parity error,DDR_CTRL DDR command channel parity error,1
INFO,POWER_CTRL,System power-on reset sequence initiated.,POWER_CTRL System power-on reset sequence initiated.,4
WARNING,AXI_CTRL,AXI slave 2 response latency increasing,AXI_CTRL AXI slave 2 response latency increasing,2
ERROR,INTERRUPT_CTRL,Invalid interrupt source ID,INTERRUPT_CTRL Invalid interrupt source ID,1
WARNING,DDR_CTRL,"DDR refresh cycle delayed, approaching critical window.","DDR_CTRL DDR refresh cycle delayed, approaching critical window.",1
CRITICAL,MEM_CTRL,Uncorrectable ECC error detected during memory scrub,MEM_CTRL Uncorrectable ECC error detected during memory scrub,1
WARNING,DDR_CTRL,DDR refresh cycle delayed due to high traffic,DDR_CTRL DDR refresh cycle delayed due to high traffic,1
ERROR,CACHE_CTRL,Invalidation request timeout,CACHE_CTRL Invalidation request timeout,1
ERROR,MEM_CTRL,Memory controller detected an invalid write mask,MEM_CTRL Memory controller detected an invalid write mask,1
ERROR,DMA_ENGINE,DMA transaction ID collision detected,DMA_ENGINE DMA transaction ID collision detected,-1
INFO,FIFO_BUF,FIFO_BUF_2 depth utilization at 75%,FIFO_BUF FIFO_BUF_2 depth utilization at 75%,5
INFO,DDR_CTRL,DDR write latency calibration complete,DDR_CTRL DDR write latency calibration complete,1
INFO,CACHE_CTRL,Cache way partitioning configured,CACHE_CTRL Cache way partitioning configured,-1
ERROR,INTERRUPT_CTRL,Non-maskable interrupt (NMI) re-trigger detected,INTERRUPT_CTRL Non-maskable interrupt (NMI) re-trigger detected,1
CRITICAL,MEM_CTRL,Memory read data returned with wrong address tag,MEM_CTRL Memory read data returned with wrong address tag,1
WARNING,DMA_ENGINE,"DMA channel 6 stalled, waiting for bus access.","DMA_ENGINE DMA channel 6 stalled, waiting for bus access.",3
WARNING,MEM_CTRL,Single-bit ECC correction occurred at address 0x9062F,MEM_CTRL Single-bit ECC correction occurred at address 0x9062F,1
WARNING,INTERRUPT_CTRL,Interrupt controller's internal queue growing,INTERRUPT_CTRL Interrupt controller's internal queue growing,1
ERROR,MEM_CTRL,Memory controller state machine entered invalid state,MEM_CTRL Memory controller state machine entered invalid state,1
CRITICAL,CLOCK_MANAGER,Fatal clock domain crossing failure in clock distribution network.,CLOCK_MANAGER Fatal clock domain crossing failure in clock distribution network.,0
INFO,CLOCK_MANAGER,Clock stability check passed,CLOCK_MANAGER Clock stability check passed,0
INFO,POWER_CTRL,Low power mode entry initiated,POWER_CTRL Low power mode entry initiated,4
INFO,FIFO_BUF,FIFO 'STATUS' read successful,FIFO_BUF FIFO 'STATUS' read successful,5
WARNING,FIFO_BUF,FIFO depth nearing 80% capacity,FIFO_BUF FIFO depth nearing 80% capacity,5
ERROR,MEM_CTRL,Memory address alignment fault at 0x9815031b.,MEM_CTRL Memory address alignment fault at 0x9815031b.,1
INFO,DMA_ENGINE,DMA transfer for peripheral ID 7 initiated.,DMA_ENGINE DMA transfer for peripheral ID 7 initiated.,3
CRITICAL,POWER_CTRL,Main power rail instability causing brown-out,POWER_CTRL Main power rail instability causing brown-out,4
ERROR,DDR_CTRL,DDR read data CRC mismatch,DDR_CTRL DDR read data CRC mismatch,1
WARNING,INTERRUPT_CTRL,Interrupt handler response time warning,INTERRUPT_CTRL Interrupt handler response time warning,-1
ERROR,CLOCK_MANAGER,Clock source output frequency instability detected,CLOCK_MANAGER Clock source output frequency instability detected,0
ERROR,AXI_CTRL,AXI write address channel timing violation,AXI_CTRL AXI write address channel timing violation,2
WARNING,CACHE_CTRL,Cache eviction queue nearing full capacity,CACHE_CTRL Cache eviction queue nearing full capacity,1
INFO,CLOCK_MANAGER,System clock frequency changed to Y MHz.,CLOCK_MANAGER System clock frequency changed to Y MHz.,0
ERROR,INTERRUPT_CTRL,Spurious interrupt detected from unmasked source,INTERRUPT_CTRL Spurious interrupt detected from unmasked source,1
INFO,INTERRUPT_CTRL,Interrupt line 3 de-asserted,INTERRUPT_CTRL Interrupt line 3 de-asserted,1
INFO,POWER_CTRL,Core voltage rail stable at 1.0V.,POWER_CTRL Core voltage rail stable at 1.0V.,4
WARNING,INTERRUPT_CTRL,"Spurious interrupt detected (minor, self-clearing)","INTERRUPT_CTRL Spurious interrupt detected (minor, self-clearing)",1
INFO,INTERRUPT_CTRL,Interrupt 5 (Timer) dispatched successfully,INTERRUPT_CTRL Interrupt 5 (Timer) dispatched successfully,1
WARNING,PCIE_CTRL,PCIe link state transition to Recovery for too long,PCIE_CTRL PCIe link state transition to Recovery for too long,6
INFO,POWER_CTRL,Power domain transition from D1 to D0,POWER_CTRL Power domain transition from D1 to D0,4
INFO,CACHE_CTRL,Cache MSHR entry allocated,CACHE_CTRL Cache MSHR entry allocated,-1
INFO,FIFO_BUF,FIFO_COMMAND_PIPE empty.,FIFO_BUF FIFO_COMMAND_PIPE empty.,5
CRITICAL,AXI_CTRL,AXI transaction issued by master 2 violated access permissions,AXI_CTRL AXI transaction issued by master 2 violated access permissions,2
INFO,CLOCK_MANAGER,Power-on Reset (POR) sequence completed,CLOCK_MANAGER Power-on Reset (POR) sequence completed,0
INFO,INTERRUPT_CTRL,All interrupt lines cleared,INTERRUPT_CTRL All interrupt lines cleared,1
CRITICAL,POWER_CTRL,Power-up sequence abort due to voltage fault,POWER_CTRL Power-up sequence abort due to voltage fault,4
WARNING,CACHE_CTRL,Cache miss rate exceeding expected operational threshold.,CACHE_CTRL Cache miss rate exceeding expected operational threshold.,1
WARNING,POWER_CTRL,Voltage rail 2.5V out of tolerance,POWER_CTRL Voltage rail 2.5V out of tolerance,4
INFO,DMA_ENGINE,DMA channel 0 idle,DMA_ENGINE DMA channel 0 idle,3
CRITICAL,DMA_ENGINE,"DMA arbiter deadlock, multiple channels locked out","DMA_ENGINE DMA arbiter deadlock, multiple channels locked out",3
ERROR,FIFO_BUF,FIFO_STATUS_PIPE write pointer corrupted.,FIFO_BUF FIFO_STATUS_PIPE write pointer corrupted.,5
WARNING,FIFO_BUF,FIFO read data rate inconsistent,FIFO_BUF FIFO read data rate inconsistent,5
WARNING,FIFO_BUF,"FIFO write pointer nearing read pointer, potential overwrite","FIFO_BUF FIFO write pointer nearing read pointer, potential overwrite",5
INFO,POWER_CTRL,Power domain VDD_NETWORK fully enabled.,POWER_CTRL Power domain VDD_NETWORK fully enabled.,-1
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL status query successful.,INTERRUPT_CTRL INTERRUPT_CTRL status query successful.,-1
ERROR,PCIE_CTRL,PCIe Root Complex hot-reset sequence failed,PCIE_CTRL PCIe Root Complex hot-reset sequence failed,6
CRITICAL,POWER_CTRL,"System watchdog timer expired, forcing reset","POWER_CTRL System watchdog timer expired, forcing reset",-1
WARNING,DDR_CTRL,DDR memory bus utilization at 95%,DDR_CTRL DDR memory bus utilization at 95%,1
CRITICAL,POWER_CTRL,Emergency shutdown initiated due to overcurrent event on CPU rail.,POWER_CTRL Emergency shutdown initiated due to overcurrent event on CPU rail.,4
ERROR,DDR_CTRL,DDR write timing violation on DQS to DQ,DDR_CTRL DDR write timing violation on DQS to DQ,-1
ERROR,PCIE_CTRL,PCIe data link layer state machine entered error state,PCIE_CTRL PCIe data link layer state machine entered error state,6
CRITICAL,CLOCK_MANAGER,PLL lock detection circuit failed,CLOCK_MANAGER PLL lock detection circuit failed,0
INFO,MEM_CTRL,MEM_CTRL self-test passed.,MEM_CTRL MEM_CTRL self-test passed.,1
INFO,CLOCK_MANAGER,Clock domain crossing FIFO operating within parameters,CLOCK_MANAGER Clock domain crossing FIFO operating within parameters,0
INFO,DDR_CTRL,Memory read transaction initiated,DDR_CTRL Memory read transaction initiated,1
INFO,POWER_CTRL,System voltage monitor active,POWER_CTRL System voltage monitor active,4
INFO,AXI_CTRL,AXI outstanding transaction count returned to normal.,AXI_CTRL AXI outstanding transaction count returned to normal.,2
WARNING,FIFO_BUF,FIFO data output not valid for full cycle,FIFO_BUF FIFO data output not valid for full cycle,5
WARNING,FIFO_BUF,FIFO almost full condition asserted.,FIFO_BUF FIFO almost full condition asserted.,5
WARNING,DMA_ENGINE,DMA engine internal FIFO nearing capacity.,DMA_ENGINE DMA engine internal FIFO nearing capacity.,3
WARNING,INTERRUPT_CTRL,Software interrupt queue backlog building up,INTERRUPT_CTRL Software interrupt queue backlog building up,1
INFO,PCIE_CTRL,PCIe Gen4 link training completed successfully.,PCIE_CTRL PCIe Gen4 link training completed successfully.,6
INFO,DDR_CTRL,DDR memory refresh cycle initiated,DDR_CTRL DDR memory refresh cycle initiated,1
ERROR,AXI_CTRL,AXI read address alignment violation detected,AXI_CTRL AXI read address alignment violation detected,2
INFO,INTERRUPT_CTRL,Interrupt priority level updated for IRQ_UART,INTERRUPT_CTRL Interrupt priority level updated for IRQ_UART,1
INFO,INTERRUPT_CTRL,Interrupt line asserted,INTERRUPT_CTRL Interrupt line asserted,1
ERROR,PCIE_CTRL,PCIe transaction layer packet (TLP) poisoning detected,PCIE_CTRL PCIe transaction layer packet (TLP) poisoning detected,6
WARNING,CACHE_CTRL,Cache tag RAM access latency increased,CACHE_CTRL Cache tag RAM access latency increased,1
ERROR,POWER_CTRL,Voltage rail current limit exceeded,POWER_CTRL Voltage rail current limit exceeded,4
INFO,CLOCK_MANAGER,Gating signal applied to secondary clock,CLOCK_MANAGER Gating signal applied to secondary clock,0
CRITICAL,CACHE_CTRL,"CRITICAL: Persistent cache data integrity error at 0xDEADBEEF, cache disabled.","CACHE_CTRL CRITICAL: Persistent cache data integrity error at 0xDEADBEEF, cache disabled.",1
INFO,INTERRUPT_CTRL,Interrupt acknowledged: Timer_0,INTERRUPT_CTRL Interrupt acknowledged: Timer_0,1
CRITICAL,CLOCK_MANAGER,Clock domain crossing integrity violation on high-speed path,CLOCK_MANAGER Clock domain crossing integrity violation on high-speed path,0
INFO,CACHE_CTRL,L2 cache prefetcher engaged successfully,CACHE_CTRL L2 cache prefetcher engaged successfully,1
WARNING,CLOCK_MANAGER,PLL re-lock procedure in progress,CLOCK_MANAGER PLL re-lock procedure in progress,0
ERROR,POWER_CTRL,Voltage regulator response timeout during load step,POWER_CTRL Voltage regulator response timeout during load step,4
ERROR,INTERRUPT_CTRL,"Interrupt handler address invalid, timing violation.","INTERRUPT_CTRL Interrupt handler address invalid, timing violation.",1
WARNING,DDR_CTRL,DDR write data buffer nearing full,DDR_CTRL DDR write data buffer nearing full,1
INFO,MEM_CTRL,Memory bank 3 entered self-refresh mode,MEM_CTRL Memory bank 3 entered self-refresh mode,1
WARNING,INTERRUPT_CTRL,Interrupt request rate exceeding maximum handling capacity,INTERRUPT_CTRL Interrupt request rate exceeding maximum handling capacity,1
INFO,POWER_CTRL,Regulator R_MEM_VDD enabled,POWER_CTRL Regulator R_MEM_VDD enabled,-1
ERROR,POWER_CTRL,Power gate isolation cell leakage current exceeding limits.,POWER_CTRL Power gate isolation cell leakage current exceeding limits.,-1
WARNING,CLOCK_MANAGER,Secondary clock source input frequency deviation,CLOCK_MANAGER Secondary clock source input frequency deviation,0
CRITICAL,PCIE_CTRL,"PCIe link down, unrecoverable error","PCIE_CTRL PCIe link down, unrecoverable error",6
ERROR,CLOCK_MANAGER,Clock domain crossing write buffer overflow,CLOCK_MANAGER Clock domain crossing write buffer overflow,0
ERROR,FIFO_BUF,FIFO read pointer advancing incorrectly,FIFO_BUF FIFO read pointer advancing incorrectly,5
INFO,MEM_CTRL,Memory controller initialized,MEM_CTRL Memory controller initialized,1
WARNING,MEM_CTRL,Memory read latency spikes observed,MEM_CTRL Memory read latency spikes observed,1
ERROR,AXI_CTRL,AXI read data bus observed to be floating,AXI_CTRL AXI read data bus observed to be floating,2
INFO,MEM_CTRL,"Memory write protection violation, denied access","MEM_CTRL Memory write protection violation, denied access",1
ERROR,FIFO_BUF,FIFO data integrity check failed on committed entry,FIFO_BUF FIFO data integrity check failed on committed entry,5
ERROR,CACHE_CTRL,Cache way allocation conflict.,CACHE_CTRL Cache way allocation conflict.,1
ERROR,PCIE_CTRL,PCIe completion timeout on request ID 0x12,PCIE_CTRL PCIe completion timeout on request ID 0x12,6
INFO,INTERRUPT_CTRL,Interrupt mask register updated,INTERRUPT_CTRL Interrupt mask register updated,1
WARNING,AXI_CTRL,AXI write data channel backpressure detected,AXI_CTRL AXI write data channel backpressure detected,2
WARNING,DDR_CTRL,DDR Read Leveling training warning,DDR_CTRL DDR Read Leveling training warning,1
CRITICAL,POWER_CTRL,Power sequence failure during boot,POWER_CTRL Power sequence failure during boot,4
ERROR,INTERRUPT_CTRL,Interrupt pending register corruption,INTERRUPT_CTRL Interrupt pending register corruption,1
WARNING,DMA_ENGINE,DMA channel 1 request queue backlog,DMA_ENGINE DMA channel 1 request queue backlog,3
ERROR,DMA_ENGINE,DMA channel descriptor queue overflow,DMA_ENGINE DMA channel descriptor queue overflow,3
CRITICAL,MEM_CTRL,Double-bit ECC error detected in critical memory region,MEM_CTRL Double-bit ECC error detected in critical memory region,1
WARNING,DMA_ENGINE,DMA controller pending requests exceeding optimal queue size,DMA_ENGINE DMA controller pending requests exceeding optimal queue size,3
ERROR,PCIE_CTRL,PCIe replay timer expired multiple times,PCIE_CTRL PCIe replay timer expired multiple times,-1
INFO,DMA_ENGINE,DMA burst transfer to peripheral initiated,DMA_ENGINE DMA burst transfer to peripheral initiated,3
WARNING,DDR_CTRL,DDR memory training sequence taking longer than expected,DDR_CTRL DDR memory training sequence taking longer than expected,1
CRITICAL,POWER_CTRL,Entire chip power loss detected,POWER_CTRL Entire chip power loss detected,4
WARNING,AXI_CTRL,AXI outstanding read transaction count reaching limit,AXI_CTRL AXI outstanding read transaction count reaching limit,2
ERROR,CACHE_CTRL,"Cache write-back failure, data loss risk","CACHE_CTRL Cache write-back failure, data loss risk",1
CRITICAL,AXI_CTRL,AXI bus arbitration priority inversion leading to system halt.,AXI_CTRL AXI bus arbitration priority inversion leading to system halt.,2
WARNING,CLOCK_MANAGER,Clock skew between CLK_A and CLK_B widening,CLOCK_MANAGER Clock skew between CLK_A and CLK_B widening,-1
CRITICAL,POWER_CTRL,Power-on sequence voltage ramp instability,POWER_CTRL Power-on sequence voltage ramp instability,4
WARNING,MEM_CTRL,Memory refresh interval approaching limit (110 cycles remaining).,MEM_CTRL Memory refresh interval approaching limit (110 cycles remaining).,1
INFO,INTERRUPT_CTRL,Interrupt coalescing enabled,INTERRUPT_CTRL Interrupt coalescing enabled,1
WARNING,PCIE_CTRL,PCIe error reporting log nearing capacity,PCIE_CTRL PCIe error reporting log nearing capacity,6
CRITICAL,MEM_CTRL,"Memory device 0 unresponsive, data path permanently broken","MEM_CTRL Memory device 0 unresponsive, data path permanently broken",1
INFO,CLOCK_MANAGER,System clock output enabled,CLOCK_MANAGER System clock output enabled,0
WARNING,INTERRUPT_CTRL,Interrupt source flooding detected,INTERRUPT_CTRL Interrupt source flooding detected,1
INFO,DDR_CTRL,DDR read command issued.,DDR_CTRL DDR read command issued.,1
CRITICAL,AXI_CTRL,AXI write-after-read hazard detected due to incorrect ordering.,AXI_CTRL AXI write-after-read hazard detected due to incorrect ordering.,-1
CRITICAL,FIFO_BUF,FIFO logic corruption detected,FIFO_BUF FIFO logic corruption detected,5
INFO,CACHE_CTRL,Cache enabled and operational.,CACHE_CTRL Cache enabled and operational.,1
CRITICAL,PCIE_CTRL,PCIe link retraining failed multiple times,PCIE_CTRL PCIe link retraining failed multiple times,6
ERROR,PCIE_CTRL,PCIe internal state machine entered invalid state,PCIE_CTRL PCIe internal state machine entered invalid state,6
ERROR,DMA_ENGINE,DMA_ENGINE: protocol mismatch - unrecognized command detected.,DMA_ENGINE DMA_ENGINE: protocol mismatch - unrecognized command detected.,3
WARNING,POWER_CTRL,Power rail sequencing anomaly during shutdown,POWER_CTRL Power rail sequencing anomaly during shutdown,4
WARNING,INTERRUPT_CTRL,Interrupt controller internal buffer nearing capacity,INTERRUPT_CTRL Interrupt controller internal buffer nearing capacity,1
INFO,PCIE_CTRL,PCIe Gen4 link speed negotiated to x8,PCIE_CTRL PCIe Gen4 link speed negotiated to x8,6
ERROR,FIFO_BUF,FIFO read enable asserted on empty FIFO,FIFO_BUF FIFO read enable asserted on empty FIFO,5
WARNING,DDR_CTRL,DDR write data integrity check detected minor discrepancy.,DDR_CTRL DDR write data integrity check detected minor discrepancy.,1
WARNING,AXI_CTRL,AXI ID tags nearing maximum allocation,AXI_CTRL AXI ID tags nearing maximum allocation,2
WARNING,PCIE_CTRL,PCIe lane re-training initiated due to marginal signal integrity,PCIE_CTRL PCIe lane re-training initiated due to marginal signal integrity,6
INFO,DMA_ENGINE,DMA channel 19 transfer status: pending,DMA_ENGINE DMA channel 19 transfer status: pending,3
INFO,PCIE_CTRL,PCIe link training status: L0,PCIE_CTRL PCIe link training status: L0,6
WARNING,PCIE_CTRL,PCIe replay buffer approaching full capacity,PCIE_CTRL PCIe replay buffer approaching full capacity,6
WARNING,FIFO_BUF,"FIFO almost full, high pressure detected","FIFO_BUF FIFO almost full, high pressure detected",5
INFO,AXI_CTRL,AXI write response received and processed,AXI_CTRL AXI write response received and processed,2
ERROR,CLOCK_MANAGER,Clock synchronizer timeout,CLOCK_MANAGER Clock synchronizer timeout,0
WARNING,AXI_CTRL,AXI bus arbitration unfairness detected,AXI_CTRL AXI bus arbitration unfairness detected,2
ERROR,DDR_CTRL,DDR memory controller state machine entered an invalid state.,DDR_CTRL DDR memory controller state machine entered an invalid state.,1
INFO,DMA_ENGINE,Scatter-gather DMA transfer concluded.,DMA_ENGINE Scatter-gather DMA transfer concluded.,3
CRITICAL,DMA_ENGINE,"DMA descriptor queue pointer corruption, irrecoverable","DMA_ENGINE DMA descriptor queue pointer corruption, irrecoverable",3
ERROR,MEM_CTRL,Memory command bus contention detected,MEM_CTRL Memory command bus contention detected,1
ERROR,DDR_CTRL,DDR read data integrity error,DDR_CTRL DDR read data integrity error,1
ERROR,MEM_CTRL,Memory BIST (Built-In Self-Test) failed,MEM_CTRL Memory BIST (Built-In Self-Test) failed,1
INFO,AXI_CTRL,AXI slave 3 acknowledged write transaction,AXI_CTRL AXI slave 3 acknowledged write transaction,2
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL module initialized.,INTERRUPT_CTRL INTERRUPT_CTRL module initialized.,1
INFO,CLOCK_MANAGER,Frequency scaled up,CLOCK_MANAGER Frequency scaled up,0
INFO,DMA_ENGINE,DMA channel transfer paused,DMA_ENGINE DMA channel transfer paused,3
WARNING,CLOCK_MANAGER,Jitter detected on output clock,CLOCK_MANAGER Jitter detected on output clock,0
ERROR,INTERRUPT_CTRL,Interrupt controller spurious interrupt detected,INTERRUPT_CTRL Interrupt controller spurious interrupt detected,1
WARNING,FIFO_BUF,Write latency on FIFO_RX_0 exceeding limits,FIFO_BUF Write latency on FIFO_RX_0 exceeding limits,5
ERROR,CLOCK_MANAGER,"Clock domain crossing FIFO overflow detected, CDC failure.","CLOCK_MANAGER Clock domain crossing FIFO overflow detected, CDC failure.",0
CRITICAL,DDR_CTRL,DDR memory controller entered an invalid power state,DDR_CTRL DDR memory controller entered an invalid power state,1
ERROR,DMA_ENGINE,DMA destination address generated an AXI SLVERR,DMA_ENGINE DMA destination address generated an AXI SLVERR,3
ERROR,CACHE_CTRL,Cache tag RAM single bit error corrected via ECC,CACHE_CTRL Cache tag RAM single bit error corrected via ECC,1
CRITICAL,AXI_CTRL,AXI bus arbiter entered invalid state,AXI_CTRL AXI bus arbiter entered invalid state,2
ERROR,DDR_CTRL,DDR command timing violation detected (TRCD). (timing violation),DDR_CTRL DDR command timing violation detected (TRCD). (timing violation),1
INFO,CLOCK_MANAGER,System clock source switched from internal to external oscillator,CLOCK_MANAGER System clock source switched from internal to external oscillator,0
INFO,MEM_CTRL,Write buffer flushed,MEM_CTRL Write buffer flushed,1
WARNING,POWER_CTRL,System thermal throttling active,POWER_CTRL System thermal throttling active,-1
INFO,POWER_CTRL,Power domain 'GFX' enabled.,POWER_CTRL Power domain 'GFX' enabled.,4
ERROR,PCIE_CTRL,PCIe TLP (Transaction Layer Packet) framing error detected,PCIE_CTRL PCIe TLP (Transaction Layer Packet) framing error detected,6
CRITICAL,AXI_CTRL,Fatal AXI agent response,AXI_CTRL Fatal AXI agent response,2
INFO,PCIE_CTRL,PCIe configuration read successful,PCIE_CTRL PCIe configuration read successful,6
ERROR,DDR_CTRL,"DDR write data mask error, parity error.","DDR_CTRL DDR write data mask error, parity error.",1
ERROR,CLOCK_MANAGER,"PLL configuration error detected, output frequency incorrect for Main_PLL","CLOCK_MANAGER PLL configuration error detected, output frequency incorrect for Main_PLL",0
ERROR,PCIE_CTRL,PCIe packet framing error detected on Rx,PCIE_CTRL PCIe packet framing error detected on Rx,6
CRITICAL,DDR_CTRL,"DDR uncorrectable ECC error detected, data loss.","DDR_CTRL DDR uncorrectable ECC error detected, data loss.",1
WARNING,DDR_CTRL,DDR refresh cycle delayed.,DDR_CTRL DDR refresh cycle delayed.,1
WARNING,AXI_CTRL,AXI outstanding read transaction count reaching limit for master ID 0x0A.,AXI_CTRL AXI outstanding read transaction count reaching limit for master ID 0x0A.,2
INFO,INTERRUPT_CTRL,Interrupt controller debug mode entered,INTERRUPT_CTRL Interrupt controller debug mode entered,1
WARNING,FIFO_BUF,"FIFO high water mark reached, but not full","FIFO_BUF FIFO high water mark reached, but not full",5
ERROR,MEM_CTRL,Memory data bus tristate violation,MEM_CTRL Memory data bus tristate violation,1
WARNING,AXI_CTRL,AXI burst type violation detected by interconnect,AXI_CTRL AXI burst type violation detected by interconnect,2
WARNING,PCIE_CTRL,"PCIe flow control credits low, potential backpressure","PCIE_CTRL PCIe flow control credits low, potential backpressure",6
ERROR,DMA_ENGINE,DMA destination address generated an address alignment fault.,DMA_ENGINE DMA destination address generated an address alignment fault.,3
CRITICAL,CLOCK_MANAGER,"PLL frequency deviation beyond tolerance, system unstable","CLOCK_MANAGER PLL frequency deviation beyond tolerance, system unstable",0
INFO,DDR_CTRL,Memory bank 0 activated for access.,DDR_CTRL Memory bank 0 activated for access.,1
CRITICAL,PCIE_CTRL,PCIe link entered recovery state and failed to exit,PCIE_CTRL PCIe link entered recovery state and failed to exit,6
ERROR,AXI_CTRL,AXI burst length inconsistent across ARSIZE and RLEN for read,AXI_CTRL AXI burst length inconsistent across ARSIZE and RLEN for read,2
WARNING,FIFO_BUF,FIFO_BUF internal FIFO read pointer approaching write pointer within 3 entries.,FIFO_BUF FIFO_BUF internal FIFO read pointer approaching write pointer within 3 entries.,5
WARNING,CLOCK_MANAGER,Clock frequency deviation detected,CLOCK_MANAGER Clock frequency deviation detected,0
ERROR,POWER_CTRL,Voltage regulator response timeout detected.,POWER_CTRL Voltage regulator response timeout detected.,4
WARNING,MEM_CTRL,ECC scrub cycle initiated,MEM_CTRL ECC scrub cycle initiated,1
INFO,INTERRUPT_CTRL,Interrupt 14 successfully acknowledged and cleared,INTERRUPT_CTRL Interrupt 14 successfully acknowledged and cleared,1
CRITICAL,MEM_CTRL,Memory controller clock input lost,MEM_CTRL Memory controller clock input lost,-1
CRITICAL,DMA_ENGINE,DMA memory access rights violation detected.,DMA_ENGINE DMA memory access rights violation detected.,3
ERROR,POWER_CTRL,Critical power rail VDD_CORE failed to enable,POWER_CTRL Critical power rail VDD_CORE failed to enable,4
INFO,INTERRUPT_CTRL,Interrupt controller cleared all pending events,INTERRUPT_CTRL Interrupt controller cleared all pending events,1
INFO,DDR_CTRL,DDR memory region marked as non-cacheable,DDR_CTRL DDR memory region marked as non-cacheable,1
ERROR,CACHE_CTRL,TLB entry invalidation failed,CACHE_CTRL TLB entry invalidation failed,1
WARNING,CACHE_CTRL,Cache miss rate exceeding performance threshold,CACHE_CTRL Cache miss rate exceeding performance threshold,1
ERROR,INTERRUPT_CTRL,"Interrupt pending status corruption, timing violation.","INTERRUPT_CTRL Interrupt pending status corruption, timing violation.",1
CRITICAL,AXI_CTRL,Fatal AXI protocol error: unrecoverable state,AXI_CTRL Fatal AXI protocol error: unrecoverable state,2
ERROR,MEM_CTRL,Memory read data mismatch during scrub operation,MEM_CTRL Memory read data mismatch during scrub operation,1
WARNING,CACHE_CTRL,Cache line eviction rate increased significantly,CACHE_CTRL Cache line eviction rate increased significantly,1
CRITICAL,CLOCK_MANAGER,"Critical clock instability, integrity compromised","CLOCK_MANAGER Critical clock instability, integrity compromised",0
ERROR,DDR_CTRL,DDR command bus parity error,DDR_CTRL DDR command bus parity error,1
CRITICAL,PCIE_CTRL,PCIe endpoint not responding to configuration requests,PCIE_CTRL PCIe endpoint not responding to configuration requests,6
INFO,POWER_CTRL,"Power-on sequence completed, all rails nominal","POWER_CTRL Power-on sequence completed, all rails nominal",4
WARNING,CLOCK_MANAGER,Clock domain crossing `async_fifo_status` showed latency fluctuations,CLOCK_MANAGER Clock domain crossing `async_fifo_status` showed latency fluctuations,0
INFO,MEM_CTRL,Memory block X initialized to zero.,MEM_CTRL Memory block X initialized to zero.,1
INFO,AXI_CTRL,AXI read data (RDATA) received,AXI_CTRL AXI read data (RDATA) received,2
WARNING,DMA_ENGINE,DMA transaction ID collision,DMA_ENGINE DMA transaction ID collision,-1
WARNING,INTERRUPT_CTRL,Interrupt nesting depth approaching limit,INTERRUPT_CTRL Interrupt nesting depth approaching limit,1
ERROR,POWER_CTRL,Power sequence controller asserted error state,POWER_CTRL Power sequence controller asserted error state,4
CRITICAL,MEM_CTRL,"Memory data integrity error, multiple bits corrupted","MEM_CTRL Memory data integrity error, multiple bits corrupted",1
WARNING,AXI_CTRL,AXI outstanding transaction count high,AXI_CTRL AXI outstanding transaction count high,2
INFO,DMA_ENGINE,DMA transfer completed successfully on channel 5,DMA_ENGINE DMA transfer completed successfully on channel 5,3
CRITICAL,MEM_CTRL,Unrecoverable memory corruption,MEM_CTRL Unrecoverable memory corruption,1
INFO,AXI_CTRL,Master 2 requested read access to memory,AXI_CTRL Master 2 requested read access to memory,2
WARNING,CACHE_CTRL,Cache write buffer approaching full,CACHE_CTRL Cache write buffer approaching full,1
CRITICAL,CACHE_CTRL,Cache directory corruption,CACHE_CTRL Cache directory corruption,1
CRITICAL,POWER_CTRL,Power supply unit detected critical overcurrent fault,POWER_CTRL Power supply unit detected critical overcurrent fault,-1
WARNING,INTERRUPT_CTRL,Interrupt acknowledge signal delayed.,INTERRUPT_CTRL Interrupt acknowledge signal delayed.,1
WARNING,CLOCK_MANAGER,Clock signal integrity degradation detected,CLOCK_MANAGER Clock signal integrity degradation detected,0
CRITICAL,PCIE_CTRL,PCIe hot-reset failed to re-establish link,PCIE_CTRL PCIe hot-reset failed to re-establish link,6
INFO,MEM_CTRL,Memory read operation successful for address.,MEM_CTRL Memory read operation successful for address.,1
WARNING,POWER_CTRL,Power rail voltage drop detected by supervisor,POWER_CTRL Power rail voltage drop detected by supervisor,4
INFO,PCIE_CTRL,TLP transmitted on lane 6.,PCIE_CTRL TLP transmitted on lane 6.,6
WARNING,CLOCK_MANAGER,Clock distribution network health degraded,CLOCK_MANAGER Clock distribution network health degraded,0
CRITICAL,POWER_CTRL,Voltage regulator thermal shutdown initiated,POWER_CTRL Voltage regulator thermal shutdown initiated,4
ERROR,DDR_CTRL,"DDR write command timeout, memory device unresponsive.","DDR_CTRL DDR write command timeout, memory device unresponsive.",1
ERROR,DDR_CTRL,DDR CAS latency timing violation,DDR_CTRL DDR CAS latency timing violation,1
ERROR,DMA_ENGINE,DMA channel control register write error,DMA_ENGINE DMA channel control register write error,3
ERROR,CLOCK_MANAGER,Clock source switch failure,CLOCK_MANAGER Clock source switch failure,0
CRITICAL,POWER_CTRL,System PMIC reported critical voltage undershoot,POWER_CTRL System PMIC reported critical voltage undershoot,4
CRITICAL,CACHE_CTRL,Cache controller entered an undefined internal state,CACHE_CTRL Cache controller entered an undefined internal state,1
ERROR,CLOCK_MANAGER,Clock gating cell for module 'DMA_ENGINE' stuck open,CLOCK_MANAGER Clock gating cell for module 'DMA_ENGINE' stuck open,-1
ERROR,DMA_ENGINE,DMA channel 1 burst length configuration error,DMA_ENGINE DMA channel 1 burst length configuration error,3
INFO,CLOCK_MANAGER,Clock divider value changed to 2,CLOCK_MANAGER Clock divider value changed to 2,0
WARNING,DDR_CTRL,DDR command re-ordering disabled due to error,DDR_CTRL DDR command re-ordering disabled due to error,1
INFO,DDR_CTRL,DDR calibration fine-tuning completed successfully.,DDR_CTRL DDR calibration fine-tuning completed successfully.,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout detected,INTERRUPT_CTRL Interrupt acknowledge timeout detected,1
CRITICAL,DMA_ENGINE,DMA engine internal deadlock detected on all channels (deadlock detected),DMA_ENGINE DMA engine internal deadlock detected on all channels (deadlock detected),3
INFO,FIFO_BUF,FIFO almost empty flag de-asserted,FIFO_BUF FIFO almost empty flag de-asserted,5
WARNING,POWER_CTRL,Power sequencing step stalled,POWER_CTRL Power sequencing step stalled,4
WARNING,DMA_ENGINE,DMA transfer completion delay observed,DMA_ENGINE DMA transfer completion delay observed,3
CRITICAL,CLOCK_MANAGER,System reset triggered due to critical clock stability issue,CLOCK_MANAGER System reset triggered due to critical clock stability issue,0
WARNING,PCIE_CTRL,PHY layer re-training initiated,PCIE_CTRL PHY layer re-training initiated,6
ERROR,INTERRUPT_CTRL,Interrupt controller vector table base address mismatch,INTERRUPT_CTRL Interrupt controller vector table base address mismatch,1
INFO,PCIE_CTRL,PCIe MSI-X interrupt enabled,PCIE_CTRL PCIe MSI-X interrupt enabled,6
INFO,FIFO_BUF,"Read pointer advanced, data consumed","FIFO_BUF Read pointer advanced, data consumed",5
INFO,CLOCK_MANAGER,New clock period configured to 5ns,CLOCK_MANAGER New clock period configured to 5ns,-1
ERROR,INTERRUPT_CTRL,"Unhandled interrupt source detected, vector 0x24","INTERRUPT_CTRL Unhandled interrupt source detected, vector 0x24",1
WARNING,CACHE_CTRL,Cache fill buffer nearing maximum capacity,CACHE_CTRL Cache fill buffer nearing maximum capacity,1
WARNING,MEM_CTRL,Memory single-bit ECC error detected and corrected,MEM_CTRL Memory single-bit ECC error detected and corrected,1
ERROR,DDR_CTRL,DDR rank 0 failed initialization sequence,DDR_CTRL DDR rank 0 failed initialization sequence,1
WARNING,POWER_CTRL,Voltage sensor calibration out of range,POWER_CTRL Voltage sensor calibration out of range,7
CRITICAL,DDR_CTRL,DDR PHY calibration sequence aborted,DDR_CTRL DDR PHY calibration sequence aborted,1
ERROR,FIFO_BUF,FIFO data integrity check failed on read,FIFO_BUF FIFO data integrity check failed on read,5
ERROR,DDR_CTRL,DDR read data capture timing violation,DDR_CTRL DDR read data capture timing violation,1
WARNING,INTERRUPT_CTRL,Interrupt controller register access contention,INTERRUPT_CTRL Interrupt controller register access contention,1
WARNING,CLOCK_MANAGER,PLL frequency drift detected,CLOCK_MANAGER PLL frequency drift detected,0
WARNING,FIFO_BUF,"FIFO nearly full, capacity at 85% of 1024 entries","FIFO_BUF FIFO nearly full, capacity at 85% of 1024 entries",5
CRITICAL,DDR_CTRL,DRAM device permanently inaccessible,DDR_CTRL DRAM device permanently inaccessible,1
CRITICAL,DMA_ENGINE,"DMA engine attempting access to restricted memory region, system lockdown.","DMA_ENGINE DMA engine attempting access to restricted memory region, system lockdown.",3
ERROR,CLOCK_MANAGER,Clock domain crossing queue underflow,CLOCK_MANAGER Clock domain crossing queue underflow,0
ERROR,MEM_CTRL,Memory data bus parity error detected on read,MEM_CTRL Memory data bus parity error detected on read,1
WARNING,DMA_ENGINE,DMA channel experiencing starvation,DMA_ENGINE DMA channel experiencing starvation,3
ERROR,INTERRUPT_CTRL,Interrupt controller register access timeout,INTERRUPT_CTRL Interrupt controller register access timeout,1
ERROR,DMA_ENGINE,DMA channel 4 internal register corruption.,DMA_ENGINE DMA channel 4 internal register corruption.,3
ERROR,PCIE_CTRL,PCIe link training failure during final phase,PCIE_CTRL PCIe link training failure during final phase,6
ERROR,CLOCK_MANAGER,Clock source jitter exceeding specifications,CLOCK_MANAGER Clock source jitter exceeding specifications,0
WARNING,AXI_CTRL,"AXI write channel backpressure detected, slowing down","AXI_CTRL AXI write channel backpressure detected, slowing down",2
INFO,DMA_ENGINE,"DMA controller idle, awaiting next task","DMA_ENGINE DMA controller idle, awaiting next task",3
ERROR,MEM_CTRL,Memory bus arbitration conflict leading to stalls,MEM_CTRL Memory bus arbitration conflict leading to stalls,1
ERROR,CLOCK_MANAGER,Clock frequency deviation exceeding acceptable limits,CLOCK_MANAGER Clock frequency deviation exceeding acceptable limits,0
ERROR,FIFO_BUF,FIFO read pointer not incrementing,FIFO_BUF FIFO read pointer not incrementing,5
ERROR,MEM_CTRL,Memory double-bit ECC error detected on address 0x1234_5678,MEM_CTRL Memory double-bit ECC error detected on address 0x1234_5678,1
ERROR,MEM_CTRL,Memory bank Y self-refresh timeout,MEM_CTRL Memory bank Y self-refresh timeout,1
INFO,POWER_CTRL,Voltage regulator response time within limits,POWER_CTRL Voltage regulator response time within limits,4
INFO,CACHE_CTRL,Cache debug features enabled,CACHE_CTRL Cache debug features enabled,-1
CRITICAL,PCIE_CTRL,PCIe fatal error detected in Transaction Layer Packet processing.,PCIE_CTRL PCIe fatal error detected in Transaction Layer Packet processing.,6
WARNING,INTERRUPT_CTRL,Interrupt latency for IRQ_TIMER_0 exceeding design target,INTERRUPT_CTRL Interrupt latency for IRQ_TIMER_0 exceeding design target,1
ERROR,INTERRUPT_CTRL,Interrupt enable register corruption detected,INTERRUPT_CTRL Interrupt enable register corruption detected,1
CRITICAL,FIFO_BUF,FIFO_CRITICAL_LOG suffered unrecoverable internal memory corruption.,FIFO_BUF FIFO_CRITICAL_LOG suffered unrecoverable internal memory corruption.,5
INFO,DDR_CTRL,Memory precharge command issued,DDR_CTRL Memory precharge command issued,1
INFO,POWER_CTRL,Power monitor reporting nominal voltage,POWER_CTRL Power monitor reporting nominal voltage,4
WARNING,AXI_CTRL,AXI transaction with invalid protection attributes,AXI_CTRL AXI transaction with invalid protection attributes,2
ERROR,DMA_ENGINE,DMA channel burst size negotiation failed,DMA_ENGINE DMA channel burst size negotiation failed,3
WARNING,DDR_CTRL,DDR controller entering high temperature mode,DDR_CTRL DDR controller entering high temperature mode,1
ERROR,FIFO_BUF,FIFO pointer wrap-around detection failed,FIFO_BUF FIFO pointer wrap-around detection failed,5
WARNING,INTERRUPT_CTRL,Interrupt line toggling rapidly,INTERRUPT_CTRL Interrupt line toggling rapidly,1
INFO,MEM_CTRL,ECC scrub initiated on memory region,MEM_CTRL ECC scrub initiated on memory region,1
ERROR,DMA_ENGINE,DMA transfer to protected memory region initiated,DMA_ENGINE DMA transfer to protected memory region initiated,3
INFO,DMA_ENGINE,DMA transfer from memory to peripheral complete,DMA_ENGINE DMA transfer from memory to peripheral complete,3
CRITICAL,MEM_CTRL,Memory controller hung due to internal deadlock,MEM_CTRL Memory controller hung due to internal deadlock,1
INFO,INTERRUPT_CTRL,GIC interrupt enabled for CPU0,INTERRUPT_CTRL GIC interrupt enabled for CPU0,-1
ERROR,DMA_ENGINE,DMA channel 0 timeout waiting for buffer,DMA_ENGINE DMA channel 0 timeout waiting for buffer,3
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure between clk_a and clk_b,CLOCK_MANAGER Clock domain crossing synchronization failure between clk_a and clk_b,0
INFO,FIFO_BUF,Write operation completed successfully.,FIFO_BUF Write operation completed successfully.,5
INFO,POWER_CTRL,Power state C0 entered,POWER_CTRL Power state C0 entered,4
WARNING,FIFO_BUF,FIFO_DEBUG_OUT buffer nearing full capacity,FIFO_BUF FIFO_DEBUG_OUT buffer nearing full capacity,5
CRITICAL,MEM_CTRL,Physical memory corruption detected at 0x20000000,MEM_CTRL Physical memory corruption detected at 0x20000000,1
WARNING,POWER_CTRL,Power-on reset assertion time too short.,POWER_CTRL Power-on reset assertion time too short.,4
INFO,DDR_CTRL,DDRZQ calibration completed successfully,DDR_CTRL DDRZQ calibration completed successfully,1
INFO,MEM_CTRL,Memory block initialized after reset,MEM_CTRL Memory block initialized after reset,1
WARNING,CLOCK_MANAGER,Clock jitter spreading to adjacent clock domains,CLOCK_MANAGER Clock jitter spreading to adjacent clock domains,0
WARNING,DMA_ENGINE,DMA descriptor chain integrity warning,DMA_ENGINE DMA descriptor chain integrity warning,3
CRITICAL,DDR_CTRL,DDR memory training sequence initialization failed,DDR_CTRL DDR memory training sequence initialization failed,1
INFO,DMA_ENGINE,"DMA transfer completed, interrupt asserted.","DMA_ENGINE DMA transfer completed, interrupt asserted.",3
WARNING,FIFO_BUF,FIFO data invalidation due to asynchronous reset,FIFO_BUF FIFO data invalidation due to asynchronous reset,5
ERROR,CACHE_CTRL,Cache eviction policy causing thrashing,CACHE_CTRL Cache eviction policy causing thrashing,1
WARNING,DDR_CTRL,DDR controller operating at reduced speed,DDR_CTRL DDR controller operating at reduced speed,1
WARNING,AXI_CTRL,AXI slave responding with decode error intermittently,AXI_CTRL AXI slave responding with decode error intermittently,2
INFO,FIFO_BUF,FIFO_BUF_5 reporting 10 entries available,FIFO_BUF FIFO_BUF_5 reporting 10 entries available,5
INFO,POWER_CTRL,Voltage regulator output stable,POWER_CTRL Voltage regulator output stable,4
INFO,POWER_CTRL,POWER_CTRL self-test passed.,POWER_CTRL POWER_CTRL self-test passed.,4
ERROR,INTERRUPT_CTRL,Interrupt controller FSM in unexpected state after reset,INTERRUPT_CTRL Interrupt controller FSM in unexpected state after reset,1
WARNING,PCIE_CTRL,PCIe flow control credit low on upstream port,PCIE_CTRL PCIe flow control credit low on upstream port,6
CRITICAL,AXI_CTRL,AXI security violation: non-secure master accessed secure region,AXI_CTRL AXI security violation: non-secure master accessed secure region,2
WARNING,POWER_CTRL,Power sequence controller reports unexpected state,POWER_CTRL Power sequence controller reports unexpected state,4
WARNING,CACHE_CTRL,TLB miss rate significantly higher than expected,CACHE_CTRL TLB miss rate significantly higher than expected,1
WARNING,DDR_CTRL,DDR memory temperature sensor reading 85 C.,DDR_CTRL DDR memory temperature sensor reading 85 C.,1
CRITICAL,CLOCK_MANAGER,"Clock generator output frequency drift detected, out of specification","CLOCK_MANAGER Clock generator output frequency drift detected, out of specification",0
CRITICAL,AXI_CTRL,AXI interconnect data path permanently stalled,AXI_CTRL AXI interconnect data path permanently stalled,2
WARNING,DDR_CTRL,DDR temperature sensor reporting high,DDR_CTRL DDR temperature sensor reporting high,1
WARNING,DMA_ENGINE,"DMA buffer pointer corruption detected, attempting recovery","DMA_ENGINE DMA buffer pointer corruption detected, attempting recovery",3
ERROR,DMA_ENGINE,DMA channel 8 target address region not configured,DMA_ENGINE DMA channel 8 target address region not configured,3
ERROR,DDR_CTRL,"DDR memory bank X not responding, hardware fault.","DDR_CTRL DDR memory bank X not responding, hardware fault.",1
ERROR,CLOCK_MANAGER,Clock MUX selection glitch detected,CLOCK_MANAGER Clock MUX selection glitch detected,0
INFO,DDR_CTRL,DDR calibration completed successfully.,DDR_CTRL DDR calibration completed successfully.,1
WARNING,INTERRUPT_CTRL,Interrupt line IRQ_DEBUG_03 toggling at very high frequency.,INTERRUPT_CTRL Interrupt line IRQ_DEBUG_03 toggling at very high frequency.,1
CRITICAL,DMA_ENGINE,"DMA engine unresponsive, critical data path blocked (channel 0x0)","DMA_ENGINE DMA engine unresponsive, critical data path blocked (channel 0x0)",3
ERROR,CACHE_CTRL,Cache snoop response timeout.,CACHE_CTRL Cache snoop response timeout.,1
INFO,AXI_CTRL,AXI transaction ID 0x123 completed without errors,AXI_CTRL AXI transaction ID 0x123 completed without errors,2
INFO,PCIE_CTRL,PCIe configuration space read completed,PCIE_CTRL PCIe configuration space read completed,6
INFO,FIFO_BUF,Read operation successful.,FIFO_BUF Read operation successful.,5
INFO,FIFO_BUF,Write operation successful on FIFO_STATUS,FIFO_BUF Write operation successful on FIFO_STATUS,5
WARNING,CLOCK_MANAGER,Spread Spectrum Clocking (SSC) deviation high,CLOCK_MANAGER Spread Spectrum Clocking (SSC) deviation high,-1
ERROR,PCIE_CTRL,PCIe link layer flow control error,PCIE_CTRL PCIe link layer flow control error,6
CRITICAL,POWER_CTRL,Voltage regulator for SoC core unresponsive to commands,POWER_CTRL Voltage regulator for SoC core unresponsive to commands,4
WARNING,CACHE_CTRL,Cache tag array parity error corrected on Way 0x1,CACHE_CTRL Cache tag array parity error corrected on Way 0x1,1
INFO,PCIE_CTRL,PCIe endpoint BAR resized,PCIE_CTRL PCIe endpoint BAR resized,6
WARNING,DMA_ENGINE,DMA channel 7 pending requests queue length high.,DMA_ENGINE DMA channel 7 pending requests queue length high.,3
CRITICAL,MEM_CTRL,"Memory controller internal FIFO overflow, command dropped","MEM_CTRL Memory controller internal FIFO overflow, command dropped",1
INFO,DMA_ENGINE,DMA channel 6 configured for peripheral-to-memory,DMA_ENGINE DMA channel 6 configured for peripheral-to-memory,3
WARNING,INTERRUPT_CTRL,Interrupt queue approaching limit: high water mark hit,INTERRUPT_CTRL Interrupt queue approaching limit: high water mark hit,-1
CRITICAL,CLOCK_MANAGER,Global clock distribution network instability,CLOCK_MANAGER Global clock distribution network instability,0
ERROR,CLOCK_MANAGER,Clock divider configuration error,CLOCK_MANAGER Clock divider configuration error,0
CRITICAL,DDR_CTRL,DDR PHY training failed to converge,DDR_CTRL DDR PHY training failed to converge,1
WARNING,FIFO_BUF,FIFO almost-full flag asserted for extended duration,FIFO_BUF FIFO almost-full flag asserted for extended duration,5
INFO,FIFO_BUF,FIFO initialization finished,FIFO_BUF FIFO initialization finished,5
ERROR,AXI_CTRL,AXI outstanding address limit exceeded,AXI_CTRL AXI outstanding address limit exceeded,2
INFO,CLOCK_MANAGER,Main PLL locked successfully (frequency stable),CLOCK_MANAGER Main PLL locked successfully (frequency stable),0
ERROR,FIFO_BUF,FIFO write operation stalled due to full condition,FIFO_BUF FIFO write operation stalled due to full condition,5
ERROR,PCIE_CTRL,"PCIe link training failure, recovery not possible","PCIE_CTRL PCIe link training failure, recovery not possible",6
INFO,POWER_CTRL,Power state transition to 'STANDBY' completed,POWER_CTRL Power state transition to 'STANDBY' completed,4
WARNING,POWER_CTRL,Power domain A transition delay detected,POWER_CTRL Power domain A transition delay detected,4
INFO,POWER_CTRL,Power management unit self-test passed.,POWER_CTRL Power management unit self-test passed.,4
CRITICAL,CLOCK_MANAGER,System clock halted unexpectedly,CLOCK_MANAGER System clock halted unexpectedly,0
ERROR,INTERRUPT_CTRL,Interrupt priority level inversion detected,INTERRUPT_CTRL Interrupt priority level inversion detected,1
WARNING,AXI_CTRL,AXI outstanding read transaction limit nearing capacity,AXI_CTRL AXI outstanding read transaction limit nearing capacity,2
ERROR,CLOCK_MANAGER,Clock distribution network reported fanout violation,CLOCK_MANAGER Clock distribution network reported fanout violation,0
WARNING,DMA_ENGINE,DMA channel 5 pending transfers exceeding threshold,DMA_ENGINE DMA channel 5 pending transfers exceeding threshold,3
WARNING,DDR_CTRL,DDR memory write buffer nearing saturation,DDR_CTRL DDR memory write buffer nearing saturation,1
WARNING,FIFO_BUF,FIFO_BUF internal buffer approaching capacity (94% full).,FIFO_BUF FIFO_BUF internal buffer approaching capacity (94% full).,5
ERROR,POWER_CTRL,Voltage regulator V_MEM_VDD response too slow,POWER_CTRL Voltage regulator V_MEM_VDD response too slow,-1
ERROR,INTERRUPT_CTRL,Interrupt controller register access permission denied,INTERRUPT_CTRL Interrupt controller register access permission denied,1
WARNING,MEM_CTRL,Memory parity error (corrected),MEM_CTRL Memory parity error (corrected),1
CRITICAL,CLOCK_MANAGER,"Main oscillator fault, system clock lost","CLOCK_MANAGER Main oscillator fault, system clock lost",0
CRITICAL,PCIE_CTRL,PCIe receiver equalization failed for lane 1,PCIE_CTRL PCIe receiver equalization failed for lane 1,6
ERROR,POWER_CTRL,Voltage drop detected on logic rail VDD_IO (0.9V instead of 1.2V),POWER_CTRL Voltage drop detected on logic rail VDD_IO (0.9V instead of 1.2V),4
CRITICAL,PCIE_CTRL,"PCIe link layer protocol error, unrecoverable","PCIE_CTRL PCIe link layer protocol error, unrecoverable",6
ERROR,FIFO_BUF,Attempted read from empty FIFO,FIFO_BUF Attempted read from empty FIFO,5
WARNING,FIFO_BUF,FIFO write latency increasing significantly,FIFO_BUF FIFO write latency increasing significantly,5
ERROR,MEM_CTRL,Memory refresh command failed to execute,MEM_CTRL Memory refresh command failed to execute,1
ERROR,INTERRUPT_CTRL,Interrupt priority inversion detected,INTERRUPT_CTRL Interrupt priority inversion detected,1
INFO,DMA_ENGINE,"DMA channel 9 halted, no more descriptors","DMA_ENGINE DMA channel 9 halted, no more descriptors",3
WARNING,INTERRUPT_CTRL,Interrupt service routine execution time exceeded,INTERRUPT_CTRL Interrupt service routine execution time exceeded,1
WARNING,DMA_ENGINE,Buffer descriptor list approaching end,DMA_ENGINE Buffer descriptor list approaching end,3
ERROR,POWER_CTRL,POWER_CTRL encountered an unexpected invalid state transition event (unexpected state change).,POWER_CTRL POWER_CTRL encountered an unexpected invalid state transition event (unexpected state change).,4
ERROR,FIFO_BUF,FIFO almost empty condition and read attempt,FIFO_BUF FIFO almost empty condition and read attempt,5
ERROR,PCIE_CTRL,PCIe completion timeout detected for request 0xABCD,PCIE_CTRL PCIe completion timeout detected for request 0xABCD,6
ERROR,PCIE_CTRL,PCIe upstream port hot-reset failed,PCIE_CTRL PCIe upstream port hot-reset failed,6
WARNING,DMA_ENGINE,DMA channel priority inversion detected,DMA_ENGINE DMA channel priority inversion detected,3
WARNING,DDR_CTRL,DDR command queue depth high.,DDR_CTRL DDR command queue depth high.,1
CRITICAL,PCIE_CTRL,PCIe link state machine entered invalid state (L2 -> LOOPBACK).,PCIE_CTRL PCIe link state machine entered invalid state (L2 -> LOOPBACK).,6
ERROR,MEM_CTRL,Invalid memory address range accessed by CPU,MEM_CTRL Invalid memory address range accessed by CPU,1
WARNING,PCIE_CTRL,PCIe PTM (Precision Timing Measurement) sync error,PCIE_CTRL PCIe PTM (Precision Timing Measurement) sync error,-1
WARNING,DMA_ENGINE,DMA target address invalid,DMA_ENGINE DMA target address invalid,3
ERROR,CACHE_CTRL,Cache data parity error detected on L1 instruction cache.,CACHE_CTRL Cache data parity error detected on L1 instruction cache.,1
WARNING,FIFO_BUF,FIFO output data ready signal stuck low,FIFO_BUF FIFO output data ready signal stuck low,5
CRITICAL,DMA_ENGINE,DMA engine master bus access denied due to security violation,DMA_ENGINE DMA engine master bus access denied due to security violation,3
INFO,DDR_CTRL,DDR memory size detected: 4GB,DDR_CTRL DDR memory size detected: 4GB,1
CRITICAL,PCIE_CTRL,"PCIe fatal error detected, device isolated","PCIE_CTRL PCIe fatal error detected, device isolated",6
ERROR,FIFO_BUF,FIFO output enable asserted during empty state,FIFO_BUF FIFO output enable asserted during empty state,5
INFO,PCIE_CTRL,PCIe link established at Gen4 x4,PCIE_CTRL PCIe link established at Gen4 x4,6
WARNING,FIFO_BUF,FIFO watermark high exceeded for 100 cycles,FIFO_BUF FIFO watermark high exceeded for 100 cycles,5
ERROR,AXI_CTRL,AXI protocol violation on read data channel.,AXI_CTRL AXI protocol violation on read data channel.,2
INFO,DDR_CTRL,DDR self-refresh entry completed.,DDR_CTRL DDR self-refresh entry completed.,1
WARNING,DDR_CTRL,DDR_CTRL backpressure asserted by DDR_CTRL for extended period.,DDR_CTRL DDR_CTRL backpressure asserted by DDR_CTRL for extended period.,-1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller internal deadlock detected, system unresponsive.","INTERRUPT_CTRL Interrupt controller internal deadlock detected, system unresponsive.",1
WARNING,CLOCK_MANAGER,Clock divider value out of range,CLOCK_MANAGER Clock divider value out of range,0
WARNING,FIFO_BUF,FIFO overflow condition detected intermittently,FIFO_BUF FIFO overflow condition detected intermittently,5
ERROR,CLOCK_MANAGER,Clock loss detected for critical domain (CLK_MEM),CLOCK_MANAGER Clock loss detected for critical domain (CLK_MEM),0
ERROR,DMA_ENGINE,DMA transfer count mismatch,DMA_ENGINE DMA transfer count mismatch,3
ERROR,PCIE_CTRL,PCIe transaction layer CRC error on received packet,PCIE_CTRL PCIe transaction layer CRC error on received packet,6
WARNING,MEM_CTRL,Memory refresh operation pending,MEM_CTRL Memory refresh operation pending,1
ERROR,INTERRUPT_CTRL,Pending interrupt count high,INTERRUPT_CTRL Pending interrupt count high,1
WARNING,FIFO_BUF,FIFO write pointer approaching end of buffer,FIFO_BUF FIFO write pointer approaching end of buffer,5
WARNING,DDR_CTRL,DDR temperature sensor reading approaching warning limit,DDR_CTRL DDR temperature sensor reading approaching warning limit,1
WARNING,CLOCK_MANAGER,Clock tree buffering issue,CLOCK_MANAGER Clock tree buffering issue,0
ERROR,MEM_CTRL,Memory access timeout detected,MEM_CTRL Memory access timeout detected,1
ERROR,FIFO_BUF,FIFO read data invalid due to previous underflow.,FIFO_BUF FIFO read data invalid due to previous underflow.,5
WARNING,INTERRUPT_CTRL,Interrupt nesting depth nearing limit,INTERRUPT_CTRL Interrupt nesting depth nearing limit,1
WARNING,INTERRUPT_CTRL,Interrupt service routine execution time exceeded threshold,INTERRUPT_CTRL Interrupt service routine execution time exceeded threshold,1
WARNING,MEM_CTRL,Memory access patterns indicate potential row hammer vulnerability.,MEM_CTRL Memory access patterns indicate potential row hammer vulnerability.,1
WARNING,PCIE_CTRL,PCIe transaction layer packet (TLP) retry counter incremented,PCIE_CTRL PCIe transaction layer packet (TLP) retry counter incremented,6
ERROR,AXI_CTRL,AXI master issued unaligned read burst,AXI_CTRL AXI master issued unaligned read burst,2
WARNING,PCIE_CTRL,PCIe received TLP with header error (correctable).,PCIE_CTRL PCIe received TLP with header error (correctable).,6
WARNING,AXI_CTRL,Outstanding write transactions approaching maximum,AXI_CTRL Outstanding write transactions approaching maximum,2
INFO,DMA_ENGINE,Transfer context switched,DMA_ENGINE Transfer context switched,3
ERROR,POWER_CTRL,Voltage sensor reports out-of-range value,POWER_CTRL Voltage sensor reports out-of-range value,7
INFO,CACHE_CTRL,"Cache miss for address 0xABCDEF00, fetching from main memory","CACHE_CTRL Cache miss for address 0xABCDEF00, fetching from main memory",1
WARNING,DDR_CTRL,DDR memory temperature sensor reading 70 C.,DDR_CTRL DDR memory temperature sensor reading 70 C.,1
CRITICAL,INTERRUPT_CTRL,Interrupt dispatch unit stuck in pending loop,INTERRUPT_CTRL Interrupt dispatch unit stuck in pending loop,1
WARNING,FIFO_BUF,FIFO empty threshold reached,FIFO_BUF FIFO empty threshold reached,5
WARNING,DMA_ENGINE,DMA source address invalid for current transaction,DMA_ENGINE DMA source address invalid for current transaction,3
WARNING,DDR_CTRL,DDR refresh cycles being delayed,DDR_CTRL DDR refresh cycles being delayed,1
CRITICAL,POWER_CTRL,System shutdown due to prolonged overcurrent,POWER_CTRL System shutdown due to prolonged overcurrent,4
INFO,PCIE_CTRL,PCIe link training completed.,PCIE_CTRL PCIe link training completed.,6
WARNING,CLOCK_MANAGER,"CLOCK_MANAGER configuration change in CLOCK_MANAGER detected, monitoring performance.","CLOCK_MANAGER CLOCK_MANAGER configuration change in CLOCK_MANAGER detected, monitoring performance.",-1
INFO,INTERRUPT_CTRL,All interrupt sources are currently disabled,INTERRUPT_CTRL All interrupt sources are currently disabled,1
CRITICAL,FIFO_BUF,"FIFO hardware corruption detected, unrecoverable","FIFO_BUF FIFO hardware corruption detected, unrecoverable",5
WARNING,AXI_CTRL,"AXI master `WLAST` asserted too late, data loss possible","AXI_CTRL AXI master `WLAST` asserted too late, data loss possible",2
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal bus error,INTERRUPT_CTRL Interrupt controller internal bus error,1
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL activity detected on interface.,INTERRUPT_CTRL INTERRUPT_CTRL activity detected on interface.,-1
INFO,DMA_ENGINE,DMA transfer completion interrupt received,DMA_ENGINE DMA transfer completion interrupt received,3
WARNING,DMA_ENGINE,DMA channel arbitration failure detected,DMA_ENGINE DMA channel arbitration failure detected,3
CRITICAL,MEM_CTRL,Uncorrectable ECC error detected in critical system memory region.,MEM_CTRL Uncorrectable ECC error detected in critical system memory region.,1
ERROR,MEM_CTRL,Memory access violation from master 8 to 0x73d32832.,MEM_CTRL Memory access violation from master 8 to 0x73d32832.,1
INFO,PCIE_CTRL,PCIe power state changed to D0,PCIE_CTRL PCIe power state changed to D0,6
ERROR,CACHE_CTRL,Cache line tag mismatch on lookup,CACHE_CTRL Cache line tag mismatch on lookup,1
INFO,CACHE_CTRL,Cache hit rate within performance targets,CACHE_CTRL Cache hit rate within performance targets,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge for IRQ_DMA_DONE never received,INTERRUPT_CTRL Interrupt acknowledge for IRQ_DMA_DONE never received,1
ERROR,POWER_CTRL,Power good signal unstable,POWER_CTRL Power good signal unstable,4
INFO,CLOCK_MANAGER,Clock source switched to internal oscillator,CLOCK_MANAGER Clock source switched to internal oscillator,0
CRITICAL,FIFO_BUF,"FIFO bypass path stuck-at fault, rendering buffer unusable.","FIFO_BUF FIFO bypass path stuck-at fault, rendering buffer unusable.",5
ERROR,AXI_CTRL,AXI read data bus contention detected,AXI_CTRL AXI read data bus contention detected,2
WARNING,DDR_CTRL,DDR auto-refresh rate adjustment required,DDR_CTRL DDR auto-refresh rate adjustment required,1
WARNING,FIFO_BUF,Read operation stalled,FIFO_BUF Read operation stalled,5
CRITICAL,DDR_CTRL,DDR calibration parameter drift exceeded tolerance,DDR_CTRL DDR calibration parameter drift exceeded tolerance,1
WARNING,AXI_CTRL,AXI_CTRL encountered a minor timing deviation.,AXI_CTRL AXI_CTRL encountered a minor timing deviation.,2
INFO,DMA_ENGINE,DMA transfer completion for channel 11,DMA_ENGINE DMA transfer completion for channel 11,3
ERROR,DMA_ENGINE,DMA request queue overflow,DMA_ENGINE DMA request queue overflow,3
INFO,POWER_CTRL,Power rail voltage stable,POWER_CTRL Power rail voltage stable,4
ERROR,MEM_CTRL,Write after read hazard detected by memory controller,MEM_CTRL Write after read hazard detected by memory controller,1
ERROR,INTERRUPT_CTRL,Interrupt request line stuck high,INTERRUPT_CTRL Interrupt request line stuck high,1
ERROR,DDR_CTRL,Memory address alignment fault,DDR_CTRL Memory address alignment fault,1
ERROR,FIFO_BUF,FIFO 'debug_status' detected a memory leak,FIFO_BUF FIFO 'debug_status' detected a memory leak,5
ERROR,POWER_CTRL,POWER_CTRL: invalid state transition - unexpected state change detected.,POWER_CTRL POWER_CTRL: invalid state transition - unexpected state change detected.,4
INFO,CACHE_CTRL,Cache line fill completed,CACHE_CTRL Cache line fill completed,1
CRITICAL,MEM_CTRL,Memory controller data path ECC error (uncorrectable),MEM_CTRL Memory controller data path ECC error (uncorrectable),1
WARNING,AXI_CTRL,AXI address phase setup time violation marginal,AXI_CTRL AXI address phase setup time violation marginal,2
CRITICAL,FIFO_BUF,FIFO critical path timing violation detected,FIFO_BUF FIFO critical path timing violation detected,5
ERROR,CACHE_CTRL,Cache line replacement policy error,CACHE_CTRL Cache line replacement policy error,1
INFO,DDR_CTRL,DDR_CTRL configuration update applied.,DDR_CTRL DDR_CTRL configuration update applied.,1
WARNING,INTERRUPT_CTRL,System ISR latency exceeding threshold,INTERRUPT_CTRL System ISR latency exceeding threshold,1
ERROR,AXI_CTRL,AXI read transaction returned data from incorrect address.,AXI_CTRL AXI read transaction returned data from incorrect address.,2
INFO,PCIE_CTRL,PCIe link established successfully at Gen3 x4.,PCIE_CTRL PCIe link established successfully at Gen3 x4.,6
INFO,PCIE_CTRL,PCIe upstream port detected link UP,PCIE_CTRL PCIe upstream port detected link UP,6
ERROR,MEM_CTRL,Memory controller detected an invalid burst length,MEM_CTRL Memory controller detected an invalid burst length,1
INFO,FIFO_BUF,FIFO 'debug_events' fill level is 50%,FIFO_BUF FIFO 'debug_events' fill level is 50%,-1
CRITICAL,DDR_CTRL,DDR memory rank calibration failed repeatedly,DDR_CTRL DDR memory rank calibration failed repeatedly,1
CRITICAL,CLOCK_MANAGER,Global clock network failure,CLOCK_MANAGER Global clock network failure,0
INFO,CLOCK_MANAGER,Auxiliary PLL successfully locked at startup,CLOCK_MANAGER Auxiliary PLL successfully locked at startup,0
ERROR,MEM_CTRL,Memory parity error detected at 0x1110e5fa during read.,MEM_CTRL Memory parity error detected at 0x1110e5fa during read.,1
ERROR,MEM_CTRL,Memory controller page table entry corruption,MEM_CTRL Memory controller page table entry corruption,1
ERROR,AXI_CTRL,AXI slave responded with invalid address (SLV_ADDR_ERR),AXI_CTRL AXI slave responded with invalid address (SLV_ADDR_ERR),2
WARNING,FIFO_BUF,FIFO data ready signal unstable.,FIFO_BUF FIFO data ready signal unstable.,5
CRITICAL,CACHE_CTRL,"Cache coherence protocol violation, potential data loss","CACHE_CTRL Cache coherence protocol violation, potential data loss",1
WARNING,DDR_CTRL,DDR DRAM temperature approaching critical threshold,DDR_CTRL DDR DRAM temperature approaching critical threshold,1
ERROR,CACHE_CTRL,Critical timing violation in CACHE_CTRL preventing further operation: unmet timing constraint.,CACHE_CTRL Critical timing violation in CACHE_CTRL preventing further operation: unmet timing constraint.,1
ERROR,FIFO_BUF,FIFO write pointer wrapped incorrectly,FIFO_BUF FIFO write pointer wrapped incorrectly,5
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding threshold (724 cycles).,INTERRUPT_CTRL Interrupt latency exceeding threshold (724 cycles).,1
WARNING,CLOCK_MANAGER,Clock 'PCLK' jitter exceeding specification,CLOCK_MANAGER Clock 'PCLK' jitter exceeding specification,0
ERROR,CACHE_CTRL,Cache way prediction error,CACHE_CTRL Cache way prediction error,1
WARNING,POWER_CTRL,Brown-out detection threshold nearing,POWER_CTRL Brown-out detection threshold nearing,4
ERROR,AXI_CTRL,AXI write transaction B_RESP invalid,AXI_CTRL AXI write transaction B_RESP invalid,2
INFO,AXI_CTRL,AXI write operation completed successfully.,AXI_CTRL AXI write operation completed successfully.,2
CRITICAL,MEM_CTRL,Memory data integrity check failed during scrubbing,MEM_CTRL Memory data integrity check failed during scrubbing,1
WARNING,INTERRUPT_CTRL,Interrupt mask register configuration warning,INTERRUPT_CTRL Interrupt mask register configuration warning,1
INFO,FIFO_BUF,FIFO reconfigured for new data width,FIFO_BUF FIFO reconfigured for new data width,5
ERROR,MEM_CTRL,Memory address translation unit assertion failure,MEM_CTRL Memory address translation unit assertion failure,1
INFO,DDR_CTRL,DDR memory training sequence initiated,DDR_CTRL DDR memory training sequence initiated,1
INFO,MEM_CTRL,Memory access permissions verified,MEM_CTRL Memory access permissions verified,1
WARNING,FIFO_BUF,"FIFO nearly full, subsequent writes may cause overflow","FIFO_BUF FIFO nearly full, subsequent writes may cause overflow",5
WARNING,DDR_CTRL,DDR read data integrity warning on specific byte lanes,DDR_CTRL DDR read data integrity warning on specific byte lanes,1
INFO,POWER_CTRL,Power state transition completed to active,POWER_CTRL Power state transition completed to active,4
CRITICAL,DDR_CTRL,"CRITICAL: DDR PHY calibration failure, memory interface unstable.","DDR_CTRL CRITICAL: DDR PHY calibration failure, memory interface unstable.",1
CRITICAL,POWER_CTRL,Voltage regulator reports permanent output instability,POWER_CTRL Voltage regulator reports permanent output instability,4
INFO,INTERRUPT_CTRL,Interrupt handler registered for new device,INTERRUPT_CTRL Interrupt handler registered for new device,1
WARNING,AXI_CTRL,AXI read latency exceeding expected maximum for master ID 0x5,AXI_CTRL AXI read latency exceeding expected maximum for master ID 0x5,2
CRITICAL,CACHE_CTRL,Inconsistent memory view due to critical cache error.,CACHE_CTRL Inconsistent memory view due to critical cache error.,1
WARNING,CACHE_CTRL,Cache line conflict count elevated.,CACHE_CTRL Cache line conflict count elevated.,1
ERROR,CACHE_CTRL,Cache line write-through operation failed,CACHE_CTRL Cache line write-through operation failed,1
INFO,CLOCK_MANAGER,CLOCK_MANAGER debug status collected.,CLOCK_MANAGER CLOCK_MANAGER debug status collected.,0
INFO,FIFO_BUF,FIFO 'spi_tx' is currently empty,FIFO_BUF FIFO 'spi_tx' is currently empty,-1
INFO,CLOCK_MANAGER,Reference clock detected and stable,CLOCK_MANAGER Reference clock detected and stable,0
CRITICAL,PCIE_CTRL,PCIE_CTRL: System-level state machine fault detected. Unrecoverable hardware state. (FSM stuck in error state),PCIE_CTRL PCIE_CTRL: System-level state machine fault detected. Unrecoverable hardware state. (FSM stuck in error state),-1
INFO,CACHE_CTRL,Cache prefetch mechanism enabled,CACHE_CTRL Cache prefetch mechanism enabled,1
WARNING,POWER_CTRL,Brown-out detection circuit reporting marginal voltage,POWER_CTRL Brown-out detection circuit reporting marginal voltage,4
INFO,POWER_CTRL,System power-off sequence initiated,POWER_CTRL System power-off sequence initiated,4
ERROR,MEM_CTRL,Memory write data not observed on bus,MEM_CTRL Memory write data not observed on bus,1
ERROR,POWER_CTRL,Supply voltage out of range,POWER_CTRL Supply voltage out of range,4
WARNING,AXI_CTRL,AXI transaction latency exceeding expected range,AXI_CTRL AXI transaction latency exceeding expected range,2
ERROR,MEM_CTRL,Memory block X write integrity check failed.,MEM_CTRL Memory block X write integrity check failed.,1
INFO,CLOCK_MANAGER,Clock domain reset asserted,CLOCK_MANAGER Clock domain reset asserted,0
WARNING,CACHE_CTRL,Cache line refill rate high.,CACHE_CTRL Cache line refill rate high.,1
INFO,PCIE_CTRL,PCIe power management state entered,PCIE_CTRL PCIe power management state entered,6
CRITICAL,MEM_CTRL,Memory controller unrecoverable ECC multi-bit error,MEM_CTRL Memory controller unrecoverable ECC multi-bit error,1
INFO,DDR_CTRL,DDR interface initialized to 1600MHz,DDR_CTRL DDR interface initialized to 1600MHz,1
CRITICAL,POWER_CTRL,Voltage sensor reports critical undervoltage,POWER_CTRL Voltage sensor reports critical undervoltage,7
INFO,DMA_ENGINE,DMA interrupt for channel 2 asserted upon completion.,DMA_ENGINE DMA interrupt for channel 2 asserted upon completion.,3
INFO,INTERRUPT_CTRL,Pending interrupt cleared,INTERRUPT_CTRL Pending interrupt cleared,1
WARNING,DMA_ENGINE,DMA request pipeline stall,DMA_ENGINE DMA request pipeline stall,3
ERROR,POWER_CTRL,System reset asserted by power monitor,POWER_CTRL System reset asserted by power monitor,4
INFO,CACHE_CTRL,Cache hit on instruction fetch,CACHE_CTRL Cache hit on instruction fetch,1
ERROR,FIFO_BUF,FIFO_BUF encountered an unexpected buffer overflow event (buffer capacity exceeded). (FIFO 'FIFO_BUF' Depth: 126),FIFO_BUF FIFO_BUF encountered an unexpected buffer overflow event (buffer capacity exceeded). (FIFO 'FIFO_BUF' Depth: 126),5
WARNING,CACHE_CTRL,"Cache eviction rate high, potential for performance impact","CACHE_CTRL Cache eviction rate high, potential for performance impact",1
INFO,DDR_CTRL,DDR read latency configured to CL11.,DDR_CTRL DDR read latency configured to CL11.,1
ERROR,DDR_CTRL,DDR rank deselect error detected,DDR_CTRL DDR rank deselect error detected,1
ERROR,PCIE_CTRL,PCIe receive buffer overflow,PCIE_CTRL PCIe receive buffer overflow,6
CRITICAL,INTERRUPT_CTRL,"Interrupt controller internal deadlock detected, no interrupts processed.","INTERRUPT_CTRL Interrupt controller internal deadlock detected, no interrupts processed.",1
WARNING,CACHE_CTRL,Cache tag entry invalidation stalled,CACHE_CTRL Cache tag entry invalidation stalled,1
CRITICAL,DMA_ENGINE,"DMA engine control registers corrupted, uncommandable","DMA_ENGINE DMA engine control registers corrupted, uncommandable",3
INFO,AXI_CTRL,AXI slave registered successfully,AXI_CTRL AXI slave registered successfully,2
INFO,DDR_CTRL,"ZQ calibration completed, DRAM impedance adjusted","DDR_CTRL ZQ calibration completed, DRAM impedance adjusted",-1
INFO,FIFO_BUF,FIFO_BUF_4 now ready for operations,FIFO_BUF FIFO_BUF_4 now ready for operations,5
ERROR,CACHE_CTRL,Cache way lock-up detected,CACHE_CTRL Cache way lock-up detected,1
INFO,POWER_CTRL,Voltage sensor for VDD_MEM reporting out of range,POWER_CTRL Voltage sensor for VDD_MEM reporting out of range,7
ERROR,AXI_CTRL,AXI burst type violation detected,AXI_CTRL AXI burst type violation detected,2
INFO,CLOCK_MANAGER,Clock tree synthesis completed successfully,CLOCK_MANAGER Clock tree synthesis completed successfully,0
INFO,POWER_CTRL,VCORE rail stable at 1.0V,POWER_CTRL VCORE rail stable at 1.0V,4
WARNING,POWER_CTRL,Power domain transition delay detected for domain IO.,POWER_CTRL Power domain transition delay detected for domain IO.,4
CRITICAL,MEM_CTRL,Double-bit ECC uncorrectable error at 0xCAFECAFE,MEM_CTRL Double-bit ECC uncorrectable error at 0xCAFECAFE,1
ERROR,MEM_CTRL,Memory single-bit ECC error corrected on read from 0x0000FFFF,MEM_CTRL Memory single-bit ECC error corrected on read from 0x0000FFFF,1
CRITICAL,AXI_CTRL,AXI master/slave persistent communication failure,AXI_CTRL AXI master/slave persistent communication failure,2
INFO,CLOCK_MANAGER,Frequency measurement for CLK_AUX confirmed,CLOCK_MANAGER Frequency measurement for CLK_AUX confirmed,-1
ERROR,INTERRUPT_CTRL,Interrupt controller unable to access vector table,INTERRUPT_CTRL Interrupt controller unable to access vector table,1
ERROR,FIFO_BUF,"FIFO pointer corruption detected, state inconsistent","FIFO_BUF FIFO pointer corruption detected, state inconsistent",5
ERROR,AXI_CTRL,AXI address decoding fault detected,AXI_CTRL AXI address decoding fault detected,2
INFO,FIFO_BUF,FIFO reset vector cleared,FIFO_BUF FIFO reset vector cleared,5
INFO,DMA_ENGINE,Ping-pong buffer swap completed for channel 1,DMA_ENGINE Ping-pong buffer swap completed for channel 1,-1
ERROR,DMA_ENGINE,DMA channel arbitration priority inversion,DMA_ENGINE DMA channel arbitration priority inversion,3
CRITICAL,AXI_CTRL,AXI write response channel (BVALID) stuck low indefinitely,AXI_CTRL AXI write response channel (BVALID) stuck low indefinitely,2
WARNING,AXI_CTRL,AXI write data accepted but not acknowledged,AXI_CTRL AXI write data accepted but not acknowledged,2
ERROR,FIFO_BUF,"FIFO status flags inconsistent (e.g., full and empty)","FIFO_BUF FIFO status flags inconsistent (e.g., full and empty)",5
CRITICAL,DMA_ENGINE,DMA controller configuration registers corrupted,DMA_ENGINE DMA controller configuration registers corrupted,3
CRITICAL,DMA_ENGINE,DMA engine state machine entered critical error state.,DMA_ENGINE DMA engine state machine entered critical error state.,3
WARNING,POWER_CTRL,Voltage rail monitoring detected minor fluctuation,POWER_CTRL Voltage rail monitoring detected minor fluctuation,4
INFO,FIFO_BUF,Read pointer advanced after data consumption,FIFO_BUF Read pointer advanced after data consumption,5
INFO,DMA_ENGINE,DMA channel 3 transfer type set to memory-to-memory,DMA_ENGINE DMA channel 3 transfer type set to memory-to-memory,3
INFO,POWER_CTRL,Voltage regulator Y stable.,POWER_CTRL Voltage regulator Y stable.,4
WARNING,AXI_CTRL,AXI AW channel handshake stalled,AXI_CTRL AXI AW channel handshake stalled,2
ERROR,PCIE_CTRL,"PCIe link training failure, no link established on controller 0x0","PCIE_CTRL PCIe link training failure, no link established on controller 0x0",6
WARNING,POWER_CTRL,Voltage fluctuation detected on V_IO rail,POWER_CTRL Voltage fluctuation detected on V_IO rail,4
CRITICAL,MEM_CTRL,Fatal memory error: system crash imminent,MEM_CTRL Fatal memory error: system crash imminent,1
WARNING,AXI_CTRL,AXI handshake delay approaching threshold for master NIC.,AXI_CTRL AXI handshake delay approaching threshold for master NIC.,2
WARNING,CACHE_CTRL,Coherence protocol warning,CACHE_CTRL Coherence protocol warning,1
ERROR,MEM_CTRL,Data bus parity error detected during writeback,MEM_CTRL Data bus parity error detected during writeback,1
WARNING,DDR_CTRL,DDR refresh command frequency slightly below target,DDR_CTRL DDR refresh command frequency slightly below target,1
WARNING,INTERRUPT_CTRL,Interrupt request line toggling excessively,INTERRUPT_CTRL Interrupt request line toggling excessively,1
WARNING,PCIE_CTRL,PCIe virtual channel buffer backpressure detected,PCIE_CTRL PCIe virtual channel buffer backpressure detected,6
INFO,DMA_ENGINE,DMA descriptor prefetching enabled,DMA_ENGINE DMA descriptor prefetching enabled,3
ERROR,POWER_CTRL,Brownout reset assertion failed,POWER_CTRL Brownout reset assertion failed,4
INFO,PCIE_CTRL,PCIe configuration space access granted.,PCIE_CTRL PCIe configuration space access granted.,6
CRITICAL,DMA_ENGINE,"DMA descriptor fetch hardware error, unrecoverable state","DMA_ENGINE DMA descriptor fetch hardware error, unrecoverable state",3
WARNING,FIFO_BUF,FIFO read pointer approaching write pointer.,FIFO_BUF FIFO read pointer approaching write pointer.,5
WARNING,AXI_CTRL,AXI_CTRL transaction retry count for AXI_CTRL is increasing.,AXI_CTRL AXI_CTRL transaction retry count for AXI_CTRL is increasing.,2
WARNING,FIFO_BUF,FIFO input buffer backpressure asserted,FIFO_BUF FIFO input buffer backpressure asserted,5
INFO,AXI_CTRL,AXI transaction with ID 0xAB completed successfully,AXI_CTRL AXI transaction with ID 0xAB completed successfully,2
INFO,FIFO_BUF,FIFO 'log_buffer' is 10% full,FIFO_BUF FIFO 'log_buffer' is 10% full,5
CRITICAL,INTERRUPT_CTRL,Interrupt controller hardware malfunction,INTERRUPT_CTRL Interrupt controller hardware malfunction,1
INFO,CACHE_CTRL,MRU update successful,CACHE_CTRL MRU update successful,-1
WARNING,INTERRUPT_CTRL,Interrupt handler execution latency exceeding threshold,INTERRUPT_CTRL Interrupt handler execution latency exceeding threshold,1
CRITICAL,INTERRUPT_CTRL,System interrupt vector table corrupted,INTERRUPT_CTRL System interrupt vector table corrupted,1
INFO,FIFO_BUF,"Write operation successful, 32 bytes added","FIFO_BUF Write operation successful, 32 bytes added",5
INFO,AXI_CTRL,AXI transaction accepted by slave,AXI_CTRL AXI transaction accepted by slave,2
ERROR,AXI_CTRL,AXI transaction burst length (LEN) violation on write channel.,AXI_CTRL AXI transaction burst length (LEN) violation on write channel.,2
INFO,DDR_CTRL,ZQ calibration completed,DDR_CTRL ZQ calibration completed,1
INFO,POWER_CTRL,Power budget allocated for performance mode,POWER_CTRL Power budget allocated for performance mode,4
WARNING,DMA_ENGINE,"DMA queue nearing saturation, internal backpressure applied","DMA_ENGINE DMA queue nearing saturation, internal backpressure applied",3
INFO,INTERRUPT_CTRL,Interrupt handler registered for source ID 5,INTERRUPT_CTRL Interrupt handler registered for source ID 5,1
INFO,POWER_CTRL,Power domain isolation logic enabled,POWER_CTRL Power domain isolation logic enabled,4
WARNING,DMA_ENGINE,DMA descriptor fetch stalled on memory access,DMA_ENGINE DMA descriptor fetch stalled on memory access,3
INFO,DMA_ENGINE,DMA descriptor fetch successful,DMA_ENGINE DMA descriptor fetch successful,3
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance,CLOCK_MANAGER Clock jitter exceeding tolerance,0
WARNING,CLOCK_MANAGER,Clock gating efficacy reduced,CLOCK_MANAGER Clock gating efficacy reduced,0
WARNING,INTERRUPT_CTRL,Interrupt pending register holding stale requests,INTERRUPT_CTRL Interrupt pending register holding stale requests,1
WARNING,AXI_CTRL,AXI `ARVALID` asserted without `ARREADY` for extended cycles,AXI_CTRL AXI `ARVALID` asserted without `ARREADY` for extended cycles,-1
ERROR,CACHE_CTRL,Cache block write permission denied,CACHE_CTRL Cache block write permission denied,1
WARNING,DDR_CTRL,"DDR refresh cycle delayed, approaching critical threshold","DDR_CTRL DDR refresh cycle delayed, approaching critical threshold",1
WARNING,CACHE_CTRL,Cache coherence probe delayed due to bus congestion,CACHE_CTRL Cache coherence probe delayed due to bus congestion,1
WARNING,FIFO_BUF,"Read operation blocked, FIFO empty.","FIFO_BUF Read operation blocked, FIFO empty.",5
WARNING,DMA_ENGINE,DMA read request queue saturation,DMA_ENGINE DMA read request queue saturation,3
INFO,DMA_ENGINE,DMA configuration valid,DMA_ENGINE DMA configuration valid,3
INFO,INTERRUPT_CTRL,Interrupt pending for 'UART_RX',INTERRUPT_CTRL Interrupt pending for 'UART_RX',1
INFO,INTERRUPT_CTRL,Interrupt controller in bypass mode,INTERRUPT_CTRL Interrupt controller in bypass mode,1
CRITICAL,DDR_CTRL,DDR DQ/DQS training failed to converge,DDR_CTRL DDR DQ/DQS training failed to converge,1
ERROR,INTERRUPT_CTRL,Interrupt controller internal timer overrun,INTERRUPT_CTRL Interrupt controller internal timer overrun,1
INFO,POWER_CTRL,Power domain H power cycle initiated,POWER_CTRL Power domain H power cycle initiated,4
INFO,DDR_CTRL,DDR refresh command issued,DDR_CTRL DDR refresh command issued,1
ERROR,CLOCK_MANAGER,Clock domain crossing data path corruption,CLOCK_MANAGER Clock domain crossing data path corruption,0
WARNING,CACHE_CTRL,MSHR entry allocation approaching limit.,CACHE_CTRL MSHR entry allocation approaching limit.,-1
INFO,CLOCK_MANAGER,Clock gating unit for module 'X' enabled.,CLOCK_MANAGER Clock gating unit for module 'X' enabled.,0
CRITICAL,DDR_CTRL,DDR training eye width below minimum,DDR_CTRL DDR training eye width below minimum,1
WARNING,FIFO_BUF,FIFO 'log_buffer' write operation stalled,FIFO_BUF FIFO 'log_buffer' write operation stalled,5
CRITICAL,MEM_CTRL,Memory controller command queue overflowed,MEM_CTRL Memory controller command queue overflowed,1
CRITICAL,POWER_CTRL,System power-down imminent due to fault,POWER_CTRL System power-down imminent due to fault,4
ERROR,PCIE_CTRL,PCIe transaction layer packet CRC mismatch on received TLP,PCIE_CTRL PCIe transaction layer packet CRC mismatch on received TLP,6
CRITICAL,CLOCK_MANAGER,Clock generation PLL failed to re-lock,CLOCK_MANAGER Clock generation PLL failed to re-lock,0
INFO,FIFO_BUF,Register write to FIFO_BUF successful (Addr: 0xAA).,FIFO_BUF Register write to FIFO_BUF successful (Addr: 0xAA).,5
CRITICAL,CLOCK_MANAGER,System clock source failure.,CLOCK_MANAGER System clock source failure.,0
ERROR,DMA_ENGINE,DMA transaction timeout for channel CH0.,DMA_ENGINE DMA transaction timeout for channel CH0.,3
ERROR,INTERRUPT_CTRL,Interrupt acknowledgment logic error,INTERRUPT_CTRL Interrupt acknowledgment logic error,1
CRITICAL,MEM_CTRL,"ECC parity mismatch detected, uncorrectable error at 0x4f15d7f7.","MEM_CTRL ECC parity mismatch detected, uncorrectable error at 0x4f15d7f7.",1
ERROR,CLOCK_MANAGER,Clock switchover instability detected.,CLOCK_MANAGER Clock switchover instability detected.,0
WARNING,INTERRUPT_CTRL,Interrupt acknowledgment delay observed,INTERRUPT_CTRL Interrupt acknowledgment delay observed,1
INFO,FIFO_BUF,Watermark levels configured,FIFO_BUF Watermark levels configured,5
CRITICAL,DDR_CTRL,DDR chip select logic exhibiting sporadic glitches,DDR_CTRL DDR chip select logic exhibiting sporadic glitches,1
ERROR,MEM_CTRL,"Memory address decoding error, access to non-existent region","MEM_CTRL Memory address decoding error, access to non-existent region",1
INFO,AXI_CTRL,AXI read address channel ready,AXI_CTRL AXI read address channel ready,2
WARNING,CACHE_CTRL,Cache tag directory lookup latency high,CACHE_CTRL Cache tag directory lookup latency high,1
ERROR,DMA_ENGINE,DMA destination buffer address out of bounds,DMA_ENGINE DMA destination buffer address out of bounds,3
WARNING,CACHE_CTRL,Cache invalidate command latency prolonged,CACHE_CTRL Cache invalidate command latency prolonged,1
WARNING,DDR_CTRL,DDR bank precharge timing close to violation,DDR_CTRL DDR bank precharge timing close to violation,1
INFO,POWER_CTRL,Power state transition to D0 completed,POWER_CTRL Power state transition to D0 completed,4
CRITICAL,PCIE_CTRL,"PCIe PHY layer failure detected, no link establishment possible.","PCIE_CTRL PCIe PHY layer failure detected, no link establishment possible.",6
INFO,DDR_CTRL,DDR frequency changed to 1600MHz,DDR_CTRL DDR frequency changed to 1600MHz,1
INFO,FIFO_BUF,"FIFO reset completed successfully, all pointers cleared.","FIFO_BUF FIFO reset completed successfully, all pointers cleared.",5
ERROR,MEM_CTRL,Invalid memory access request,MEM_CTRL Invalid memory access request,1
ERROR,CACHE_CTRL,Data corruption in cache line,CACHE_CTRL Data corruption in cache line,1
CRITICAL,MEM_CTRL,Uncorrectable multi-bit ECC error detected in memory bank 0,MEM_CTRL Uncorrectable multi-bit ECC error detected in memory bank 0,1
INFO,DMA_ENGINE,DMA configuration loaded.,DMA_ENGINE DMA configuration loaded.,3
INFO,FIFO_BUF,Global enable signal asserted for FIFO_BUF.,FIFO_BUF Global enable signal asserted for FIFO_BUF.,5
CRITICAL,AXI_CTRL,AXI crossbar arbitration deadlock detected,AXI_CTRL AXI crossbar arbitration deadlock detected,2
ERROR,DMA_ENGINE,DMA channel descriptor read access violation,DMA_ENGINE DMA channel descriptor read access violation,3
WARNING,CLOCK_MANAGER,Asynchronous reset propagation delay exceeded,CLOCK_MANAGER Asynchronous reset propagation delay exceeded,0
ERROR,MEM_CTRL,Data integrity check failure on memory write,MEM_CTRL Data integrity check failure on memory write,1
CRITICAL,DDR_CTRL,"DDR training sequence failed, unrecoverable state machine fault.","DDR_CTRL DDR training sequence failed, unrecoverable state machine fault.",1
INFO,INTERRUPT_CTRL,Interrupt 'WAKEUP_INT' cleared,INTERRUPT_CTRL Interrupt 'WAKEUP_INT' cleared,-1
CRITICAL,MEM_CTRL,"CRITICAL: Double bit ECC corruption detected at address 0xDEADBEEF, uncorrectable.","MEM_CTRL CRITICAL: Double bit ECC corruption detected at address 0xDEADBEEF, uncorrectable.",1
ERROR,PCIE_CTRL,PCIe Configuration Space Access failure,PCIE_CTRL PCIe Configuration Space Access failure,6
CRITICAL,CACHE_CTRL,Cache coherence persistent failure,CACHE_CTRL Cache coherence persistent failure,1
INFO,CLOCK_MANAGER,Secondary clock source activated.,CLOCK_MANAGER Secondary clock source activated.,0
INFO,FIFO_BUF,FIFO_BUF_15 read data matches expected pattern,FIFO_BUF FIFO_BUF_15 read data matches expected pattern,5
WARNING,DMA_ENGINE,DMA transfer completion count discrepancy,DMA_ENGINE DMA transfer completion count discrepancy,3
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected.,DMA_ENGINE DMA buffer pointer corruption detected.,3
WARNING,DDR_CTRL,DDR command queue average depth 200.,DDR_CTRL DDR command queue average depth 200.,1
CRITICAL,CACHE_CTRL,L2 cache permanently disabled due to fatal error,CACHE_CTRL L2 cache permanently disabled due to fatal error,1
WARNING,AXI_CTRL,AXI write transaction outstanding for too long,AXI_CTRL AXI write transaction outstanding for too long,2
ERROR,INTERRUPT_CTRL,"Interrupt priority inversion detected, arbitration conflict.","INTERRUPT_CTRL Interrupt priority inversion detected, arbitration conflict.",1
WARNING,PCIE_CTRL,PCIe hot reset sequence completed with minor issues,PCIE_CTRL PCIe hot reset sequence completed with minor issues,6
INFO,DMA_ENGINE,DMA channel 7 stopped by hardware,DMA_ENGINE DMA channel 7 stopped by hardware,3
INFO,MEM_CTRL,Memory write cycle executed,MEM_CTRL Memory write cycle executed,1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller internal FIFO overflow, vector loss.","INTERRUPT_CTRL Interrupt controller internal FIFO overflow, vector loss.",1
WARNING,INTERRUPT_CTRL,Interrupt controller servicing latency increasing,INTERRUPT_CTRL Interrupt controller servicing latency increasing,1
WARNING,DDR_CTRL,DDR write data eye integrity marginal,DDR_CTRL DDR write data eye integrity marginal,1
WARNING,DDR_CTRL,DDR controller reports high power consumption from 3D stacked memory,DDR_CTRL DDR controller reports high power consumption from 3D stacked memory,1
INFO,CLOCK_MANAGER,Frequency counter updated to 100MHz,CLOCK_MANAGER Frequency counter updated to 100MHz,0
WARNING,CACHE_CTRL,Cache victim buffer nearing capacity,CACHE_CTRL Cache victim buffer nearing capacity,1
INFO,FIFO_BUF,"FIFO reset completed, ready for use","FIFO_BUF FIFO reset completed, ready for use",5
ERROR,CLOCK_MANAGER,Clock domain crossing (CDC) data loss on critical path,CLOCK_MANAGER Clock domain crossing (CDC) data loss on critical path,0
ERROR,INTERRUPT_CTRL,Interrupt controller internal data path error,INTERRUPT_CTRL Interrupt controller internal data path error,1
CRITICAL,MEM_CTRL,Memory controller internal FIFO overflow,MEM_CTRL Memory controller internal FIFO overflow,1
WARNING,CLOCK_MANAGER,Clock domain crossing 'reset_sync' metastability counter incremented,CLOCK_MANAGER Clock domain crossing 'reset_sync' metastability counter incremented,0
WARNING,FIFO_BUF,FIFO_RX read pointer lagging behind expected,FIFO_BUF FIFO_RX read pointer lagging behind expected,5
ERROR,AXI_CTRL,AXI burst type violation detected (fixed burst on non-aligned address),AXI_CTRL AXI burst type violation detected (fixed burst on non-aligned address),2
INFO,MEM_CTRL,Memory controller command queue overflow,MEM_CTRL Memory controller command queue overflow,1
WARNING,AXI_CTRL,AXI transaction ID collision potential detected,AXI_CTRL AXI transaction ID collision potential detected,2
CRITICAL,POWER_CTRL,"Main power rail instability, system reset imminent.","POWER_CTRL Main power rail instability, system reset imminent.",4
CRITICAL,DMA_ENGINE,DMA target address generation logic produced an out-of-bounds address,DMA_ENGINE DMA target address generation logic produced an out-of-bounds address,3
WARNING,INTERRUPT_CTRL,Interrupt controller FIFO nearing capacity,INTERRUPT_CTRL Interrupt controller FIFO nearing capacity,1
ERROR,DMA_ENGINE,DMA descriptor format mismatch,DMA_ENGINE DMA descriptor format mismatch,3
WARNING,INTERRUPT_CTRL,"Interrupt vector table CRC mismatch detected, corrected","INTERRUPT_CTRL Interrupt vector table CRC mismatch detected, corrected",1
INFO,FIFO_BUF,FIFO initialized,FIFO_BUF FIFO initialized,5
INFO,INTERRUPT_CTRL,Interrupt controller operating in legacy mode,INTERRUPT_CTRL Interrupt controller operating in legacy mode,-1
ERROR,INTERRUPT_CTRL,Interrupt handler exited abnormally,INTERRUPT_CTRL Interrupt handler exited abnormally,1
WARNING,CACHE_CTRL,Coherence probe from peer processor delayed.,CACHE_CTRL Coherence probe from peer processor delayed.,1
INFO,POWER_CTRL,System entered low power mode.,POWER_CTRL System entered low power mode.,4
INFO,DMA_ENGINE,DMA channel 20 configured for peripheral-to-memory,DMA_ENGINE DMA channel 20 configured for peripheral-to-memory,3
INFO,DDR_CTRL,DDR prefetch buffer utilization at 50%,DDR_CTRL DDR prefetch buffer utilization at 50%,1
INFO,FIFO_BUF,FIFO depth reconfigured to 128.,FIFO_BUF FIFO depth reconfigured to 128.,5
ERROR,AXI_CTRL,AXI outstanding write limit reached,AXI_CTRL AXI outstanding write limit reached,2
INFO,DMA_ENGINE,Burst transfer initiated,DMA_ENGINE Burst transfer initiated,3
WARNING,DMA_ENGINE,DMA descriptor fetching stalled,DMA_ENGINE DMA descriptor fetching stalled,3
WARNING,CACHE_CTRL,Snooping traffic elevated,CACHE_CTRL Snooping traffic elevated,1
INFO,MEM_CTRL,Memory read-modify-write cycle completed,MEM_CTRL Memory read-modify-write cycle completed,1
CRITICAL,DMA_ENGINE,DMA engine unable to respond to arbitration requests,DMA_ENGINE DMA engine unable to respond to arbitration requests,3
INFO,FIFO_BUF,FIFO empty,FIFO_BUF FIFO empty,5
WARNING,FIFO_BUF,FIFO_ADC data output latency increasing,FIFO_BUF FIFO_ADC data output latency increasing,5
WARNING,DDR_CTRL,DDR memory access pattern causing excessive page closes,DDR_CTRL DDR memory access pattern causing excessive page closes,1
CRITICAL,CLOCK_MANAGER,Global clock signal instability detected,CLOCK_MANAGER Global clock signal instability detected,0
INFO,POWER_CTRL,Low power mode entered.,POWER_CTRL Low power mode entered.,4
WARNING,DDR_CTRL,DDR memory bank conflict rate increasing,DDR_CTRL DDR memory bank conflict rate increasing,1
INFO,INTERRUPT_CTRL,Interrupt controller re-enabled after mask,INTERRUPT_CTRL Interrupt controller re-enabled after mask,1
WARNING,DDR_CTRL,DDR address bus glitches detected,DDR_CTRL DDR address bus glitches detected,1
ERROR,CACHE_CTRL,"Cache tag RAM corruption, multiple entries affected","CACHE_CTRL Cache tag RAM corruption, multiple entries affected",1
ERROR,DMA_ENGINE,DMA channel access violation.,DMA_ENGINE DMA channel access violation.,3
INFO,MEM_CTRL,Memory write data committed to physical memory,MEM_CTRL Memory write data committed to physical memory,1
WARNING,PCIE_CTRL,PCIe transaction layer latency exceeding specification,PCIE_CTRL PCIe transaction layer latency exceeding specification,6
INFO,FIFO_BUF,FIFO push operation successful,FIFO_BUF FIFO push operation successful,5
ERROR,CACHE_CTRL,Cache line eviction failure,CACHE_CTRL Cache line eviction failure,1
ERROR,DDR_CTRL,DDR command protocol mismatch,DDR_CTRL DDR command protocol mismatch,1
INFO,DDR_CTRL,DDR controller in low power mode,DDR_CTRL DDR controller in low power mode,1
ERROR,DMA_ENGINE,DMA channel enable signal stuck low,DMA_ENGINE DMA channel enable signal stuck low,3
ERROR,PCIE_CTRL,PCIE_CTRL: timing violation - setup/hold time violation detected.,PCIE_CTRL PCIE_CTRL: timing violation - setup/hold time violation detected.,-1
INFO,POWER_CTRL,Deep sleep mode entered,POWER_CTRL Deep sleep mode entered,4
WARNING,CLOCK_MANAGER,Clock frequency deviation exceeding 5%,CLOCK_MANAGER Clock frequency deviation exceeding 5%,0
INFO,CLOCK_MANAGER,Global clock enable status is active,CLOCK_MANAGER Global clock enable status is active,0
INFO,POWER_CTRL,Voltage monitoring active,POWER_CTRL Voltage monitoring active,4
WARNING,DMA_ENGINE,DMA channel utilization above 90%,DMA_ENGINE DMA channel utilization above 90%,3
WARNING,FIFO_BUF,FIFO read latency exceeded expected software polling interval.,FIFO_BUF FIFO read latency exceeded expected software polling interval.,5
INFO,POWER_CTRL,Power state 'deep_sleep' entered successfully,POWER_CTRL Power state 'deep_sleep' entered successfully,4
INFO,FIFO_BUF,FIFO 'status_output' depth is 0,FIFO_BUF FIFO 'status_output' depth is 0,5
CRITICAL,CLOCK_MANAGER,Clock gating logic for module X stuck in gated state,CLOCK_MANAGER Clock gating logic for module X stuck in gated state,0
INFO,INTERRUPT_CTRL,Interrupt vector table successfully loaded,INTERRUPT_CTRL Interrupt vector table successfully loaded,1
WARNING,MEM_CTRL,Memory write buffer nearing full.,MEM_CTRL Memory write buffer nearing full.,1
WARNING,PCIE_CTRL,PCIe non-posted request retry limit reached,PCIE_CTRL PCIe non-posted request retry limit reached,6
INFO,POWER_CTRL,Low power mode entry successful,POWER_CTRL Low power mode entry successful,4
CRITICAL,PCIE_CTRL,PCIe endpoint unresponsive after reset,PCIE_CTRL PCIe endpoint unresponsive after reset,6
INFO,MEM_CTRL,Memory error injection test passed,MEM_CTRL Memory error injection test passed,1
WARNING,CACHE_CTRL,Cache hit rate below 90% threshold,CACHE_CTRL Cache hit rate below 90% threshold,1
ERROR,FIFO_BUF,FIFO read operation attempted on empty buffer,FIFO_BUF FIFO read operation attempted on empty buffer,5
WARNING,AXI_CTRL,AXI protocol violation: AWLEN and ARLEN mismatch for linked transactions,AXI_CTRL AXI protocol violation: AWLEN and ARLEN mismatch for linked transactions,2
INFO,CACHE_CTRL,Cache snooping operation completed,CACHE_CTRL Cache snooping operation completed,1
ERROR,DDR_CTRL,DDR Read Leveling sequence failed to converge,DDR_CTRL DDR Read Leveling sequence failed to converge,1
CRITICAL,DDR_CTRL,Critical DDR timing violation leading to unrecoverable data corruption,DDR_CTRL Critical DDR timing violation leading to unrecoverable data corruption,1
CRITICAL,POWER_CTRL,Power sequencing controller entered an unrecoverable state,POWER_CTRL Power sequencing controller entered an unrecoverable state,4
ERROR,CACHE_CTRL,Cache line invalidation failure detected,CACHE_CTRL Cache line invalidation failure detected,1
INFO,PCIE_CTRL,PCIe Function 0 BAR registers updated.,PCIE_CTRL PCIe Function 0 BAR registers updated.,6
ERROR,MEM_CTRL,Memory bus read data mismatch,MEM_CTRL Memory bus read data mismatch,1
ERROR,AXI_CTRL,AXI protocol violation on write response channel,AXI_CTRL AXI protocol violation on write response channel,2
ERROR,DDR_CTRL,"DDR command timing violation detected (e.g., tRFC) on channel CH0.","DDR_CTRL DDR command timing violation detected (e.g., tRFC) on channel CH0.",1
WARNING,FIFO_BUF,FIFO fill level at 85% capacity,FIFO_BUF FIFO fill level at 85% capacity,5
ERROR,POWER_CTRL,Voltage supply sequencing error during power-up,POWER_CTRL Voltage supply sequencing error during power-up,4
INFO,CLOCK_MANAGER,Clock manager initialized successfully.,CLOCK_MANAGER Clock manager initialized successfully.,0
CRITICAL,PCIE_CTRL,"PCIe uncorrectable internal error, component reset required","PCIE_CTRL PCIe uncorrectable internal error, component reset required",6
ERROR,CACHE_CTRL,Data cache coherency protocol violation,CACHE_CTRL Data cache coherency protocol violation,1
INFO,DMA_ENGINE,DMA channel 2 transfer paused by software,DMA_ENGINE DMA channel 2 transfer paused by software,3
WARNING,CLOCK_MANAGER,PLL lock time exceeding specification.,CLOCK_MANAGER PLL lock time exceeding specification.,0
WARNING,MEM_CTRL,Memory access latency exceeding average,MEM_CTRL Memory access latency exceeding average,1
INFO,AXI_CTRL,AXI bus arbitration successful,AXI_CTRL AXI bus arbitration successful,2
INFO,PCIE_CTRL,PCIe link de-asserted.,PCIE_CTRL PCIe link de-asserted.,6
CRITICAL,DMA_ENGINE,"DMA channel 0 bus contention detected, potentially fatal. (bus contention)","DMA_ENGINE DMA channel 0 bus contention detected, potentially fatal. (bus contention)",3
WARNING,DMA_ENGINE,DMA transfer size exceeding maximum payload,DMA_ENGINE DMA transfer size exceeding maximum payload,3
WARNING,POWER_CTRL,Power domain transition delay detected for System.,POWER_CTRL Power domain transition delay detected for System.,4
INFO,AXI_CTRL,AXI channel arbitration scheme configured as round-robin.,AXI_CTRL AXI channel arbitration scheme configured as round-robin.,2
ERROR,CACHE_CTRL,"Cache dirty bit not set after write, data loss possible","CACHE_CTRL Cache dirty bit not set after write, data loss possible",1
WARNING,AXI_CTRL,AXI slave asserting perpetual DECODE_ERROR,AXI_CTRL AXI slave asserting perpetual DECODE_ERROR,2
INFO,POWER_CTRL,Register write to POWER_CTRL successful (Addr: 0x98).,POWER_CTRL Register write to POWER_CTRL successful (Addr: 0x98).,-1
INFO,CACHE_CTRL,Cache line allocated in Way 1.,CACHE_CTRL Cache line allocated in Way 1.,1
ERROR,AXI_CTRL,AXI protocol violation: unaligned address for burst,AXI_CTRL AXI protocol violation: unaligned address for burst,2
ERROR,DMA_ENGINE,DMA channel arbitration failure for channel 3,DMA_ENGINE DMA channel arbitration failure for channel 3,3
WARNING,DDR_CTRL,DDR command bus utilization is peaking,DDR_CTRL DDR command bus utilization is peaking,1
INFO,DDR_CTRL,DDR calibration passed for all ranks,DDR_CTRL DDR calibration passed for all ranks,1
WARNING,POWER_CTRL,Auxiliary power rail voltage ripple exceeding tolerance,POWER_CTRL Auxiliary power rail voltage ripple exceeding tolerance,4
INFO,PCIE_CTRL,PCIe link partner negotiated to lower speed,PCIE_CTRL PCIe link partner negotiated to lower speed,6
INFO,INTERRUPT_CTRL,Interrupt 0xF dispatched,INTERRUPT_CTRL Interrupt 0xF dispatched,1
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for source 20.,INTERRUPT_CTRL Interrupt dispatch completed for source 20.,1
CRITICAL,MEM_CTRL,"Memory controller state machine entered invalid state, system unresponsive. (invalid state transition)","MEM_CTRL Memory controller state machine entered invalid state, system unresponsive. (invalid state transition)",1
WARNING,DDR_CTRL,DDR command bus utilization nearing 100%,DDR_CTRL DDR command bus utilization nearing 100%,1
INFO,INTERRUPT_CTRL,Interrupt controller debug counters cleared,INTERRUPT_CTRL Interrupt controller debug counters cleared,1
WARNING,CACHE_CTRL,L2 cache eviction rate higher than expected,CACHE_CTRL L2 cache eviction rate higher than expected,1
CRITICAL,DDR_CTRL,DDR memory data strobe (DQS) signal permanently disabled,DDR_CTRL DDR memory data strobe (DQS) signal permanently disabled,-1
CRITICAL,MEM_CTRL,ECC parity mismatch detected.,MEM_CTRL ECC parity mismatch detected.,1
WARNING,DDR_CTRL,DDR power consumption higher than expected,DDR_CTRL DDR power consumption higher than expected,1
INFO,DMA_ENGINE,"DMA transfer complete, 4096 bytes transferred","DMA_ENGINE DMA transfer complete, 4096 bytes transferred",3
WARNING,MEM_CTRL,ECC error count increasing in bank 1,MEM_CTRL ECC error count increasing in bank 1,1
INFO,INTERRUPT_CTRL,Interrupt handler for timer completed,INTERRUPT_CTRL Interrupt handler for timer completed,1
WARNING,CACHE_CTRL,Cache directory coherence check taking too long,CACHE_CTRL Cache directory coherence check taking too long,1
CRITICAL,MEM_CTRL,Memory controller in unrecoverable error state,MEM_CTRL Memory controller in unrecoverable error state,1
INFO,DMA_ENGINE,DMA_ENGINE resource allocation successful.,DMA_ENGINE DMA_ENGINE resource allocation successful.,3
ERROR,CACHE_CTRL,Cache directory entry corruption,CACHE_CTRL Cache directory entry corruption,1
INFO,FIFO_BUF,FIFO reset complete.,FIFO_BUF FIFO reset complete.,5
ERROR,FIFO_BUF,FIFO 'ctrl_q' read operation attempted on empty FIFO,FIFO_BUF FIFO 'ctrl_q' read operation attempted on empty FIFO,5
CRITICAL,DDR_CTRL,DDR memory command parser internal error,DDR_CTRL DDR memory command parser internal error,1
INFO,DMA_ENGINE,DMA engine now ready for new requests,DMA_ENGINE DMA engine now ready for new requests,3
ERROR,CLOCK_MANAGER,Internal clock distribution network error,CLOCK_MANAGER Internal clock distribution network error,0
CRITICAL,DMA_ENGINE,DMA channel 4 experienced descriptor fetch deadlock,DMA_ENGINE DMA channel 4 experienced descriptor fetch deadlock,3
CRITICAL,DDR_CTRL,"DDR training sequence failed, system unbootable","DDR_CTRL DDR training sequence failed, system unbootable",1
CRITICAL,MEM_CTRL,Memory controller internal register access fault,MEM_CTRL Memory controller internal register access fault,1
WARNING,INTERRUPT_CTRL,"Too many pending interrupts, dispatch latency growing","INTERRUPT_CTRL Too many pending interrupts, dispatch latency growing",1
INFO,POWER_CTRL,Power-on reset sequence completed.,POWER_CTRL Power-on reset sequence completed.,4
WARNING,POWER_CTRL,Power rail overvoltage condition detected,POWER_CTRL Power rail overvoltage condition detected,4
ERROR,DMA_ENGINE,DMA channel 2 address mapping error,DMA_ENGINE DMA channel 2 address mapping error,3
WARNING,CACHE_CTRL,Cache way prediction accuracy degraded.,CACHE_CTRL Cache way prediction accuracy degraded.,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal delayed excessively,INTERRUPT_CTRL Interrupt acknowledge signal delayed excessively,1
CRITICAL,DMA_ENGINE,DMA engine halt due to unrecoverable descriptor error. (state machine fault),DMA_ENGINE DMA engine halt due to unrecoverable descriptor error. (state machine fault),3
INFO,POWER_CTRL,Power-on sequence initiated,POWER_CTRL Power-on sequence initiated,4
INFO,AXI_CTRL,AXI master/slave link established,AXI_CTRL AXI master/slave link established,2
INFO,POWER_CTRL,VDD_DSP voltage adjusted to 0.8V.,POWER_CTRL VDD_DSP voltage adjusted to 0.8V.,-1
WARNING,CLOCK_MANAGER,Clock glitch detected on sensitive path.,CLOCK_MANAGER Clock glitch detected on sensitive path.,0
INFO,FIFO_BUF,FIFO status register polled for empty,FIFO_BUF FIFO status register polled for empty,5
CRITICAL,DDR_CTRL,DDR memory write leveling completely failed,DDR_CTRL DDR memory write leveling completely failed,1
CRITICAL,MEM_CTRL,ECC logic reported uncorrectable error on critical boot code,MEM_CTRL ECC logic reported uncorrectable error on critical boot code,1
INFO,CACHE_CTRL,Cache line allocation completed,CACHE_CTRL Cache line allocation completed,1
INFO,MEM_CTRL,Memory BIST (Built-In Self Test) initiated,MEM_CTRL Memory BIST (Built-In Self Test) initiated,1
INFO,CLOCK_MANAGER,Dynamic frequency scaling enabled,CLOCK_MANAGER Dynamic frequency scaling enabled,0
WARNING,DMA_ENGINE,DMA channel X paused due to peripheral readiness,DMA_ENGINE DMA channel X paused due to peripheral readiness,3
CRITICAL,CLOCK_MANAGER,"Primary PLL lost lock, system clock unstable","CLOCK_MANAGER Primary PLL lost lock, system clock unstable",0
WARNING,INTERRUPT_CTRL,Interrupt handling routine taking excessive time,INTERRUPT_CTRL Interrupt handling routine taking excessive time,1
INFO,DMA_ENGINE,DMA block transfer mode enabled,DMA_ENGINE DMA block transfer mode enabled,3
ERROR,AXI_CTRL,AXI atomic operation failed due to bus contention,AXI_CTRL AXI atomic operation failed due to bus contention,2
INFO,AXI_CTRL,AXI read data received,AXI_CTRL AXI read data received,2
ERROR,PCIE_CTRL,PCIe Completion Timeout (CTO) on EP,PCIE_CTRL PCIe Completion Timeout (CTO) on EP,6
WARNING,AXI_CTRL,AXI read channel deadlock detected,AXI_CTRL AXI read channel deadlock detected,2
INFO,CLOCK_MANAGER,Clock frequency configuration updated to 500MHz,CLOCK_MANAGER Clock frequency configuration updated to 500MHz,0
INFO,DDR_CTRL,DDR self-refresh initiated for power saving,DDR_CTRL DDR self-refresh initiated for power saving,1
WARNING,POWER_CTRL,Voltage spike detected on peripheral rail,POWER_CTRL Voltage spike detected on peripheral rail,4
ERROR,PCIE_CTRL,PCIe uncorrectable internal error detected,PCIE_CTRL PCIe uncorrectable internal error detected,6
WARNING,DDR_CTRL,DDR command bus utilization is high,DDR_CTRL DDR command bus utilization is high,1
CRITICAL,DDR_CTRL,DRAM device initialization failed,DDR_CTRL DRAM device initialization failed,1
ERROR,PCIE_CTRL,PCIE_CTRL encountered an unexpected arbitration conflict event (fairness algorithm failure).,PCIE_CTRL PCIE_CTRL encountered an unexpected arbitration conflict event (fairness algorithm failure).,-1
WARNING,AXI_CTRL,AXI master 0x0 reports `SLVERR` from slave 0x1,AXI_CTRL AXI master 0x0 reports `SLVERR` from slave 0x1,2
ERROR,DDR_CTRL,"DDR bank conflict detected, performance impact for request 0x3F615174","DDR_CTRL DDR bank conflict detected, performance impact for request 0x3F615174",1
CRITICAL,PCIE_CTRL,PCIe link training sequence stalled indefinitely,PCIE_CTRL PCIe link training sequence stalled indefinitely,6
WARNING,FIFO_BUF,Almost empty threshold reached,FIFO_BUF Almost empty threshold reached,5
WARNING,AXI_CTRL,AXI `BRESP` not `OKAY` for all write bursts,AXI_CTRL AXI `BRESP` not `OKAY` for all write bursts,-1
INFO,FIFO_BUF,FIFO buffer statistics reset,FIFO_BUF FIFO buffer statistics reset,5
CRITICAL,MEM_CTRL,"Memory controller state machine entered invalid state, system crash.","MEM_CTRL Memory controller state machine entered invalid state, system crash.",1
ERROR,MEM_CTRL,Memory controller internal state machine entered invalid state,MEM_CTRL Memory controller internal state machine entered invalid state,1
CRITICAL,POWER_CTRL,"Power rail VDD_IO instability detected, critical components affected","POWER_CTRL Power rail VDD_IO instability detected, critical components affected",4
ERROR,MEM_CTRL,Memory controller state machine entered invalid state 0x07.,MEM_CTRL Memory controller state machine entered invalid state 0x07.,1
CRITICAL,CLOCK_MANAGER,"PLL feedback path broken, output clock unstable.","CLOCK_MANAGER PLL feedback path broken, output clock unstable.",0
WARNING,DDR_CTRL,DDR memory temperature above threshold.,DDR_CTRL DDR memory temperature above threshold.,1
ERROR,FIFO_BUF,FIFO write pointer incremented without valid data,FIFO_BUF FIFO write pointer incremented without valid data,5
INFO,INTERRUPT_CTRL,Global interrupt mask applied,INTERRUPT_CTRL Global interrupt mask applied,1
INFO,CACHE_CTRL,Cache flush completed successfully for all ways,CACHE_CTRL Cache flush completed successfully for all ways,1
CRITICAL,FIFO_BUF,FIFO data corruption detected during read,FIFO_BUF FIFO data corruption detected during read,5
WARNING,MEM_CTRL,Memory page access density for region 0x10000000 high,MEM_CTRL Memory page access density for region 0x10000000 high,1
CRITICAL,CACHE_CTRL,"L3 cache internal data corruption, affecting system memory view.","CACHE_CTRL L3 cache internal data corruption, affecting system memory view.",1
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal register file parity error,INTERRUPT_CTRL Interrupt controller internal register file parity error,1
INFO,FIFO_BUF,FIFO 'debug_trace' successfully reset and cleared,FIFO_BUF FIFO 'debug_trace' successfully reset and cleared,5
ERROR,CACHE_CTRL,Cache data array read/write error,CACHE_CTRL Cache data array read/write error,1
CRITICAL,AXI_CTRL,AXI data integrity error detected on bus,AXI_CTRL AXI data integrity error detected on bus,2
WARNING,FIFO_BUF,FIFO empty assertion de-asserted unexpectedly,FIFO_BUF FIFO empty assertion de-asserted unexpectedly,5
ERROR,CACHE_CTRL,Cache tag parity error detected in L2 cache controller.,CACHE_CTRL Cache tag parity error detected in L2 cache controller.,1
INFO,CLOCK_MANAGER,Clock gating for idle modules applied,CLOCK_MANAGER Clock gating for idle modules applied,0
CRITICAL,PCIE_CTRL,PCIe link state machine stuck,PCIE_CTRL PCIe link state machine stuck,6
CRITICAL,DMA_ENGINE,"DMA bus master arbitration failed, permanent grant to wrong master","DMA_ENGINE DMA bus master arbitration failed, permanent grant to wrong master",3
ERROR,DDR_CTRL,DDR CAS latency (CL) violation,DDR_CTRL DDR CAS latency (CL) violation,1
ERROR,CLOCK_MANAGER,Glitch detected on internal clock signal,CLOCK_MANAGER Glitch detected on internal clock signal,0
WARNING,DDR_CTRL,"DDR refresh cycle delayed, approaching critical window","DDR_CTRL DDR refresh cycle delayed, approaching critical window",1
WARNING,INTERRUPT_CTRL,Interrupt acknowledge timeout detected for critical event,INTERRUPT_CTRL Interrupt acknowledge timeout detected for critical event,1
CRITICAL,CACHE_CTRL,"CRITICAL: Cache tag array corruption, cache lookup unreliable and disabled.","CACHE_CTRL CRITICAL: Cache tag array corruption, cache lookup unreliable and disabled.",1
CRITICAL,DMA_ENGINE,"DMA buffer descriptor list corruption, system crash imminent","DMA_ENGINE DMA buffer descriptor list corruption, system crash imminent",3
ERROR,CLOCK_MANAGER,Clock domain crossing synchronizer assertion failure,CLOCK_MANAGER Clock domain crossing synchronizer assertion failure,0
INFO,PCIE_CTRL,TLP processed,PCIE_CTRL TLP processed,6
ERROR,POWER_CTRL,Voltage regulator output ripple exceeding tolerance,POWER_CTRL Voltage regulator output ripple exceeding tolerance,4
ERROR,POWER_CTRL,Core rail power-on reset assertion failure,POWER_CTRL Core rail power-on reset assertion failure,4
ERROR,DMA_ENGINE,DMA burst size exceeds maximum configured,DMA_ENGINE DMA burst size exceeds maximum configured,3
WARNING,POWER_CTRL,Regulator output ripple exceeding specification,POWER_CTRL Regulator output ripple exceeding specification,4
INFO,PCIE_CTRL,PCIe hot-reset issued to downstream port,PCIE_CTRL PCIe hot-reset issued to downstream port,6
WARNING,DMA_ENGINE,DMA queue for channel 6 nearing saturation,DMA_ENGINE DMA queue for channel 6 nearing saturation,3
INFO,CLOCK_MANAGER,Clock tree synthesis report generated,CLOCK_MANAGER Clock tree synthesis report generated,0
WARNING,MEM_CTRL,"ECC scrub operation required for bank 2, pending","MEM_CTRL ECC scrub operation required for bank 2, pending",-1
WARNING,FIFO_BUF,FIFO input ready signal de-asserted unexpectedly,FIFO_BUF FIFO input ready signal de-asserted unexpectedly,5
CRITICAL,DMA_ENGINE,Fatal data transfer corruption detected by DMA integrity check.,DMA_ENGINE Fatal data transfer corruption detected by DMA integrity check.,3
INFO,AXI_CTRL,Configuration parameters loaded for AXI_CTRL.,AXI_CTRL Configuration parameters loaded for AXI_CTRL.,2
CRITICAL,CACHE_CTRL,Cache directory coherence protocol failure,CACHE_CTRL Cache directory coherence protocol failure,1
ERROR,DMA_ENGINE,DMA channel arbitration logic failure,DMA_ENGINE DMA channel arbitration logic failure,3
WARNING,DMA_ENGINE,DMA channel starvation detected,DMA_ENGINE DMA channel starvation detected,3
WARNING,CLOCK_MANAGER,Clock monitor detected abnormal duty cycle,CLOCK_MANAGER Clock monitor detected abnormal duty cycle,0
ERROR,FIFO_BUF,"FIFO write pointer corrupted, pointing to an invalid address","FIFO_BUF FIFO write pointer corrupted, pointing to an invalid address",5
INFO,FIFO_BUF,FIFO 'data_in' port acknowledged write,FIFO_BUF FIFO 'data_in' port acknowledged write,5
INFO,CLOCK_MANAGER,Clock monitor self-calibration initiated,CLOCK_MANAGER Clock monitor self-calibration initiated,-1
WARNING,AXI_CTRL,AXI interconnect latency increasing,AXI_CTRL AXI interconnect latency increasing,2
INFO,POWER_CTRL,Power state transition completed to STANDBY,POWER_CTRL Power state transition completed to STANDBY,4
ERROR,CACHE_CTRL,Cache tag array parity error detected,CACHE_CTRL Cache tag array parity error detected,1
WARNING,DDR_CTRL,"DDR refresh cycle delayed, data integrity at risk","DDR_CTRL DDR refresh cycle delayed, data integrity at risk",1
ERROR,MEM_CTRL,Memory read data validity signal asserted prematurely,MEM_CTRL Memory read data validity signal asserted prematurely,1
INFO,DDR_CTRL,DDR memory power-down mode entered,DDR_CTRL DDR memory power-down mode entered,1
INFO,AXI_CTRL,AXI bridge arbitration priority updated,AXI_CTRL AXI bridge arbitration priority updated,2
CRITICAL,DDR_CTRL,DDR memory physical address corruption detected,DDR_CTRL DDR memory physical address corruption detected,1
INFO,CLOCK_MANAGER,Clock generator initialized,CLOCK_MANAGER Clock generator initialized,0
WARNING,CACHE_CTRL,Cache bypass mode enabled due to error,CACHE_CTRL Cache bypass mode enabled due to error,1
ERROR,AXI_CTRL,AXI slave responded with DECERR on write address channel,AXI_CTRL AXI slave responded with DECERR on write address channel,2
CRITICAL,CLOCK_MANAGER,"System PLL lost lock, unrecoverable clock tree failure","CLOCK_MANAGER System PLL lost lock, unrecoverable clock tree failure",0
INFO,CACHE_CTRL,Cache way replacement policy set to LRU,CACHE_CTRL Cache way replacement policy set to LRU,1
ERROR,MEM_CTRL,Memory write protection violation,MEM_CTRL Memory write protection violation,1
ERROR,FIFO_BUF,FIFO output data parity error,FIFO_BUF FIFO output data parity error,5
CRITICAL,FIFO_BUF,"FIFO internal clocking failure, complete data loss.","FIFO_BUF FIFO internal clocking failure, complete data loss.",5
WARNING,INTERRUPT_CTRL,Interrupt queue approaching saturation (10/12 entries),INTERRUPT_CTRL Interrupt queue approaching saturation (10/12 entries),1
ERROR,POWER_CTRL,Power domain X state machine failure,POWER_CTRL Power domain X state machine failure,4
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected in descriptor table,DMA_ENGINE DMA buffer pointer corruption detected in descriptor table,3
ERROR,FIFO_BUF,FIFO read request issued when FIFO is empty,FIFO_BUF FIFO read request issued when FIFO is empty,5
WARNING,CLOCK_MANAGER,Clock skew between two synchronous domains approaching unsafe range.,CLOCK_MANAGER Clock skew between two synchronous domains approaching unsafe range.,0
CRITICAL,FIFO_BUF,"FIFO controller in invalid state, data integrity compromised","FIFO_BUF FIFO controller in invalid state, data integrity compromised",5
WARNING,CACHE_CTRL,Cache dirty line count exceeding 95% of total.,CACHE_CTRL Cache dirty line count exceeding 95% of total.,1
CRITICAL,DMA_ENGINE,"DMA master arbitration failure, starvation detected","DMA_ENGINE DMA master arbitration failure, starvation detected",3
WARNING,DMA_ENGINE,Descriptor prefetch buffer nearing saturation,DMA_ENGINE Descriptor prefetch buffer nearing saturation,3
ERROR,DMA_ENGINE,DMA transfer timeout detected for channel 0.,DMA_ENGINE DMA transfer timeout detected for channel 0.,3
CRITICAL,CLOCK_MANAGER,"Primary PLL lost lock, system halted","CLOCK_MANAGER Primary PLL lost lock, system halted",0
WARNING,DDR_CTRL,DDR rank X entering self-refresh due to inactivity,DDR_CTRL DDR rank X entering self-refresh due to inactivity,1
WARNING,CLOCK_MANAGER,Clock enable signal glitch detected,CLOCK_MANAGER Clock enable signal glitch detected,0
INFO,MEM_CTRL,ECC single-bit error corrected at address 0xDEADBEEF,MEM_CTRL ECC single-bit error corrected at address 0xDEADBEEF,1
INFO,DMA_ENGINE,DMA controller arbitration priority updated,DMA_ENGINE DMA controller arbitration priority updated,3
WARNING,CACHE_CTRL,Cache invalidation queue backlog,CACHE_CTRL Cache invalidation queue backlog,1
ERROR,INTERRUPT_CTRL,Interrupt mask register write protection violation,INTERRUPT_CTRL Interrupt mask register write protection violation,1
WARNING,CLOCK_MANAGER,Global clock enable signal de-asserted unexpectedly,CLOCK_MANAGER Global clock enable signal de-asserted unexpectedly,0
ERROR,POWER_CTRL,Overcurrent protection triggered on power rail,POWER_CTRL Overcurrent protection triggered on power rail,4
INFO,DDR_CTRL,DDR ZQ calibration complete,DDR_CTRL DDR ZQ calibration complete,1
WARNING,DMA_ENGINE,"DMA arbitration conflict detected, minor delay","DMA_ENGINE DMA arbitration conflict detected, minor delay",3
ERROR,CACHE_CTRL,"Cache coherence violation detected, stale data accessed","CACHE_CTRL Cache coherence violation detected, stale data accessed",1
WARNING,INTERRUPT_CTRL,"Pending interrupt count high, potential for missed interrupts","INTERRUPT_CTRL Pending interrupt count high, potential for missed interrupts",1
ERROR,MEM_CTRL,Memory bus arbitration deadlock detected,MEM_CTRL Memory bus arbitration deadlock detected,1
INFO,CLOCK_MANAGER,Clock buffer drive strength adjusted,CLOCK_MANAGER Clock buffer drive strength adjusted,0
INFO,INTERRUPT_CTRL,New power state engaged for INTERRUPT_CTRL.,INTERRUPT_CTRL New power state engaged for INTERRUPT_CTRL.,4
WARNING,DMA_ENGINE,DMA channel 0 arbitration priority contested,DMA_ENGINE DMA channel 0 arbitration priority contested,3
ERROR,MEM_CTRL,Memory address alignment fault,MEM_CTRL Memory address alignment fault,1
WARNING,MEM_CTRL,"Memory refresh interval approaching limit, next cycle soon","MEM_CTRL Memory refresh interval approaching limit, next cycle soon",1
ERROR,INTERRUPT_CTRL,Interrupt status register corruption,INTERRUPT_CTRL Interrupt status register corruption,1
INFO,DDR_CTRL,DDR controller initialized for LPDDR4 memory,DDR_CTRL DDR controller initialized for LPDDR4 memory,1
ERROR,AXI_CTRL,AXI write response channel unexpected RRESP,AXI_CTRL AXI write response channel unexpected RRESP,2
ERROR,INTERRUPT_CTRL,Interrupt controller register corruption,INTERRUPT_CTRL Interrupt controller register corruption,1
ERROR,MEM_CTRL,Memory controller ECC scrubbing encountered an uncorrectable bit,MEM_CTRL Memory controller ECC scrubbing encountered an uncorrectable bit,1
ERROR,CLOCK_MANAGER,Clock multiplexer selected illegal source,CLOCK_MANAGER Clock multiplexer selected illegal source,0
INFO,INTERRUPT_CTRL,Interrupt masking applied for ID Z,INTERRUPT_CTRL Interrupt masking applied for ID Z,-1
ERROR,CACHE_CTRL,Cache line not invalidated after snoop transaction,CACHE_CTRL Cache line not invalidated after snoop transaction,1
WARNING,PCIE_CTRL,TLP latency increasing,PCIE_CTRL TLP latency increasing,6
CRITICAL,POWER_CTRL,System power-on-reset sequence failed,POWER_CTRL System power-on-reset sequence failed,4
WARNING,FIFO_BUF,FIFO fill level nearing 90% capacity,FIFO_BUF FIFO fill level nearing 90% capacity,5
INFO,DDR_CTRL,DDR memory module operating at optimal temperature,DDR_CTRL DDR memory module operating at optimal temperature,1
INFO,CLOCK_MANAGER,Clock frequency changed to 500MHz,CLOCK_MANAGER Clock frequency changed to 500MHz,0
WARNING,PCIE_CTRL,"PCIe hot-plug event detected, link training initiated","PCIE_CTRL PCIe hot-plug event detected, link training initiated",6
INFO,PCIE_CTRL,PCIe lane re-initialization completed.,PCIE_CTRL PCIe lane re-initialization completed.,6
ERROR,POWER_CTRL,Dynamic voltage and frequency scaling (DVFS) transition failed,POWER_CTRL Dynamic voltage and frequency scaling (DVFS) transition failed,9
ERROR,CACHE_CTRL,Cache line eviction policy violation,CACHE_CTRL Cache line eviction policy violation,1
INFO,CACHE_CTRL,Cache way prediction logic enabled,CACHE_CTRL Cache way prediction logic enabled,1
ERROR,FIFO_BUF,Data integrity check failed on FIFO read,FIFO_BUF Data integrity check failed on FIFO read,5
ERROR,DMA_ENGINE,DMA queue nearing saturation causing stall,DMA_ENGINE DMA queue nearing saturation causing stall,3
INFO,CLOCK_MANAGER,"Dynamic frequency scaling activated, new target 500MHz","CLOCK_MANAGER Dynamic frequency scaling activated, new target 500MHz",0
ERROR,PCIE_CTRL,PCIe transaction layer packet CRC error,PCIE_CTRL PCIe transaction layer packet CRC error,6
CRITICAL,MEM_CTRL,Memory controller FSM entered illegal state 0b1101,MEM_CTRL Memory controller FSM entered illegal state 0b1101,1
ERROR,CACHE_CTRL,Cache line tag invalidation failure,CACHE_CTRL Cache line tag invalidation failure,1
INFO,INTERRUPT_CTRL,Interrupt masked successfully,INTERRUPT_CTRL Interrupt masked successfully,1
CRITICAL,CACHE_CTRL,Cache directory coherence mismatch detected,CACHE_CTRL Cache directory coherence mismatch detected,1
ERROR,PCIE_CTRL,PCIe protocol violation: AWID/WID mismatch.,PCIE_CTRL PCIe protocol violation: AWID/WID mismatch.,-1
ERROR,CLOCK_MANAGER,PLL lock lost on main clock generation unit,CLOCK_MANAGER PLL lock lost on main clock generation unit,0
CRITICAL,MEM_CTRL,Memory controller internal FSM entered undefined state,MEM_CTRL Memory controller internal FSM entered undefined state,1
ERROR,POWER_CTRL,Voltage regulator control interface timeout,POWER_CTRL Voltage regulator control interface timeout,4
INFO,CACHE_CTRL,Cache line replaced by LRU algorithm,CACHE_CTRL Cache line replaced by LRU algorithm,1
CRITICAL,POWER_CTRL,"Power management unit fatal error, unable to control rails","POWER_CTRL Power management unit fatal error, unable to control rails",4
CRITICAL,POWER_CTRL,PMIC unrecoverable error detected,POWER_CTRL PMIC unrecoverable error detected,4
ERROR,INTERRUPT_CTRL,Interrupt clear-on-read timeout for pending IRQ,INTERRUPT_CTRL Interrupt clear-on-read timeout for pending IRQ,1
ERROR,AXI_CTRL,AXI response channel SLVERR received repeatedly,AXI_CTRL AXI response channel SLVERR received repeatedly,2
CRITICAL,FIFO_BUF,"CRITICAL: Persistent FIFO pointer corruption detected, data path unreliable.","FIFO_BUF CRITICAL: Persistent FIFO pointer corruption detected, data path unreliable.",5
CRITICAL,MEM_CTRL,Uncorrectable multi-bit ECC error detected in crucial memory region,MEM_CTRL Uncorrectable multi-bit ECC error detected in crucial memory region,1
ERROR,AXI_CTRL,AXI write address channel asserted `AWVALID` without `AWREADY`,AXI_CTRL AXI write address channel asserted `AWVALID` without `AWREADY`,2
WARNING,MEM_CTRL,Memory block access privileges violated,MEM_CTRL Memory block access privileges violated,1
WARNING,AXI_CTRL,AXI burst type changed mid-transaction,AXI_CTRL AXI burst type changed mid-transaction,2
WARNING,AXI_CTRL,AXI interconnect reporting high transaction retry count,AXI_CTRL AXI interconnect reporting high transaction retry count,2
WARNING,AXI_CTRL,AXI slave 'X' responds with `SLVERR`,AXI_CTRL AXI slave 'X' responds with `SLVERR`,2
WARNING,CLOCK_MANAGER,Phase-locked loop (PLL) re-locking sequence initiated.,CLOCK_MANAGER Phase-locked loop (PLL) re-locking sequence initiated.,0
CRITICAL,PCIE_CTRL,"PCIe power domain collapse, critical power failure.","PCIE_CTRL PCIe power domain collapse, critical power failure.",6
INFO,AXI_CTRL,AXI burst read of 64 bytes to 0x2000 initiated,AXI_CTRL AXI burst read of 64 bytes to 0x2000 initiated,2
ERROR,DMA_ENGINE,DMA channel 11 encountered bus error during transfer,DMA_ENGINE DMA channel 11 encountered bus error during transfer,3
ERROR,DMA_ENGINE,DMA channel 10 encountered bus error during transfer,DMA_ENGINE DMA channel 10 encountered bus error during transfer,3
WARNING,DMA_ENGINE,Unused DMA channel accumulating pending requests,DMA_ENGINE Unused DMA channel accumulating pending requests,3
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal FSM entered illegal state,INTERRUPT_CTRL Interrupt controller internal FSM entered illegal state,1
WARNING,POWER_CTRL,Power consumption approaching limit,POWER_CTRL Power consumption approaching limit,4
WARNING,AXI_CTRL,AXI slave issued a DECOERR response unexpectedly,AXI_CTRL AXI slave issued a DECOERR response unexpectedly,2
ERROR,DDR_CTRL,DDR initialization sequence hung at CALIBRATION stage,DDR_CTRL DDR initialization sequence hung at CALIBRATION stage,1
INFO,CLOCK_MANAGER,Clock source selected: external crystal,CLOCK_MANAGER Clock source selected: external crystal,0
ERROR,AXI_CTRL,AXI read data bus observed floating,AXI_CTRL AXI read data bus observed floating,2
ERROR,POWER_CTRL,Brown-out detection circuit trip,POWER_CTRL Brown-out detection circuit trip,4
ERROR,PCIE_CTRL,PCIe Completion Timeout detected,PCIE_CTRL PCIe Completion Timeout detected,6
ERROR,AXI_CTRL,AXI master detected an unexpected response for a write transaction,AXI_CTRL AXI master detected an unexpected response for a write transaction,2
INFO,INTERRUPT_CTRL,IRQ 0 registered by CPU.,INTERRUPT_CTRL IRQ 0 registered by CPU.,1
INFO,PCIE_CTRL,PCIe MSI/MSI-X capabilities registered,PCIE_CTRL PCIe MSI/MSI-X capabilities registered,6
ERROR,AXI_CTRL,AXI transaction ID mismatch detected,AXI_CTRL AXI transaction ID mismatch detected,2
CRITICAL,DDR_CTRL,"DDR controller unrecoverable state, data access halted.","DDR_CTRL DDR controller unrecoverable state, data access halted.",1
CRITICAL,MEM_CTRL,Memory controller received unexecutable command code,MEM_CTRL Memory controller received unexecutable command code,1
CRITICAL,POWER_CTRL,"Core power rail catastrophic failure, system shutdown.","POWER_CTRL Core power rail catastrophic failure, system shutdown.",4
CRITICAL,POWER_CTRL,System voltage out of range,POWER_CTRL System voltage out of range,7
ERROR,MEM_CTRL,Memory bus arbitration conflict,MEM_CTRL Memory bus arbitration conflict,1
INFO,FIFO_BUF,"FIFO write operation successful, new data added","FIFO_BUF FIFO write operation successful, new data added",5
WARNING,DMA_ENGINE,DMA channel bandwidth utilization suboptimal,DMA_ENGINE DMA channel bandwidth utilization suboptimal,3
INFO,PCIE_CTRL,PCIe link established successfully.,PCIE_CTRL PCIe link established successfully.,6
CRITICAL,CLOCK_MANAGER,Clock tree reset propagation failure,CLOCK_MANAGER Clock tree reset propagation failure,0
WARNING,CLOCK_MANAGER,Clock domain crossing data path delay warning,CLOCK_MANAGER Clock domain crossing data path delay warning,0
INFO,PCIE_CTRL,PCIe link width changed to x8.,PCIE_CTRL PCIe link width changed to x8.,6
CRITICAL,POWER_CTRL,Power management unit unresponsive to software requests,POWER_CTRL Power management unit unresponsive to software requests,4
ERROR,AXI_CTRL,AXI burst write response 'SLVERR' received unexpectedly,AXI_CTRL AXI burst write response 'SLVERR' received unexpectedly,2
WARNING,DMA_ENGINE,DMA channel busy for an extended period,DMA_ENGINE DMA channel busy for an extended period,3
INFO,PCIE_CTRL,PCIe link established successfully at Gen3 x8,PCIE_CTRL PCIe link established successfully at Gen3 x8,6
ERROR,DDR_CTRL,DDR command timing violation during a burst read.,DDR_CTRL DDR command timing violation during a burst read.,1
ERROR,CACHE_CTRL,Cache dirty line flush failure,CACHE_CTRL Cache dirty line flush failure,1
INFO,DDR_CTRL,DDR memory controller in ready state,DDR_CTRL DDR memory controller in ready state,1
INFO,INTERRUPT_CTRL,Interrupt priority updated,INTERRUPT_CTRL Interrupt priority updated,1
WARNING,CLOCK_MANAGER,Clock domain crossing path 'debug_data_cdc' shows high metastability rate,CLOCK_MANAGER Clock domain crossing path 'debug_data_cdc' shows high metastability rate,0
WARNING,INTERRUPT_CTRL,Interrupt queue approaching limit,INTERRUPT_CTRL Interrupt queue approaching limit,1
INFO,CACHE_CTRL,Cache flushing initiated for security domain,CACHE_CTRL Cache flushing initiated for security domain,-1
INFO,POWER_CTRL,VCORE rail voltage stable at 1.05V,POWER_CTRL VCORE rail voltage stable at 1.05V,4
INFO,POWER_CTRL,VDD_IO voltage regulator enabled,POWER_CTRL VDD_IO voltage regulator enabled,4
WARNING,MEM_CTRL,Memory read response time variation,MEM_CTRL Memory read response time variation,1
ERROR,DMA_ENGINE,DMA transfer count mismatch with descriptor,DMA_ENGINE DMA transfer count mismatch with descriptor,3
INFO,CLOCK_MANAGER,Spread spectrum clocking enabled,CLOCK_MANAGER Spread spectrum clocking enabled,-1
INFO,POWER_CTRL,Voltage regulator X output showing ripple.,POWER_CTRL Voltage regulator X output showing ripple.,4
CRITICAL,MEM_CTRL,Memory controller access to internal registers failed,MEM_CTRL Memory controller access to internal registers failed,1
ERROR,POWER_CTRL,Power-on reset deassertion delayed,POWER_CTRL Power-on reset deassertion delayed,4
ERROR,DMA_ENGINE,DMA channel descriptor fetch timeout,DMA_ENGINE DMA channel descriptor fetch timeout,3
WARNING,CACHE_CTRL,Directory update backlog,CACHE_CTRL Directory update backlog,1
CRITICAL,DMA_ENGINE,"DMA engine internal bus parity error, data corruption likely","DMA_ENGINE DMA engine internal bus parity error, data corruption likely",3
ERROR,CLOCK_MANAGER,Clock phase locked loop (PLL) configuration error detected.,CLOCK_MANAGER Clock phase locked loop (PLL) configuration error detected.,0
ERROR,CLOCK_MANAGER,PLL configuration error detected,CLOCK_MANAGER PLL configuration error detected,0
WARNING,POWER_CTRL,Voltage regulator output nearing tolerance limit,POWER_CTRL Voltage regulator output nearing tolerance limit,4
ERROR,DMA_ENGINE,DMA channel 0 configuration invalid,DMA_ENGINE DMA channel 0 configuration invalid,3
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL resource allocation successful.,INTERRUPT_CTRL INTERRUPT_CTRL resource allocation successful.,1
INFO,DDR_CTRL,DDR self-refresh entry successful.,DDR_CTRL DDR self-refresh entry successful.,1
ERROR,AXI_CTRL,AXI read channel protocol violation,AXI_CTRL AXI read channel protocol violation,2
INFO,FIFO_BUF,FIFO 'STATUS_A' read success,FIFO_BUF FIFO 'STATUS_A' read success,5
ERROR,FIFO_BUF,FIFO overflow detected,FIFO_BUF FIFO overflow detected,5
CRITICAL,MEM_CTRL,Memory controller state machine entered an assertion failure,MEM_CTRL Memory controller state machine entered an assertion failure,1
INFO,DMA_ENGINE,DMA channel 5 completion interrupt cleared,DMA_ENGINE DMA channel 5 completion interrupt cleared,3
INFO,INTERRUPT_CTRL,"Interrupt status register polled, no pending interrupts","INTERRUPT_CTRL Interrupt status register polled, no pending interrupts",1
ERROR,PCIE_CTRL,PCIe AER (Advanced Error Reporting) fatal error,PCIE_CTRL PCIe AER (Advanced Error Reporting) fatal error,6
INFO,PCIE_CTRL,PCIe endpoint configuration successful,PCIE_CTRL PCIe endpoint configuration successful,6
ERROR,MEM_CTRL,Write buffer data corruption,MEM_CTRL Write buffer data corruption,1
CRITICAL,PCIE_CTRL,PCIe link retraining attempts exhausted,PCIE_CTRL PCIe link retraining attempts exhausted,6
WARNING,CLOCK_MANAGER,Clock source switching latency high,CLOCK_MANAGER Clock source switching latency high,0
INFO,CACHE_CTRL,Cache prefetch request issued,CACHE_CTRL Cache prefetch request issued,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout after service routine,INTERRUPT_CTRL Interrupt acknowledge timeout after service routine,1
INFO,FIFO_BUF,FIFO full status cleared after reads,FIFO_BUF FIFO full status cleared after reads,5
WARNING,POWER_CTRL,Secondary power rail voltage fluctuating slightly,POWER_CTRL Secondary power rail voltage fluctuating slightly,4
ERROR,POWER_CTRL,Main power rail instability detected by PMIC,POWER_CTRL Main power rail instability detected by PMIC,4
WARNING,FIFO_BUF,"FIFO fill level at 90%, potential overflow imminent.","FIFO_BUF FIFO fill level at 90%, potential overflow imminent.",5
INFO,POWER_CTRL,Power state D3 entered,POWER_CTRL Power state D3 entered,4
INFO,DMA_ENGINE,DMA channel 1 in active transfer state,DMA_ENGINE DMA channel 1 in active transfer state,3
INFO,PCIE_CTRL,PCIe link width configured to x16,PCIE_CTRL PCIe link width configured to x16,6
CRITICAL,CLOCK_MANAGER,Clock domain crossing bridge experiencing metastability,CLOCK_MANAGER Clock domain crossing bridge experiencing metastability,0
WARNING,POWER_CTRL,Power consumption trending upwards significantly,POWER_CTRL Power consumption trending upwards significantly,4
WARNING,AXI_CTRL,AXI burst size requested exceeds recommended maximum,AXI_CTRL AXI burst size requested exceeds recommended maximum,2
WARNING,CLOCK_MANAGER,Global reset pulse width out of specification,CLOCK_MANAGER Global reset pulse width out of specification,-1
CRITICAL,DDR_CTRL,DDR memory interface protocol mismatch.,DDR_CTRL DDR memory interface protocol mismatch.,1
ERROR,MEM_CTRL,Memory controller detected a read-after-write hazard without forwarding,MEM_CTRL Memory controller detected a read-after-write hazard without forwarding,1
WARNING,CACHE_CTRL,Cache MSHR (Miss Status Handling Register) approaching full,CACHE_CTRL Cache MSHR (Miss Status Handling Register) approaching full,-1
WARNING,DMA_ENGINE,DMA channel 3 busy bit asserted for prolonged duration.,DMA_ENGINE DMA channel 3 busy bit asserted for prolonged duration.,3
WARNING,CLOCK_MANAGER,Clock jitter margin for SerDes clock reduced,CLOCK_MANAGER Clock jitter margin for SerDes clock reduced,0
INFO,AXI_CTRL,AXI outstanding transaction count returned to zero,AXI_CTRL AXI outstanding transaction count returned to zero,2
CRITICAL,MEM_CTRL,System memory map corruption,MEM_CTRL System memory map corruption,1
ERROR,CACHE_CTRL,Cache tag parity error detected in L1i,CACHE_CTRL Cache tag parity error detected in L1i,1
CRITICAL,DDR_CTRL,DDR read data capture window failure,DDR_CTRL DDR read data capture window failure,1
WARNING,MEM_CTRL,Single-bit ECC correction occurred at address 0x367F6,MEM_CTRL Single-bit ECC correction occurred at address 0x367F6,1
INFO,CACHE_CTRL,Cache line write-through to main memory,CACHE_CTRL Cache line write-through to main memory,1
WARNING,AXI_CTRL,AXI transaction timeout on M1 port nearing limit,AXI_CTRL AXI transaction timeout on M1 port nearing limit,2
CRITICAL,CACHE_CTRL,Cache coherence state machine entered invalid state,CACHE_CTRL Cache coherence state machine entered invalid state,1
ERROR,PCIE_CTRL,PCIE_CTRL detected a severe bus contention: multiple masters asserting bus ownership.,PCIE_CTRL PCIE_CTRL detected a severe bus contention: multiple masters asserting bus ownership.,2
WARNING,INTERRUPT_CTRL,Interrupt request line stuck high,INTERRUPT_CTRL Interrupt request line stuck high,1
INFO,FIFO_BUF,"FIFO nearing capacity, producer throttled","FIFO_BUF FIFO nearing capacity, producer throttled",5
WARNING,CACHE_CTRL,Cache line locking contention,CACHE_CTRL Cache line locking contention,1
ERROR,AXI_CTRL,AXI transaction ID Z timed out after 1000 cycles.,AXI_CTRL AXI transaction ID Z timed out after 1000 cycles.,2
WARNING,DMA_ENGINE,DMA channel 1 transfer completion status is ambiguous,DMA_ENGINE DMA channel 1 transfer completion status is ambiguous,3
INFO,CACHE_CTRL,Cache tag entry updated,CACHE_CTRL Cache tag entry updated,1
WARNING,PCIE_CTRL,PCIe retry buffer nearing capacity.,PCIE_CTRL PCIe retry buffer nearing capacity.,6
WARNING,FIFO_BUF,Input FIFO 'cmd_fifo' approaching empty threshold,FIFO_BUF Input FIFO 'cmd_fifo' approaching empty threshold,5
CRITICAL,DDR_CTRL,DDR multi-bit ECC uncorrectable error on bank 0,DDR_CTRL DDR multi-bit ECC uncorrectable error on bank 0,1
WARNING,DDR_CTRL,DDR controller command queue nearing maximum depth,DDR_CTRL DDR controller command queue nearing maximum depth,1
INFO,CLOCK_MANAGER,Clock output buffer strength adjusted,CLOCK_MANAGER Clock output buffer strength adjusted,0
INFO,DMA_ENGINE,Scatter-gather list processed,DMA_ENGINE Scatter-gather list processed,3
CRITICAL,DDR_CTRL,DRAM device returned invalid status during refresh,DDR_CTRL DRAM device returned invalid status during refresh,1
CRITICAL,PCIE_CTRL,"PCIe root complex communication failure, device isolated (controller 0x0)","PCIE_CTRL PCIe root complex communication failure, device isolated (controller 0x0)",6
ERROR,AXI_CTRL,AXI master GPU issued unaligned access to 0x12345678.,AXI_CTRL AXI master GPU issued unaligned access to 0x12345678.,-1
CRITICAL,INTERRUPT_CTRL,"CRITICAL: Interrupt controller unable to process pending interrupts, system unresponsive.","INTERRUPT_CTRL CRITICAL: Interrupt controller unable to process pending interrupts, system unresponsive.",1
INFO,MEM_CTRL,Memory controller idle,MEM_CTRL Memory controller idle,1
INFO,AXI_CTRL,AXI read transaction completed successfully,AXI_CTRL AXI read transaction completed successfully,2
INFO,PCIE_CTRL,PCIe root complex received request,PCIE_CTRL PCIe root complex received request,6
ERROR,FIFO_BUF,FIFO data output stuck at previous value,FIFO_BUF FIFO data output stuck at previous value,5
ERROR,CLOCK_MANAGER,Asynchronous reset propagation failure,CLOCK_MANAGER Asynchronous reset propagation failure,0
WARNING,DDR_CTRL,DDR bus turnaround time exceeding limit,DDR_CTRL DDR bus turnaround time exceeding limit,1
ERROR,INTERRUPT_CTRL,Interrupt vector table corrupted during update,INTERRUPT_CTRL Interrupt vector table corrupted during update,1
ERROR,FIFO_BUF,"FIFO 'ethernet_rx' synchronization error detected, dropped packets","FIFO_BUF FIFO 'ethernet_rx' synchronization error detected, dropped packets",-1
INFO,AXI_CTRL,AXI slave responded with 'OKAY' for write transaction,AXI_CTRL AXI slave responded with 'OKAY' for write transaction,2
CRITICAL,POWER_CTRL,Power rail instability detected,POWER_CTRL Power rail instability detected,4
ERROR,PCIE_CTRL,PCIe device enumeration failure,PCIE_CTRL PCIe device enumeration failure,6
ERROR,AXI_CTRL,AXI master 0x0C observed multiple RRESP errors.,AXI_CTRL AXI master 0x0C observed multiple RRESP errors.,2
CRITICAL,DMA_ENGINE,"DMA engine register write detected incorrect value, critical fault","DMA_ENGINE DMA engine register write detected incorrect value, critical fault",3
CRITICAL,DDR_CTRL,DDR calibration loop failed to stabilize,DDR_CTRL DDR calibration loop failed to stabilize,1
ERROR,POWER_CTRL,Power distribution network integrity check failed.,POWER_CTRL Power distribution network integrity check failed.,-1
WARNING,POWER_CTRL,Power draw spike detected on main bus,POWER_CTRL Power draw spike detected on main bus,4
ERROR,DDR_CTRL,DDR DRAM chip 'U2' failed to respond to refresh command,DDR_CTRL DDR DRAM chip 'U2' failed to respond to refresh command,1
INFO,FIFO_BUF,Write operation to FIFO_BUF_0 successful,FIFO_BUF Write operation to FIFO_BUF_0 successful,5
ERROR,AXI_CTRL,"AXI_CTRL encountered an unexpected bus contention event (drive conflict on bus). (Master ID: 1, AXI ID: 2)","AXI_CTRL AXI_CTRL encountered an unexpected bus contention event (drive conflict on bus). (Master ID: 1, AXI ID: 2)",2
ERROR,FIFO_BUF,FIFO read without available data (underflow condition).,FIFO_BUF FIFO read without available data (underflow condition).,5
CRITICAL,CLOCK_MANAGER,Main system clock input signal loss detected,CLOCK_MANAGER Main system clock input signal loss detected,0
CRITICAL,MEM_CTRL,Memory scrub operation reported persistent ECC errors,MEM_CTRL Memory scrub operation reported persistent ECC errors,1
INFO,FIFO_BUF,FIFO full status cleared,FIFO_BUF FIFO full status cleared,5
WARNING,DMA_ENGINE,DMA descriptor chain length exceeding recommended value,DMA_ENGINE DMA descriptor chain length exceeding recommended value,3
INFO,AXI_CTRL,AXI master access granted after arbitration,AXI_CTRL AXI master access granted after arbitration,2
ERROR,DDR_CTRL,DDR initialization sequence failure,DDR_CTRL DDR initialization sequence failure,1
INFO,CLOCK_MANAGER,Clock gating for peripheral 'X' enabled,CLOCK_MANAGER Clock gating for peripheral 'X' enabled,0
INFO,INTERRUPT_CTRL,Interrupt 6 (GPIO) pending,INTERRUPT_CTRL Interrupt 6 (GPIO) pending,1
ERROR,AXI_CTRL,"AXI burst length violation detected on write channel, expected 8, got 10","AXI_CTRL AXI burst length violation detected on write channel, expected 8, got 10",2
ERROR,DMA_ENGINE,DMA internal buffer overflow,DMA_ENGINE DMA internal buffer overflow,3
INFO,AXI_CTRL,AXI read burst initiated on master 0,AXI_CTRL AXI read burst initiated on master 0,2
INFO,POWER_CTRL,Power rail 1.0V enabled,POWER_CTRL Power rail 1.0V enabled,4
WARNING,DMA_ENGINE,DMA transfer completion signal asserted prematurely,DMA_ENGINE DMA transfer completion signal asserted prematurely,3
WARNING,DMA_ENGINE,DMA latency increasing under high system load.,DMA_ENGINE DMA latency increasing under high system load.,3
CRITICAL,FIFO_BUF,FIFO read/write pointer deadlock,FIFO_BUF FIFO read/write pointer deadlock,5
ERROR,CACHE_CTRL,Cache TLB entry invalidation failure,CACHE_CTRL Cache TLB entry invalidation failure,1
WARNING,DMA_ENGINE,DMA channel priority override detected,DMA_ENGINE DMA channel priority override detected,3
ERROR,MEM_CTRL,Memory controller arbitration deadlock between two masters,MEM_CTRL Memory controller arbitration deadlock between two masters,1
INFO,CLOCK_MANAGER,Phase-Locked Loop (PLL) locked successfully,CLOCK_MANAGER Phase-Locked Loop (PLL) locked successfully,0
ERROR,CACHE_CTRL,Cache directory lookup failure for address 0x12345678.,CACHE_CTRL Cache directory lookup failure for address 0x12345678.,1
WARNING,FIFO_BUF,"FIFO almost full condition asserted, nearing overflow","FIFO_BUF FIFO almost full condition asserted, nearing overflow",5
WARNING,DDR_CTRL,DDR read data hold time violation nearing critical limit,DDR_CTRL DDR read data hold time violation nearing critical limit,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller hardware fault detected,INTERRUPT_CTRL Interrupt controller hardware fault detected,1
ERROR,CACHE_CTRL,Cache controller internal bus contention,CACHE_CTRL Cache controller internal bus contention,1
WARNING,PCIE_CTRL,PCIe transaction layer CRC error count incrementing,PCIE_CTRL PCIe transaction layer CRC error count incrementing,6
ERROR,PCIE_CTRL,PCIe link training sequence failed,PCIE_CTRL PCIe link training sequence failed,6
ERROR,MEM_CTRL,Memory address alignment violation on write to 0x10000003,MEM_CTRL Memory address alignment violation on write to 0x10000003,1
INFO,FIFO_BUF,FIFO 'tx_buffer' has 100 entries available,FIFO_BUF FIFO 'tx_buffer' has 100 entries available,5
CRITICAL,MEM_CTRL,Uncorrectable ECC error detected on memory bank 0,MEM_CTRL Uncorrectable ECC error detected on memory bank 0,1
INFO,DDR_CTRL,DDR training sequence passed,DDR_CTRL DDR training sequence passed,1
ERROR,MEM_CTRL,Memory controller received an illegal command sequence,MEM_CTRL Memory controller received an illegal command sequence,1
ERROR,DMA_ENGINE,DMA channel 3 transfer length register mismatch,DMA_ENGINE DMA channel 3 transfer length register mismatch,3
INFO,CACHE_CTRL,L2 cache coherence mechanism enabled,CACHE_CTRL L2 cache coherence mechanism enabled,1
INFO,CLOCK_MANAGER,PLL frequency stable at 1GHz,CLOCK_MANAGER PLL frequency stable at 1GHz,0
INFO,PCIE_CTRL,PCIe root complex received configuration write,PCIE_CTRL PCIe root complex received configuration write,6
WARNING,INTERRUPT_CTRL,Interrupt line 'Timer_0' deasserted too quickly,INTERRUPT_CTRL Interrupt line 'Timer_0' deasserted too quickly,1
WARNING,POWER_CTRL,Voltage rail 1.2V fluctuating,POWER_CTRL Voltage rail 1.2V fluctuating,4
ERROR,PCIE_CTRL,PCIe endpoint received malformed TLP header.,PCIE_CTRL PCIe endpoint received malformed TLP header.,6
CRITICAL,DMA_ENGINE,"CRITICAL: DMA engine deadlocked, all channels unresponsive (channel 0).","DMA_ENGINE CRITICAL: DMA engine deadlocked, all channels unresponsive (channel 0).",3
WARNING,CACHE_CTRL,L1 data cache write-back buffer approaching full,CACHE_CTRL L1 data cache write-back buffer approaching full,1
ERROR,FIFO_BUF,FIFO 'debug_log' write pointer advanced past read pointer without data,FIFO_BUF FIFO 'debug_log' write pointer advanced past read pointer without data,5
ERROR,MEM_CTRL,Memory controller detected unaligned read access,MEM_CTRL Memory controller detected unaligned read access,1
INFO,DMA_ENGINE,DMA channel priorities re-ordered,DMA_ENGINE DMA channel priorities re-ordered,3
INFO,FIFO_BUF,FIFO 'data_in_fifo' current fill level: 128 entries,FIFO_BUF FIFO 'data_in_fifo' current fill level: 128 entries,5
ERROR,PCIE_CTRL,PCIE_CTRL: deadlock detected - circular dependency stall detected.,PCIE_CTRL PCIE_CTRL: deadlock detected - circular dependency stall detected.,-1
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal hardware fault,INTERRUPT_CTRL Interrupt controller internal hardware fault,1
CRITICAL,PCIE_CTRL,PCIe fatal error: physical layer issue,PCIE_CTRL PCIe fatal error: physical layer issue,6
ERROR,FIFO_BUF,"FIFO read operation failed, data unavailable","FIFO_BUF FIFO read operation failed, data unavailable",5
CRITICAL,DDR_CTRL,"DDR memory training sequence failed, unrecoverable memory access","DDR_CTRL DDR memory training sequence failed, unrecoverable memory access",1
ERROR,DMA_ENGINE,DMA transfer terminated by internal error,DMA_ENGINE DMA transfer terminated by internal error,3
CRITICAL,POWER_CTRL,"Power sequence initiation failed, stuck in reset","POWER_CTRL Power sequence initiation failed, stuck in reset",4
ERROR,INTERRUPT_CTRL,Interrupt priority inversion detected for IRQ 12,INTERRUPT_CTRL Interrupt priority inversion detected for IRQ 12,1
WARNING,DDR_CTRL,DDR read latency increasing,DDR_CTRL DDR read latency increasing,1
ERROR,POWER_CTRL,Power rail integrity check failed,POWER_CTRL Power rail integrity check failed,4
INFO,AXI_CTRL,AXI read burst completed,AXI_CTRL AXI read burst completed,2
CRITICAL,INTERRUPT_CTRL,Global interrupt controller became unresponsive,INTERRUPT_CTRL Global interrupt controller became unresponsive,1
INFO,DDR_CTRL,DDR memory training completed successfully with optimal timings.,DDR_CTRL DDR memory training completed successfully with optimal timings.,1
WARNING,CACHE_CTRL,"Cache miss rate exceeding expected threshold, performance impact.","CACHE_CTRL Cache miss rate exceeding expected threshold, performance impact.",1
ERROR,FIFO_BUF,FIFO almost full condition ignored by writer,FIFO_BUF FIFO almost full condition ignored by writer,5
CRITICAL,MEM_CTRL,Uncorrectable double-bit ECC error on memory bank 0,MEM_CTRL Uncorrectable double-bit ECC error on memory bank 0,1
INFO,DDR_CTRL,DDR BIST passed with no errors,DDR_CTRL DDR BIST passed with no errors,1
INFO,MEM_CTRL,Memory controller state machine in idle state,MEM_CTRL Memory controller state machine in idle state,1
ERROR,FIFO_BUF,FIFO full condition detected during write operation,FIFO_BUF FIFO full condition detected during write operation,5
WARNING,INTERRUPT_CTRL,Interrupt acknowledge latency exceeding threshold,INTERRUPT_CTRL Interrupt acknowledge latency exceeding threshold,1
WARNING,PCIE_CTRL,PCIe transmit buffer approaching low water mark,PCIE_CTRL PCIe transmit buffer approaching low water mark,-1
INFO,DDR_CTRL,DDR low power mode entered,DDR_CTRL DDR low power mode entered,1
INFO,FIFO_BUF,Read pointer advanced for FIFO,FIFO_BUF Read pointer advanced for FIFO,5
INFO,DDR_CTRL,DDR timing parameters updated,DDR_CTRL DDR timing parameters updated,1
CRITICAL,DDR_CTRL,DDR memory self-refresh mode entry failure,DDR_CTRL DDR memory self-refresh mode entry failure,1
ERROR,INTERRUPT_CTRL,Software interrupt vector table corruption detected,INTERRUPT_CTRL Software interrupt vector table corruption detected,1
WARNING,FIFO_BUF,"FIFO nearly full, capacity at 85%","FIFO_BUF FIFO nearly full, capacity at 85%",5
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected for channel 6,DMA_ENGINE DMA buffer pointer corruption detected for channel 6,3
WARNING,MEM_CTRL,Read-modify-write operation pending.,MEM_CTRL Read-modify-write operation pending.,1
WARNING,DMA_ENGINE,DMA engine unable to allocate requested bandwidth,DMA_ENGINE DMA engine unable to allocate requested bandwidth,3
ERROR,INTERRUPT_CTRL,"Interrupt vector table corrupted, spurious interrupt detected","INTERRUPT_CTRL Interrupt vector table corrupted, spurious interrupt detected",1
CRITICAL,CLOCK_MANAGER,Main system clock derived from unstable source,CLOCK_MANAGER Main system clock derived from unstable source,0
INFO,DDR_CTRL,"DDR memory training complete, 1600 MHz","DDR_CTRL DDR memory training complete, 1600 MHz",1
ERROR,INTERRUPT_CTRL,Interrupt controller hardware watchdog timeout,INTERRUPT_CTRL Interrupt controller hardware watchdog timeout,1
INFO,DMA_ENGINE,DMA channel paused by software,DMA_ENGINE DMA channel paused by software,3
INFO,CACHE_CTRL,Cache line allocated for new data,CACHE_CTRL Cache line allocated for new data,1
WARNING,PCIE_CTRL,PCIe replay buffer nearly full,PCIE_CTRL PCIe replay buffer nearly full,6
ERROR,PCIE_CTRL,PCIe DLLP sequence error detected,PCIE_CTRL PCIe DLLP sequence error detected,6
WARNING,CLOCK_MANAGER,"Clock gating efficiency reduced, potential power impact","CLOCK_MANAGER Clock gating efficiency reduced, potential power impact",-1
INFO,AXI_CTRL,AXI slave responded with OKAY,AXI_CTRL AXI slave responded with OKAY,2
ERROR,INTERRUPT_CTRL,Unhandled critical interrupt vector,INTERRUPT_CTRL Unhandled critical interrupt vector,1
ERROR,INTERRUPT_CTRL,Interrupt priority level inversion observed for critical event,INTERRUPT_CTRL Interrupt priority level inversion observed for critical event,1
INFO,INTERRUPT_CTRL,Interrupt dispatch for IRQ_GPIO_1 successful,INTERRUPT_CTRL Interrupt dispatch for IRQ_GPIO_1 successful,1
ERROR,AXI_CTRL,AXI read address (ARADDR) issued to non-existent slave.,AXI_CTRL AXI read address (ARADDR) issued to non-existent slave.,2
ERROR,DMA_ENGINE,DMA descriptor fetch address invalid,DMA_ENGINE DMA descriptor fetch address invalid,3
ERROR,POWER_CTRL,Power controller state machine entered invalid state.,POWER_CTRL Power controller state machine entered invalid state.,4
ERROR,POWER_CTRL,Power rail instability detected,POWER_CTRL Power rail instability detected,4
ERROR,POWER_CTRL,Voltage regulator response time for VDD_MEM rail out of spec.,POWER_CTRL Voltage regulator response time for VDD_MEM rail out of spec.,-1
ERROR,PCIE_CTRL,PCIe link training failure detected (phase 6).,PCIE_CTRL PCIe link training failure detected (phase 6).,6
INFO,INTERRUPT_CTRL,Interrupt priority level 4 configured,INTERRUPT_CTRL Interrupt priority level 4 configured,1
INFO,POWER_CTRL,Core power domain entered sleep state,POWER_CTRL Core power domain entered sleep state,4
WARNING,CACHE_CTRL,"Cache line snoop hit on dirty line, potential race condition","CACHE_CTRL Cache line snoop hit on dirty line, potential race condition",1
ERROR,PCIE_CTRL,PCIe packet framing error detected on incoming TLP.,PCIE_CTRL PCIe packet framing error detected on incoming TLP.,6
INFO,PCIE_CTRL,PCIe link speed configured to Gen4,PCIE_CTRL PCIe link speed configured to Gen4,6
INFO,AXI_CTRL,AXI burst write to memory initiated,AXI_CTRL AXI burst write to memory initiated,2
INFO,POWER_CTRL,Regulator V_IO enabled,POWER_CTRL Regulator V_IO enabled,4
CRITICAL,DDR_CTRL,DDR PHY training logic stuck,DDR_CTRL DDR PHY training logic stuck,1
ERROR,AXI_CTRL,AXI read response SLVERR received for critical transaction.,AXI_CTRL AXI read response SLVERR received for critical transaction.,2
WARNING,PCIE_CTRL,PCIe error reporting mechanism triggered for uncorrected error,PCIE_CTRL PCIe error reporting mechanism triggered for uncorrected error,6
CRITICAL,AXI_CTRL,AXI master 11 issued illegal address 0xef10156d.,AXI_CTRL AXI master 11 issued illegal address 0xef10156d.,2
INFO,CLOCK_MANAGER,Clock frequency scaled to 1601 MHz,CLOCK_MANAGER Clock frequency scaled to 1601 MHz,0
INFO,AXI_CTRL,AXI response received with user-defined sideband signal.,AXI_CTRL AXI response received with user-defined sideband signal.,-1
ERROR,AXI_CTRL,AXI protocol violation - Multiple masters asserting same ID,AXI_CTRL AXI protocol violation - Multiple masters asserting same ID,2
CRITICAL,DDR_CTRL,"DDR training sequence repeatedly failing, memory uncalibrated","DDR_CTRL DDR training sequence repeatedly failing, memory uncalibrated",1
ERROR,DDR_CTRL,DDR burst integrity check failed for write transaction,DDR_CTRL DDR burst integrity check failed for write transaction,1
CRITICAL,CLOCK_MANAGER,Global reset asserted due to clock monitor trip,CLOCK_MANAGER Global reset asserted due to clock monitor trip,0
ERROR,DMA_ENGINE,DMA transfer completion transaction timeout.,DMA_ENGINE DMA transfer completion transaction timeout.,3
INFO,FIFO_BUF,Data written to FIFO successfully,FIFO_BUF Data written to FIFO successfully,5
WARNING,MEM_CTRL,Memory refresh interval approaching limit,MEM_CTRL Memory refresh interval approaching limit,1
ERROR,FIFO_BUF,FIFO synchronization error on clock domain crossing,FIFO_BUF FIFO synchronization error on clock domain crossing,5
INFO,POWER_CTRL,Power domain entered active state,POWER_CTRL Power domain entered active state,4
WARNING,AXI_CTRL,AXI_CTRL internal buffer approaching capacity (93% full).,AXI_CTRL AXI_CTRL internal buffer approaching capacity (93% full).,-1
INFO,POWER_CTRL,Voltage rail X stabilized,POWER_CTRL Voltage rail X stabilized,4
INFO,DMA_ENGINE,DMA transfer for channel 1 started,DMA_ENGINE DMA transfer for channel 1 started,3
INFO,CACHE_CTRL,Cache prefetcher engaged,CACHE_CTRL Cache prefetcher engaged,1
WARNING,CLOCK_MANAGER,Clock domain crossing status warning,CLOCK_MANAGER Clock domain crossing status warning,0
ERROR,FIFO_BUF,FIFO empty status asserted incorrectly,FIFO_BUF FIFO empty status asserted incorrectly,5
INFO,MEM_CTRL,Memory test pattern 0x55AA55AA passed,MEM_CTRL Memory test pattern 0x55AA55AA passed,1
INFO,PCIE_CTRL,PCIe hot-plug event processed,PCIE_CTRL PCIe hot-plug event processed,6
WARNING,DDR_CTRL,DDR command reordering causing timing violations,DDR_CTRL DDR command reordering causing timing violations,1
INFO,DDR_CTRL,DDR controller initiated power-down sequence,DDR_CTRL DDR controller initiated power-down sequence,1
CRITICAL,MEM_CTRL,Uncorrectable ECC error on address 0xDEADBEEF,MEM_CTRL Uncorrectable ECC error on address 0xDEADBEEF,1
ERROR,DDR_CTRL,Memory address alignment fault in DDR access.,DDR_CTRL Memory address alignment fault in DDR access.,1
INFO,DMA_ENGINE,DMA transfer paused for external request,DMA_ENGINE DMA transfer paused for external request,3
WARNING,PCIE_CTRL,PCIe flow control credits approaching zero for VC0,PCIE_CTRL PCIe flow control credits approaching zero for VC0,6
INFO,AXI_CTRL,AXI transaction ID 0x5 completed,AXI_CTRL AXI transaction ID 0x5 completed,2
ERROR,CLOCK_MANAGER,External clock input signal lost,CLOCK_MANAGER External clock input signal lost,0
ERROR,AXI_CTRL,AXI outstanding read limit exceeded,AXI_CTRL AXI outstanding read limit exceeded,2
WARNING,POWER_CTRL,POWER_CTRL encountered a minor timing deviation.,POWER_CTRL POWER_CTRL encountered a minor timing deviation.,4
INFO,FIFO_BUF,FIFO_SENSOR_DATA write successful,FIFO_BUF FIFO_SENSOR_DATA write successful,5
INFO,MEM_CTRL,Memory test completed with no errors,MEM_CTRL Memory test completed with no errors,1
INFO,DMA_ENGINE,DMA channel 1 paused,DMA_ENGINE DMA channel 1 paused,3
INFO,DMA_ENGINE,DMA transfer completed successfully,DMA_ENGINE DMA transfer completed successfully,3
WARNING,MEM_CTRL,Memory block X refresh pending,MEM_CTRL Memory block X refresh pending,1
ERROR,FIFO_BUF,"FIFO_DMA_TX full condition detected, blocking writes","FIFO_BUF FIFO_DMA_TX full condition detected, blocking writes",5
INFO,INTERRUPT_CTRL,Interrupt pending status cleared,INTERRUPT_CTRL Interrupt pending status cleared,1
CRITICAL,CACHE_CTRL,"Cache directory corruption detected, critical data inconsistency","CACHE_CTRL Cache directory corruption detected, critical data inconsistency",1
WARNING,FIFO_BUF,FIFO output data valid signal stuck,FIFO_BUF FIFO output data valid signal stuck,5
WARNING,MEM_CTRL,Memory refresh scheduling delayed by high priority transaction.,MEM_CTRL Memory refresh scheduling delayed by high priority transaction.,1
CRITICAL,MEM_CTRL,Memory controller encountered unexpected protocol violation on data path,MEM_CTRL Memory controller encountered unexpected protocol violation on data path,1
ERROR,PCIE_CTRL,PCIe link width negotiation failure,PCIE_CTRL PCIe link width negotiation failure,6
CRITICAL,AXI_CTRL,AXI read transaction responded with EXOKAY but data corrupt,AXI_CTRL AXI read transaction responded with EXOKAY but data corrupt,2
INFO,CACHE_CTRL,L2 cache invalidation completed,CACHE_CTRL L2 cache invalidation completed,1
WARNING,INTERRUPT_CTRL,Interrupt pending register shows unmasked interrupt,INTERRUPT_CTRL Interrupt pending register shows unmasked interrupt,1
WARNING,INTERRUPT_CTRL,Interrupt controller internal FSM in abnormal state,INTERRUPT_CTRL Interrupt controller internal FSM in abnormal state,1
INFO,PCIE_CTRL,PCIe device configuration space access successful,PCIE_CTRL PCIe device configuration space access successful,6
INFO,POWER_CTRL,Power domain GFX switched to low-power state,POWER_CTRL Power domain GFX switched to low-power state,4
INFO,DMA_ENGINE,DMA_ENGINE monitoring initiated.,DMA_ENGINE DMA_ENGINE monitoring initiated.,3
CRITICAL,CACHE_CTRL,Cache coherence deadlock detected between CPU cores,CACHE_CTRL Cache coherence deadlock detected between CPU cores,1
ERROR,AXI_CTRL,AXI transaction ID mismatch on response,AXI_CTRL AXI transaction ID mismatch on response,2
ERROR,MEM_CTRL,Data corruption detected during memory block copy.,MEM_CTRL Data corruption detected during memory block copy.,1
INFO,MEM_CTRL,Memory page 0xABCD0000 marked as clean,MEM_CTRL Memory page 0xABCD0000 marked as clean,1
INFO,CLOCK_MANAGER,Secondary clock source validation complete,CLOCK_MANAGER Secondary clock source validation complete,0
WARNING,AXI_CTRL,AXI read address channel backpressure asserted by slave,AXI_CTRL AXI read address channel backpressure asserted by slave,2
ERROR,POWER_CTRL,Core voltage rail sags below operational tolerance,POWER_CTRL Core voltage rail sags below operational tolerance,4
WARNING,DDR_CTRL,DDR auto-refresh interval deviation,DDR_CTRL DDR auto-refresh interval deviation,1
WARNING,PCIE_CTRL,PCIe credit depletion warning,PCIE_CTRL PCIe credit depletion warning,6
INFO,POWER_CTRL,Voltage regulator in bypass mode,POWER_CTRL Voltage regulator in bypass mode,4
ERROR,MEM_CTRL,Memory byte lane 3 always reads zero,MEM_CTRL Memory byte lane 3 always reads zero,1
CRITICAL,MEM_CTRL,Memory controller ECC scrubbing disabled unexpectedly,MEM_CTRL Memory controller ECC scrubbing disabled unexpectedly,1
WARNING,DMA_ENGINE,"DMA engine idle for extended period (10 cycles), check for pending transfers.","DMA_ENGINE DMA engine idle for extended period (10 cycles), check for pending transfers.",3
INFO,POWER_CTRL,Power domain CPU exited reset,POWER_CTRL Power domain CPU exited reset,4
ERROR,CACHE_CTRL,L1 cache invalidation coherence failure,CACHE_CTRL L1 cache invalidation coherence failure,1
WARNING,DMA_ENGINE,DMA transfer size not aligned to burst length,DMA_ENGINE DMA transfer size not aligned to burst length,3
INFO,CACHE_CTRL,L3 cache statistics collected,CACHE_CTRL L3 cache statistics collected,1
INFO,AXI_CTRL,AXI read operation successful,AXI_CTRL AXI read operation successful,2
WARNING,POWER_CTRL,Core voltage fluctuating slightly (1.0V +/- 50mV),POWER_CTRL Core voltage fluctuating slightly (1.0V +/- 50mV),4
WARNING,FIFO_BUF,FIFO write operation blocked by external backpressure,FIFO_BUF FIFO write operation blocked by external backpressure,5
INFO,FIFO_BUF,FIFO 'CONTROL' register written,FIFO_BUF FIFO 'CONTROL' register written,5
WARNING,FIFO_BUF,FIFO high watermark reached for the third time,FIFO_BUF FIFO high watermark reached for the third time,5
INFO,CACHE_CTRL,Cache coherence unit reinitialized,CACHE_CTRL Cache coherence unit reinitialized,1
INFO,DDR_CTRL,DDR memory temperature within operational limits,DDR_CTRL DDR memory temperature within operational limits,1
WARNING,CACHE_CTRL,"Cache dirty line count increasing, potential write-back stall","CACHE_CTRL Cache dirty line count increasing, potential write-back stall",1
WARNING,PCIE_CTRL,PCIe lane re-training initiated due to CRC errors,PCIE_CTRL PCIe lane re-training initiated due to CRC errors,6
INFO,AXI_CTRL,AXI master 'gpu_core' successfully performed a read burst,AXI_CTRL AXI master 'gpu_core' successfully performed a read burst,2
ERROR,POWER_CTRL,Power state machine stuck in intermediate state,POWER_CTRL Power state machine stuck in intermediate state,4
INFO,INTERRUPT_CTRL,IRQ 0 registered and enabled,INTERRUPT_CTRL IRQ 0 registered and enabled,1
ERROR,DDR_CTRL,Memory timing parameter violation,DDR_CTRL Memory timing parameter violation,1
ERROR,CACHE_CTRL,Cache eviction policy violation,CACHE_CTRL Cache eviction policy violation,1
CRITICAL,DMA_ENGINE,DMA engine entered a permanent halted state due to internal error,DMA_ENGINE DMA engine entered a permanent halted state due to internal error,3
WARNING,CACHE_CTRL,L1 instruction cache hit rate slightly below target,CACHE_CTRL L1 instruction cache hit rate slightly below target,1
ERROR,DDR_CTRL,"DDR read latency unexpectedly high, exceeding 100 cycles.","DDR_CTRL DDR read latency unexpectedly high, exceeding 100 cycles.",1
CRITICAL,PCIE_CTRL,PCIe root complex detected unrecoverable link error,PCIE_CTRL PCIe root complex detected unrecoverable link error,6
ERROR,AXI_CTRL,AXI write address channel setup timing violation,AXI_CTRL AXI write address channel setup timing violation,2
INFO,DDR_CTRL,DDR memory training steps completed,DDR_CTRL DDR memory training steps completed,1
WARNING,INTERRUPT_CTRL,Interrupt dispatch latency increasing,INTERRUPT_CTRL Interrupt dispatch latency increasing,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout detected.,INTERRUPT_CTRL Interrupt acknowledge timeout detected.,1
CRITICAL,DDR_CTRL,DDR memory controller failed to achieve stable clocking.,DDR_CTRL DDR memory controller failed to achieve stable clocking.,1
WARNING,CLOCK_MANAGER,Watchdog timer close to reset,CLOCK_MANAGER Watchdog timer close to reset,-1
WARNING,DMA_ENGINE,DMA burst size configured exceeds maximum,DMA_ENGINE DMA burst size configured exceeds maximum,3
INFO,MEM_CTRL,Read request to memory address 0x1000 completed,MEM_CTRL Read request to memory address 0x1000 completed,1
WARNING,DMA_ENGINE,DMA channel prefetch buffer empty,DMA_ENGINE DMA channel prefetch buffer empty,3
WARNING,AXI_CTRL,AXI bridge buffer occupancy high,AXI_CTRL AXI bridge buffer occupancy high,-1
WARNING,DMA_ENGINE,DMA channel 0 descriptor fetch latency exceeding expected threshold.,DMA_ENGINE DMA channel 0 descriptor fetch latency exceeding expected threshold.,3
INFO,MEM_CTRL,Memory self-test passed,MEM_CTRL Memory self-test passed,1
WARNING,MEM_CTRL,Page table walk depth exceeding threshold,MEM_CTRL Page table walk depth exceeding threshold,-1
ERROR,CLOCK_MANAGER,Clock domain crossing handshake failure (data loss),CLOCK_MANAGER Clock domain crossing handshake failure (data loss),0
WARNING,DMA_ENGINE,DMA access to peripheral bridge exhibiting high contention.,DMA_ENGINE DMA access to peripheral bridge exhibiting high contention.,-1
ERROR,DMA_ENGINE,DMA channel deadlock,DMA_ENGINE DMA channel deadlock,3
CRITICAL,POWER_CTRL,Core voltage rail under-voltage causing processor reset,POWER_CTRL Core voltage rail under-voltage causing processor reset,4
CRITICAL,DDR_CTRL,"DDR memory rank unrecoverable, system cannot boot.","DDR_CTRL DDR memory rank unrecoverable, system cannot boot.",1
INFO,DDR_CTRL,DDR memory temperature within limits,DDR_CTRL DDR memory temperature within limits,1
WARNING,INTERRUPT_CTRL,Interrupt acknowledge timeout from CPU for IRQ_N,INTERRUPT_CTRL Interrupt acknowledge timeout from CPU for IRQ_N,1
WARNING,PCIE_CTRL,PCIe AER (Advanced Error Reporting) queue nearing capacity,PCIE_CTRL PCIe AER (Advanced Error Reporting) queue nearing capacity,6
INFO,DDR_CTRL,DDR refresh scheduling optimized,DDR_CTRL DDR refresh scheduling optimized,1
INFO,POWER_CTRL,Power domain reset successfully completed,POWER_CTRL Power domain reset successfully completed,4
INFO,INTERRUPT_CTRL,Interrupt handler registered for GPIO event,INTERRUPT_CTRL Interrupt handler registered for GPIO event,1
INFO,PCIE_CTRL,TLP received and forwarded to target.,PCIE_CTRL TLP received and forwarded to target.,6
WARNING,DMA_ENGINE,DMA descriptor queue depth exceeding threshold,DMA_ENGINE DMA descriptor queue depth exceeding threshold,3
ERROR,CACHE_CTRL,Cache line protection violation,CACHE_CTRL Cache line protection violation,1
ERROR,INTERRUPT_CTRL,Interrupt controller internal watchdog timeout,INTERRUPT_CTRL Interrupt controller internal watchdog timeout,1
WARNING,FIFO_BUF,Read-ahead buffer 2 nearing capacity.,FIFO_BUF Read-ahead buffer 2 nearing capacity.,5
INFO,FIFO_BUF,FIFO initialized to empty state,FIFO_BUF FIFO initialized to empty state,5
WARNING,INTERRUPT_CTRL,Interrupt controller received multiple identical IRQs without clear.,INTERRUPT_CTRL Interrupt controller received multiple identical IRQs without clear.,1
WARNING,DDR_CTRL,"DDR_CTRL configuration change in DDR_CTRL detected, monitoring performance.","DDR_CTRL DDR_CTRL configuration change in DDR_CTRL detected, monitoring performance.",1
CRITICAL,DMA_ENGINE,DMA controller internal bus error,DMA_ENGINE DMA controller internal bus error,3
INFO,CLOCK_MANAGER,"Frequency scaling applied successfully, core at 800MHz.","CLOCK_MANAGER Frequency scaling applied successfully, core at 800MHz.",0
CRITICAL,AXI_CTRL,AXI transaction ID collision detected on multiple masters,AXI_CTRL AXI transaction ID collision detected on multiple masters,2
WARNING,CACHE_CTRL,Cache fill buffer occupancy high,CACHE_CTRL Cache fill buffer occupancy high,1
WARNING,FIFO_BUF,FIFO internal read pointer value invalid,FIFO_BUF FIFO internal read pointer value invalid,5
ERROR,DMA_ENGINE,DMA descriptor chain integrity check failed for channel 1.,DMA_ENGINE DMA descriptor chain integrity check failed for channel 1.,3
CRITICAL,POWER_CTRL,Power management unit critical fault,POWER_CTRL Power management unit critical fault,4
CRITICAL,FIFO_BUF,FIFO reset sequence failed to clear all data,FIFO_BUF FIFO reset sequence failed to clear all data,5
ERROR,DDR_CTRL,"DDR memory bank conflict detected, potential data corruption","DDR_CTRL DDR memory bank conflict detected, potential data corruption",1
ERROR,DMA_ENGINE,DMA channel transfer count mismatch,DMA_ENGINE DMA channel transfer count mismatch,3
INFO,DMA_ENGINE,DMA engine initialized and self-test passed,DMA_ENGINE DMA engine initialized and self-test passed,3
ERROR,AXI_CTRL,AXI response channel SLVERR received from peripheral,AXI_CTRL AXI response channel SLVERR received from peripheral,2
INFO,MEM_CTRL,Memory refresh policy set to aggressive,MEM_CTRL Memory refresh policy set to aggressive,1
WARNING,AXI_CTRL,AXI write response channel BVALID asserted without BREADY,AXI_CTRL AXI write response channel BVALID asserted without BREADY,2
ERROR,DDR_CTRL,DDR write data strobe (DQS) calibration failed,DDR_CTRL DDR write data strobe (DQS) calibration failed,1
ERROR,MEM_CTRL,Memory controller entered invalid state,MEM_CTRL Memory controller entered invalid state,1
INFO,AXI_CTRL,AXI outstanding transactions cleared,AXI_CTRL AXI outstanding transactions cleared,2
INFO,POWER_CTRL,System entered low power state L1,POWER_CTRL System entered low power state L1,4
INFO,CLOCK_MANAGER,Clock frequency scaling initiated,CLOCK_MANAGER Clock frequency scaling initiated,0
CRITICAL,INTERRUPT_CTRL,"Critical interrupt (NMI) unserviced for too long, system halt imminent","INTERRUPT_CTRL Critical interrupt (NMI) unserviced for too long, system halt imminent",-1
INFO,FIFO_BUF,FIFO_BUF_3 flushed successfully,FIFO_BUF FIFO_BUF_3 flushed successfully,5
WARNING,CLOCK_MANAGER,Clock source switching latency exceeds tolerance,CLOCK_MANAGER Clock source switching latency exceeds tolerance,0
INFO,MEM_CTRL,Memory ECC scrub initiated,MEM_CTRL Memory ECC scrub initiated,1
WARNING,DMA_ENGINE,DMA channel prefetch buffer nearing capacity,DMA_ENGINE DMA channel prefetch buffer nearing capacity,3
ERROR,CLOCK_MANAGER,Core clock signal glitch detected,CLOCK_MANAGER Core clock signal glitch detected,0
ERROR,PCIE_CTRL,PCIe Lane 0 synchronization lost during operation,PCIE_CTRL PCIe Lane 0 synchronization lost during operation,6
ERROR,INTERRUPT_CTRL,Interrupt controller register read protection violation,INTERRUPT_CTRL Interrupt controller register read protection violation,1
INFO,DDR_CTRL,DDR memory controller initialized.,DDR_CTRL DDR memory controller initialized.,1
INFO,DDR_CTRL,DDR power-down entry sequence initiated.,DDR_CTRL DDR power-down entry sequence initiated.,1
ERROR,FIFO_BUF,FIFO synchronization logic detected clock domain crossing metastability,FIFO_BUF FIFO synchronization logic detected clock domain crossing metastability,5
CRITICAL,PCIE_CTRL,PCIe configuration space integrity protocol mismatch.,PCIE_CTRL PCIe configuration space integrity protocol mismatch.,6
ERROR,MEM_CTRL,Parity error detected on memory data bus at address 0x76543210,MEM_CTRL Parity error detected on memory data bus at address 0x76543210,1
INFO,CLOCK_MANAGER,Clock gating enabled for module X,CLOCK_MANAGER Clock gating enabled for module X,0
INFO,DMA_ENGINE,DMA transfer completed with zero byte count,DMA_ENGINE DMA transfer completed with zero byte count,3
ERROR,INTERRUPT_CTRL,Priority inversion detected in interrupt arbitration,INTERRUPT_CTRL Priority inversion detected in interrupt arbitration,1
ERROR,AXI_CTRL,AXI burst length violation detected.,AXI_CTRL AXI burst length violation detected.,2
WARNING,DMA_ENGINE,DMA channel 6 burst size misconfigured for target memory,DMA_ENGINE DMA channel 6 burst size misconfigured for target memory,3
ERROR,MEM_CTRL,Memory access permissions arbitration conflict.,MEM_CTRL Memory access permissions arbitration conflict.,1
WARNING,POWER_CTRL,Power domain reset deassertion race condition,POWER_CTRL Power domain reset deassertion race condition,4
INFO,DDR_CTRL,Read deskew performed,DDR_CTRL Read deskew performed,-1
CRITICAL,DDR_CTRL,DDR memory array read/write paths corrupted,DDR_CTRL DDR memory array read/write paths corrupted,1
WARNING,POWER_CTRL,Power gate isolation cell leakage current increasing,POWER_CTRL Power gate isolation cell leakage current increasing,-1
CRITICAL,POWER_CTRL,Critical power rail voltage dropped below safe operating limit.,POWER_CTRL Critical power rail voltage dropped below safe operating limit.,4
ERROR,AXI_CTRL,AXI slave error (SLVERR) received from address 0x1BBCE,AXI_CTRL AXI slave error (SLVERR) received from address 0x1BBCE,2
CRITICAL,PCIE_CTRL,PCIe PHY reset sequence failed,PCIE_CTRL PCIe PHY reset sequence failed,6
ERROR,POWER_CTRL,Power domain 'USB_VDD' failed to isolate,POWER_CTRL Power domain 'USB_VDD' failed to isolate,4
ERROR,PCIE_CTRL,PCIe transaction layer timeout,PCIE_CTRL PCIe transaction layer timeout,6
CRITICAL,PCIE_CTRL,"PCIe PHY layer error, link untrainable","PCIE_CTRL PCIe PHY layer error, link untrainable",6
CRITICAL,MEM_CTRL,Memory address decoding fault detected,MEM_CTRL Memory address decoding fault detected,1
WARNING,DMA_ENGINE,DMA engine clock gate bypassed for debug purposes,DMA_ENGINE DMA engine clock gate bypassed for debug purposes,-1
ERROR,MEM_CTRL,Memory protection unit (MPU) fault,MEM_CTRL Memory protection unit (MPU) fault,1
INFO,MEM_CTRL,Memory bank activated,MEM_CTRL Memory bank activated,1
ERROR,FIFO_BUF,FIFO internal buffer read error,FIFO_BUF FIFO internal buffer read error,5
ERROR,CACHE_CTRL,Cacheway 3 tag comparator mismatch,CACHE_CTRL Cacheway 3 tag comparator mismatch,1
CRITICAL,PCIE_CTRL,"PCIe fatal error detected, system requires reset","PCIE_CTRL PCIe fatal error detected, system requires reset",6
WARNING,DMA_ENGINE,DMA channel 0 paused due to data starvation,DMA_ENGINE DMA channel 0 paused due to data starvation,3
WARNING,CACHE_CTRL,Cache hit rate below acceptable levels,CACHE_CTRL Cache hit rate below acceptable levels,1
CRITICAL,POWER_CTRL,Critical power rail voltage collapse detected,POWER_CTRL Critical power rail voltage collapse detected,4
INFO,FIFO_BUF,Data successfully written to buffer,FIFO_BUF Data successfully written to buffer,5
ERROR,FIFO_BUF,FIFO 'sd_cmd' read operation returned garbage data,FIFO_BUF FIFO 'sd_cmd' read operation returned garbage data,-1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge logic timeout,INTERRUPT_CTRL Interrupt acknowledge logic timeout,1
CRITICAL,POWER_CTRL,"Power rail instability detected, shutting down system","POWER_CTRL Power rail instability detected, shutting down system",4
INFO,AXI_CTRL,AXI master arbitration won,AXI_CTRL AXI master arbitration won,2
ERROR,POWER_CTRL,Voltage regulator X output below minimum threshold.,POWER_CTRL Voltage regulator X output below minimum threshold.,4
INFO,PCIE_CTRL,PCIe link established successfully at Gen2 x4,PCIE_CTRL PCIe link established successfully at Gen2 x4,6
INFO,CACHE_CTRL,L1 data cache write-through policy enabled,CACHE_CTRL L1 data cache write-through policy enabled,1
WARNING,AXI_CTRL,AXI write channel latency exceeding arbitration threshold,AXI_CTRL AXI write channel latency exceeding arbitration threshold,2
CRITICAL,FIFO_BUF,"FIFO access violation, potential system instability","FIFO_BUF FIFO access violation, potential system instability",5
INFO,DMA_ENGINE,DMA channel configured,DMA_ENGINE DMA channel configured,3
WARNING,MEM_CTRL,Memory read/write buffer nearing capacity,MEM_CTRL Memory read/write buffer nearing capacity,1
ERROR,CLOCK_MANAGER,Clock recovery circuit instability,CLOCK_MANAGER Clock recovery circuit instability,0
ERROR,CLOCK_MANAGER,"Secondary PLL lock lost, switching to backup","CLOCK_MANAGER Secondary PLL lock lost, switching to backup",0
ERROR,MEM_CTRL,Memory write transaction reported `DECERR` on AXI bus,MEM_CTRL Memory write transaction reported `DECERR` on AXI bus,-1
WARNING,CACHE_CTRL,Cache snoop filter nearing capacity,CACHE_CTRL Cache snoop filter nearing capacity,1
INFO,MEM_CTRL,Memory page table entry updated,MEM_CTRL Memory page table entry updated,1
WARNING,DDR_CTRL,DDR read data CRC mismatch on single bit,DDR_CTRL DDR read data CRC mismatch on single bit,-1
ERROR,DDR_CTRL,DDR address mapping translation failure,DDR_CTRL DDR address mapping translation failure,-1
ERROR,DMA_ENGINE,DMA transfer completion timeout,DMA_ENGINE DMA transfer completion timeout,3
WARNING,CLOCK_MANAGER,Clock signal integrity degradation,CLOCK_MANAGER Clock signal integrity degradation,0
ERROR,AXI_CTRL,AXI burst length set to zero,AXI_CTRL AXI burst length set to zero,2
ERROR,MEM_CTRL,ECC parity mismatch detected (uncorrectable single bit),MEM_CTRL ECC parity mismatch detected (uncorrectable single bit),1
INFO,INTERRUPT_CTRL,Interrupt debouncing circuit activated,INTERRUPT_CTRL Interrupt debouncing circuit activated,-1
ERROR,INTERRUPT_CTRL,"Interrupt handler address invalid, parity error.","INTERRUPT_CTRL Interrupt handler address invalid, parity error.",1
WARNING,FIFO_BUF,FIFO data output not synchronizing correctly to destination clock,FIFO_BUF FIFO data output not synchronizing correctly to destination clock,5
INFO,MEM_CTRL,Memory controller detected no pending transactions,MEM_CTRL Memory controller detected no pending transactions,1
INFO,CACHE_CTRL,Cache line written back to memory,CACHE_CTRL Cache line written back to memory,1
CRITICAL,DDR_CTRL,"Fatal DDR timing violation leading to memory corruption, system crash.","DDR_CTRL Fatal DDR timing violation leading to memory corruption, system crash.",1
ERROR,POWER_CTRL,Power-on reset (POR) circuit failure.,POWER_CTRL Power-on reset (POR) circuit failure.,4
INFO,INTERRUPT_CTRL,Software interrupt triggered for task switch,INTERRUPT_CTRL Software interrupt triggered for task switch,1
INFO,FIFO_BUF,FIFO_DEBUG_LOG reset complete.,FIFO_BUF FIFO_DEBUG_LOG reset complete.,5
WARNING,INTERRUPT_CTRL,Interrupt pending for extended duration,INTERRUPT_CTRL Interrupt pending for extended duration,1
WARNING,DMA_ENGINE,DMA channel 3 pending for arbitration for extended duration,DMA_ENGINE DMA channel 3 pending for arbitration for extended duration,3
ERROR,FIFO_BUF,FIFO buffer internal consistency check failed,FIFO_BUF FIFO buffer internal consistency check failed,5
INFO,POWER_CTRL,Power domain entered low-power mode,POWER_CTRL Power domain entered low-power mode,4
CRITICAL,CACHE_CTRL,Cache deadlock detected during directory lookup.,CACHE_CTRL Cache deadlock detected during directory lookup.,1
WARNING,INTERRUPT_CTRL,Interrupt dispatch latency increased,INTERRUPT_CTRL Interrupt dispatch latency increased,1
WARNING,DDR_CTRL,"DDR read latency increasing, potential contention","DDR_CTRL DDR read latency increasing, potential contention",1
ERROR,MEM_CTRL,"Memory read data mismatch detected, data corruption.","MEM_CTRL Memory read data mismatch detected, data corruption.",1
ERROR,CACHE_CTRL,L2 cache directory corruption detected,CACHE_CTRL L2 cache directory corruption detected,1
WARNING,DDR_CTRL,DDR command scheduling priority inverted,DDR_CTRL DDR command scheduling priority inverted,1
INFO,CACHE_CTRL,L2 cache line invalidation successful,CACHE_CTRL L2 cache line invalidation successful,1
WARNING,CLOCK_MANAGER,Clock period variation exceeding expected range,CLOCK_MANAGER Clock period variation exceeding expected range,0
INFO,POWER_CTRL,Voltage regulator enabled for core domain,POWER_CTRL Voltage regulator enabled for core domain,4
INFO,CACHE_CTRL,Cache flush completed for region 0x1000-0x2000,CACHE_CTRL Cache flush completed for region 0x1000-0x2000,-1
WARNING,FIFO_BUF,FIFO almost-full signal active,FIFO_BUF FIFO almost-full signal active,5
WARNING,DDR_CTRL,DDR write leveling failing in specific DQ lanes,DDR_CTRL DDR write leveling failing in specific DQ lanes,-1
INFO,DDR_CTRL,Memory rank detected,DDR_CTRL Memory rank detected,1
ERROR,AXI_CTRL,AXI response channel deadlock detected,AXI_CTRL AXI response channel deadlock detected,2
WARNING,PCIE_CTRL,PCIe NAK received too frequently.,PCIE_CTRL PCIe NAK received too frequently.,-1
ERROR,CLOCK_MANAGER,Reference clock missing,CLOCK_MANAGER Reference clock missing,0
WARNING,CLOCK_MANAGER,Clock domain crossing bridge experiencing stalls,CLOCK_MANAGER Clock domain crossing bridge experiencing stalls,0
INFO,DMA_ENGINE,DMA engine 0 busy status de-asserted,DMA_ENGINE DMA engine 0 busy status de-asserted,3
ERROR,CLOCK_MANAGER,Clock distribution network fault detected,CLOCK_MANAGER Clock distribution network fault detected,0
ERROR,CLOCK_MANAGER,Clock domain crossing FIFO asserted full during transfer,CLOCK_MANAGER Clock domain crossing FIFO asserted full during transfer,0
CRITICAL,POWER_CTRL,Power rail voltage out of specification (undervoltage) on VCC_CORE,POWER_CTRL Power rail voltage out of specification (undervoltage) on VCC_CORE,4
ERROR,PCIE_CTRL,PCIe link training sequence unstable,PCIE_CTRL PCIe link training sequence unstable,6
CRITICAL,DDR_CTRL,DDR memory device unrecoverable failure,DDR_CTRL DDR memory device unrecoverable failure,1
INFO,FIFO_BUF,"Data read from FIFO, buffer now less full","FIFO_BUF Data read from FIFO, buffer now less full",5
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, potential starvation","FIFO_BUF FIFO read pointer approaching write pointer, potential starvation",5
INFO,POWER_CTRL,Power-on sequence completed,POWER_CTRL Power-on sequence completed,4
WARNING,DMA_ENGINE,DMA queue nearing saturation for channel 0.,DMA_ENGINE DMA queue nearing saturation for channel 0.,3
CRITICAL,INTERRUPT_CTRL,INTERRUPT_CTRL: System-level arbitration conflict detected. Unrecoverable hardware state. (fairness algorithm failure),INTERRUPT_CTRL INTERRUPT_CTRL: System-level arbitration conflict detected. Unrecoverable hardware state. (fairness algorithm failure),1
INFO,FIFO_BUF,FIFO reset sequence initiated,FIFO_BUF FIFO reset sequence initiated,5
WARNING,PCIE_CTRL,"PCIe received malformed TLP, dropped","PCIE_CTRL PCIe received malformed TLP, dropped",6
ERROR,DMA_ENGINE,DMA channel hung due to descriptor loop,DMA_ENGINE DMA channel hung due to descriptor loop,3
INFO,FIFO_BUF,FIFO watermark levels adjusted,FIFO_BUF FIFO watermark levels adjusted,5
ERROR,PCIE_CTRL,PCIe TLP sequence number mismatch,PCIE_CTRL PCIe TLP sequence number mismatch,6
INFO,AXI_CTRL,AXI slave 'S4' registered on interconnect,AXI_CTRL AXI slave 'S4' registered on interconnect,2
INFO,CACHE_CTRL,Cache hit rate for L1 is 92%,CACHE_CTRL Cache hit rate for L1 is 92%,1
ERROR,CACHE_CTRL,Cache tag comparison error,CACHE_CTRL Cache tag comparison error,1
INFO,CACHE_CTRL,Cache line allocated successfully,CACHE_CTRL Cache line allocated successfully,1
WARNING,INTERRUPT_CTRL,"Interrupt queue empty, but pending interrupt exists","INTERRUPT_CTRL Interrupt queue empty, but pending interrupt exists",1
ERROR,DDR_CTRL,DDR CKE signal violation detected,DDR_CTRL DDR CKE signal violation detected,-1
ERROR,AXI_CTRL,AXI write burst length inconsistent with transaction type,AXI_CTRL AXI write burst length inconsistent with transaction type,2
ERROR,DMA_ENGINE,DMA descriptor fetch resulted in an AXI error response,DMA_ENGINE DMA descriptor fetch resulted in an AXI error response,3
ERROR,AXI_CTRL,AXI write response channel RVALID asserted without WVALID,AXI_CTRL AXI write response channel RVALID asserted without WVALID,2
INFO,PCIE_CTRL,PCIe ASPM state entered successfully,PCIE_CTRL PCIe ASPM state entered successfully,6
WARNING,POWER_CTRL,Power domain transition delay detected for domain DDR,POWER_CTRL Power domain transition delay detected for domain DDR,4
WARNING,CACHE_CTRL,L2 cache backpressure asserted.,CACHE_CTRL L2 cache backpressure asserted.,-1
CRITICAL,PCIE_CTRL,PCIe hot reset initiated due to unrecoverable error.,PCIE_CTRL PCIe hot reset initiated due to unrecoverable error.,6
WARNING,MEM_CTRL,Memory BIST (Built-In Self-Test) still running,MEM_CTRL Memory BIST (Built-In Self-Test) still running,1
ERROR,DMA_ENGINE,DMA engine internal register corruption,DMA_ENGINE DMA engine internal register corruption,3
ERROR,MEM_CTRL,Memory data integrity error on read,MEM_CTRL Memory data integrity error on read,1
INFO,CACHE_CTRL,Cache hit detected for recent access,CACHE_CTRL Cache hit detected for recent access,1
CRITICAL,PCIE_CTRL,PCIe Root Port encountered uncorrectable fatal error.,PCIE_CTRL PCIe Root Port encountered uncorrectable fatal error.,6
WARNING,CLOCK_MANAGER,Frequency deviation detected on main PLL output,CLOCK_MANAGER Frequency deviation detected on main PLL output,0
ERROR,MEM_CTRL,Memory arbiter locked on specific request,MEM_CTRL Memory arbiter locked on specific request,1
ERROR,CACHE_CTRL,Cache line tag array corruption,CACHE_CTRL Cache line tag array corruption,1
ERROR,DMA_ENGINE,DMA_ENGINE detected a severe protocol mismatch: invalid handshake sequence.,DMA_ENGINE DMA_ENGINE detected a severe protocol mismatch: invalid handshake sequence.,3
CRITICAL,DMA_ENGINE,DMA engine internal bus contention leading to stall,DMA_ENGINE DMA engine internal bus contention leading to stall,3
WARNING,PCIE_CTRL,PCIe TLP processing latency increasing,PCIE_CTRL PCIe TLP processing latency increasing,6
ERROR,DMA_ENGINE,DMA channel arbitration failure detected,DMA_ENGINE DMA channel arbitration failure detected,3
WARNING,DMA_ENGINE,DMA request with invalid priority,DMA_ENGINE DMA request with invalid priority,3
INFO,POWER_CTRL,Power domain X enabled successfully.,POWER_CTRL Power domain X enabled successfully.,4
CRITICAL,INTERRUPT_CTRL,Critical interrupt handling routine re-entered prematurely,INTERRUPT_CTRL Critical interrupt handling routine re-entered prematurely,1
ERROR,PCIE_CTRL,PCIe data link layer protocol violation.,PCIE_CTRL PCIe data link layer protocol violation.,6
ERROR,POWER_CTRL,On-chip debugger (OCD) power domain access violation,POWER_CTRL On-chip debugger (OCD) power domain access violation,-1
ERROR,CLOCK_MANAGER,Clock gating logic introducing unintended glitches,CLOCK_MANAGER Clock gating logic introducing unintended glitches,0
CRITICAL,DMA_ENGINE,DMA engine controller state machine entered invalid state,DMA_ENGINE DMA engine controller state machine entered invalid state,3
INFO,AXI_CTRL,AXI read outstanding transactions limit reached,AXI_CTRL AXI read outstanding transactions limit reached,2
ERROR,AXI_CTRL,AXI data strobe error detected,AXI_CTRL AXI data strobe error detected,2
CRITICAL,FIFO_BUF,"Multiple FIFO pointer corruptions detected, unrecoverable","FIFO_BUF Multiple FIFO pointer corruptions detected, unrecoverable",5
ERROR,MEM_CTRL,Memory write data not matching read-back data after refresh,MEM_CTRL Memory write data not matching read-back data after refresh,1
INFO,CLOCK_MANAGER,PLL lock achieved for primary clock,CLOCK_MANAGER PLL lock achieved for primary clock,0
ERROR,AXI_CTRL,"Functional failure in AXI_CTRL due to deadlock detected (circular dependency stall). (Master ID: 0, AXI ID: 15)","AXI_CTRL Functional failure in AXI_CTRL due to deadlock detected (circular dependency stall). (Master ID: 0, AXI ID: 15)",2
CRITICAL,POWER_CTRL,"Critical power rail voltage instability, system shutdown","POWER_CTRL Critical power rail voltage instability, system shutdown",4
WARNING,DDR_CTRL,"DDR command queue depth increasing, potential buffer overflow.","DDR_CTRL DDR command queue depth increasing, potential buffer overflow.",1
CRITICAL,MEM_CTRL,Memory retention failure detected during deep sleep mode exit,MEM_CTRL Memory retention failure detected during deep sleep mode exit,1
INFO,PCIE_CTRL,"PCIe hotplug event detected, new device enumerated","PCIE_CTRL PCIe hotplug event detected, new device enumerated",6
INFO,FIFO_BUF,New data pushed to FIFO,FIFO_BUF New data pushed to FIFO,5
INFO,INTERRUPT_CTRL,Interrupt vector 7 acknowledged by CPU,INTERRUPT_CTRL Interrupt vector 7 acknowledged by CPU,1
CRITICAL,CLOCK_MANAGER,Global clock buffer output stuck,CLOCK_MANAGER Global clock buffer output stuck,0
INFO,CACHE_CTRL,L2 cache way 0 fully enabled,CACHE_CTRL L2 cache way 0 fully enabled,1
ERROR,AXI_CTRL,AXI protocol mismatch: BVALID asserted without BRESP,AXI_CTRL AXI protocol mismatch: BVALID asserted without BRESP,2
INFO,INTERRUPT_CTRL,Interrupt 1 successfully acknowledged.,INTERRUPT_CTRL Interrupt 1 successfully acknowledged.,1
ERROR,AXI_CTRL,AXI data phase timing violation.,AXI_CTRL AXI data phase timing violation.,2
WARNING,PCIE_CTRL,PCIe receiver equalization error rate increasing,PCIE_CTRL PCIe receiver equalization error rate increasing,6
INFO,INTERRUPT_CTRL,Global interrupt enable asserted,INTERRUPT_CTRL Global interrupt enable asserted,1
CRITICAL,DMA_ENGINE,DMA engine internal state machine entered unrecoverable state,DMA_ENGINE DMA engine internal state machine entered unrecoverable state,3
INFO,CLOCK_MANAGER,Clock domain crossing bridge in synchronous mode,CLOCK_MANAGER Clock domain crossing bridge in synchronous mode,0
INFO,CLOCK_MANAGER,Clock distribution network stable,CLOCK_MANAGER Clock distribution network stable,0
CRITICAL,INTERRUPT_CTRL,"Interrupt controller memory corruption, ECC failure on vector table.","INTERRUPT_CTRL Interrupt controller memory corruption, ECC failure on vector table.",1
ERROR,CACHE_CTRL,Invalid access to protected cache region by CPU,CACHE_CTRL Invalid access to protected cache region by CPU,-1
INFO,CLOCK_MANAGER,Clock monitor enabled,CLOCK_MANAGER Clock monitor enabled,0
WARNING,DDR_CTRL,DDR self-refresh entry delayed due to pending commands,DDR_CTRL DDR self-refresh entry delayed due to pending commands,1
INFO,INTERRUPT_CTRL,Interrupt dispatch for IRQ_DMA completed,INTERRUPT_CTRL Interrupt dispatch for IRQ_DMA completed,1
WARNING,DMA_ENGINE,DMA channel 3 descriptor queue 80% full,DMA_ENGINE DMA channel 3 descriptor queue 80% full,3
CRITICAL,CLOCK_MANAGER,Clock distribution network fault,CLOCK_MANAGER Clock distribution network fault,0
ERROR,INTERRUPT_CTRL,Interrupt controller pending bit stuck for IRQ_07,INTERRUPT_CTRL Interrupt controller pending bit stuck for IRQ_07,1
WARNING,FIFO_BUF,FIFO peek operation attempted on empty buffer.,FIFO_BUF FIFO peek operation attempted on empty buffer.,5
ERROR,FIFO_BUF,FIFO write pointer advancement error,FIFO_BUF FIFO write pointer advancement error,5
WARNING,AXI_CTRL,AXI read address channel backpressure,AXI_CTRL AXI read address channel backpressure,2
WARNING,CACHE_CTRL,Cache line fill operation taking excessive cycles,CACHE_CTRL Cache line fill operation taking excessive cycles,1
ERROR,MEM_CTRL,Memory address alignment fault during access to 0x367F6,MEM_CTRL Memory address alignment fault during access to 0x367F6,1
INFO,INTERRUPT_CTRL,Interrupt acknowledgment logic tested,INTERRUPT_CTRL Interrupt acknowledgment logic tested,1
WARNING,POWER_CTRL,Core voltage ripple exceeding spec,POWER_CTRL Core voltage ripple exceeding spec,4
INFO,FIFO_BUF,FIFO_BUF_19 current fill level: 90%,FIFO_BUF FIFO_BUF_19 current fill level: 90%,5
WARNING,PCIE_CTRL,PCIe TLP buffer nearly full,PCIE_CTRL PCIe TLP buffer nearly full,6
ERROR,FIFO_BUF,FIFO data mismatch between write and read operations,FIFO_BUF FIFO data mismatch between write and read operations,5
CRITICAL,INTERRUPT_CTRL,"Interrupt controller hung, no interrupts processed","INTERRUPT_CTRL Interrupt controller hung, no interrupts processed",1
ERROR,FIFO_BUF,FIFO 'event_queue' encountered persistent full condition,FIFO_BUF FIFO 'event_queue' encountered persistent full condition,5
CRITICAL,POWER_CTRL,"Power rail ""VDD_CPU"" unstable, fluctuating","POWER_CTRL Power rail ""VDD_CPU"" unstable, fluctuating",4
WARNING,DMA_ENGINE,DMA channel busy for extended period,DMA_ENGINE DMA channel busy for extended period,3
WARNING,MEM_CTRL,Memory address decoding warning: overlapping regions,MEM_CTRL Memory address decoding warning: overlapping regions,1
ERROR,AXI_CTRL,AXI burst length violation detected on read transaction,AXI_CTRL AXI burst length violation detected on read transaction,2
INFO,CLOCK_MANAGER,Primary clock PLL achieved lock status,CLOCK_MANAGER Primary clock PLL achieved lock status,0
INFO,POWER_CTRL,System entered low-power idle state,POWER_CTRL System entered low-power idle state,4
WARNING,DDR_CTRL,DDR timing margins reduced after temperature increase.,DDR_CTRL DDR timing margins reduced after temperature increase.,1
ERROR,FIFO_BUF,FIFO 'rx_pkt_queue' experienced a persistent underrun,FIFO_BUF FIFO 'rx_pkt_queue' experienced a persistent underrun,-1
ERROR,FIFO_BUF,FIFO read pointer underflow detected on channel X,FIFO_BUF FIFO read pointer underflow detected on channel X,5
ERROR,CACHE_CTRL,Cache invalidation failure,CACHE_CTRL Cache invalidation failure,1
ERROR,PCIE_CTRL,PCIe packet framing error detected.,PCIE_CTRL PCIe packet framing error detected.,6
ERROR,POWER_CTRL,Power domain X voltage droop exceeded threshold.,POWER_CTRL Power domain X voltage droop exceeded threshold.,4
WARNING,MEM_CTRL,Partial memory bank refresh pending,MEM_CTRL Partial memory bank refresh pending,1
WARNING,CACHE_CTRL,Dirty cache lines count exceeding software threshold,CACHE_CTRL Dirty cache lines count exceeding software threshold,1
ERROR,CACHE_CTRL,Cache line fill operation failed due to memory access error,CACHE_CTRL Cache line fill operation failed due to memory access error,1
INFO,CLOCK_MANAGER,Clock output buffer configured for optimal slew,CLOCK_MANAGER Clock output buffer configured for optimal slew,-1
INFO,CLOCK_MANAGER,Clock output buffer enabled,CLOCK_MANAGER Clock output buffer enabled,0
WARNING,POWER_CTRL,Voltage regulator on VDD_CORE rail showing minor fluctuations.,POWER_CTRL Voltage regulator on VDD_CORE rail showing minor fluctuations.,4
INFO,DMA_ENGINE,DMA channel 0 burst size updated,DMA_ENGINE DMA channel 0 burst size updated,3
INFO,CACHE_CTRL,Cache line allocation successful for new process,CACHE_CTRL Cache line allocation successful for new process,1
ERROR,DDR_CTRL,DDR burst integrity check failed for address 0x12345678,DDR_CTRL DDR burst integrity check failed for address 0x12345678,1
WARNING,INTERRUPT_CTRL,Masked interrupt count exceeding expected range,INTERRUPT_CTRL Masked interrupt count exceeding expected range,1
INFO,PCIE_CTRL,PCIe hot-reset completed successfully,PCIE_CTRL PCIe hot-reset completed successfully,6
WARNING,AXI_CTRL,AXI slave response latency high.,AXI_CTRL AXI slave response latency high.,2
CRITICAL,MEM_CTRL,Memory write protection violation detected,MEM_CTRL Memory write protection violation detected,1
WARNING,DDR_CTRL,DDR command timing violation detected for activate command,DDR_CTRL DDR command timing violation detected for activate command,1
ERROR,CACHE_CTRL,Cache coherence protocol deadlock on broadcast invalidate,CACHE_CTRL Cache coherence protocol deadlock on broadcast invalidate,1
WARNING,FIFO_BUF,"FIFO nearly empty, asserting empty flag","FIFO_BUF FIFO nearly empty, asserting empty flag",5
ERROR,CACHE_CTRL,Cache line fill operation interrupted by high-priority eviction,CACHE_CTRL Cache line fill operation interrupted by high-priority eviction,1
INFO,DDR_CTRL,DDR memory entered power-down mode.,DDR_CTRL DDR memory entered power-down mode.,1
ERROR,CACHE_CTRL,Cache controller state machine entered invalid state,CACHE_CTRL Cache controller state machine entered invalid state,1
INFO,CACHE_CTRL,Cache coherence request sent,CACHE_CTRL Cache coherence request sent,1
ERROR,MEM_CTRL,Memory bus contention detected on shared resource,MEM_CTRL Memory bus contention detected on shared resource,1
INFO,INTERRUPT_CTRL,Interrupt request line asserted,INTERRUPT_CTRL Interrupt request line asserted,1
WARNING,INTERRUPT_CTRL,"Interrupt storm detected, rate limit active.","INTERRUPT_CTRL Interrupt storm detected, rate limit active.",1
ERROR,CACHE_CTRL,Cache tag parity error detected for address 0x5678.,CACHE_CTRL Cache tag parity error detected for address 0x5678.,1
WARNING,AXI_CTRL,AXI address decoding miss for transaction from M3,AXI_CTRL AXI address decoding miss for transaction from M3,2
CRITICAL,CLOCK_MANAGER,Primary clock source deemed unstable,CLOCK_MANAGER Primary clock source deemed unstable,0
ERROR,DDR_CTRL,Memory controller observed uncommanded access to restricted region.,DDR_CTRL Memory controller observed uncommanded access to restricted region.,1
ERROR,INTERRUPT_CTRL,Invalid interrupt priority level detected,INTERRUPT_CTRL Invalid interrupt priority level detected,1
ERROR,CACHE_CTRL,Cache data integrity error after fill.,CACHE_CTRL Cache data integrity error after fill.,1
INFO,DMA_ENGINE,DMA burst size configured to 16,DMA_ENGINE DMA burst size configured to 16,3
INFO,CLOCK_MANAGER,Jitter measurement within tolerance,CLOCK_MANAGER Jitter measurement within tolerance,0
ERROR,DMA_ENGINE,DMA transfer error: byte count mismatch (1000 vs 16).,DMA_ENGINE DMA transfer error: byte count mismatch (1000 vs 16).,3
ERROR,DDR_CTRL,DDR training eye closure detected,DDR_CTRL DDR training eye closure detected,-1
WARNING,FIFO_BUF,FIFO nearing empty (59%).,FIFO_BUF FIFO nearing empty (59%).,5
INFO,CLOCK_MANAGER,Clock gate logic enabled,CLOCK_MANAGER Clock gate logic enabled,0
ERROR,CACHE_CTRL,Cache tag RAM access timeout,CACHE_CTRL Cache tag RAM access timeout,1
CRITICAL,CLOCK_MANAGER,Clock generation PLL has permanently lost lock,CLOCK_MANAGER Clock generation PLL has permanently lost lock,0
ERROR,POWER_CTRL,Power management unit (PMU) state machine entered invalid state.,POWER_CTRL Power management unit (PMU) state machine entered invalid state.,4
WARNING,PCIE_CTRL,PCIe link error count increasing beyond soft threshold,PCIE_CTRL PCIe link error count increasing beyond soft threshold,6
WARNING,MEM_CTRL,"Memory ECC correction count increasing, monitor health.","MEM_CTRL Memory ECC correction count increasing, monitor health.",1
CRITICAL,CLOCK_MANAGER,"Global clock signal failure, no functional clock distributed","CLOCK_MANAGER Global clock signal failure, no functional clock distributed",0
WARNING,PCIE_CTRL,PCIe non-posted request queue depth increasing rapidly,PCIE_CTRL PCIe non-posted request queue depth increasing rapidly,6
ERROR,CLOCK_MANAGER,Clock tree synthesis mismatch,CLOCK_MANAGER Clock tree synthesis mismatch,0
ERROR,POWER_CTRL,"Power domain X failed to transition, invalid state transition.","POWER_CTRL Power domain X failed to transition, invalid state transition.",4
INFO,CACHE_CTRL,Cache line written to memory with clean status,CACHE_CTRL Cache line written to memory with clean status,1
ERROR,CACHE_CTRL,Cache directory lookup failed,CACHE_CTRL Cache directory lookup failed,1
ERROR,FIFO_BUF,"FIFO write operation failed, internal buffer full.","FIFO_BUF FIFO write operation failed, internal buffer full.",5
INFO,DDR_CTRL,DDR memory self-refresh entered.,DDR_CTRL DDR memory self-refresh entered.,1
ERROR,DDR_CTRL,DDR command queue arbitration starvation detected.,DDR_CTRL DDR command queue arbitration starvation detected.,1
INFO,FIFO_BUF,Flow control re-enabled,FIFO_BUF Flow control re-enabled,5
WARNING,CLOCK_MANAGER,Jitter measurement on clock CLK_PERIPH approaching tolerance limit,CLOCK_MANAGER Jitter measurement on clock CLK_PERIPH approaching tolerance limit,0
CRITICAL,POWER_CTRL,Voltage regulator feedback loop instability detected,POWER_CTRL Voltage regulator feedback loop instability detected,4
CRITICAL,DMA_ENGINE,DMA access to I/O registers caused system freeze,DMA_ENGINE DMA access to I/O registers caused system freeze,3
ERROR,POWER_CTRL,Power management unit reported an internal error,POWER_CTRL Power management unit reported an internal error,4
WARNING,PCIE_CTRL,PCIe flow control credits approaching depletion.,PCIE_CTRL PCIe flow control credits approaching depletion.,6
INFO,CLOCK_MANAGER,Clock multiplexer switched to backup source,CLOCK_MANAGER Clock multiplexer switched to backup source,0
INFO,INTERRUPT_CTRL,Interrupt handler return pointer updated,INTERRUPT_CTRL Interrupt handler return pointer updated,1
INFO,POWER_CTRL,Power rail enabled for subsystem.,POWER_CTRL Power rail enabled for subsystem.,4
INFO,INTERRUPT_CTRL,Interrupt controller initialized to default settings,INTERRUPT_CTRL Interrupt controller initialized to default settings,1
WARNING,AXI_CTRL,AXI outstanding write transactions reaching limit,AXI_CTRL AXI outstanding write transactions reaching limit,2
CRITICAL,AXI_CTRL,AXI interconnect detected a global deadlock condition,AXI_CTRL AXI interconnect detected a global deadlock condition,2
INFO,FIFO_BUF,FIFO depth configuration applied.,FIFO_BUF FIFO depth configuration applied.,5
INFO,DDR_CTRL,DDR memory initialization successful,DDR_CTRL DDR memory initialization successful,1
CRITICAL,CACHE_CTRL,Cache tag RAM detected a multi-bit error,CACHE_CTRL Cache tag RAM detected a multi-bit error,1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller unresponsive, system hang","INTERRUPT_CTRL Interrupt controller unresponsive, system hang",1
ERROR,CLOCK_MANAGER,Global clock buffer output slew rate violation,CLOCK_MANAGER Global clock buffer output slew rate violation,-1
INFO,AXI_CTRL,AXI write transaction to 0xABCD_0000 completed,AXI_CTRL AXI write transaction to 0xABCD_0000 completed,2
ERROR,DDR_CTRL,"DDR training sequence failed, read/write leveling error.","DDR_CTRL DDR training sequence failed, read/write leveling error.",1
INFO,FIFO_BUF,FIFO read operation completed.,FIFO_BUF FIFO read operation completed.,5
WARNING,MEM_CTRL,Memory controller read data CRC mismatch (correctable),MEM_CTRL Memory controller read data CRC mismatch (correctable),1
INFO,DMA_ENGINE,DMA channel 6 transfer request canceled,DMA_ENGINE DMA channel 6 transfer request canceled,3
INFO,MEM_CTRL,Single bit ECC corrected successfully,MEM_CTRL Single bit ECC corrected successfully,1
WARNING,CACHE_CTRL,"Cache miss rate 15%, exceeding typical operating threshold.","CACHE_CTRL Cache miss rate 15%, exceeding typical operating threshold.",1
WARNING,DDR_CTRL,DDR calibration reports marginal timing for specific ranks,DDR_CTRL DDR calibration reports marginal timing for specific ranks,-1
WARNING,DMA_ENGINE,DMA request queue reaching high watermark,DMA_ENGINE DMA request queue reaching high watermark,3
ERROR,DMA_ENGINE,DMA transfer completion status register stuck,DMA_ENGINE DMA transfer completion status register stuck,3
INFO,CACHE_CTRL,Cache entry validated,CACHE_CTRL Cache entry validated,1
ERROR,AXI_CTRL,AXI read burst alignment violation at address 0xABCDEF01.,AXI_CTRL AXI read burst alignment violation at address 0xABCDEF01.,2
ERROR,CACHE_CTRL,Cache way predictor logic misprediction rate critical,CACHE_CTRL Cache way predictor logic misprediction rate critical,1
WARNING,DMA_ENGINE,DMA descriptor fetch taking too long,DMA_ENGINE DMA descriptor fetch taking too long,3
WARNING,DDR_CTRL,DDR memory read command re-ordered excessively,DDR_CTRL DDR memory read command re-ordered excessively,1
INFO,POWER_CTRL,All power rails stable and within tolerance,POWER_CTRL All power rails stable and within tolerance,4
ERROR,AXI_CTRL,AXI exclusive access monitor detected violation,AXI_CTRL AXI exclusive access monitor detected violation,2
INFO,PCIE_CTRL,PCIe link width changed to x4,PCIE_CTRL PCIe link width changed to x4,6
CRITICAL,DMA_ENGINE,"DMA engine encountered a fatal descriptor processing error, halting all channels.","DMA_ENGINE DMA engine encountered a fatal descriptor processing error, halting all channels.",3
ERROR,INTERRUPT_CTRL,"Masked interrupt received, but still pending","INTERRUPT_CTRL Masked interrupt received, but still pending",1
CRITICAL,PCIE_CTRL,"PCIe protocol layer fatal error, link re-training required","PCIE_CTRL PCIe protocol layer fatal error, link re-training required",6
CRITICAL,AXI_CTRL,"AXI bus deadlock detected, system hung","AXI_CTRL AXI bus deadlock detected, system hung",2
ERROR,PCIE_CTRL,PCIe TLP retry limit exceeded for request,PCIE_CTRL PCIe TLP retry limit exceeded for request,6
INFO,PCIE_CTRL,PCIe device enumerated successfully with vendor ID 0x10DE,PCIE_CTRL PCIe device enumerated successfully with vendor ID 0x10DE,6
ERROR,CLOCK_MANAGER,Clock glitch detected on critical path to module CPU,CLOCK_MANAGER Clock glitch detected on critical path to module CPU,0
WARNING,DMA_ENGINE,DMA channel 1 stalled awaiting peripheral response,DMA_ENGINE DMA channel 1 stalled awaiting peripheral response,3
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected on channel 2.,DMA_ENGINE DMA buffer pointer corruption detected on channel 2.,3
INFO,FIFO_BUF,FIFO write pointer reset initiated,FIFO_BUF FIFO write pointer reset initiated,5
WARNING,INTERRUPT_CTRL,Interrupt enable register write ignored,INTERRUPT_CTRL Interrupt enable register write ignored,1
INFO,DMA_ENGINE,Descriptor loaded into engine,DMA_ENGINE Descriptor loaded into engine,3
CRITICAL,MEM_CTRL,Memory controller internal bus deadlocked on a specific master,MEM_CTRL Memory controller internal bus deadlocked on a specific master,1
WARNING,PCIE_CTRL,PCIe link speed negotiation ongoing,PCIE_CTRL PCIe link speed negotiation ongoing,6
INFO,DDR_CTRL,DDR self-refresh entered,DDR_CTRL DDR self-refresh entered,1
WARNING,DDR_CTRL,"DDR access latency spike observed, performance issue.","DDR_CTRL DDR access latency spike observed, performance issue.",1
ERROR,CACHE_CTRL,Cache tag comparison failure for L1 instruction cache,CACHE_CTRL Cache tag comparison failure for L1 instruction cache,1
CRITICAL,CACHE_CTRL,"System-wide cache coherence failure detected, data integrity compromised.","CACHE_CTRL System-wide cache coherence failure detected, data integrity compromised.",1
WARNING,FIFO_BUF,FIFO depth usage consistently high.,FIFO_BUF FIFO depth usage consistently high.,5
WARNING,DMA_ENGINE,DMA completion interrupt delayed,DMA_ENGINE DMA completion interrupt delayed,3
INFO,CLOCK_MANAGER,PLL status indicates locked and stable frequency,CLOCK_MANAGER PLL status indicates locked and stable frequency,0
INFO,AXI_CTRL,AXI bus master 0x3 completed 5 transactions,AXI_CTRL AXI bus master 0x3 completed 5 transactions,2
ERROR,MEM_CTRL,Multi-bit ECC correction attempted but failed,MEM_CTRL Multi-bit ECC correction attempted but failed,1
WARNING,CLOCK_MANAGER,Clock integrity check warning,CLOCK_MANAGER Clock integrity check warning,0
CRITICAL,CACHE_CTRL,Cache memory ECC failure.,CACHE_CTRL Cache memory ECC failure.,1
CRITICAL,FIFO_BUF,"FIFO pointer wrap-around detection failed, data loss imminent","FIFO_BUF FIFO pointer wrap-around detection failed, data loss imminent",5
WARNING,POWER_CTRL,Voltage supply ripple exceeding specifications.,POWER_CTRL Voltage supply ripple exceeding specifications.,4
ERROR,POWER_CTRL,Power management IC (PMIC) communication error,POWER_CTRL Power management IC (PMIC) communication error,4
ERROR,DDR_CTRL,CAS/RAS latency violation,DDR_CTRL CAS/RAS latency violation,1
INFO,MEM_CTRL,Memory address alignment violation on write,MEM_CTRL Memory address alignment violation on write,1
WARNING,DDR_CTRL,DDR auto-refresh pending for extended duration,DDR_CTRL DDR auto-refresh pending for extended duration,1
INFO,POWER_CTRL,Power domain X enabled,POWER_CTRL Power domain X enabled,4
CRITICAL,MEM_CTRL,Address mapping unit (AMU) returned an invalid address,MEM_CTRL Address mapping unit (AMU) returned an invalid address,1
WARNING,MEM_CTRL,Memory ECC error count increasing steadily,MEM_CTRL Memory ECC error count increasing steadily,1
INFO,INTERRUPT_CTRL,Interrupt mask updated for timer interrupt,INTERRUPT_CTRL Interrupt mask updated for timer interrupt,1
CRITICAL,CLOCK_MANAGER,"Primary system PLL lost lock, initiating clock failover sequence.","CLOCK_MANAGER Primary system PLL lost lock, initiating clock failover sequence.",0
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal deasserted prematurely,INTERRUPT_CTRL Interrupt acknowledge signal deasserted prematurely,1
CRITICAL,MEM_CTRL,Memory controller bus bridge fault,MEM_CTRL Memory controller bus bridge fault,1
INFO,MEM_CTRL,Memory controller calibration data loaded,MEM_CTRL Memory controller calibration data loaded,1
CRITICAL,PCIE_CTRL,"PCIe hot reset failure, link unresponsive","PCIE_CTRL PCIe hot reset failure, link unresponsive",6
INFO,POWER_CTRL,Low power mode entered,POWER_CTRL Low power mode entered,4
INFO,DDR_CTRL,DDR memory bandwidth utilization at 70%,DDR_CTRL DDR memory bandwidth utilization at 70%,1
WARNING,MEM_CTRL,Memory controller in debug mode,MEM_CTRL Memory controller in debug mode,1
WARNING,AXI_CTRL,AXI write data channel outstanding limit reached,AXI_CTRL AXI write data channel outstanding limit reached,2
INFO,INTERRUPT_CTRL,Maskable interrupt X asserted,INTERRUPT_CTRL Maskable interrupt X asserted,1
WARNING,MEM_CTRL,"Memory bank Y response slow, performance degradation.","MEM_CTRL Memory bank Y response slow, performance degradation.",1
INFO,DMA_ENGINE,DMA transaction programmed,DMA_ENGINE DMA transaction programmed,3
ERROR,INTERRUPT_CTRL,Interrupt signal stuck high,INTERRUPT_CTRL Interrupt signal stuck high,1
INFO,MEM_CTRL,Memory refresh complete,MEM_CTRL Memory refresh complete,1
INFO,DDR_CTRL,DDR controller enters active power mode,DDR_CTRL DDR controller enters active power mode,1
WARNING,MEM_CTRL,Pending memory writes exceeding critical threshold,MEM_CTRL Pending memory writes exceeding critical threshold,1
WARNING,FIFO_BUF,FIFO_BUF internal FIFO write pointer approaching read pointer within 4 entries.,FIFO_BUF FIFO_BUF internal FIFO write pointer approaching read pointer within 4 entries.,5
WARNING,AXI_CTRL,AXI handshake delay approaching critical threshold on write path,AXI_CTRL AXI handshake delay approaching critical threshold on write path,2
WARNING,DDR_CTRL,DDR ECC correction threshold exceeded,DDR_CTRL DDR ECC correction threshold exceeded,1
INFO,MEM_CTRL,Memory read/write port arbitration granted,MEM_CTRL Memory read/write port arbitration granted,1
WARNING,INTERRUPT_CTRL,INTERRUPT_CTRL pending operations queue growing (count: 9).,INTERRUPT_CTRL INTERRUPT_CTRL pending operations queue growing (count: 9).,1
WARNING,AXI_CTRL,AXI read address channel asserting unaligned addresses,AXI_CTRL AXI read address channel asserting unaligned addresses,2
CRITICAL,MEM_CTRL,"CRITICAL: Double bit ECC corruption detected at address 0x00000000, uncorrectable.","MEM_CTRL CRITICAL: Double bit ECC corruption detected at address 0x00000000, uncorrectable.",1
INFO,INTERRUPT_CTRL,Interrupt source 2 acknowledged,INTERRUPT_CTRL Interrupt source 2 acknowledged,1
INFO,CLOCK_MANAGER,Clock gating enabled for module CPU.,CLOCK_MANAGER Clock gating enabled for module CPU.,0
WARNING,CLOCK_MANAGER,Clock source drift exceeding tolerance,CLOCK_MANAGER Clock source drift exceeding tolerance,0
INFO,PCIE_CTRL,PCIE_CTRL module initialized.,PCIE_CTRL PCIE_CTRL module initialized.,6
INFO,AXI_CTRL,AXI manager granted access to shared bus,AXI_CTRL AXI manager granted access to shared bus,2
ERROR,CACHE_CTRL,Cache line '0x0123' data parity error detected during read,CACHE_CTRL Cache line '0x0123' data parity error detected during read,1
ERROR,POWER_CTRL,Power gate isolation failure in domain X.,POWER_CTRL Power gate isolation failure in domain X.,4
ERROR,DMA_ENGINE,DMA configuration error: invalid channel ID,DMA_ENGINE DMA configuration error: invalid channel ID,3
ERROR,FIFO_BUF,FIFO pointer arithmetic error,FIFO_BUF FIFO pointer arithmetic error,5
ERROR,INTERRUPT_CTRL,Interrupt controller state machine fault,INTERRUPT_CTRL Interrupt controller state machine fault,1
INFO,INTERRUPT_CTRL,Interrupt cleared at source,INTERRUPT_CTRL Interrupt cleared at source,1
INFO,CLOCK_MANAGER,Clock frequency configuration applied,CLOCK_MANAGER Clock frequency configuration applied,0
INFO,DDR_CTRL,DDR training sequence re-initiated,DDR_CTRL DDR training sequence re-initiated,1
WARNING,CLOCK_MANAGER,Clock gate enable/disable sequence out of order,CLOCK_MANAGER Clock gate enable/disable sequence out of order,0
ERROR,AXI_CTRL,AXI protocol violation: AWLEN and ARLEN mismatch with burst type.,AXI_CTRL AXI protocol violation: AWLEN and ARLEN mismatch with burst type.,2
CRITICAL,DMA_ENGINE,DMA system bus master access fault,DMA_ENGINE DMA system bus master access fault,3
INFO,CLOCK_MANAGER,Primary clock source switched to backup,CLOCK_MANAGER Primary clock source switched to backup,0
ERROR,DDR_CTRL,DDR command timing violation detected (tRCD),DDR_CTRL DDR command timing violation detected (tRCD),1
INFO,INTERRUPT_CTRL,Interrupt controller firmware loaded,INTERRUPT_CTRL Interrupt controller firmware loaded,1
ERROR,POWER_CTRL,Power-on sequence interrupted,POWER_CTRL Power-on sequence interrupted,4
ERROR,DDR_CTRL,DDR read data strobe (DQS) calibration failed.,DDR_CTRL DDR read data strobe (DQS) calibration failed.,1
WARNING,MEM_CTRL,ECC error rate increasing,MEM_CTRL ECC error rate increasing,1
INFO,DMA_ENGINE,DMA channel 4 transfer setup completed,DMA_ENGINE DMA channel 4 transfer setup completed,3
ERROR,DDR_CTRL,Dynamic refresh rate adjustment failed to converge,DDR_CTRL Dynamic refresh rate adjustment failed to converge,1
ERROR,FIFO_BUF,FIFO access timeout,FIFO_BUF FIFO access timeout,5
WARNING,DMA_ENGINE,DMA channel 1 transfer completion delay detected,DMA_ENGINE DMA channel 1 transfer completion delay detected,3
INFO,CLOCK_MANAGER,PLL status indicates locked state,CLOCK_MANAGER PLL status indicates locked state,0
ERROR,DMA_ENGINE,DMA descriptor fetch failed for channel 0.,DMA_ENGINE DMA descriptor fetch failed for channel 0.,3
CRITICAL,FIFO_BUF,Persistent FIFO overflow condition,FIFO_BUF Persistent FIFO overflow condition,5
CRITICAL,CACHE_CTRL,"Cache directory lookup failed, disabling L1 cache","CACHE_CTRL Cache directory lookup failed, disabling L1 cache",1
CRITICAL,PCIE_CTRL,"PCIe root complex detection failure, no device enumeration","PCIE_CTRL PCIe root complex detection failure, no device enumeration",6
INFO,PCIE_CTRL,PCIe link state transitioned to L0,PCIE_CTRL PCIe link state transitioned to L0,6
ERROR,INTERRUPT_CTRL,Interrupt controller programming error,INTERRUPT_CTRL Interrupt controller programming error,1
ERROR,FIFO_BUF,FIFO read data error due to asynchronous clock domains,FIFO_BUF FIFO read data error due to asynchronous clock domains,5
CRITICAL,PCIE_CTRL,"PCIe root complex internal error, unrecoverable state transition.","PCIE_CTRL PCIe root complex internal error, unrecoverable state transition.",6
INFO,INTERRUPT_CTRL,Interrupt controller re-enabled after reset,INTERRUPT_CTRL Interrupt controller re-enabled after reset,1
ERROR,POWER_CTRL,Power sequence controller entered invalid state,POWER_CTRL Power sequence controller entered invalid state,4
ERROR,PCIE_CTRL,PCIe device link renegotiation failed,PCIE_CTRL PCIe device link renegotiation failed,6
WARNING,POWER_CTRL,Power domain isolation integrity warning,POWER_CTRL Power domain isolation integrity warning,4
INFO,CLOCK_MANAGER,Clock gate for module X enabled,CLOCK_MANAGER Clock gate for module X enabled,0
INFO,AXI_CTRL,AXI outstanding transaction count reset,AXI_CTRL AXI outstanding transaction count reset,2
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lock lost, critical system failure.","CLOCK_MANAGER Clock generation PLL lock lost, critical system failure.",0
CRITICAL,POWER_CTRL,Power management unit self-test failed,POWER_CTRL Power management unit self-test failed,4
WARNING,FIFO_BUF,FIFO data integrity check reporting intermittent errors,FIFO_BUF FIFO data integrity check reporting intermittent errors,5
WARNING,PCIE_CTRL,PCIe link bandwidth utilization below configured rate,PCIE_CTRL PCIe link bandwidth utilization below configured rate,6
WARNING,DDR_CTRL,DDR read latency exceeding specified maximum,DDR_CTRL DDR read latency exceeding specified maximum,1
CRITICAL,CACHE_CTRL,"Persistent cache coherence violations, system-wide data corruption","CACHE_CTRL Persistent cache coherence violations, system-wide data corruption",1
WARNING,DMA_ENGINE,DMA transfer descriptor read timeout,DMA_ENGINE DMA transfer descriptor read timeout,3
INFO,INTERRUPT_CTRL,Interrupt pending register shows no active requests,INTERRUPT_CTRL Interrupt pending register shows no active requests,1
WARNING,DMA_ENGINE,DMA transfer completion latency exceeding soft threshold,DMA_ENGINE DMA transfer completion latency exceeding soft threshold,3
WARNING,PCIE_CTRL,PCIe completion queue nearing saturation,PCIE_CTRL PCIe completion queue nearing saturation,6
INFO,DMA_ENGINE,DMA transfer completed on channel 2 with 1024 bytes,DMA_ENGINE DMA transfer completed on channel 2 with 1024 bytes,3
ERROR,CLOCK_MANAGER,Reset deassertion synchronization failure on module Y,CLOCK_MANAGER Reset deassertion synchronization failure on module Y,-1
WARNING,MEM_CTRL,"Memory refresh scheduling delay detected, nearing data retention limit.","MEM_CTRL Memory refresh scheduling delay detected, nearing data retention limit.",1
INFO,AXI_CTRL,AXI read request completed on ID 0x33.,AXI_CTRL AXI read request completed on ID 0x33.,2
ERROR,CLOCK_MANAGER,Clock multiplexer selected incorrect clock source.,CLOCK_MANAGER Clock multiplexer selected incorrect clock source.,0
INFO,DMA_ENGINE,DMA channel 7 started new transfer,DMA_ENGINE DMA channel 7 started new transfer,3
WARNING,DDR_CTRL,DDR channel A read latency variance,DDR_CTRL DDR channel A read latency variance,1
INFO,POWER_CTRL,Core voltage rail stable at 1.05V.,POWER_CTRL Core voltage rail stable at 1.05V.,4
WARNING,CACHE_CTRL,Cache way prediction logic reporting low accuracy,CACHE_CTRL Cache way prediction logic reporting low accuracy,1
INFO,FIFO_BUF,FIFO read operation completed successfully,FIFO_BUF FIFO read operation completed successfully,5
INFO,DMA_ENGINE,"DMA transfer to memory initiated, 1KB size","DMA_ENGINE DMA transfer to memory initiated, 1KB size",3
WARNING,DMA_ENGINE,DMA channel idle timeout detected,DMA_ENGINE DMA channel idle timeout detected,3
INFO,CLOCK_MANAGER,Dynamic voltage frequency scaling (DVFS) adjusted,CLOCK_MANAGER Dynamic voltage frequency scaling (DVFS) adjusted,-1
WARNING,POWER_CTRL,Temperature sensor reading 0x7E3F0 approaching limit,POWER_CTRL Temperature sensor reading 0x7E3F0 approaching limit,4
WARNING,DMA_ENGINE,Descriptor fetch latency elevated,DMA_ENGINE Descriptor fetch latency elevated,3
INFO,FIFO_BUF,FIFO_TX buffer empty,FIFO_BUF FIFO_TX buffer empty,5
INFO,FIFO_BUF,FIFO full status de-asserted,FIFO_BUF FIFO full status de-asserted,5
CRITICAL,FIFO_BUF,FIFO memory cell corruption detected,FIFO_BUF FIFO memory cell corruption detected,5
INFO,CLOCK_MANAGER,Clock domain crossing synchronizer reset asserted,CLOCK_MANAGER Clock domain crossing synchronizer reset asserted,0
WARNING,POWER_CTRL,Core voltage droop during high load observed,POWER_CTRL Core voltage droop during high load observed,4
INFO,CACHE_CTRL,Cache bypass mode enabled,CACHE_CTRL Cache bypass mode enabled,1
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold of 448 cycles,FIFO_BUF FIFO latency exceeding expected threshold of 448 cycles,5
INFO,INTERRUPT_CTRL,Interrupt pending for timer event,INTERRUPT_CTRL Interrupt pending for timer event,1
INFO,POWER_CTRL,Power domain power-gated,POWER_CTRL Power domain power-gated,4
WARNING,AXI_CTRL,AXI handshake delay approaching threshold.,AXI_CTRL AXI handshake delay approaching threshold.,2
ERROR,AXI_CTRL,AXI ID tag mismatch on read response,AXI_CTRL AXI ID tag mismatch on read response,2
ERROR,CACHE_CTRL,Cache tag entry for address 0x4000_1234 indicates inconsistent state.,CACHE_CTRL Cache tag entry for address 0x4000_1234 indicates inconsistent state.,1
CRITICAL,DDR_CTRL,DDR memory module self-test failure,DDR_CTRL DDR memory module self-test failure,1
INFO,INTERRUPT_CTRL,Interrupt controller status polled,INTERRUPT_CTRL Interrupt controller status polled,1
ERROR,CACHE_CTRL,"Cache line not written back, dirty bit set","CACHE_CTRL Cache line not written back, dirty bit set",1
INFO,INTERRUPT_CTRL,Interrupt prioritization logic reconfigured,INTERRUPT_CTRL Interrupt prioritization logic reconfigured,1
ERROR,MEM_CTRL,"Memory read data mismatch at address 0xABCD, expected 0x1234, got 0x5678","MEM_CTRL Memory read data mismatch at address 0xABCD, expected 0x1234, got 0x5678",1
WARNING,CACHE_CTRL,Cache eviction policy causing performance drop,CACHE_CTRL Cache eviction policy causing performance drop,1
WARNING,CLOCK_MANAGER,Clock divider output duty cycle deviation,CLOCK_MANAGER Clock divider output duty cycle deviation,0
ERROR,AXI_CTRL,AXI address channel invalid opcode,AXI_CTRL AXI address channel invalid opcode,2
ERROR,DDR_CTRL,DDR controller state machine trapped,DDR_CTRL DDR controller state machine trapped,1
WARNING,POWER_CTRL,Power consumption exceeding estimated budget by 75%.,POWER_CTRL Power consumption exceeding estimated budget by 75%.,4
WARNING,MEM_CTRL,High-frequency memory access patterns observed,MEM_CTRL High-frequency memory access patterns observed,1
ERROR,PCIE_CTRL,PCIe flow control credit exhaustion,PCIE_CTRL PCIe flow control credit exhaustion,6
WARNING,DMA_ENGINE,DMA queue nearing saturation on channel 6 (91%).,DMA_ENGINE DMA queue nearing saturation on channel 6 (91%).,3
ERROR,DDR_CTRL,"Write leveling training failed, memory access unreliable","DDR_CTRL Write leveling training failed, memory access unreliable",1
ERROR,CLOCK_MANAGER,Reset deassertion synchronizer failed to toggle,CLOCK_MANAGER Reset deassertion synchronizer failed to toggle,0
CRITICAL,PCIE_CTRL,PCIe root complex unable to enumerate device,PCIE_CTRL PCIe root complex unable to enumerate device,6
INFO,CLOCK_MANAGER,System clock frequency set to 1GHz,CLOCK_MANAGER System clock frequency set to 1GHz,0
WARNING,DDR_CTRL,DDR training sequence showing marginal results,DDR_CTRL DDR training sequence showing marginal results,1
INFO,MEM_CTRL,Memory controller entering low power state,MEM_CTRL Memory controller entering low power state,1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller hardware fault, no interrupts dispatching","INTERRUPT_CTRL Interrupt controller hardware fault, no interrupts dispatching",1
INFO,DMA_ENGINE,DMA channel opened successfully,DMA_ENGINE DMA channel opened successfully,3
INFO,INTERRUPT_CTRL,Interrupt pending signal deasserted,INTERRUPT_CTRL Interrupt pending signal deasserted,1
ERROR,FIFO_BUF,FIFO underflow condition detected on read,FIFO_BUF FIFO underflow condition detected on read,5
INFO,CACHE_CTRL,Cache coherency protocol enabled,CACHE_CTRL Cache coherency protocol enabled,1
ERROR,MEM_CTRL,Memory access permissions protocol mismatch.,MEM_CTRL Memory access permissions protocol mismatch.,1
CRITICAL,PCIE_CTRL,PCIe root complex reported fatal link error,PCIE_CTRL PCIe root complex reported fatal link error,6
CRITICAL,PCIE_CTRL,"PCIe link in unrecoverable error state, no communication","PCIE_CTRL PCIe link in unrecoverable error state, no communication",6
WARNING,CACHE_CTRL,Cache way miss for critical section,CACHE_CTRL Cache way miss for critical section,1
CRITICAL,MEM_CTRL,"Data integrity violation on memory read, expected 0xABCDEF, got 0x123456","MEM_CTRL Data integrity violation on memory read, expected 0xABCDEF, got 0x123456",1
ERROR,DMA_ENGINE,DMA channel arbitration failure detected for channel 2.,DMA_ENGINE DMA channel arbitration failure detected for channel 2.,3
CRITICAL,DMA_ENGINE,"DMA engine unable to access system memory, fatal error","DMA_ENGINE DMA engine unable to access system memory, fatal error",3
ERROR,DMA_ENGINE,DMA descriptor fetch address misalignment,DMA_ENGINE DMA descriptor fetch address misalignment,3
WARNING,CACHE_CTRL,"Dirty cache line count increasing, pending writebacks","CACHE_CTRL Dirty cache line count increasing, pending writebacks",1
WARNING,DMA_ENGINE,DMA transfer completion interrupt not received,DMA_ENGINE DMA transfer completion interrupt not received,3
WARNING,AXI_CTRL,AXI outstanding write transactions nearing limit on master 0,AXI_CTRL AXI outstanding write transactions nearing limit on master 0,2
WARNING,CACHE_CTRL,Cache fill operation taking too long,CACHE_CTRL Cache fill operation taking too long,1
WARNING,POWER_CTRL,Temperature sensor exceeding warning threshold,POWER_CTRL Temperature sensor exceeding warning threshold,4
ERROR,DMA_ENGINE,DMA descriptor chain corruption detected,DMA_ENGINE DMA descriptor chain corruption detected,3
WARNING,POWER_CTRL,Power sequence start-up delay observed for VDD_RF,POWER_CTRL Power sequence start-up delay observed for VDD_RF,4
INFO,DMA_ENGINE,DMA channel 7 software reset complete,DMA_ENGINE DMA channel 7 software reset complete,3
INFO,CACHE_CTRL,Cache flush operation initiated,CACHE_CTRL Cache flush operation initiated,1
INFO,CACHE_CTRL,Cache miss handled by L2,CACHE_CTRL Cache miss handled by L2,1
ERROR,DDR_CTRL,DDR command queue experienced an unexpected overflow,DDR_CTRL DDR command queue experienced an unexpected overflow,1
INFO,POWER_CTRL,Power mode changed to active state,POWER_CTRL Power mode changed to active state,4
WARNING,DDR_CTRL,DDR command queue depth approaching saturation,DDR_CTRL DDR command queue depth approaching saturation,1
WARNING,CLOCK_MANAGER,CLOCK_MANAGER pending operations in CLOCK_MANAGER accumulating.,CLOCK_MANAGER CLOCK_MANAGER pending operations in CLOCK_MANAGER accumulating.,0
INFO,DMA_ENGINE,DMA channel 13 configured for memory-to-memory,DMA_ENGINE DMA channel 13 configured for memory-to-memory,3
ERROR,CACHE_CTRL,Snoop response error during coherence transaction,CACHE_CTRL Snoop response error during coherence transaction,1
CRITICAL,AXI_CTRL,AXI protocol critical violation leading to bus unresponsiveness,AXI_CTRL AXI protocol critical violation leading to bus unresponsiveness,2
WARNING,DMA_ENGINE,DMA engine requested more memory bandwidth than available.,DMA_ENGINE DMA engine requested more memory bandwidth than available.,3
WARNING,CACHE_CTRL,Cache way tag conflict increasing thrashing,CACHE_CTRL Cache way tag conflict increasing thrashing,1
WARNING,CACHE_CTRL,"Cache dirty line count elevated, awaiting writeback","CACHE_CTRL Cache dirty line count elevated, awaiting writeback",1
CRITICAL,PCIE_CTRL,PCIe device BAR configuration failure,PCIE_CTRL PCIe device BAR configuration failure,6
WARNING,CLOCK_MANAGER,Clock domain crossing bridge experiencing data loss.,CLOCK_MANAGER Clock domain crossing bridge experiencing data loss.,0
WARNING,INTERRUPT_CTRL,Interrupt controller queue depth increasing.,INTERRUPT_CTRL Interrupt controller queue depth increasing.,1
WARNING,INTERRUPT_CTRL,Interrupt queue depth approaching limit,INTERRUPT_CTRL Interrupt queue depth approaching limit,1
CRITICAL,MEM_CTRL,Memory controller internal deadlock detected.,MEM_CTRL Memory controller internal deadlock detected.,1
WARNING,DMA_ENGINE,DMA transfer in progress for extended duration,DMA_ENGINE DMA transfer in progress for extended duration,3
INFO,INTERRUPT_CTRL,Interrupt handler for IRQ 7 dispatched,INTERRUPT_CTRL Interrupt handler for IRQ 7 dispatched,1
ERROR,FIFO_BUF,FIFO write operation aborted due to full condition,FIFO_BUF FIFO write operation aborted due to full condition,5
ERROR,CACHE_CTRL,Cache line fill operation received invalid data,CACHE_CTRL Cache line fill operation received invalid data,1
ERROR,INTERRUPT_CTRL,Interrupt source not registered in vector table,INTERRUPT_CTRL Interrupt source not registered in vector table,1
ERROR,DMA_ENGINE,DMA channel 1 burst length violation,DMA_ENGINE DMA channel 1 burst length violation,3
ERROR,POWER_CTRL,Core voltage rail sags below minimum operating threshold,POWER_CTRL Core voltage rail sags below minimum operating threshold,4
WARNING,CLOCK_MANAGER,Clock distribution network delay variation,CLOCK_MANAGER Clock distribution network delay variation,0
INFO,DMA_ENGINE,DMA engine configured for burst transfers,DMA_ENGINE DMA engine configured for burst transfers,3
CRITICAL,POWER_CTRL,System power-on reset circuit failure,POWER_CTRL System power-on reset circuit failure,4
WARNING,PCIE_CTRL,PCIe PHY layer error counter incrementing rapidly,PCIE_CTRL PCIe PHY layer error counter incrementing rapidly,6
CRITICAL,POWER_CTRL,"Voltage regulator output unstable, critical","POWER_CTRL Voltage regulator output unstable, critical",4
CRITICAL,CLOCK_MANAGER,Clock generation PLL lock lost (230MHz).,CLOCK_MANAGER Clock generation PLL lock lost (230MHz).,0
INFO,CLOCK_MANAGER,Clock gate enable signal glitches detected,CLOCK_MANAGER Clock gate enable signal glitches detected,0
WARNING,FIFO_BUF,Input FIFO buffer occupancy reached 95%,FIFO_BUF Input FIFO buffer occupancy reached 95%,5
WARNING,FIFO_BUF,FIFO_BRIDGE_A_B throughput degraded by 15%.,FIFO_BUF FIFO_BRIDGE_A_B throughput degraded by 15%.,-1
INFO,DMA_ENGINE,DMA channel 3 transfer verification successful,DMA_ENGINE DMA channel 3 transfer verification successful,3
CRITICAL,POWER_CTRL,Voltage regulator output short detected,POWER_CTRL Voltage regulator output short detected,-1
CRITICAL,POWER_CTRL,Critical power rail shutdown initiated,POWER_CTRL Critical power rail shutdown initiated,4
INFO,FIFO_BUF,FIFO_BUF_7 successfully drained,FIFO_BUF FIFO_BUF_7 successfully drained,-1
WARNING,PCIE_CTRL,PCIe deskew processing approaching limit,PCIE_CTRL PCIe deskew processing approaching limit,6
WARNING,CLOCK_MANAGER,Clock domain crossing bridge latency increasing,CLOCK_MANAGER Clock domain crossing bridge latency increasing,0
WARNING,FIFO_BUF,FIFO almost-empty signal active for extended period,FIFO_BUF FIFO almost-empty signal active for extended period,5
CRITICAL,DDR_CTRL,"DDR memory bank conflict detected, leading to data corruption","DDR_CTRL DDR memory bank conflict detected, leading to data corruption",1
ERROR,POWER_CTRL,Power management controller response timeout.,POWER_CTRL Power management controller response timeout.,4
CRITICAL,DMA_ENGINE,DMA engine unable to respond to configuration writes,DMA_ENGINE DMA engine unable to respond to configuration writes,3
CRITICAL,MEM_CTRL,Memory controller detected an invalid address range access,MEM_CTRL Memory controller detected an invalid address range access,1
WARNING,POWER_CTRL,Power management unit activity logging disabled,POWER_CTRL Power management unit activity logging disabled,-1
ERROR,DMA_ENGINE,DMA source/destination address alignment violation,DMA_ENGINE DMA source/destination address alignment violation,3
ERROR,CLOCK_MANAGER,"PLL loss of lock, timing violation.","CLOCK_MANAGER PLL loss of lock, timing violation.",0
WARNING,MEM_CTRL,Memory refresh cycle delayed beyond optimal window,MEM_CTRL Memory refresh cycle delayed beyond optimal window,1
ERROR,CACHE_CTRL,Cache coherence violation detected.,CACHE_CTRL Cache coherence violation detected.,1
CRITICAL,CLOCK_MANAGER,Global clock tree integrity compromised,CLOCK_MANAGER Global clock tree integrity compromised,0
WARNING,INTERRUPT_CTRL,Multiple interrupts asserted simultaneously for low priority,INTERRUPT_CTRL Multiple interrupts asserted simultaneously for low priority,1
ERROR,DDR_CTRL,"DDR command queue timeout, unable to issue next command","DDR_CTRL DDR command queue timeout, unable to issue next command",1
ERROR,POWER_CTRL,Power domain X voltage ripple exceeded specification,POWER_CTRL Power domain X voltage ripple exceeded specification,4
CRITICAL,DDR_CTRL,"DDR controller entered critical error state, system memory unavailable (controller 0x0)","DDR_CTRL DDR controller entered critical error state, system memory unavailable (controller 0x0)",1
INFO,MEM_CTRL,Memory initialization sequence completed,MEM_CTRL Memory initialization sequence completed,1
CRITICAL,POWER_CTRL,Main power rail instability led to brown-out reset,POWER_CTRL Main power rail instability led to brown-out reset,4
INFO,CACHE_CTRL,L1 cache statistics reset,CACHE_CTRL L1 cache statistics reset,1
CRITICAL,CLOCK_MANAGER,CDC metastability event detected on critical path,CLOCK_MANAGER CDC metastability event detected on critical path,0
WARNING,AXI_CTRL,AXI exclusive access sequence violation,AXI_CTRL AXI exclusive access sequence violation,2
ERROR,INTERRUPT_CTRL,Interrupt controller shadow register mismatch,INTERRUPT_CTRL Interrupt controller shadow register mismatch,-1
ERROR,DDR_CTRL,DDR write data group latency violation,DDR_CTRL DDR write data group latency violation,1
ERROR,CLOCK_MANAGER,Clock phase detection failure for high-speed serial link.,CLOCK_MANAGER Clock phase detection failure for high-speed serial link.,-1
INFO,INTERRUPT_CTRL,Software interrupt triggered,INTERRUPT_CTRL Software interrupt triggered,1
INFO,CACHE_CTRL,Cache line replacement policy active,CACHE_CTRL Cache line replacement policy active,1
ERROR,DDR_CTRL,DDR training sequence failed,DDR_CTRL DDR training sequence failed,1
ERROR,INTERRUPT_CTRL,Interrupt vector table lookup failed for IRQ 5,INTERRUPT_CTRL Interrupt vector table lookup failed for IRQ 5,1
ERROR,PCIE_CTRL,PCIe flow control credit deadlock detected,PCIE_CTRL PCIe flow control credit deadlock detected,6
CRITICAL,POWER_CTRL,"Primary power supply unit reporting fatal error, system shutdown.","POWER_CTRL Primary power supply unit reporting fatal error, system shutdown.",4
WARNING,FIFO_BUF,Backpressure asserted,FIFO_BUF Backpressure asserted,5
INFO,POWER_CTRL,Power domain G power-on sequence started,POWER_CTRL Power domain G power-on sequence started,4
WARNING,DDR_CTRL,DDR memory write latency above threshold,DDR_CTRL DDR memory write latency above threshold,1
WARNING,CLOCK_MANAGER,Clock domain crossing FIFO fill level nearing full.,CLOCK_MANAGER Clock domain crossing FIFO fill level nearing full.,0
INFO,DMA_ENGINE,DMA channel 2 transfer data count set,DMA_ENGINE DMA channel 2 transfer data count set,3
ERROR,FIFO_BUF,FIFO watermark event triggered unexpectedly,FIFO_BUF FIFO watermark event triggered unexpectedly,5
INFO,DMA_ENGINE,DMA channel 0 paused by software request,DMA_ENGINE DMA channel 0 paused by software request,3
INFO,CACHE_CTRL,"Cache eviction queue nearing capacity, consider flush","CACHE_CTRL Cache eviction queue nearing capacity, consider flush",1
WARNING,MEM_CTRL,Memory bank 2 experiencing higher than average error rate.,MEM_CTRL Memory bank 2 experiencing higher than average error rate.,1
ERROR,CACHE_CTRL,Snoop filter integrity check failed.,CACHE_CTRL Snoop filter integrity check failed.,1
ERROR,MEM_CTRL,Memory write data integrity check failure,MEM_CTRL Memory write data integrity check failure,1
WARNING,PCIE_CTRL,PCIe TLP receive buffer 0 nearing overflow.,PCIE_CTRL PCIe TLP receive buffer 0 nearing overflow.,6
WARNING,CLOCK_MANAGER,Clock signal overshoot detected on rising edge,CLOCK_MANAGER Clock signal overshoot detected on rising edge,0
INFO,AXI_CTRL,AXI write transaction completed on channel Y.,AXI_CTRL AXI write transaction completed on channel Y.,2
ERROR,CACHE_CTRL,Cache line invalidated while still dirty,CACHE_CTRL Cache line invalidated while still dirty,1
INFO,DDR_CTRL,DDR low power state entered successfully,DDR_CTRL DDR low power state entered successfully,1
WARNING,DDR_CTRL,DRAM temperature approaching critical threshold,DDR_CTRL DRAM temperature approaching critical threshold,1
INFO,INTERRUPT_CTRL,Interrupt pending for device ID 0x2C,INTERRUPT_CTRL Interrupt pending for device ID 0x2C,1
INFO,CLOCK_MANAGER,Clock divider configuration updated,CLOCK_MANAGER Clock divider configuration updated,0
ERROR,FIFO_BUF,FIFO output underflow detected,FIFO_BUF FIFO output underflow detected,5
INFO,INTERRUPT_CTRL,Interrupt controller debug registers read,INTERRUPT_CTRL Interrupt controller debug registers read,1
WARNING,DMA_ENGINE,"DMA channel 8 stall detected, potential data path blockage","DMA_ENGINE DMA channel 8 stall detected, potential data path blockage",3
ERROR,POWER_CTRL,Power rail sequencing timeout during power-down,POWER_CTRL Power rail sequencing timeout during power-down,4
INFO,DDR_CTRL,DDR controller operating in command pass-through mode,DDR_CTRL DDR controller operating in command pass-through mode,1
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding maximum,INTERRUPT_CTRL Interrupt latency exceeding maximum,1
INFO,DDR_CTRL,DDR controller exiting low power mode,DDR_CTRL DDR controller exiting low power mode,1
INFO,INTERRUPT_CTRL,Interrupt priority encoder configured,INTERRUPT_CTRL Interrupt priority encoder configured,1
ERROR,DMA_ENGINE,DMA channel arbitration conflict.,DMA_ENGINE DMA channel arbitration conflict.,3
CRITICAL,PCIE_CTRL,PCIe root complex bridge in unrecoverable state,PCIE_CTRL PCIe root complex bridge in unrecoverable state,6
ERROR,POWER_CTRL,Functional failure in POWER_CTRL due to invalid state transition (unexpected state change).,POWER_CTRL Functional failure in POWER_CTRL due to invalid state transition (unexpected state change).,4
INFO,MEM_CTRL,MEM_CTRL configuration update applied.,MEM_CTRL MEM_CTRL configuration update applied.,-1
INFO,CLOCK_MANAGER,Clock frequency change pending,CLOCK_MANAGER Clock frequency change pending,0
ERROR,POWER_CTRL,Power rail sequencing error during boot-up,POWER_CTRL Power rail sequencing error during boot-up,4
INFO,CLOCK_MANAGER,Clock synthesizer frequency sweep initiated,CLOCK_MANAGER Clock synthesizer frequency sweep initiated,-1
CRITICAL,MEM_CTRL,Memory controller state machine entered an unrecoverable hung state,MEM_CTRL Memory controller state machine entered an unrecoverable hung state,1
INFO,DDR_CTRL,DDR_CTRL monitoring initiated.,DDR_CTRL DDR_CTRL monitoring initiated.,1
WARNING,AXI_CTRL,"AXI burst length greater than 16 detected, potential bottleneck","AXI_CTRL AXI burst length greater than 16 detected, potential bottleneck",2
INFO,INTERRUPT_CTRL,Interrupt 0x20 cleared by ISR,INTERRUPT_CTRL Interrupt 0x20 cleared by ISR,1
ERROR,FIFO_BUF,FIFO 'result_buffer' reported persistent underflow,FIFO_BUF FIFO 'result_buffer' reported persistent underflow,5
ERROR,PCIE_CTRL,PCIe poisoned TLP detected,PCIE_CTRL PCIe poisoned TLP detected,6
ERROR,FIFO_BUF,FIFO read data output corrupted,FIFO_BUF FIFO read data output corrupted,5
WARNING,DDR_CTRL,DDR write data mask timing deviation,DDR_CTRL DDR write data mask timing deviation,1
CRITICAL,DDR_CTRL,DDR initialization sequence failed at memory training phase,DDR_CTRL DDR initialization sequence failed at memory training phase,1
WARNING,DDR_CTRL,DDR self-refresh entry/exit timing deviation,DDR_CTRL DDR self-refresh entry/exit timing deviation,1
INFO,AXI_CTRL,AXI master 0 released bus ownership,AXI_CTRL AXI master 0 released bus ownership,2
INFO,CACHE_CTRL,Cache line prefetch initiated,CACHE_CTRL Cache line prefetch initiated,1
WARNING,CLOCK_MANAGER,"Main PLL temperature elevated (85C), monitor closely","CLOCK_MANAGER Main PLL temperature elevated (85C), monitor closely",-1
WARNING,DDR_CTRL,DDR write latency variance detected,DDR_CTRL DDR write latency variance detected,1
CRITICAL,MEM_CTRL,Uncorrectable multi-bit ECC error detected in main memory block,MEM_CTRL Uncorrectable multi-bit ECC error detected in main memory block,1
CRITICAL,POWER_CTRL,"Power rail instability detected, forced shutdown","POWER_CTRL Power rail instability detected, forced shutdown",4
CRITICAL,CLOCK_MANAGER,"Clock tree integrity check failed, critical clock missing","CLOCK_MANAGER Clock tree integrity check failed, critical clock missing",0
CRITICAL,MEM_CTRL,Memory controller self-test failed critically,MEM_CTRL Memory controller self-test failed critically,1
INFO,CLOCK_MANAGER,Clock domain stable.,CLOCK_MANAGER Clock domain stable.,0
CRITICAL,DDR_CTRL,DDR double-bit ECC error detected during scrub.,DDR_CTRL DDR double-bit ECC error detected during scrub.,1
CRITICAL,POWER_CTRL,Core voltage rail unresponsive,POWER_CTRL Core voltage rail unresponsive,4
WARNING,MEM_CTRL,Memory access latency increasing on bank 2,MEM_CTRL Memory access latency increasing on bank 2,1
WARNING,POWER_CTRL,Voltage regulator V_SOC output ripple exceeding specification,POWER_CTRL Voltage regulator V_SOC output ripple exceeding specification,4
CRITICAL,MEM_CTRL,Memory controller experienced catastrophic data integrity issue,MEM_CTRL Memory controller experienced catastrophic data integrity issue,1
ERROR,POWER_CTRL,Power controller internal state machine error at state 0xF0.,POWER_CTRL Power controller internal state machine error at state 0xF0.,4
CRITICAL,FIFO_BUF,"FIFO internal pointer corruption detected, unable to recover","FIFO_BUF FIFO internal pointer corruption detected, unable to recover",5
ERROR,POWER_CTRL,Voltage level detection circuit malfunction,POWER_CTRL Voltage level detection circuit malfunction,-1
ERROR,PCIE_CTRL,PCIe CRC error detected on received TLP,PCIE_CTRL PCIe CRC error detected on received TLP,6
INFO,AXI_CTRL,AXI master 'video_encoder' initiated read burst,AXI_CTRL AXI master 'video_encoder' initiated read burst,2
ERROR,AXI_CTRL,AXI atomic operation protocol mismatch detected.,AXI_CTRL AXI atomic operation protocol mismatch detected.,2
CRITICAL,MEM_CTRL,Double bit ECC detected during memory writeback,MEM_CTRL Double bit ECC detected during memory writeback,1
WARNING,DMA_ENGINE,DMA transfer rate below expected performance for channel CH1.,DMA_ENGINE DMA transfer rate below expected performance for channel CH1.,3
INFO,FIFO_BUF,FIFO status register polled for empty flag,FIFO_BUF FIFO status register polled for empty flag,5
INFO,DDR_CTRL,DDR power-down mode entered,DDR_CTRL DDR power-down mode entered,1
ERROR,INTERRUPT_CTRL,Interrupt dispatch timeout for 'TIMER_IRQ',INTERRUPT_CTRL Interrupt dispatch timeout for 'TIMER_IRQ',1
ERROR,POWER_CTRL,Power-on reset deassertion timeout,POWER_CTRL Power-on reset deassertion timeout,4
INFO,DMA_ENGINE,DMA transfer setup for channel 1,DMA_ENGINE DMA transfer setup for channel 1,3
WARNING,AXI_CTRL,AXI master requesting out-of-order responses without reordering capability,AXI_CTRL AXI master requesting out-of-order responses without reordering capability,-1
CRITICAL,DMA_ENGINE,DMA control register readback mismatch after write.,DMA_ENGINE DMA control register readback mismatch after write.,3
INFO,DMA_ENGINE,DMA descriptor fetch successful for channel 4,DMA_ENGINE DMA descriptor fetch successful for channel 4,3
CRITICAL,POWER_CTRL,Voltage regulator output current limit exceeded,POWER_CTRL Voltage regulator output current limit exceeded,4
WARNING,FIFO_BUF,FIFO_PCI_BRIDGE read pointer about to overtake write pointer.,FIFO_BUF FIFO_PCI_BRIDGE read pointer about to overtake write pointer.,5
CRITICAL,AXI_CTRL,AXI bus master 3 permanently stalled on write response,AXI_CTRL AXI bus master 3 permanently stalled on write response,2
ERROR,CLOCK_MANAGER,Primary clock source failed to lock,CLOCK_MANAGER Primary clock source failed to lock,0
ERROR,INTERRUPT_CTRL,INTERRUPT_CTRL detected a severe deadlock detected: resource contention deadlock. (Conflicting IRQ IDs: 29 and 19),INTERRUPT_CTRL INTERRUPT_CTRL detected a severe deadlock detected: resource contention deadlock. (Conflicting IRQ IDs: 29 and 19),1
ERROR,AXI_CTRL,AXI outstanding write transaction limit exceeded,AXI_CTRL AXI outstanding write transaction limit exceeded,2
INFO,FIFO_BUF,FIFO data available for consumption,FIFO_BUF FIFO data available for consumption,5
ERROR,DDR_CTRL,DDR burst boundary violation,DDR_CTRL DDR burst boundary violation,1
WARNING,DDR_CTRL,DDR refresh cycle delayed (915 cycles).,DDR_CTRL DDR refresh cycle delayed (915 cycles).,1
WARNING,DDR_CTRL,DDR command timing violation detected on precharge command,DDR_CTRL DDR command timing violation detected on precharge command,1
ERROR,DDR_CTRL,DDR MRS command timing violation,DDR_CTRL DDR MRS command timing violation,1
INFO,CACHE_CTRL,Cache line replacement using LRU policy,CACHE_CTRL Cache line replacement using LRU policy,1
WARNING,AXI_CTRL,AXI transaction with inconsistent ID values,AXI_CTRL AXI transaction with inconsistent ID values,2
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold (15%),CACHE_CTRL Cache miss rate exceeding expected threshold (15%),1
ERROR,CLOCK_MANAGER,Clock generation PLL unable to relock,CLOCK_MANAGER Clock generation PLL unable to relock,0
ERROR,FIFO_BUF,FIFO 'queue_in' detected persistent overflow condition,FIFO_BUF FIFO 'queue_in' detected persistent overflow condition,5
WARNING,AXI_CTRL,AXI read address channel pending for too long,AXI_CTRL AXI read address channel pending for too long,2
CRITICAL,POWER_CTRL,"Core voltage out of specification (power rail instability), hardware damage possible","POWER_CTRL Core voltage out of specification (power rail instability), hardware damage possible",4
ERROR,AXI_CTRL,AXI read data channel stall detected,AXI_CTRL AXI read data channel stall detected,2
INFO,AXI_CTRL,AXI bus master 0x4 issued a WLAST=1 write,AXI_CTRL AXI bus master 0x4 issued a WLAST=1 write,2
ERROR,FIFO_BUF,FIFO almost full condition persistent,FIFO_BUF FIFO almost full condition persistent,5
ERROR,CACHE_CTRL,Cache M-state transition failed due to contention,CACHE_CTRL Cache M-state transition failed due to contention,1
ERROR,INTERRUPT_CTRL,"Interrupt arbitration unit hung, IRQs not being processed","INTERRUPT_CTRL Interrupt arbitration unit hung, IRQs not being processed",1
INFO,PCIE_CTRL,PCIe hot-reset issued to device 0x02.,PCIE_CTRL PCIe hot-reset issued to device 0x02.,6
WARNING,AXI_CTRL,AXI response channel backpressure detected,AXI_CTRL AXI response channel backpressure detected,2
ERROR,INTERRUPT_CTRL,"Interrupt controller arbiter stuck, no new interrupts dispatched","INTERRUPT_CTRL Interrupt controller arbiter stuck, no new interrupts dispatched",1
WARNING,CACHE_CTRL,Cache associativity conflicts increasing,CACHE_CTRL Cache associativity conflicts increasing,1
INFO,CACHE_CTRL,Cache flush operation completed,CACHE_CTRL Cache flush operation completed,1
INFO,AXI_CTRL,AXI write transaction completed on slave 1,AXI_CTRL AXI write transaction completed on slave 1,2
INFO,INTERRUPT_CTRL,Interrupt vector updated for new driver,INTERRUPT_CTRL Interrupt vector updated for new driver,1
ERROR,POWER_CTRL,Voltage regulator module (VRM) reports fault condition,POWER_CTRL Voltage regulator module (VRM) reports fault condition,-1
INFO,DDR_CTRL,DDR controller entered low power state,DDR_CTRL DDR controller entered low power state,1
CRITICAL,DMA_ENGINE,DMA descriptor fetched with zero transfer size,DMA_ENGINE DMA descriptor fetched with zero transfer size,3
INFO,FIFO_BUF,FIFO_I2C_RX buffer empty,FIFO_BUF FIFO_I2C_RX buffer empty,5
ERROR,CACHE_CTRL,Cache dirty bit corruption detected,CACHE_CTRL Cache dirty bit corruption detected,1
WARNING,INTERRUPT_CTRL,"Interrupt request IRQ_SENSOR_02 asserted, but not acknowledged for extended period.","INTERRUPT_CTRL Interrupt request IRQ_SENSOR_02 asserted, but not acknowledged for extended period.",-1
WARNING,POWER_CTRL,Voltage rail ripple increasing,POWER_CTRL Voltage rail ripple increasing,4
ERROR,MEM_CTRL,Memory burst length violation detected,MEM_CTRL Memory burst length violation detected,1
ERROR,MEM_CTRL,Read-after-write data coherency violation,MEM_CTRL Read-after-write data coherency violation,1
INFO,POWER_CTRL,System power consumption within specification,POWER_CTRL System power consumption within specification,4
CRITICAL,DMA_ENGINE,DMA controller encountered uncorrectable bus error on descriptor fetch,DMA_ENGINE DMA controller encountered uncorrectable bus error on descriptor fetch,3
WARNING,POWER_CTRL,Auxiliary power rail current draw above specification,POWER_CTRL Auxiliary power rail current draw above specification,-1
WARNING,FIFO_BUF,FIFO almost full threshold reached,FIFO_BUF FIFO almost full threshold reached,5
ERROR,POWER_CTRL,Main power supply ripple exceeding specification,POWER_CTRL Main power supply ripple exceeding specification,4
ERROR,DMA_ENGINE,DMA channel 14 configuration register corruption,DMA_ENGINE DMA channel 14 configuration register corruption,3
INFO,AXI_CTRL,AW/AR channels are idle.,AXI_CTRL AW/AR channels are idle.,-1
WARNING,DDR_CTRL,DDR command queue depth high,DDR_CTRL DDR command queue depth high,1
INFO,MEM_CTRL,Memory integrity check passed.,MEM_CTRL Memory integrity check passed.,1
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold for L1d,CACHE_CTRL Cache miss rate exceeding expected threshold for L1d,1
WARNING,CACHE_CTRL,Cache refill pending due to high bus traffic,CACHE_CTRL Cache refill pending due to high bus traffic,1
CRITICAL,CLOCK_MANAGER,Clock network distribution integrity check failed,CLOCK_MANAGER Clock network distribution integrity check failed,0
ERROR,FIFO_BUF,Output FIFO data corruption detected,FIFO_BUF Output FIFO data corruption detected,5
ERROR,PCIE_CTRL,PCIe MSI-X table access violation,PCIE_CTRL PCIe MSI-X table access violation,-1
CRITICAL,MEM_CTRL,Persistent memory parity errors across multiple accesses,MEM_CTRL Persistent memory parity errors across multiple accesses,1
CRITICAL,AXI_CTRL,Unrecoverable AXI protocol error leading to system halt,AXI_CTRL Unrecoverable AXI protocol error leading to system halt,2
WARNING,CLOCK_MANAGER,Clock mux selection changed without proper synchronization,CLOCK_MANAGER Clock mux selection changed without proper synchronization,0
INFO,PCIE_CTRL,PCIe maximum payload size configured to 256 bytes,PCIE_CTRL PCIe maximum payload size configured to 256 bytes,6
INFO,PCIE_CTRL,TLP transmitted on lane 5.,PCIE_CTRL TLP transmitted on lane 5.,6
ERROR,PCIE_CTRL,"PCIe transaction queue full, dropping packets","PCIE_CTRL PCIe transaction queue full, dropping packets",6
CRITICAL,POWER_CTRL,Power management unit lost communication with core,POWER_CTRL Power management unit lost communication with core,4
INFO,CLOCK_MANAGER,Clock divider for module AXI_CTRL configured,CLOCK_MANAGER Clock divider for module AXI_CTRL configured,-1
CRITICAL,PCIE_CTRL,PCIe link width reduction detected,PCIE_CTRL PCIe link width reduction detected,6
WARNING,INTERRUPT_CTRL,Non-maskable interrupt (NMI) assert de-assert glitch,INTERRUPT_CTRL Non-maskable interrupt (NMI) assert de-assert glitch,1
WARNING,AXI_CTRL,AXI outstanding transaction count nearing maximum on M2,AXI_CTRL AXI outstanding transaction count nearing maximum on M2,2
CRITICAL,MEM_CTRL,"CRITICAL: Memory controller response to reset sequence failed, memory unresponsive.","MEM_CTRL CRITICAL: Memory controller response to reset sequence failed, memory unresponsive.",1
ERROR,AXI_CTRL,"AXI_CTRL: transaction timeout - no response to transaction request detected. (Master ID: 2, AXI ID: 14)","AXI_CTRL AXI_CTRL: transaction timeout - no response to transaction request detected. (Master ID: 2, AXI ID: 14)",2
INFO,CACHE_CTRL,Cache hit detected for address 0x00000000.,CACHE_CTRL Cache hit detected for address 0x00000000.,1
INFO,MEM_CTRL,Memory controller state reset to idle,MEM_CTRL Memory controller state reset to idle,1
ERROR,PCIE_CTRL,PCIe link Layer Replay Timeout detected.,PCIE_CTRL PCIe link Layer Replay Timeout detected.,6
ERROR,DDR_CTRL,DDR bank activate command timing violation,DDR_CTRL DDR bank activate command timing violation,1
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range for sensitive path,CLOCK_MANAGER Clock skew approaching unsafe range for sensitive path,0
WARNING,AXI_CTRL,AXI read address channel congestion,AXI_CTRL AXI read address channel congestion,2
ERROR,PCIE_CTRL,PCIe transaction layer packet (TLP) CRC error,PCIE_CTRL PCIe transaction layer packet (TLP) CRC error,6
WARNING,CLOCK_MANAGER,System reset deassertion timing not optimal,CLOCK_MANAGER System reset deassertion timing not optimal,0
WARNING,DDR_CTRL,DDR read latency variation detected across banks,DDR_CTRL DDR read latency variation detected across banks,1
CRITICAL,POWER_CTRL,"Sustained power rail instability detected across multiple domains, initiating emergency shutdown.","POWER_CTRL Sustained power rail instability detected across multiple domains, initiating emergency shutdown.",4
INFO,FIFO_BUF,FIFO write operation acknowledged,FIFO_BUF FIFO write operation acknowledged,5
ERROR,POWER_CTRL,"Brown-out detection asserted unexpectedly, state machine fault.","POWER_CTRL Brown-out detection asserted unexpectedly, state machine fault.",4
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold (75%).,CACHE_CTRL Cache miss rate exceeding expected threshold (75%).,1
ERROR,FIFO_BUF,FIFO 'command_response' pointer values diverged,FIFO_BUF FIFO 'command_response' pointer values diverged,-1
WARNING,DDR_CTRL,DDR memory address bus showing intermittent errors,DDR_CTRL DDR memory address bus showing intermittent errors,1
ERROR,DDR_CTRL,DDR address bus inversion (ABI) calibration failed,DDR_CTRL DDR address bus inversion (ABI) calibration failed,-1
CRITICAL,CLOCK_MANAGER,"Primary clock buffer failure, system clock degraded","CLOCK_MANAGER Primary clock buffer failure, system clock degraded",0
WARNING,FIFO_BUF,FIFO write operation rejected due to busy status,FIFO_BUF FIFO write operation rejected due to busy status,5
INFO,CLOCK_MANAGER,Gate clock status: active,CLOCK_MANAGER Gate clock status: active,0
WARNING,INTERRUPT_CTRL,Interrupt controller polling rate for slow devices reduced due to load.,INTERRUPT_CTRL Interrupt controller polling rate for slow devices reduced due to load.,-1
WARNING,DDR_CTRL,DDR bank access conflict detected,DDR_CTRL DDR bank access conflict detected,1
WARNING,POWER_CTRL,Voltage rail VDD_IO marginally out of range (1.17V),POWER_CTRL Voltage rail VDD_IO marginally out of range (1.17V),4
INFO,INTERRUPT_CTRL,Interrupt source ID 2 asserted,INTERRUPT_CTRL Interrupt source ID 2 asserted,1
WARNING,AXI_CTRL,AXI outstanding write transaction count exceeding 12,AXI_CTRL AXI outstanding write transaction count exceeding 12,2
ERROR,POWER_CTRL,Voltage regulator response timeout detected on VDD_GPU rail.,POWER_CTRL Voltage regulator response timeout detected on VDD_GPU rail.,4
INFO,INTERRUPT_CTRL,Interrupt vector updated by firmware,INTERRUPT_CTRL Interrupt vector updated by firmware,1
INFO,POWER_CTRL,All power domains reported stable,POWER_CTRL All power domains reported stable,4
WARNING,CLOCK_MANAGER,High-speed clock domain power-gating not fully engaged,CLOCK_MANAGER High-speed clock domain power-gating not fully engaged,-1
WARNING,AXI_CTRL,AXI arbiter fairness issue detected,AXI_CTRL AXI arbiter fairness issue detected,2
ERROR,FIFO_BUF,FIFO_TX_0 overflow condition,FIFO_BUF FIFO_TX_0 overflow condition,5
ERROR,INTERRUPT_CTRL,"Spurious interrupt detected, vector ID unknown","INTERRUPT_CTRL Spurious interrupt detected, vector ID unknown",1
WARNING,PCIE_CTRL,PCIe error logging buffer nearing capacity,PCIE_CTRL PCIe error logging buffer nearing capacity,6
ERROR,AXI_CTRL,"AXI burst length violation detected (length=38, max 86).","AXI_CTRL AXI burst length violation detected (length=38, max 86).",2
WARNING,DMA_ENGINE,DMA transfer pending for high priority channel,DMA_ENGINE DMA transfer pending for high priority channel,3
ERROR,DDR_CTRL,DDR command scheduling conflict detected.,DDR_CTRL DDR command scheduling conflict detected.,1
CRITICAL,PCIE_CTRL,PCIe core configuration registers corrupted,PCIE_CTRL PCIe core configuration registers corrupted,6
WARNING,AXI_CTRL,AXI read data width mismatch detected,AXI_CTRL AXI read data width mismatch detected,2
WARNING,POWER_CTRL,Standby power mode entry delay,POWER_CTRL Standby power mode entry delay,4
ERROR,DMA_ENGINE,DMA transaction integrity check failed,DMA_ENGINE DMA transaction integrity check failed,3
WARNING,DDR_CTRL,DDR refresh command frequency too low,DDR_CTRL DDR refresh command frequency too low,1
ERROR,DMA_ENGINE,"DMA channel 2 descriptor fetch failed, invalid pointer","DMA_ENGINE DMA channel 2 descriptor fetch failed, invalid pointer",3
ERROR,DDR_CTRL,Data strobe timing error,DDR_CTRL Data strobe timing error,1
INFO,FIFO_BUF,FIFO_BUF_13 successfully re-initialized,FIFO_BUF FIFO_BUF_13 successfully re-initialized,5
ERROR,AXI_CTRL,AXI response channel `RRESP` indicating decode error,AXI_CTRL AXI response channel `RRESP` indicating decode error,2
WARNING,DDR_CTRL,DDR refresh controller missed a cycle,DDR_CTRL DDR refresh controller missed a cycle,1
ERROR,CACHE_CTRL,Cache coherency protocol violation,CACHE_CTRL Cache coherency protocol violation,1
WARNING,DDR_CTRL,DDR write latency jitter exceeding threshold.,DDR_CTRL DDR write latency jitter exceeding threshold.,1
INFO,FIFO_BUF,FIFO level below watermark A,FIFO_BUF FIFO level below watermark A,5
WARNING,CLOCK_MANAGER,Clock synchronization handshake timeout detected,CLOCK_MANAGER Clock synchronization handshake timeout detected,0
ERROR,MEM_CTRL,Multi-channel memory arbitration conflict detected,MEM_CTRL Multi-channel memory arbitration conflict detected,1
ERROR,CACHE_CTRL,Cache directory coherence check failed,CACHE_CTRL Cache directory coherence check failed,1
CRITICAL,DDR_CTRL,DDR memory DIMM failure,DDR_CTRL DDR memory DIMM failure,1
WARNING,MEM_CTRL,Memory write latency exceeding acceptable limits,MEM_CTRL Memory write latency exceeding acceptable limits,1
ERROR,MEM_CTRL,Memory controller internal state machine error,MEM_CTRL Memory controller internal state machine error,1
WARNING,PCIE_CTRL,PCIe hot-reset sequence initiated due to error,PCIE_CTRL PCIe hot-reset sequence initiated due to error,6
WARNING,DMA_ENGINE,DMA channel 'FLASH_WR' transfer rate degraded,DMA_ENGINE DMA channel 'FLASH_WR' transfer rate degraded,3
CRITICAL,CACHE_CTRL,"Cache coherence failure detected, system integrity compromised","CACHE_CTRL Cache coherence failure detected, system integrity compromised",1
ERROR,DMA_ENGINE,DMA transfer completion interrupt not asserted after data transfer,DMA_ENGINE DMA transfer completion interrupt not asserted after data transfer,3
WARNING,PCIE_CTRL,PCIe link bandwidth negotiated lower than expected,PCIE_CTRL PCIe link bandwidth negotiated lower than expected,6
INFO,POWER_CTRL,Power domain VDD_DSP enabled.,POWER_CTRL Power domain VDD_DSP enabled.,-1
INFO,PCIE_CTRL,PCIe device BAR configuration completed,PCIE_CTRL PCIe device BAR configuration completed,6
ERROR,INTERRUPT_CTRL,Unmasked interrupt detected during critical section,INTERRUPT_CTRL Unmasked interrupt detected during critical section,1
CRITICAL,DDR_CTRL,DDR memory controller reset assertion failure,DDR_CTRL DDR memory controller reset assertion failure,1
CRITICAL,CACHE_CTRL,Cache data corruption due to write-after-read hazard,CACHE_CTRL Cache data corruption due to write-after-read hazard,1
CRITICAL,POWER_CTRL,System power good signal lost,POWER_CTRL System power good signal lost,4
WARNING,AXI_CTRL,AXI read address channel handshake delay,AXI_CTRL AXI read address channel handshake delay,2
WARNING,FIFO_BUF,FIFO write latency increasing,FIFO_BUF FIFO write latency increasing,5
ERROR,MEM_CTRL,Uncorrectable ECC error in cacheable region,MEM_CTRL Uncorrectable ECC error in cacheable region,1
ERROR,FIFO_BUF,FIFO synchronization error detected on write_clock.,FIFO_BUF FIFO synchronization error detected on write_clock.,5
WARNING,PCIE_CTRL,PCIe upstream flow control credit deficit detected.,PCIE_CTRL PCIe upstream flow control credit deficit detected.,6
INFO,FIFO_BUF,FIFO watermarks configured,FIFO_BUF FIFO watermarks configured,5
WARNING,AXI_CTRL,AXI write channel backpressure released,AXI_CTRL AXI write channel backpressure released,2
INFO,PCIE_CTRL,PCIe link speed negotiation completed,PCIE_CTRL PCIe link speed negotiation completed,6
CRITICAL,MEM_CTRL,Critical configuration register corruption detected,MEM_CTRL Critical configuration register corruption detected,1
INFO,AXI_CTRL,AXI outstanding read limit not exceeded,AXI_CTRL AXI outstanding read limit not exceeded,2
WARNING,INTERRUPT_CTRL,Interrupt pending bits not clearing,INTERRUPT_CTRL Interrupt pending bits not clearing,1
CRITICAL,AXI_CTRL,"AXI arbiter entered invalid state, bus unresponsive","AXI_CTRL AXI arbiter entered invalid state, bus unresponsive",2
INFO,FIFO_BUF,FIFO reset sequence successfully completed,FIFO_BUF FIFO reset sequence successfully completed,5
CRITICAL,POWER_CTRL,Voltage regulator output stuck high,POWER_CTRL Voltage regulator output stuck high,4
WARNING,AXI_CTRL,AXI slave 0 response latency high,AXI_CTRL AXI slave 0 response latency high,2
WARNING,DDR_CTRL,DDR command queue depth exceeding 80%,DDR_CTRL DDR command queue depth exceeding 80%,1
WARNING,AXI_CTRL,AXI read request reordering detected,AXI_CTRL AXI read request reordering detected,2
ERROR,INTERRUPT_CTRL,Interrupt vector table corruption,INTERRUPT_CTRL Interrupt vector table corruption,1
ERROR,INTERRUPT_CTRL,Interrupt prioritization logic fault,INTERRUPT_CTRL Interrupt prioritization logic fault,1
WARNING,CLOCK_MANAGER,Clock frequency deviation detected on secondary clock,CLOCK_MANAGER Clock frequency deviation detected on secondary clock,0
ERROR,DDR_CTRL,DDR calibration parameter out of bounds,DDR_CTRL DDR calibration parameter out of bounds,1
ERROR,DMA_ENGINE,DMA descriptor memory address out of bounds,DMA_ENGINE DMA descriptor memory address out of bounds,3
ERROR,INTERRUPT_CTRL,Interrupt disable mask not applied,INTERRUPT_CTRL Interrupt disable mask not applied,1
INFO,DMA_ENGINE,DMA_ENGINE self-test passed.,DMA_ENGINE DMA_ENGINE self-test passed.,3
INFO,CLOCK_MANAGER,Clock gate for peripheral X enabled,CLOCK_MANAGER Clock gate for peripheral X enabled,0
ERROR,AXI_CTRL,AXI slave responded with decode error,AXI_CTRL AXI slave responded with decode error,2
WARNING,FIFO_BUF,FIFO latency exceeding specification,FIFO_BUF FIFO latency exceeding specification,5
CRITICAL,CLOCK_MANAGER,Main PLL frequency drift detected,CLOCK_MANAGER Main PLL frequency drift detected,0
WARNING,FIFO_BUF,FIFO input write rate exceeding output read rate,FIFO_BUF FIFO input write rate exceeding output read rate,5
WARNING,MEM_CTRL,Memory write latency exceeding threshold,MEM_CTRL Memory write latency exceeding threshold,1
WARNING,INTERRUPT_CTRL,INTERRUPT_CTRL performance counter for INTERRUPT_CTRL indicating suboptimal behavior.,INTERRUPT_CTRL INTERRUPT_CTRL performance counter for INTERRUPT_CTRL indicating suboptimal behavior.,-1
INFO,FIFO_BUF,Resetting FIFO pointers to initial state,FIFO_BUF Resetting FIFO pointers to initial state,5
ERROR,FIFO_BUF,FIFO access timing violation,FIFO_BUF FIFO access timing violation,5
ERROR,AXI_CTRL,AXI read address channel unaligned access detected,AXI_CTRL AXI read address channel unaligned access detected,2
WARNING,MEM_CTRL,Memory controller write buffer nearing saturation point,MEM_CTRL Memory controller write buffer nearing saturation point,1
WARNING,POWER_CTRL,Power rail voltage instability detected,POWER_CTRL Power rail voltage instability detected,4
WARNING,INTERRUPT_CTRL,"Warning: SPURIOUS_INTERRUPT detected, source unknown.","INTERRUPT_CTRL Warning: SPURIOUS_INTERRUPT detected, source unknown.",1
ERROR,MEM_CTRL,Memory controller state machine deadlock detected,MEM_CTRL Memory controller state machine deadlock detected,1
INFO,CLOCK_MANAGER,Clock generator output divided by 4,CLOCK_MANAGER Clock generator output divided by 4,-1
ERROR,POWER_CTRL,POWER_CTRL: state machine fault - FSM stuck in error state detected.,POWER_CTRL POWER_CTRL: state machine fault - FSM stuck in error state detected.,4
WARNING,DMA_ENGINE,DMA transfer completion interrupt pending too long,DMA_ENGINE DMA transfer completion interrupt pending too long,3
CRITICAL,MEM_CTRL,Unrecoverable multi-bit ECC error in main memory,MEM_CTRL Unrecoverable multi-bit ECC error in main memory,1
INFO,CACHE_CTRL,Cache line replacement policy configured to LRU,CACHE_CTRL Cache line replacement policy configured to LRU,1
WARNING,PCIE_CTRL,PCIe AER reporting multiple recoverable errors,PCIE_CTRL PCIe AER reporting multiple recoverable errors,6
WARNING,DDR_CTRL,DDR write data not matching expected pattern,DDR_CTRL DDR write data not matching expected pattern,1
WARNING,CLOCK_MANAGER,Clock tree synthesis report indicates high skew,CLOCK_MANAGER Clock tree synthesis report indicates high skew,0
ERROR,CLOCK_MANAGER,Clock input source instability detected,CLOCK_MANAGER Clock input source instability detected,0
CRITICAL,CLOCK_MANAGER,Clock domain crossing failure leading to data corruption and system hang,CLOCK_MANAGER Clock domain crossing failure leading to data corruption and system hang,0
ERROR,AXI_CTRL,AXI transaction timeout detected for master ID 0x33B61D17,AXI_CTRL AXI transaction timeout detected for master ID 0x33B61D17,2
INFO,CACHE_CTRL,Cache coherence state updated for address 0xDEADBEEF,CACHE_CTRL Cache coherence state updated for address 0xDEADBEEF,1
INFO,PCIE_CTRL,PCIe link status good,PCIE_CTRL PCIe link status good,6
INFO,INTERRUPT_CTRL,Interrupt vector table loaded successfully,INTERRUPT_CTRL Interrupt vector table loaded successfully,1
ERROR,DMA_ENGINE,DMA descriptor fetch failed from system memory.,DMA_ENGINE DMA descriptor fetch failed from system memory.,3
ERROR,INTERRUPT_CTRL,Interrupt controller hardware deadlock,INTERRUPT_CTRL Interrupt controller hardware deadlock,1
INFO,AXI_CTRL,AXI write channel arbitration granted.,AXI_CTRL AXI write channel arbitration granted.,2
CRITICAL,CLOCK_MANAGER,Clock source switching resulted in critical glitch,CLOCK_MANAGER Clock source switching resulted in critical glitch,0
ERROR,FIFO_BUF,FIFO read pointer advanced without valid data,FIFO_BUF FIFO read pointer advanced without valid data,5
WARNING,FIFO_BUF,"Output FIFO almost empty, impending underflow","FIFO_BUF Output FIFO almost empty, impending underflow",5
ERROR,DMA_ENGINE,DMA descriptor memory access fault.,DMA_ENGINE DMA descriptor memory access fault.,3
ERROR,FIFO_BUF,FIFO almost full threshold logic error,FIFO_BUF FIFO almost full threshold logic error,5
WARNING,DDR_CTRL,DRAM temperature sensor reading high,DDR_CTRL DRAM temperature sensor reading high,1
CRITICAL,CLOCK_MANAGER,System clock source switch fault,CLOCK_MANAGER System clock source switch fault,0
CRITICAL,MEM_CTRL,Memory controller state machine entered invalid state (REFRESH -> UNKNOWN).,MEM_CTRL Memory controller state machine entered invalid state (REFRESH -> UNKNOWN).,1
ERROR,INTERRUPT_CTRL,Interrupt controller configuration error.,INTERRUPT_CTRL Interrupt controller configuration error.,1
INFO,FIFO_BUF,FIFO 'debug_trace' 75% full,FIFO_BUF FIFO 'debug_trace' 75% full,5
ERROR,AXI_CTRL,AXI write address channel (AW) protocol violation,AXI_CTRL AXI write address channel (AW) protocol violation,2
ERROR,POWER_CTRL,Over-voltage condition detected on peripheral rail,POWER_CTRL Over-voltage condition detected on peripheral rail,4
WARNING,FIFO_BUF,"FIFO_OUTPUT_QUEUE fill level is below 10%, nearing underflow.","FIFO_BUF FIFO_OUTPUT_QUEUE fill level is below 10%, nearing underflow.",-1
WARNING,DDR_CTRL,DDR controller read latency variation exceeding limits,DDR_CTRL DDR controller read latency variation exceeding limits,1
ERROR,INTERRUPT_CTRL,Interrupt priority conflict leading to starvation,INTERRUPT_CTRL Interrupt priority conflict leading to starvation,1
ERROR,MEM_CTRL,Memory address decoding error detected,MEM_CTRL Memory address decoding error detected,1
WARNING,AXI_CTRL,Slave response latency elevated,AXI_CTRL Slave response latency elevated,2
ERROR,DDR_CTRL,DDR command queue arbitration failure,DDR_CTRL DDR command queue arbitration failure,1
WARNING,DDR_CTRL,DDR memory module temperature exceeding threshold,DDR_CTRL DDR memory module temperature exceeding threshold,1
INFO,DDR_CTRL,DDR read latency statistics captured,DDR_CTRL DDR read latency statistics captured,1
ERROR,DDR_CTRL,DDR command timing violation: tRP exceeded,DDR_CTRL DDR command timing violation: tRP exceeded,1
WARNING,AXI_CTRL,AXI slave response delay exceeding expected,AXI_CTRL AXI slave response delay exceeding expected,2
INFO,FIFO_BUF,FIFO data written at 0x10 bytes,FIFO_BUF FIFO data written at 0x10 bytes,5
WARNING,DMA_ENGINE,DMA engine internal resource arbitration taking too long.,DMA_ENGINE DMA engine internal resource arbitration taking too long.,3
WARNING,INTERRUPT_CTRL,"Spurious interrupt detected, cleared","INTERRUPT_CTRL Spurious interrupt detected, cleared",1
WARNING,AXI_CTRL,AXI write response channel (B) experiencing backpressure,AXI_CTRL AXI write response channel (B) experiencing backpressure,2
INFO,INTERRUPT_CTRL,Interrupt handler registered for device ID 0x1234,INTERRUPT_CTRL Interrupt handler registered for device ID 0x1234,1
ERROR,POWER_CTRL,Power management unit state machine entered invalid state.,POWER_CTRL Power management unit state machine entered invalid state.,4
CRITICAL,INTERRUPT_CTRL,"Interrupt storm detected, system overwhelmed","INTERRUPT_CTRL Interrupt storm detected, system overwhelmed",1
INFO,DMA_ENGINE,DMA channel 7 configuration loaded,DMA_ENGINE DMA channel 7 configuration loaded,3
WARNING,AXI_CTRL,AXI transaction queue depth increasing,AXI_CTRL AXI transaction queue depth increasing,2
ERROR,PCIE_CTRL,PCIe TLB entry invalidation failure,PCIE_CTRL PCIe TLB entry invalidation failure,6
CRITICAL,CLOCK_MANAGER,"Critical clock rail voltage drop, potential reset required","CLOCK_MANAGER Critical clock rail voltage drop, potential reset required",-1
WARNING,DDR_CTRL,DDR read data capture window narrowing,DDR_CTRL DDR read data capture window narrowing,1
ERROR,FIFO_BUF,FIFO almost-full/almost-empty logic misdetection.,FIFO_BUF FIFO almost-full/almost-empty logic misdetection.,5
ERROR,DDR_CTRL,DDR memory module row hammer attack detected,DDR_CTRL DDR memory module row hammer attack detected,-1
INFO,MEM_CTRL,Memory access to region 0x40000000 completed,MEM_CTRL Memory access to region 0x40000000 completed,1
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold (12.3%).,CACHE_CTRL Cache miss rate exceeding expected threshold (12.3%).,1
WARNING,AXI_CTRL,AXI bus outstanding transaction count nearing limit for slave Y,AXI_CTRL AXI bus outstanding transaction count nearing limit for slave Y,2
ERROR,CLOCK_MANAGER,Clock jitter exceeding tolerance on CPU clock,CLOCK_MANAGER Clock jitter exceeding tolerance on CPU clock,0
CRITICAL,MEM_CTRL,Memory controller FSM entered unexpected idle state,MEM_CTRL Memory controller FSM entered unexpected idle state,1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout on pending request,INTERRUPT_CTRL Interrupt acknowledge timeout on pending request,1
ERROR,FIFO_BUF,FIFO data entry corrupted during shift operation,FIFO_BUF FIFO data entry corrupted during shift operation,5
WARNING,CLOCK_MANAGER,Clock frequency deviation exceeding permissible range,CLOCK_MANAGER Clock frequency deviation exceeding permissible range,0
INFO,MEM_CTRL,Memory prefetch buffer cleared,MEM_CTRL Memory prefetch buffer cleared,1
ERROR,INTERRUPT_CTRL,Interrupt vector table corruption detected,INTERRUPT_CTRL Interrupt vector table corruption detected,1
CRITICAL,MEM_CTRL,Memory controller issued an invalid command sequence,MEM_CTRL Memory controller issued an invalid command sequence,1
CRITICAL,DDR_CTRL,"DDR memory controller initialization failed, unrecoverable","DDR_CTRL DDR memory controller initialization failed, unrecoverable",1
CRITICAL,CACHE_CTRL,"Cache coherence fatal error, unrecoverable data integrity issue","CACHE_CTRL Cache coherence fatal error, unrecoverable data integrity issue",1
CRITICAL,POWER_CTRL,Failsafe power-down sequence initiated due to critical rail failure,POWER_CTRL Failsafe power-down sequence initiated due to critical rail failure,4
WARNING,MEM_CTRL,ECC scrub operation detected correctable errors in memory block.,MEM_CTRL ECC scrub operation detected correctable errors in memory block.,1
WARNING,PCIE_CTRL,PCIe transaction latency variance exceeding threshold,PCIE_CTRL PCIe transaction latency variance exceeding threshold,6
WARNING,DDR_CTRL,DDR read data capture window jitter detected,DDR_CTRL DDR read data capture window jitter detected,1
CRITICAL,MEM_CTRL,Memory protection violation for privileged access,MEM_CTRL Memory protection violation for privileged access,1
WARNING,POWER_CTRL,Power domain 'PERIPH' current draw spiking,POWER_CTRL Power domain 'PERIPH' current draw spiking,-1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal not asserted,INTERRUPT_CTRL Interrupt acknowledge signal not asserted,1
INFO,PCIE_CTRL,PCIe power management transition to D0 successful,PCIE_CTRL PCIe power management transition to D0 successful,6
ERROR,CACHE_CTRL,Cache fill buffer overflow during heavy write-back traffic.,CACHE_CTRL Cache fill buffer overflow during heavy write-back traffic.,1
INFO,POWER_CTRL,Power domain 'PERIPH_VDD' transitioning to off state,POWER_CTRL Power domain 'PERIPH_VDD' transitioning to off state,4
WARNING,POWER_CTRL,Current drawn by module X is higher than expected,POWER_CTRL Current drawn by module X is higher than expected,-1
INFO,POWER_CTRL,Low-power state entry for domain B successful,POWER_CTRL Low-power state entry for domain B successful,4
INFO,CLOCK_MANAGER,PLL lock detected on primary clock,CLOCK_MANAGER PLL lock detected on primary clock,0
WARNING,FIFO_BUF,FIFO latency exceeding software threshold,FIFO_BUF FIFO latency exceeding software threshold,5
INFO,CACHE_CTRL,Cache line invalidated at 0x100,CACHE_CTRL Cache line invalidated at 0x100,1
INFO,MEM_CTRL,Memory region marked as non-cacheable,MEM_CTRL Memory region marked as non-cacheable,1
WARNING,POWER_CTRL,Voltage regulator response time exceeding limits,POWER_CTRL Voltage regulator response time exceeding limits,4
ERROR,FIFO_BUF,"FIFO write pointer corruption detected, data out of order.","FIFO_BUF FIFO write pointer corruption detected, data out of order.",5
ERROR,DMA_ENGINE,DMA_ENGINE: protocol mismatch - unexpected transaction type detected.,DMA_ENGINE DMA_ENGINE: protocol mismatch - unexpected transaction type detected.,3
WARNING,DMA_ENGINE,DMA completion status register read discrepancy,DMA_ENGINE DMA completion status register read discrepancy,3
WARNING,AXI_CTRL,AXI interconnect deadlock detection threshold reached,AXI_CTRL AXI interconnect deadlock detection threshold reached,2
INFO,DMA_ENGINE,"DMA engine idle, all channels complete","DMA_ENGINE DMA engine idle, all channels complete",3
WARNING,DMA_ENGINE,DMA channel arbitration priority conflict,DMA_ENGINE DMA channel arbitration priority conflict,3
CRITICAL,CACHE_CTRL,Cache coherence protocol deadlock detected,CACHE_CTRL Cache coherence protocol deadlock detected,1
WARNING,POWER_CTRL,Power domain transition delay exceeding specified maximum.,POWER_CTRL Power domain transition delay exceeding specified maximum.,4
INFO,CLOCK_MANAGER,System clock frequency scaled to 800MHz,CLOCK_MANAGER System clock frequency scaled to 800MHz,0
WARNING,AXI_CTRL,AXI outstanding transactions exceeding threshold (75/100),AXI_CTRL AXI outstanding transactions exceeding threshold (75/100),2
CRITICAL,MEM_CTRL,Multi-bit ECC error on system critical data structure,MEM_CTRL Multi-bit ECC error on system critical data structure,1
INFO,CLOCK_MANAGER,Secondary clock domain synchronized,CLOCK_MANAGER Secondary clock domain synchronized,0
WARNING,MEM_CTRL,Single-bit ECC correction applied to address 0xDEADBEEF.,MEM_CTRL Single-bit ECC correction applied to address 0xDEADBEEF.,1
CRITICAL,DDR_CTRL,DDR memory initialization sequence failed,DDR_CTRL DDR memory initialization sequence failed,1
ERROR,POWER_CTRL,Power rail voltage droop beyond acceptable limits,POWER_CTRL Power rail voltage droop beyond acceptable limits,4
WARNING,INTERRUPT_CTRL,Interrupt vector table corrupted in non-critical entry,INTERRUPT_CTRL Interrupt vector table corrupted in non-critical entry,1
ERROR,FIFO_BUF,FIFO read access to empty buffer,FIFO_BUF FIFO read access to empty buffer,5
CRITICAL,FIFO_BUF,FIFO write channel stuck in handshake,FIFO_BUF FIFO write channel stuck in handshake,-1
ERROR,INTERRUPT_CTRL,Interrupt priority encoder mismatch with configuration,INTERRUPT_CTRL Interrupt priority encoder mismatch with configuration,1
INFO,AXI_CTRL,AXI burst read transaction initiated,AXI_CTRL AXI burst read transaction initiated,2
INFO,DDR_CTRL,Memory read data valid,DDR_CTRL Memory read data valid,1
INFO,PCIE_CTRL,PCIe device reset de-asserted,PCIE_CTRL PCIe device reset de-asserted,6
CRITICAL,CLOCK_MANAGER,Primary system clock source lost lock,CLOCK_MANAGER Primary system clock source lost lock,0
INFO,PCIE_CTRL,PCIe device capabilities enumerated,PCIE_CTRL PCIe device capabilities enumerated,6
WARNING,CLOCK_MANAGER,Clock skew between 'core_clk' and 'periph_clk' increasing,CLOCK_MANAGER Clock skew between 'core_clk' and 'periph_clk' increasing,0
CRITICAL,CLOCK_MANAGER,Clock signal lost on primary domain,CLOCK_MANAGER Clock signal lost on primary domain,0
CRITICAL,MEM_CTRL,"Double bit ECC failure detected in critical memory region (Bank 1, ECC bits: 0x93).","MEM_CTRL Double bit ECC failure detected in critical memory region (Bank 1, ECC bits: 0x93).",1
INFO,MEM_CTRL,Memory BIST (Built-In Self-Test) initiated,MEM_CTRL Memory BIST (Built-In Self-Test) initiated,1
ERROR,DDR_CTRL,DDR command bus voltage levels out of spec,DDR_CTRL DDR command bus voltage levels out of spec,-1
INFO,DMA_ENGINE,DMA descriptor successfully fetched,DMA_ENGINE DMA descriptor successfully fetched,3
ERROR,PCIE_CTRL,PCIe completion timeout on request,PCIE_CTRL PCIe completion timeout on request,6
WARNING,FIFO_BUF,FIFO read pointer approaching write pointer on 'tx_ring',FIFO_BUF FIFO read pointer approaching write pointer on 'tx_ring',5
WARNING,POWER_CTRL,External power supply voltage sag,POWER_CTRL External power supply voltage sag,-1
INFO,INTERRUPT_CTRL,"Interrupt vector mismatch detected, system recalibrating","INTERRUPT_CTRL Interrupt vector mismatch detected, system recalibrating",1
ERROR,CACHE_CTRL,Cache lookup table (LUT) data corruption,CACHE_CTRL Cache lookup table (LUT) data corruption,-1
INFO,FIFO_BUF,"Write operation successful, FIFO not full","FIFO_BUF Write operation successful, FIFO not full",5
ERROR,AXI_CTRL,AXI read burst alignment violation detected,AXI_CTRL AXI read burst alignment violation detected,2
INFO,DDR_CTRL,DDR controller configured for frequency.,DDR_CTRL DDR controller configured for frequency.,1
WARNING,AXI_CTRL,AXI master 2 outstanding transactions at limit,AXI_CTRL AXI master 2 outstanding transactions at limit,2
ERROR,PCIE_CTRL,PCIe link training failure detected (phase 2).,PCIE_CTRL PCIe link training failure detected (phase 2).,6
CRITICAL,POWER_CTRL,Brownout condition detected on system rail,POWER_CTRL Brownout condition detected on system rail,4
WARNING,FIFO_BUF,FIFO nearing capacity.,FIFO_BUF FIFO nearing capacity.,5
WARNING,AXI_CTRL,AXI write data channel bandwidth saturation,AXI_CTRL AXI write data channel bandwidth saturation,2
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on control path,CLOCK_MANAGER Clock domain crossing synchronization failure on control path,0
INFO,CACHE_CTRL,Diagnostic routine passed for CACHE_CTRL.,CACHE_CTRL Diagnostic routine passed for CACHE_CTRL.,1
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding soft threshold,INTERRUPT_CTRL Interrupt latency exceeding soft threshold,1
INFO,MEM_CTRL,Memory region write-protected,MEM_CTRL Memory region write-protected,1
CRITICAL,POWER_CTRL,System power-on sequence aborted,POWER_CTRL System power-on sequence aborted,4
CRITICAL,MEM_CTRL,Fatal memory state machine error: entered undefined state.,MEM_CTRL Fatal memory state machine error: entered undefined state.,1
INFO,INTERRUPT_CTRL,Interrupt latency measured: 120ns,INTERRUPT_CTRL Interrupt latency measured: 120ns,1
ERROR,INTERRUPT_CTRL,Interrupt controller internal register corruption.,INTERRUPT_CTRL Interrupt controller internal register corruption.,1
WARNING,PCIE_CTRL,PCIe link partner reporting error messages,PCIE_CTRL PCIe link partner reporting error messages,6
WARNING,MEM_CTRL,Memory controller command queue depth 1000 of max 256.,MEM_CTRL Memory controller command queue depth 1000 of max 256.,1
INFO,DDR_CTRL,DDR precharge command issued successfully,DDR_CTRL DDR precharge command issued successfully,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller detected a spurious interrupt storm.,INTERRUPT_CTRL Interrupt controller detected a spurious interrupt storm.,1
ERROR,INTERRUPT_CTRL,Spurious interrupt vector detected,INTERRUPT_CTRL Spurious interrupt vector detected,1
ERROR,INTERRUPT_CTRL,Interrupt controller arbitration logic deadlock,INTERRUPT_CTRL Interrupt controller arbitration logic deadlock,1
ERROR,INTERRUPT_CTRL,Interrupt controller internal FIFO overflow,INTERRUPT_CTRL Interrupt controller internal FIFO overflow,1
ERROR,DMA_ENGINE,DMA channel configuration register corrupted,DMA_ENGINE DMA channel configuration register corrupted,3
ERROR,POWER_CTRL,Voltage regulator response timeout detected,POWER_CTRL Voltage regulator response timeout detected,4
ERROR,POWER_CTRL,Brown-out detection circuit triggered,POWER_CTRL Brown-out detection circuit triggered,4
CRITICAL,AXI_CTRL,AXI read transaction completed with wrong slave ID,AXI_CTRL AXI read transaction completed with wrong slave ID,2
WARNING,DMA_ENGINE,DMA target address out of bounds,DMA_ENGINE DMA target address out of bounds,3
WARNING,DDR_CTRL,DDR MRS update pending due to busy status,DDR_CTRL DDR MRS update pending due to busy status,-1
ERROR,CACHE_CTRL,Cache miss rate alarm threshold exceeded,CACHE_CTRL Cache miss rate alarm threshold exceeded,1
WARNING,PCIE_CTRL,PCIe link retraining initiated due to correctable errors,PCIE_CTRL PCIe link retraining initiated due to correctable errors,6
ERROR,POWER_CTRL,Voltage monitor internal self-test failed,POWER_CTRL Voltage monitor internal self-test failed,4
ERROR,FIFO_BUF,"Input FIFO depth exceeded, data dropped","FIFO_BUF Input FIFO depth exceeded, data dropped",5
WARNING,MEM_CTRL,Memory refresh interval approaching limit.,MEM_CTRL Memory refresh interval approaching limit.,1
INFO,DDR_CTRL,DDR command queue cleared,DDR_CTRL DDR command queue cleared,1
WARNING,INTERRUPT_CTRL,Interrupt queue fill level at critical threshold,INTERRUPT_CTRL Interrupt queue fill level at critical threshold,1
ERROR,FIFO_BUF,"FIFO write operation stalled indefinitely, potential deadlock","FIFO_BUF FIFO write operation stalled indefinitely, potential deadlock",5
ERROR,AXI_CTRL,"AXI bus contention detected, address phase stall","AXI_CTRL AXI bus contention detected, address phase stall",2
CRITICAL,DDR_CTRL,"DDR training sequence failed, unrecoverable memory access issue","DDR_CTRL DDR training sequence failed, unrecoverable memory access issue",1
INFO,INTERRUPT_CTRL,Interrupt controller debug register access,INTERRUPT_CTRL Interrupt controller debug register access,1
INFO,CACHE_CTRL,L1 data cache writeback completed for all dirty lines,CACHE_CTRL L1 data cache writeback completed for all dirty lines,1
INFO,CACHE_CTRL,Cache invalidate operation in progress,CACHE_CTRL Cache invalidate operation in progress,1
INFO,INTERRUPT_CTRL,Interrupt vector table initialized,INTERRUPT_CTRL Interrupt vector table initialized,1
INFO,AXI_CTRL,AXI master granted access,AXI_CTRL AXI master granted access,2
INFO,DMA_ENGINE,DMA engine self-test passed,DMA_ENGINE DMA engine self-test passed,3
WARNING,DMA_ENGINE,DMA transaction latency elevated,DMA_ENGINE DMA transaction latency elevated,3
INFO,MEM_CTRL,Memory initialization pattern verification successful,MEM_CTRL Memory initialization pattern verification successful,1
CRITICAL,POWER_CTRL,"Power rail voltage critical drop, automatic shutdown initiated","POWER_CTRL Power rail voltage critical drop, automatic shutdown initiated",4
WARNING,CACHE_CTRL,Cache directory lookup latency exceeding threshold,CACHE_CTRL Cache directory lookup latency exceeding threshold,1
INFO,POWER_CTRL,Power state transition completed to D3.,POWER_CTRL Power state transition completed to D3.,4
INFO,CACHE_CTRL,Cache prefetcher statistics reset.,CACHE_CTRL Cache prefetcher statistics reset.,1
INFO,INTERRUPT_CTRL,Interrupt vector 12 mapped to handler address 0xABCD0000,INTERRUPT_CTRL Interrupt vector 12 mapped to handler address 0xABCD0000,1
INFO,POWER_CTRL,Device entered idle power state,POWER_CTRL Device entered idle power state,4
CRITICAL,DDR_CTRL,DDR memory initialization sequence failure,DDR_CTRL DDR memory initialization sequence failure,1
WARNING,MEM_CTRL,Memory bank 2 refresh cycle overdue,MEM_CTRL Memory bank 2 refresh cycle overdue,1
CRITICAL,POWER_CTRL,Power supply voltage outside acceptable limits,POWER_CTRL Power supply voltage outside acceptable limits,4
WARNING,CACHE_CTRL,Cache line replacement algorithm performing poorly,CACHE_CTRL Cache line replacement algorithm performing poorly,1
INFO,FIFO_BUF,FIFO buffer cleared and reinitialized.,FIFO_BUF FIFO buffer cleared and reinitialized.,5
INFO,DDR_CTRL,DDR PHY calibration routine completed,DDR_CTRL DDR PHY calibration routine completed,1
INFO,POWER_CTRL,System entered deep sleep state,POWER_CTRL System entered deep sleep state,4
WARNING,AXI_CTRL,AXI read data channel busy for too long,AXI_CTRL AXI read data channel busy for too long,2
WARNING,DMA_ENGINE,DMA transfer pending on external acknowledgement,DMA_ENGINE DMA transfer pending on external acknowledgement,3
INFO,MEM_CTRL,Memory read from 0x5000_0000 completed,MEM_CTRL Memory read from 0x5000_0000 completed,1
INFO,FIFO_BUF,FIFO 'status_updates' successfully written 5 entries,FIFO_BUF FIFO 'status_updates' successfully written 5 entries,-1
ERROR,PCIE_CTRL,"PCIe CRC error on received TLP, link layer retry initiated","PCIE_CTRL PCIe CRC error on received TLP, link layer retry initiated",6
CRITICAL,POWER_CTRL,Main power supply output voltage failure,POWER_CTRL Main power supply output voltage failure,-1
CRITICAL,FIFO_BUF,FIFO control logic stuck in reset state,FIFO_BUF FIFO control logic stuck in reset state,5
WARNING,POWER_CTRL,Power domain transition delay detected for domain CPU,POWER_CTRL Power domain transition delay detected for domain CPU,4
WARNING,MEM_CTRL,Memory access latency spike,MEM_CTRL Memory access latency spike,1
CRITICAL,MEM_CTRL,"Fatal memory access violation, system halt required","MEM_CTRL Fatal memory access violation, system halt required",1
CRITICAL,POWER_CTRL,Power rail collapse detected on VDD_CORE (0.0V),POWER_CTRL Power rail collapse detected on VDD_CORE (0.0V),4
INFO,PCIE_CTRL,PCIe link established successfully at Gen3 x16,PCIE_CTRL PCIe link established successfully at Gen3 x16,6
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL monitoring initiated.,INTERRUPT_CTRL INTERRUPT_CTRL monitoring initiated.,1
ERROR,FIFO_BUF,FIFO reset de-assertion caused unexpected pointer values,FIFO_BUF FIFO reset de-assertion caused unexpected pointer values,5
ERROR,AXI_CTRL,AXI bus contention detected between master 'M0' and 'M1',AXI_CTRL AXI bus contention detected between master 'M0' and 'M1',2
ERROR,DDR_CTRL,"DDR write data mask error, timing violation.","DDR_CTRL DDR write data mask error, timing violation.",1
CRITICAL,FIFO_BUF,FIFO reset failed to clear all internal state,FIFO_BUF FIFO reset failed to clear all internal state,5
CRITICAL,MEM_CTRL,"Double bit ECC corruption detected, unrecoverable","MEM_CTRL Double bit ECC corruption detected, unrecoverable",1
INFO,CACHE_CTRL,Cache line allocated for address 0xDEADBEEF,CACHE_CTRL Cache line allocated for address 0xDEADBEEF,1
CRITICAL,DDR_CTRL,DDR memory module not detected during enumeration,DDR_CTRL DDR memory module not detected during enumeration,1
ERROR,DMA_ENGINE,"DMA transaction timeout for channel 0, stuck transfer","DMA_ENGINE DMA transaction timeout for channel 0, stuck transfer",3
WARNING,DDR_CTRL,DDR command queue depth increasing rapidly,DDR_CTRL DDR command queue depth increasing rapidly,1
INFO,AXI_CTRL,AXI burst write completed successfully,AXI_CTRL AXI burst write completed successfully,2
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure between DDR_DOMAIN and PERIPH_DOMAIN.,CLOCK_MANAGER Clock domain crossing synchronization failure between DDR_DOMAIN and PERIPH_DOMAIN.,0
ERROR,DMA_ENGINE,DMA channel 1 burst alignment violation,DMA_ENGINE DMA channel 1 burst alignment violation,3
INFO,FIFO_BUF,FIFO data peeked successfully,FIFO_BUF FIFO data peeked successfully,5
WARNING,AXI_CTRL,AXI response delay observed for master 10,AXI_CTRL AXI response delay observed for master 10,2
INFO,AXI_CTRL,AXI master CPU initiated burst read.,AXI_CTRL AXI master CPU initiated burst read.,2
INFO,CACHE_CTRL,Cache prefetch operation successful,CACHE_CTRL Cache prefetch operation successful,1
INFO,AXI_CTRL,AXI burst length maximum achieved,AXI_CTRL AXI burst length maximum achieved,2
INFO,DMA_ENGINE,"DMA engine enabled, awaiting requests.","DMA_ENGINE DMA engine enabled, awaiting requests.",3
CRITICAL,MEM_CTRL,Data bus ECC uncorrectable error detected,MEM_CTRL Data bus ECC uncorrectable error detected,1
WARNING,INTERRUPT_CTRL,"Interrupt rate high, potential interrupt storm detected","INTERRUPT_CTRL Interrupt rate high, potential interrupt storm detected",1
INFO,AXI_CTRL,AXI read transaction 0x1A initiated.,AXI_CTRL AXI read transaction 0x1A initiated.,2
WARNING,FIFO_BUF,FIFO almost empty condition reported,FIFO_BUF FIFO almost empty condition reported,5
INFO,AXI_CTRL,AXI stream data flow enabled,AXI_CTRL AXI stream data flow enabled,2
WARNING,DDR_CTRL,DDR read data burst incomplete,DDR_CTRL DDR read data burst incomplete,1
INFO,PCIE_CTRL,PCIe Gen5 link established at 32 GT/s,PCIE_CTRL PCIe Gen5 link established at 32 GT/s,6
ERROR,POWER_CTRL,Voltage sensor reports undervoltage on periphery rail,POWER_CTRL Voltage sensor reports undervoltage on periphery rail,-1
CRITICAL,POWER_CTRL,Power-on sequence failed to bring up all rails,POWER_CTRL Power-on sequence failed to bring up all rails,4
WARNING,DMA_ENGINE,DMA completion queue nearing saturation,DMA_ENGINE DMA completion queue nearing saturation,3
ERROR,AXI_CTRL,"AXI_CTRL: transaction timeout - outstanding request expired detected. (Master ID: 0, AXI ID: 12)","AXI_CTRL AXI_CTRL: transaction timeout - outstanding request expired detected. (Master ID: 0, AXI ID: 12)",2
INFO,DMA_ENGINE,Configuration parameters loaded for DMA_ENGINE.,DMA_ENGINE Configuration parameters loaded for DMA_ENGINE.,3
WARNING,FIFO_BUF,FIFO synchronization error detected on write path,FIFO_BUF FIFO synchronization error detected on write path,5
INFO,CACHE_CTRL,"Cache initialized successfully (64KB, 8-way).","CACHE_CTRL Cache initialized successfully (64KB, 8-way).",1
WARNING,INTERRUPT_CTRL,Interrupt request queue reaching high watermark,INTERRUPT_CTRL Interrupt request queue reaching high watermark,-1
ERROR,CACHE_CTRL,Cache data parity error detected on read from bank 0,CACHE_CTRL Cache data parity error detected on read from bank 0,1
INFO,INTERRUPT_CTRL,IRQ 12 masked,INTERRUPT_CTRL IRQ 12 masked,1
WARNING,INTERRUPT_CTRL,Interrupt priority level change requested by low priority task,INTERRUPT_CTRL Interrupt priority level change requested by low priority task,1
WARNING,INTERRUPT_CTRL,Unhandled interrupt pending in queue for module AXI_CTRL,INTERRUPT_CTRL Unhandled interrupt pending in queue for module AXI_CTRL,1
CRITICAL,POWER_CTRL,Power-on reset de-assertion failure,POWER_CTRL Power-on reset de-assertion failure,4
CRITICAL,MEM_CTRL,"CRITICAL: Double bit ECC corruption detected at address 0x12345678, uncorrectable.","MEM_CTRL CRITICAL: Double bit ECC corruption detected at address 0x12345678, uncorrectable.",1
ERROR,POWER_CTRL,Power sequencing controller stuck in 'power-on-reset' state,POWER_CTRL Power sequencing controller stuck in 'power-on-reset' state,4
ERROR,INTERRUPT_CTRL,Interrupt acknowledgment signal not de-asserting,INTERRUPT_CTRL Interrupt acknowledgment signal not de-asserting,1
ERROR,DDR_CTRL,DDR power-down entry sequence failed,DDR_CTRL DDR power-down entry sequence failed,1
INFO,PCIE_CTRL,Register write to PCIE_CTRL successful (Addr: 0x93).,PCIE_CTRL Register write to PCIE_CTRL successful (Addr: 0x93).,6
CRITICAL,CLOCK_MANAGER,Primary clock source frequency deviation detected,CLOCK_MANAGER Primary clock source frequency deviation detected,0
INFO,POWER_CTRL,Power rail 'VCC_DDR' voltage stable,POWER_CTRL Power rail 'VCC_DDR' voltage stable,4
WARNING,INTERRUPT_CTRL,Pending interrupt count high,INTERRUPT_CTRL Pending interrupt count high,1
INFO,CACHE_CTRL,Cache line prefetcher active,CACHE_CTRL Cache line prefetcher active,1
ERROR,CLOCK_MANAGER,PLL lock lost for clock domain 'CORE'.,CLOCK_MANAGER PLL lock lost for clock domain 'CORE'.,0
ERROR,DDR_CTRL,DDR controller unable to achieve critical timing parameters,DDR_CTRL DDR controller unable to achieve critical timing parameters,1
INFO,CACHE_CTRL,Cache hit rate optimal at 95%,CACHE_CTRL Cache hit rate optimal at 95%,1
CRITICAL,MEM_CTRL,Multi-bit ECC corruption in page table,MEM_CTRL Multi-bit ECC corruption in page table,1
INFO,AXI_CTRL,AXI master arbitration priority updated,AXI_CTRL AXI master arbitration priority updated,2
CRITICAL,PCIE_CTRL,PCIe endpoint BAR configuration space access error,PCIE_CTRL PCIe endpoint BAR configuration space access error,6
WARNING,AXI_CTRL,AXI response channel stall detected,AXI_CTRL AXI response channel stall detected,2
WARNING,DMA_ENGINE,DMA channel unable to gain bus mastership,DMA_ENGINE DMA channel unable to gain bus mastership,3
WARNING,FIFO_BUF,FIFO output data rate fluctuating beyond acceptable range,FIFO_BUF FIFO output data rate fluctuating beyond acceptable range,5
CRITICAL,FIFO_BUF,FIFO reset not clearing all internal pointers,FIFO_BUF FIFO reset not clearing all internal pointers,5
INFO,INTERRUPT_CTRL,Interrupt controller enabled for all sources,INTERRUPT_CTRL Interrupt controller enabled for all sources,1
WARNING,AXI_CTRL,AXI write response channel exhibiting out-of-order behavior,AXI_CTRL AXI write response channel exhibiting out-of-order behavior,2
INFO,FIFO_BUF,FIFO empty status asserted,FIFO_BUF FIFO empty status asserted,5
INFO,AXI_CTRL,AXI master issued write transaction,AXI_CTRL AXI master issued write transaction,2
CRITICAL,AXI_CTRL,AXI bus arbiter stuck in round-robin state,AXI_CTRL AXI bus arbiter stuck in round-robin state,2
ERROR,AXI_CTRL,"AXI read burst alignment violation, transaction aborted","AXI_CTRL AXI read burst alignment violation, transaction aborted",2
WARNING,DDR_CTRL,DDR memory initialization parameters invalid,DDR_CTRL DDR memory initialization parameters invalid,1
INFO,CACHE_CTRL,Cache coherence state for line 0x100000 is shared,CACHE_CTRL Cache coherence state for line 0x100000 is shared,1
ERROR,INTERRUPT_CTRL,Interrupt pending register stuck with old event,INTERRUPT_CTRL Interrupt pending register stuck with old event,1
CRITICAL,PCIE_CTRL,PCIe lane re-initialization failed to restore full link width,PCIE_CTRL PCIe lane re-initialization failed to restore full link width,6
WARNING,POWER_CTRL,Power domain transition delay detected.,POWER_CTRL Power domain transition delay detected.,4
ERROR,CACHE_CTRL,Cache line fill operation aborted due to timeout,CACHE_CTRL Cache line fill operation aborted due to timeout,1
ERROR,POWER_CTRL,Power-on reset sequence interrupted prematurely,POWER_CTRL Power-on reset sequence interrupted prematurely,4
INFO,DMA_ENGINE,DMA internal status registers cleared,DMA_ENGINE DMA internal status registers cleared,3
CRITICAL,CLOCK_MANAGER,Clock tree catastrophic failure,CLOCK_MANAGER Clock tree catastrophic failure,0
WARNING,CLOCK_MANAGER,Clock gating logic introducing race condition,CLOCK_MANAGER Clock gating logic introducing race condition,0
CRITICAL,DMA_ENGINE,DMA hardware accelerator internal deadlock detected.,DMA_ENGINE DMA hardware accelerator internal deadlock detected.,3
INFO,AXI_CTRL,AXI_CTRL activity detected on interface.,AXI_CTRL AXI_CTRL activity detected on interface.,-1
INFO,DMA_ENGINE,DMA channel 1 burst length configured,DMA_ENGINE DMA channel 1 burst length configured,3
ERROR,AXI_CTRL,"AXI read burst alignment error, crossing 4KB boundary","AXI_CTRL AXI read burst alignment error, crossing 4KB boundary",2
ERROR,AXI_CTRL,AXI burst length violation detected on master ID 3. (protocol mismatch),AXI_CTRL AXI burst length violation detected on master ID 3. (protocol mismatch),2
WARNING,INTERRUPT_CTRL,"Spurious interrupt detected, source unknown","INTERRUPT_CTRL Spurious interrupt detected, source unknown",1
INFO,MEM_CTRL,Memory self-test completed without errors,MEM_CTRL Memory self-test completed without errors,1
ERROR,POWER_CTRL,Power-on reset sequence out of order,POWER_CTRL Power-on reset sequence out of order,4
INFO,FIFO_BUF,FIFO almost-empty flag asserted,FIFO_BUF FIFO almost-empty flag asserted,5
WARNING,AXI_CTRL,AXI outstanding transaction limit approaching,AXI_CTRL AXI outstanding transaction limit approaching,2
INFO,POWER_CTRL,Power state transition completed to D2.,POWER_CTRL Power state transition completed to D2.,4
ERROR,CLOCK_MANAGER,CLOCK_MANAGER: clock domain crossing failure - data corruption across clock boundary detected.,CLOCK_MANAGER CLOCK_MANAGER: clock domain crossing failure - data corruption across clock boundary detected.,0
CRITICAL,AXI_CTRL,AXI global clock domain crossing failure.,AXI_CTRL AXI global clock domain crossing failure.,2
WARNING,INTERRUPT_CTRL,Interrupt 'SW_INT' asserted repeatedly,INTERRUPT_CTRL Interrupt 'SW_INT' asserted repeatedly,-1
ERROR,MEM_CTRL,"Memory controller internal arbitration failure, bus contention.","MEM_CTRL Memory controller internal arbitration failure, bus contention.",1
WARNING,MEM_CTRL,Memory bank busy status detected,MEM_CTRL Memory bank busy status detected,1
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for source 2.,INTERRUPT_CTRL Interrupt dispatch completed for source 2.,1
ERROR,CACHE_CTRL,Cache line address tag mismatch on lookup,CACHE_CTRL Cache line address tag mismatch on lookup,1
WARNING,POWER_CTRL,IO voltage rail VDD_IO showing slight instability,POWER_CTRL IO voltage rail VDD_IO showing slight instability,4
WARNING,INTERRUPT_CTRL,Unhandled interrupt source detected.,INTERRUPT_CTRL Unhandled interrupt source detected.,1
INFO,PCIE_CTRL,PCIe hot-reset completed successfully for device 'NIC',PCIE_CTRL PCIe hot-reset completed successfully for device 'NIC',6
CRITICAL,AXI_CTRL,"Master stuck in WAIT state indefinitely, system hung","AXI_CTRL Master stuck in WAIT state indefinitely, system hung",2
WARNING,POWER_CTRL,"Power domain transition stalled, waiting for handshake","POWER_CTRL Power domain transition stalled, waiting for handshake",4
ERROR,INTERRUPT_CTRL,Unexpected interrupt vector 0x0 received (vector mismatch),INTERRUPT_CTRL Unexpected interrupt vector 0x0 received (vector mismatch),1
WARNING,DMA_ENGINE,DMA transfer completion count mismatch with expected value,DMA_ENGINE DMA transfer completion count mismatch with expected value,3
WARNING,CLOCK_MANAGER,Clock jitter exceeding specified tolerance,CLOCK_MANAGER Clock jitter exceeding specified tolerance,0
ERROR,DMA_ENGINE,Invalid DMA descriptor format,DMA_ENGINE Invalid DMA descriptor format,3
CRITICAL,DDR_CTRL,DDR memory command parser entered undefined state,DDR_CTRL DDR memory command parser entered undefined state,1
INFO,FIFO_BUF,Pointer reset,FIFO_BUF Pointer reset,5
ERROR,CLOCK_MANAGER,Clock input signal jitter exceeding specification,CLOCK_MANAGER Clock input signal jitter exceeding specification,0
WARNING,AXI_CTRL,AXI read burst alignment violation detected (unaligned access),AXI_CTRL AXI read burst alignment violation detected (unaligned access),2
WARNING,DMA_ENGINE,Pending DMA transfers high,DMA_ENGINE Pending DMA transfers high,3
CRITICAL,POWER_CTRL,System PMIC reported critical overvoltage condition,POWER_CTRL System PMIC reported critical overvoltage condition,4
ERROR,INTERRUPT_CTRL,Interrupt controller vector table corruption,INTERRUPT_CTRL Interrupt controller vector table corruption,1
INFO,DMA_ENGINE,DMA channel 2 programmed with a new descriptor,DMA_ENGINE DMA channel 2 programmed with a new descriptor,3
CRITICAL,DMA_ENGINE,Fatal DMA transfer arbitration failure,DMA_ENGINE Fatal DMA transfer arbitration failure,3
WARNING,DDR_CTRL,DDR controller refresh backlog growing,DDR_CTRL DDR controller refresh backlog growing,-1
CRITICAL,AXI_CTRL,CRITICAL: Multiple AXI masters detected asserting conflicting grants.,AXI_CTRL CRITICAL: Multiple AXI masters detected asserting conflicting grants.,-1
ERROR,PCIE_CTRL,PCIe link training failed to achieve L0 state,PCIE_CTRL PCIe link training failed to achieve L0 state,6
CRITICAL,POWER_CTRL,System-wide voltage brownout detected,POWER_CTRL System-wide voltage brownout detected,4
WARNING,POWER_CTRL,Sleep mode entry delayed due to active peripheral,POWER_CTRL Sleep mode entry delayed due to active peripheral,4
INFO,FIFO_BUF,FIFO 'RESULT' emptied,FIFO_BUF FIFO 'RESULT' emptied,5
WARNING,CACHE_CTRL,Cache preload operation failed to complete,CACHE_CTRL Cache preload operation failed to complete,1
INFO,POWER_CTRL,Power rail sequencing completed for display controller,POWER_CTRL Power rail sequencing completed for display controller,-1
ERROR,CLOCK_MANAGER,Clock frequency drift detected from target,CLOCK_MANAGER Clock frequency drift detected from target,0
CRITICAL,CLOCK_MANAGER,Clock generation PLL lost lock permanently,CLOCK_MANAGER Clock generation PLL lost lock permanently,0
CRITICAL,PCIE_CTRL,"PCIe root complex communication lost, system halt","PCIE_CTRL PCIe root complex communication lost, system halt",6
CRITICAL,POWER_CTRL,Power domain transition sequence halted,POWER_CTRL Power domain transition sequence halted,4
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout on pending interrupt,INTERRUPT_CTRL Interrupt acknowledge timeout on pending interrupt,1
INFO,PCIE_CTRL,PCIe link established at Gen4 x8,PCIE_CTRL PCIe link established at Gen4 x8,6
WARNING,PCIE_CTRL,"PCIe L1/L2 entry delay observed, timing violation performance impact.","PCIE_CTRL PCIe L1/L2 entry delay observed, timing violation performance impact.",-1
CRITICAL,DDR_CTRL,DDR memory training sequence diverged unexpectedly,DDR_CTRL DDR memory training sequence diverged unexpectedly,1
CRITICAL,MEM_CTRL,Memory controller entered a fatal deadlock state,MEM_CTRL Memory controller entered a fatal deadlock state,1
WARNING,CACHE_CTRL,CACHE_CTRL resource allocation nearing limit (85% utilized).,CACHE_CTRL CACHE_CTRL resource allocation nearing limit (85% utilized).,1
INFO,FIFO_BUF,"Read operation successful, FIFO now less full.","FIFO_BUF Read operation successful, FIFO now less full.",5
INFO,AXI_CTRL,AXI read response with SLVERR status,AXI_CTRL AXI read response with SLVERR status,2
CRITICAL,DMA_ENGINE,Persistent DMA arbitration conflict causing stalls,DMA_ENGINE Persistent DMA arbitration conflict causing stalls,3
WARNING,MEM_CTRL,"Memory refresh interval approaching limit, scheduling soon for bank 0x3","MEM_CTRL Memory refresh interval approaching limit, scheduling soon for bank 0x3",1
WARNING,DDR_CTRL,DDR self-refresh entry latency above specification,DDR_CTRL DDR self-refresh entry latency above specification,1
WARNING,CACHE_CTRL,"Stale cache line detected, requiring forced invalidate","CACHE_CTRL Stale cache line detected, requiring forced invalidate",1
ERROR,POWER_CTRL,Voltage regulator startup sequence failure,POWER_CTRL Voltage regulator startup sequence failure,4
WARNING,INTERRUPT_CTRL,Interrupt clear-on-read operation missed a pending event.,INTERRUPT_CTRL Interrupt clear-on-read operation missed a pending event.,1
WARNING,INTERRUPT_CTRL,Interrupt enable register inconsistent,INTERRUPT_CTRL Interrupt enable register inconsistent,1
INFO,CLOCK_MANAGER,System reset synchronized across all domains,CLOCK_MANAGER System reset synchronized across all domains,0
ERROR,CACHE_CTRL,Cache coherence protocol mismatch detected between CPU cores,CACHE_CTRL Cache coherence protocol mismatch detected between CPU cores,1
CRITICAL,DMA_ENGINE,DMA_ENGINE: System-level arbitration conflict detected. Unrecoverable hardware state. (arbitration logic malfunction),DMA_ENGINE DMA_ENGINE: System-level arbitration conflict detected. Unrecoverable hardware state. (arbitration logic malfunction),3
ERROR,CLOCK_MANAGER,Clock gating unit for CLOCK_A generated a glitch on output.,CLOCK_MANAGER Clock gating unit for CLOCK_A generated a glitch on output.,0
INFO,CLOCK_MANAGER,Clock frequency configuration applied (4269MHz).,CLOCK_MANAGER Clock frequency configuration applied (4269MHz).,0
WARNING,DMA_ENGINE,DMA channel transfer remaining byte count is inaccurate,DMA_ENGINE DMA channel transfer remaining byte count is inaccurate,3
WARNING,DMA_ENGINE,DMA channel 11 experiencing frequent descriptor re-fetching.,DMA_ENGINE DMA channel 11 experiencing frequent descriptor re-fetching.,3
ERROR,DDR_CTRL,DDR MRS command invalid address,DDR_CTRL DDR MRS command invalid address,-1
INFO,PCIE_CTRL,PCIe configuration space read successful for device 0:1:0,PCIE_CTRL PCIe configuration space read successful for device 0:1:0,6
INFO,PCIE_CTRL,PCIe configuration space read for device ID 0x1234.,PCIE_CTRL PCIe configuration space read for device ID 0x1234.,6
INFO,FIFO_BUF,Read operation from FIFO_BUF_1 completed,FIFO_BUF Read operation from FIFO_BUF_1 completed,5
WARNING,AXI_CTRL,"AXI protocol violation, unexpected response","AXI_CTRL AXI protocol violation, unexpected response",2
WARNING,INTERRUPT_CTRL,Interrupt controller queue approaching maximum capacity,INTERRUPT_CTRL Interrupt controller queue approaching maximum capacity,1
CRITICAL,DMA_ENGINE,"DMA engine deadlock, system halt required","DMA_ENGINE DMA engine deadlock, system halt required",3
ERROR,MEM_CTRL,Memory controller request queue arbitration failure,MEM_CTRL Memory controller request queue arbitration failure,1
INFO,AXI_CTRL,AXI transaction logger enabled,AXI_CTRL AXI transaction logger enabled,-1
WARNING,DMA_ENGINE,DMA channel 1 transfer rate below expected performance,DMA_ENGINE DMA channel 1 transfer rate below expected performance,3
INFO,CACHE_CTRL,Cacheable region marked for bypass,CACHE_CTRL Cacheable region marked for bypass,-1
CRITICAL,PCIE_CTRL,PCIe link retraining failed consecutively.,PCIE_CTRL PCIe link retraining failed consecutively.,6
WARNING,POWER_CTRL,Power domain transition too rapid,POWER_CTRL Power domain transition too rapid,4
WARNING,AXI_CTRL,AXI write burst with non-aligned address detected,AXI_CTRL AXI write burst with non-aligned address detected,2
CRITICAL,POWER_CTRL,Core voltage regulator failure,POWER_CTRL Core voltage regulator failure,4
WARNING,CLOCK_MANAGER,Clock domain crossing synchronizer latency warning,CLOCK_MANAGER Clock domain crossing synchronizer latency warning,0
CRITICAL,AXI_CTRL,AXI interconnect data integrity failure,AXI_CTRL AXI interconnect data integrity failure,2
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected for descriptor 0x5000.,DMA_ENGINE DMA buffer pointer corruption detected for descriptor 0x5000.,3
INFO,DMA_ENGINE,DMA channel 9 burst read completed,DMA_ENGINE DMA channel 9 burst read completed,3
CRITICAL,DDR_CTRL,"DDR training sequence failed catastrophically, memory uninitialized. (training failure)","DDR_CTRL DDR training sequence failed catastrophically, memory uninitialized. (training failure)",1
WARNING,FIFO_BUF,FIFO_INSTRUCTION_QUEUE has 10 free entries remaining.,FIFO_BUF FIFO_INSTRUCTION_QUEUE has 10 free entries remaining.,-1
WARNING,PCIE_CTRL,PCIe flow control credit exhaustion warning,PCIE_CTRL PCIe flow control credit exhaustion warning,6
ERROR,INTERRUPT_CTRL,Interrupt pending register bit stuck,INTERRUPT_CTRL Interrupt pending register bit stuck,1
ERROR,DDR_CTRL,DDR read data timing violation detected,DDR_CTRL DDR read data timing violation detected,1
INFO,INTERRUPT_CTRL,Interrupt controller configuration updated,INTERRUPT_CTRL Interrupt controller configuration updated,1
ERROR,DMA_ENGINE,DMA channel halted due to descriptor error,DMA_ENGINE DMA channel halted due to descriptor error,3
ERROR,CACHE_CTRL,Cache tag comparison mismatch,CACHE_CTRL Cache tag comparison mismatch,1
INFO,FIFO_BUF,FIFO depth usage at 10%,FIFO_BUF FIFO depth usage at 10%,5
ERROR,MEM_CTRL,Memory page fault detected,MEM_CTRL Memory page fault detected,1
WARNING,DDR_CTRL,DDR PHY impedance mismatch detected,DDR_CTRL DDR PHY impedance mismatch detected,-1
WARNING,MEM_CTRL,Memory access patterns showing increased row conflicts,MEM_CTRL Memory access patterns showing increased row conflicts,1
ERROR,AXI_CTRL,AXI burst length violation detected,AXI_CTRL AXI burst length violation detected,2
WARNING,AXI_CTRL,AXI protocol violation: unaligned burst address,AXI_CTRL AXI protocol violation: unaligned burst address,2
ERROR,DMA_ENGINE,DMA scatter-gather descriptor list corruption detected,DMA_ENGINE DMA scatter-gather descriptor list corruption detected,3
ERROR,DMA_ENGINE,DMA channel 1 arbitration failure,DMA_ENGINE DMA channel 1 arbitration failure,3
WARNING,PCIE_CTRL,Non-fatal PCIe error detected (CRC error on TLP).,PCIE_CTRL Non-fatal PCIe error detected (CRC error on TLP).,6
INFO,CLOCK_MANAGER,Clock output frequency verified,CLOCK_MANAGER Clock output frequency verified,0
ERROR,AXI_CTRL,AXI outstanding transaction limit exceeded,AXI_CTRL AXI outstanding transaction limit exceeded,2
INFO,AXI_CTRL,AXI burst write to 0xABCD0000 completed successfully,AXI_CTRL AXI burst write to 0xABCD0000 completed successfully,2
CRITICAL,MEM_CTRL,Uncorrectable ECC error in critical memory region,MEM_CTRL Uncorrectable ECC error in critical memory region,1
ERROR,PCIE_CTRL,PCIe link training failure during equalization phase,PCIE_CTRL PCIe link training failure during equalization phase,6
WARNING,FIFO_BUF,FIFO almost full condition persistent,FIFO_BUF FIFO almost full condition persistent,5
INFO,PCIE_CTRL,PCIe link established at Gen4 x16,PCIE_CTRL PCIe link established at Gen4 x16,6
INFO,DMA_ENGINE,DMA engine 'GFX' initiated transfer.,DMA_ENGINE DMA engine 'GFX' initiated transfer.,3
WARNING,DDR_CTRL,DDR read data integrity check failed,DDR_CTRL DDR read data integrity check failed,1
INFO,AXI_CTRL,AXI read transaction completed successfully.,AXI_CTRL AXI read transaction completed successfully.,2
WARNING,FIFO_BUF,"FIFO write pointer approaching read pointer, potential data overwrite.","FIFO_BUF FIFO write pointer approaching read pointer, potential data overwrite.",5
CRITICAL,MEM_CTRL,Memory read operation returned unexpected data pattern,MEM_CTRL Memory read operation returned unexpected data pattern,1
INFO,PCIE_CTRL,PCIe endpoint detected new link configuration,PCIE_CTRL PCIe endpoint detected new link configuration,6
ERROR,CLOCK_MANAGER,Reference clock frequency out of range,CLOCK_MANAGER Reference clock frequency out of range,0
INFO,INTERRUPT_CTRL,Interrupt controller in active sleep mode,INTERRUPT_CTRL Interrupt controller in active sleep mode,-1
WARNING,DMA_ENGINE,DMA channel 0 paused due to external dependency,DMA_ENGINE DMA channel 0 paused due to external dependency,3
CRITICAL,PCIE_CTRL,"Fatal PCIe protocol error detected, requiring system reset","PCIE_CTRL Fatal PCIe protocol error detected, requiring system reset",6
ERROR,CACHE_CTRL,Cache coherence protocol deadlock detected during M-state transition.,CACHE_CTRL Cache coherence protocol deadlock detected during M-state transition.,1
ERROR,DMA_ENGINE,DMA channel 1 burst size configuration mismatch,DMA_ENGINE DMA channel 1 burst size configuration mismatch,3
INFO,PCIE_CTRL,PCIe clock recovery successful for lane 1,PCIE_CTRL PCIe clock recovery successful for lane 1,6
INFO,CACHE_CTRL,Cache line for address 0xCAFE loaded,CACHE_CTRL Cache line for address 0xCAFE loaded,1
ERROR,FIFO_BUF,Read operation attempted on empty FIFO,FIFO_BUF Read operation attempted on empty FIFO,5
ERROR,FIFO_BUF,FIFO reset command failed to propagate to all stages,FIFO_BUF FIFO reset command failed to propagate to all stages,5
INFO,PCIE_CTRL,PCIe device enumeration completed.,PCIE_CTRL PCIe device enumeration completed.,6
INFO,FIFO_BUF,FIFO depth reported as 64 entries,FIFO_BUF FIFO depth reported as 64 entries,5
WARNING,CLOCK_MANAGER,Clock synchronization handshake delay,CLOCK_MANAGER Clock synchronization handshake delay,0
WARNING,PCIE_CTRL,PCIe retransmission buffer utilization increasing,PCIE_CTRL PCIe retransmission buffer utilization increasing,6
ERROR,INTERRUPT_CTRL,"Interrupt priority inversion detected, critical task delayed for IRQ 0x0","INTERRUPT_CTRL Interrupt priority inversion detected, critical task delayed for IRQ 0x0",1
WARNING,INTERRUPT_CTRL,Interrupt queue nearing capacity,INTERRUPT_CTRL Interrupt queue nearing capacity,1
ERROR,MEM_CTRL,Data bus parity error on memory read,MEM_CTRL Data bus parity error on memory read,1
CRITICAL,CLOCK_MANAGER,"Clock mux selection logic fault, incorrect clock source applied","CLOCK_MANAGER Clock mux selection logic fault, incorrect clock source applied",0
INFO,PCIE_CTRL,PCIe device `vendor_id:device_id` found,PCIE_CTRL PCIe device `vendor_id:device_id` found,6
WARNING,DMA_ENGINE,DMA transfer completion delay detected,DMA_ENGINE DMA transfer completion delay detected,3
ERROR,DDR_CTRL,DDR controller detected a refresh cycle delay beyond threshold,DDR_CTRL DDR controller detected a refresh cycle delay beyond threshold,1
INFO,DMA_ENGINE,DMA channel 0 reset initiated,DMA_ENGINE DMA channel 0 reset initiated,3
CRITICAL,POWER_CTRL,Main power rail dropped below threshold,POWER_CTRL Main power rail dropped below threshold,4
ERROR,AXI_CTRL,AXI write address parity error detected,AXI_CTRL AXI write address parity error detected,2
WARNING,CLOCK_MANAGER,Clock jitter on high-speed interface exceeding 10ps RMS.,CLOCK_MANAGER Clock jitter on high-speed interface exceeding 10ps RMS.,0
ERROR,MEM_CTRL,Memory data bus stuck-at fault,MEM_CTRL Memory data bus stuck-at fault,1
ERROR,INTERRUPT_CTRL,Interrupt controller software attempted to write to read-only register,INTERRUPT_CTRL Interrupt controller software attempted to write to read-only register,1
INFO,FIFO_BUF,FIFO occupancy 50%,FIFO_BUF FIFO occupancy 50%,5
ERROR,PCIE_CTRL,PCIe TLP CRC error received,PCIE_CTRL PCIe TLP CRC error received,6
ERROR,CACHE_CTRL,Cache line write-back error to main memory,CACHE_CTRL Cache line write-back error to main memory,1
WARNING,POWER_CTRL,Core voltage rail fluctuating,POWER_CTRL Core voltage rail fluctuating,4
WARNING,PCIE_CTRL,PCIe device driver reporting resource contention,PCIE_CTRL PCIe device driver reporting resource contention,6
ERROR,DMA_ENGINE,DMA channel 1 stalled due to peripheral not ready,DMA_ENGINE DMA channel 1 stalled due to peripheral not ready,3
INFO,CACHE_CTRL,L2 cache prefetcher enabled,CACHE_CTRL L2 cache prefetcher enabled,1
ERROR,AXI_CTRL,AXI burst size larger than allowable,AXI_CTRL AXI burst size larger than allowable,2
WARNING,DDR_CTRL,DDR self-refresh entry/exit timing deviation.,DDR_CTRL DDR self-refresh entry/exit timing deviation.,1
ERROR,DMA_ENGINE,DMA channel 2 data transfer mismatch detected,DMA_ENGINE DMA channel 2 data transfer mismatch detected,3
ERROR,POWER_CTRL,Over-voltage condition detected on 1.8V rail,POWER_CTRL Over-voltage condition detected on 1.8V rail,4
INFO,FIFO_BUF,FIFO empty status transition observed,FIFO_BUF FIFO empty status transition observed,5
CRITICAL,CLOCK_MANAGER,System PLL frequency drift exceeding specification,CLOCK_MANAGER System PLL frequency drift exceeding specification,0
ERROR,POWER_CTRL,Thermal sensor failed to respond,POWER_CTRL Thermal sensor failed to respond,4
INFO,AXI_CTRL,AXI read transaction ID W accepted,AXI_CTRL AXI read transaction ID W accepted,2
ERROR,AXI_CTRL,AXI write transaction ID mismatch,AXI_CTRL AXI write transaction ID mismatch,2
WARNING,CLOCK_MANAGER,Reference clock quality degraded (minor),CLOCK_MANAGER Reference clock quality degraded (minor),0
WARNING,PCIE_CTRL,PCIe flow control credit nearing limit,PCIE_CTRL PCIe flow control credit nearing limit,6
INFO,DDR_CTRL,DDR write data capture aligned,DDR_CTRL DDR write data capture aligned,-1
WARNING,DDR_CTRL,DDR write latency exceeding typical operating range,DDR_CTRL DDR write latency exceeding typical operating range,1
INFO,INTERRUPT_CTRL,Pending interrupt count is zero.,INTERRUPT_CTRL Pending interrupt count is zero.,1
WARNING,DMA_ENGINE,DMA request queue building up,DMA_ENGINE DMA request queue building up,3
CRITICAL,INTERRUPT_CTRL,System cannot process interrupts,INTERRUPT_CTRL System cannot process interrupts,1
INFO,DMA_ENGINE,DMA channel reconfigured,DMA_ENGINE DMA channel reconfigured,3
CRITICAL,CLOCK_MANAGER,Unrecoverable clock tree fault,CLOCK_MANAGER Unrecoverable clock tree fault,0
INFO,DDR_CTRL,Global enable signal asserted for DDR_CTRL.,DDR_CTRL Global enable signal asserted for DDR_CTRL.,-1
CRITICAL,AXI_CTRL,AXI global reset asserted unexpectedly,AXI_CTRL AXI global reset asserted unexpectedly,-1
ERROR,FIFO_BUF,"Write operation to full FIFO attempted, data lost","FIFO_BUF Write operation to full FIFO attempted, data lost",5
INFO,CLOCK_MANAGER,Clock divider updated for new frequency,CLOCK_MANAGER Clock divider updated for new frequency,0
WARNING,DMA_ENGINE,"DMA engine idle for extended period, potential hang","DMA_ENGINE DMA engine idle for extended period, potential hang",3
INFO,MEM_CTRL,Memory write transaction initiated,MEM_CTRL Memory write transaction initiated,1
ERROR,AXI_CTRL,AXI read data bus parity error detected,AXI_CTRL AXI read data bus parity error detected,2
INFO,INTERRUPT_CTRL,Interrupt vector table reload successful,INTERRUPT_CTRL Interrupt vector table reload successful,1
ERROR,INTERRUPT_CTRL,Unhandled interrupt asserted from source 24.,INTERRUPT_CTRL Unhandled interrupt asserted from source 24.,1
INFO,FIFO_BUF,FIFO 'tx_data' has 64 entries remaining,FIFO_BUF FIFO 'tx_data' has 64 entries remaining,5
ERROR,PCIE_CTRL,PCIe transaction ID collision detected,PCIE_CTRL PCIe transaction ID collision detected,6
ERROR,DDR_CTRL,DDR command timing violation detected for consecutive ACT/PRE.,DDR_CTRL DDR command timing violation detected for consecutive ACT/PRE.,1
CRITICAL,INTERRUPT_CTRL,Critical interrupt handling logic fault,INTERRUPT_CTRL Critical interrupt handling logic fault,1
INFO,DDR_CTRL,DDR calibration completed successfully,DDR_CTRL DDR calibration completed successfully,1
ERROR,MEM_CTRL,Memory buffer overflow,MEM_CTRL Memory buffer overflow,1
WARNING,CACHE_CTRL,Cache eviction queue nearing capacity (100 entries).,CACHE_CTRL Cache eviction queue nearing capacity (100 entries).,1
ERROR,INTERRUPT_CTRL,Interrupt controller state machine fault.,INTERRUPT_CTRL Interrupt controller state machine fault.,1
CRITICAL,DDR_CTRL,"DDR PLL lock lost, memory clock unstable","DDR_CTRL DDR PLL lock lost, memory clock unstable",1
ERROR,PCIE_CTRL,PCIE_CTRL control logic stalled due to state machine fault (FSM stuck in error state).,PCIE_CTRL PCIE_CTRL control logic stalled due to state machine fault (FSM stuck in error state).,-1
CRITICAL,FIFO_BUF,FIFO depth detected as zero after configuration,FIFO_BUF FIFO depth detected as zero after configuration,5
ERROR,MEM_CTRL,Write-after-read hazard detected by memory arbiter,MEM_CTRL Write-after-read hazard detected by memory arbiter,1
WARNING,INTERRUPT_CTRL,Interrupt pending count consistently high,INTERRUPT_CTRL Interrupt pending count consistently high,1
WARNING,INTERRUPT_CTRL,Interrupt priority encoder observed incorrect input,INTERRUPT_CTRL Interrupt priority encoder observed incorrect input,1
ERROR,PCIE_CTRL,PCIe link state transition timeout,PCIE_CTRL PCIe link state transition timeout,6
INFO,CACHE_CTRL,Cache dirty line writeback initiated,CACHE_CTRL Cache dirty line writeback initiated,1
ERROR,PCIE_CTRL,PCIe inbound memory access violation,PCIE_CTRL PCIe inbound memory access violation,6
INFO,CLOCK_MANAGER,Clock gating enabled for idle blocks,CLOCK_MANAGER Clock gating enabled for idle blocks,0
WARNING,DDR_CTRL,DDR read latency variation detected,DDR_CTRL DDR read latency variation detected,1
ERROR,AXI_CTRL,AXI protocol violation: AWID/RID mismatch.,AXI_CTRL AXI protocol violation: AWID/RID mismatch.,2
ERROR,MEM_CTRL,Memory address alignment fault on write access,MEM_CTRL Memory address alignment fault on write access,1
WARNING,DDR_CTRL,DDR_CTRL internal buffer approaching capacity (91% full).,DDR_CTRL DDR_CTRL internal buffer approaching capacity (91% full).,1
CRITICAL,MEM_CTRL,Memory access generated an MMU page fault,MEM_CTRL Memory access generated an MMU page fault,1
WARNING,INTERRUPT_CTRL,Interrupt request signal stuck high,INTERRUPT_CTRL Interrupt request signal stuck high,1
WARNING,PCIE_CTRL,PCIe link error rate for Gen5 higher than target,PCIE_CTRL PCIe link error rate for Gen5 higher than target,6
INFO,DDR_CTRL,DDR memory initialized for system boot,DDR_CTRL DDR memory initialized for system boot,1
ERROR,INTERRUPT_CTRL,Interrupt masking logic failed to block a disabled interrupt,INTERRUPT_CTRL Interrupt masking logic failed to block a disabled interrupt,1
INFO,MEM_CTRL,Memory access granted for high priority.,MEM_CTRL Memory access granted for high priority.,1
ERROR,DDR_CTRL,Read latency calibration out of specified range,DDR_CTRL Read latency calibration out of specified range,1
CRITICAL,CACHE_CTRL,Cache internal FSM entered illegal state,CACHE_CTRL Cache internal FSM entered illegal state,1
WARNING,DDR_CTRL,DDR burst integrity check failure rate increasing,DDR_CTRL DDR burst integrity check failure rate increasing,1
ERROR,DDR_CTRL,DDR write leveling calibration detected severe impedance mismatch,DDR_CTRL DDR write leveling calibration detected severe impedance mismatch,1
ERROR,INTERRUPT_CTRL,Interrupt pending bit set for disabled interrupt,INTERRUPT_CTRL Interrupt pending bit set for disabled interrupt,1
CRITICAL,MEM_CTRL,Double bit ECC corruption detected,MEM_CTRL Double bit ECC corruption detected,1
WARNING,POWER_CTRL,Power consumption spike detected during workload burst.,POWER_CTRL Power consumption spike detected during workload burst.,4
INFO,DMA_ENGINE,DMA loopback test started,DMA_ENGINE DMA loopback test started,3
INFO,INTERRUPT_CTRL,Interrupts globally enabled,INTERRUPT_CTRL Interrupts globally enabled,1
WARNING,FIFO_BUF,FIFO 'status_fifo' read data valid but no corresponding read request,FIFO_BUF FIFO 'status_fifo' read data valid but no corresponding read request,5
ERROR,MEM_CTRL,Memory controller command queue overflow,MEM_CTRL Memory controller command queue overflow,1
ERROR,DMA_ENGINE,DMA channel 7 configuration register write error,DMA_ENGINE DMA channel 7 configuration register write error,3
INFO,DDR_CTRL,DDR dynamic ODT enabled,DDR_CTRL DDR dynamic ODT enabled,-1
INFO,DMA_ENGINE,DMA channel 8 configuration applied,DMA_ENGINE DMA channel 8 configuration applied,3
ERROR,CLOCK_MANAGER,Critical clock signal missing,CLOCK_MANAGER Critical clock signal missing,0
ERROR,AXI_CTRL,AXI read data channel ID mismatch detected for transaction 0x1234,AXI_CTRL AXI read data channel ID mismatch detected for transaction 0x1234,2
WARNING,DDR_CTRL,DDR precharge cycle timing marginal,DDR_CTRL DDR precharge cycle timing marginal,1
CRITICAL,CACHE_CTRL,Cache line deadlock detected during dirty writeback,CACHE_CTRL Cache line deadlock detected during dirty writeback,1
ERROR,DMA_ENGINE,DMA channel arbitration priority inversion detected,DMA_ENGINE DMA channel arbitration priority inversion detected,3
INFO,DDR_CTRL,DDR power-down entry sequence initiated,DDR_CTRL DDR power-down entry sequence initiated,1
CRITICAL,DMA_ENGINE,DMA engine hung due to arbitration deadlock with CPU,DMA_ENGINE DMA engine hung due to arbitration deadlock with CPU,3
INFO,INTERRUPT_CTRL,Interrupt controller enabled.,INTERRUPT_CTRL Interrupt controller enabled.,1
INFO,DDR_CTRL,DDR memory controller configured,DDR_CTRL DDR memory controller configured,1
ERROR,CACHE_CTRL,Cache tag RAM parity error detected,CACHE_CTRL Cache tag RAM parity error detected,1
ERROR,FIFO_BUF,FIFO full status not asserted at capacity,FIFO_BUF FIFO full status not asserted at capacity,5
WARNING,POWER_CTRL,System power consumption nearing peak budget,POWER_CTRL System power consumption nearing peak budget,4
CRITICAL,DDR_CTRL,DDR controller state machine deadlock,DDR_CTRL DDR controller state machine deadlock,1
INFO,FIFO_BUF,FIFO depth usage reported as 25%,FIFO_BUF FIFO depth usage reported as 25%,5
WARNING,INTERRUPT_CTRL,Interrupt coalescing buffer almost full.,INTERRUPT_CTRL Interrupt coalescing buffer almost full.,1
WARNING,CACHE_CTRL,Cache coherency probe responses showing delays,CACHE_CTRL Cache coherency probe responses showing delays,1
WARNING,PCIE_CTRL,PCIe link state transitions unexpectedly,PCIE_CTRL PCIe link state transitions unexpectedly,6
ERROR,POWER_CTRL,Power sequencing controller fault,POWER_CTRL Power sequencing controller fault,4
CRITICAL,DMA_ENGINE,DMA engine clock domain crossing bridge failure.,DMA_ENGINE DMA engine clock domain crossing bridge failure.,-1
ERROR,POWER_CTRL,Power rail instability detected on 5V supply,POWER_CTRL Power rail instability detected on 5V supply,4
INFO,CLOCK_MANAGER,Clock frequency configured to 200MHz,CLOCK_MANAGER Clock frequency configured to 200MHz,0
INFO,INTERRUPT_CTRL,Interrupt controller configuration saved,INTERRUPT_CTRL Interrupt controller configuration saved,1
INFO,FIFO_BUF,Read pointer successfully reset,FIFO_BUF Read pointer successfully reset,5
CRITICAL,FIFO_BUF,FIFO memory parity error.,FIFO_BUF FIFO memory parity error.,5
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal observed too early,INTERRUPT_CTRL Interrupt acknowledge signal observed too early,1
ERROR,MEM_CTRL,Memory controller state machine unexpected transition,MEM_CTRL Memory controller state machine unexpected transition,1
ERROR,PCIE_CTRL,PCIe link training failure detected for endpoint device,PCIE_CTRL PCIe link training failure detected for endpoint device,6
INFO,AXI_CTRL,AXI transactions progressing normally,AXI_CTRL AXI transactions progressing normally,2
WARNING,DDR_CTRL,"DDR memory temperature rising, nearing threshold","DDR_CTRL DDR memory temperature rising, nearing threshold",1
WARNING,FIFO_BUF,FIFO write latency exceeding expected threshold,FIFO_BUF FIFO write latency exceeding expected threshold,5
ERROR,INTERRUPT_CTRL,Interrupt line 15 asserted without corresponding enable.,INTERRUPT_CTRL Interrupt line 15 asserted without corresponding enable.,1
WARNING,DMA_ENGINE,DMA descriptor pool has only 10% of entries remaining.,DMA_ENGINE DMA descriptor pool has only 10% of entries remaining.,3
WARNING,POWER_CTRL,Voltage on POWER_CTRL rail showing minor fluctuations.,POWER_CTRL Voltage on POWER_CTRL rail showing minor fluctuations.,4
INFO,FIFO_BUF,FIFO_BUF_12 current fill level 40%,FIFO_BUF FIFO_BUF_12 current fill level 40%,5
ERROR,CLOCK_MANAGER,Clock domain crossing handshake failure,CLOCK_MANAGER Clock domain crossing handshake failure,0
INFO,DDR_CTRL,Memory refresh cycle performed by controller,DDR_CTRL Memory refresh cycle performed by controller,1
ERROR,FIFO_BUF,FIFO capacity reporting inconsistency,FIFO_BUF FIFO capacity reporting inconsistency,5
INFO,CLOCK_MANAGER,Clock divider ratio updated,CLOCK_MANAGER Clock divider ratio updated,0
ERROR,INTERRUPT_CTRL,Interrupt masking error,INTERRUPT_CTRL Interrupt masking error,1
CRITICAL,DDR_CTRL,DDR training sequence failed persistently,DDR_CTRL DDR training sequence failed persistently,1
WARNING,INTERRUPT_CTRL,Interrupt latency for high priority IRQ_CRITICAL_FAULT exceeding 50 cycles.,INTERRUPT_CTRL Interrupt latency for high priority IRQ_CRITICAL_FAULT exceeding 50 cycles.,1
WARNING,CACHE_CTRL,Cache L1 data invalidation in progress,CACHE_CTRL Cache L1 data invalidation in progress,1
ERROR,DMA_ENGINE,DMA channel 2 address translation fault.,DMA_ENGINE DMA channel 2 address translation fault.,3
WARNING,DMA_ENGINE,DMA channel 0 paused by external debug signal,DMA_ENGINE DMA channel 0 paused by external debug signal,3
WARNING,DMA_ENGINE,DMA status register read contention,DMA_ENGINE DMA status register read contention,3
WARNING,AXI_CTRL,AXI read transaction ID tag mismatch,AXI_CTRL AXI read transaction ID tag mismatch,2
ERROR,FIFO_BUF,Invalid read request on empty FIFO,FIFO_BUF Invalid read request on empty FIFO,5
INFO,AXI_CTRL,AXI master initiating new transaction,AXI_CTRL AXI master initiating new transaction,2
INFO,CLOCK_MANAGER,PLL locked to target frequency 1.2GHz,CLOCK_MANAGER PLL locked to target frequency 1.2GHz,0
WARNING,AXI_CTRL,AXI outstanding transactions count nearing limit (200).,AXI_CTRL AXI outstanding transactions count nearing limit (200).,2
ERROR,CACHE_CTRL,Cache line not found during expected hit,CACHE_CTRL Cache line not found during expected hit,1
ERROR,MEM_CTRL,Memory protection unit (MPU) violation on instruction fetch,MEM_CTRL Memory protection unit (MPU) violation on instruction fetch,1
ERROR,FIFO_BUF,FIFO write pointer corruption,FIFO_BUF FIFO write pointer corruption,5
WARNING,CACHE_CTRL,Cache victim buffer nearing capacity.,CACHE_CTRL Cache victim buffer nearing capacity.,1
WARNING,MEM_CTRL,Memory refresh delayed due to high priority access.,MEM_CTRL Memory refresh delayed due to high priority access.,1
WARNING,DDR_CTRL,DDR read data timing margin reduced,DDR_CTRL DDR read data timing margin reduced,1
CRITICAL,MEM_CTRL,"Double bit ECC corruption detected, uncorrectable error.","MEM_CTRL Double bit ECC corruption detected, uncorrectable error.",1
ERROR,AXI_CTRL,AXI write burst length violation detected,AXI_CTRL AXI write burst length violation detected,2
CRITICAL,MEM_CTRL,Firmware detected memory bus deadlock,MEM_CTRL Firmware detected memory bus deadlock,1
ERROR,CACHE_CTRL,Cache dirty line writeback timeout,CACHE_CTRL Cache dirty line writeback timeout,1
INFO,FIFO_BUF,FIFO depth check passed,FIFO_BUF FIFO depth check passed,5
WARNING,PCIE_CTRL,PCIe internal buffer nearly exhausted,PCIE_CTRL PCIe internal buffer nearly exhausted,6
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding threshold,INTERRUPT_CTRL Interrupt latency exceeding threshold,1
CRITICAL,PCIE_CTRL,"PCIe fatal error detected, link permanently down","PCIE_CTRL PCIe fatal error detected, link permanently down",6
WARNING,DDR_CTRL,"DDR controller detected high burst activity, increasing power","DDR_CTRL DDR controller detected high burst activity, increasing power",1
ERROR,FIFO_BUF,FIFO_BUF: buffer underflow - read from empty buffer detected. (FIFO 'FIFO_BUF' Depth: 226),FIFO_BUF FIFO_BUF: buffer underflow - read from empty buffer detected. (FIFO 'FIFO_BUF' Depth: 226),5
INFO,PCIE_CTRL,PCIe configuration space read.,PCIE_CTRL PCIe configuration space read.,6
WARNING,DDR_CTRL,DDR row hammer effect mitigated,DDR_CTRL DDR row hammer effect mitigated,-1
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance for clock Z.,CLOCK_MANAGER Clock jitter exceeding tolerance for clock Z.,0
INFO,DMA_ENGINE,DMA transfer completed successfully for block 0x2000,DMA_ENGINE DMA transfer completed successfully for block 0x2000,3
INFO,MEM_CTRL,Read data retrieved from address 0x1000,MEM_CTRL Read data retrieved from address 0x1000,1
INFO,DMA_ENGINE,Buffer deallocated,DMA_ENGINE Buffer deallocated,3
INFO,PCIE_CTRL,PCIe receive buffer cleared,PCIE_CTRL PCIe receive buffer cleared,6
CRITICAL,POWER_CTRL,System power controller entered bypass mode unexpectedly,POWER_CTRL System power controller entered bypass mode unexpectedly,-1
ERROR,INTERRUPT_CTRL,Interrupt prioritization logic error,INTERRUPT_CTRL Interrupt prioritization logic error,1
WARNING,FIFO_BUF,Buffer occupancy high,FIFO_BUF Buffer occupancy high,5
WARNING,CLOCK_MANAGER,PLL reference clock input unstable,CLOCK_MANAGER PLL reference clock input unstable,0
INFO,PCIE_CTRL,PCIe MSI-X vector configuration updated,PCIE_CTRL PCIe MSI-X vector configuration updated,-1
WARNING,POWER_CTRL,Temperature sensor reading approaching critical limit,POWER_CTRL Temperature sensor reading approaching critical limit,4
ERROR,FIFO_BUF,FIFO synchronization error detected across clock domains,FIFO_BUF FIFO synchronization error detected across clock domains,5
CRITICAL,DMA_ENGINE,DMA internal state machine entered an unrecoverable error state,DMA_ENGINE DMA internal state machine entered an unrecoverable error state,3
ERROR,AXI_CTRL,AXI transaction ID not found,AXI_CTRL AXI transaction ID not found,2
WARNING,AXI_CTRL,AXI write transaction queue depth consistently high.,AXI_CTRL AXI write transaction queue depth consistently high.,2
CRITICAL,DMA_ENGINE,"DMA descriptor ring buffer corrupted, all channels halted","DMA_ENGINE DMA descriptor ring buffer corrupted, all channels halted",3
ERROR,CLOCK_MANAGER,Clock source 'HCLK' experienced a momentary glitch,CLOCK_MANAGER Clock source 'HCLK' experienced a momentary glitch,-1
ERROR,AXI_CTRL,AXI slave responded with OKAY but data transfer was incomplete.,AXI_CTRL AXI slave responded with OKAY but data transfer was incomplete.,2
WARNING,POWER_CTRL,Power domain 'IO_VDD' current draw exceeding typical,POWER_CTRL Power domain 'IO_VDD' current draw exceeding typical,-1
CRITICAL,DMA_ENGINE,DMA state machine stuck in 'transfer_active' without progress.,DMA_ENGINE DMA state machine stuck in 'transfer_active' without progress.,3
INFO,PCIE_CTRL,PCIe hot-reset sequence initiated.,PCIE_CTRL PCIe hot-reset sequence initiated.,6
WARNING,INTERRUPT_CTRL,Interrupt dispatch queue experiencing elevated latency,INTERRUPT_CTRL Interrupt dispatch queue experiencing elevated latency,1
ERROR,AXI_CTRL,AXI read data channel parity error,AXI_CTRL AXI read data channel parity error,2
WARNING,CLOCK_MANAGER,CLOCK_MANAGER diagnostic error register for CLOCK_MANAGER shows a sticky bit.,CLOCK_MANAGER CLOCK_MANAGER diagnostic error register for CLOCK_MANAGER shows a sticky bit.,0
ERROR,AXI_CTRL,AW channel AXI ID tag mismatch,AXI_CTRL AW channel AXI ID tag mismatch,2
WARNING,FIFO_BUF,FIFO synchronization logic reports occasional phase difference.,FIFO_BUF FIFO synchronization logic reports occasional phase difference.,5
WARNING,DDR_CTRL,"DDR command queue build-up, latency increasing","DDR_CTRL DDR command queue build-up, latency increasing",1
INFO,MEM_CTRL,Memory controller configured for burst reads,MEM_CTRL Memory controller configured for burst reads,1
ERROR,DMA_ENGINE,"DMA channel X command timeout, peripheral unresponsive.","DMA_ENGINE DMA channel X command timeout, peripheral unresponsive.",3
WARNING,PCIE_CTRL,"Bad TLP received, corrected","PCIE_CTRL Bad TLP received, corrected",6
CRITICAL,MEM_CTRL,Memory refresh controller inoperable,MEM_CTRL Memory refresh controller inoperable,1
WARNING,POWER_CTRL,Voltage regulator output ripple exceeding specification.,POWER_CTRL Voltage regulator output ripple exceeding specification.,4
INFO,FIFO_BUF,"Data block written to FIFO, available entries reduced","FIFO_BUF Data block written to FIFO, available entries reduced",5
INFO,MEM_CTRL,Memory test completed successfully,MEM_CTRL Memory test completed successfully,1
INFO,AXI_CTRL,AXI write response channel observed busy,AXI_CTRL AXI write response channel observed busy,2
INFO,POWER_CTRL,System power state changed to S0,POWER_CTRL System power state changed to S0,4
CRITICAL,FIFO_BUF,"FIFO hardware malfunction, unable to perform any operations","FIFO_BUF FIFO hardware malfunction, unable to perform any operations",5
INFO,DDR_CTRL,Memory scrub operation initiated,DDR_CTRL Memory scrub operation initiated,1
WARNING,DMA_ENGINE,DMA engine internal arbitration conflict,DMA_ENGINE DMA engine internal arbitration conflict,3
ERROR,INTERRUPT_CTRL,INTERRUPT_CTRL: arbitration conflict - fairness algorithm failure detected. (Conflicting IRQ IDs: 19 and 22),INTERRUPT_CTRL INTERRUPT_CTRL: arbitration conflict - fairness algorithm failure detected. (Conflicting IRQ IDs: 19 and 22),1
CRITICAL,AXI_CTRL,"AXI arbiter entered invalid state, bus stalled.","AXI_CTRL AXI arbiter entered invalid state, bus stalled.",2
INFO,MEM_CTRL,Memory address 0x933FE successfully written,MEM_CTRL Memory address 0x933FE successfully written,1
CRITICAL,MEM_CTRL,Memory controller arbitration deadlock detected,MEM_CTRL Memory controller arbitration deadlock detected,1
WARNING,MEM_CTRL,Memory refresh pending,MEM_CTRL Memory refresh pending,1
WARNING,FIFO_BUF,Output FIFO backpressure asserted by downstream module,FIFO_BUF Output FIFO backpressure asserted by downstream module,5
WARNING,POWER_CTRL,"Core rail voltage fluctuating, near lower bound for 3.3V.","POWER_CTRL Core rail voltage fluctuating, near lower bound for 3.3V.",4
CRITICAL,POWER_CTRL,System PMIC reports critical fault,POWER_CTRL System PMIC reports critical fault,4
CRITICAL,DDR_CTRL,DDR memory controller initiated unexpected hard reset due to internal error.,DDR_CTRL DDR memory controller initiated unexpected hard reset due to internal error.,1
WARNING,FIFO_BUF,FIFO latency spikes detected during burst transfers,FIFO_BUF FIFO latency spikes detected during burst transfers,5
INFO,INTERRUPT_CTRL,Interrupt controller re-enabled after critical section,INTERRUPT_CTRL Interrupt controller re-enabled after critical section,1
INFO,MEM_CTRL,MEM_CTRL entered idle state.,MEM_CTRL MEM_CTRL entered idle state.,1
ERROR,DMA_ENGINE,DMA descriptor queue overflow,DMA_ENGINE DMA descriptor queue overflow,3
INFO,DDR_CTRL,DDR ZQ calibration completed,DDR_CTRL DDR ZQ calibration completed,1
WARNING,DDR_CTRL,DDR command queue filling rapidly,DDR_CTRL DDR command queue filling rapidly,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal reset failed to assert,INTERRUPT_CTRL Interrupt controller internal reset failed to assert,1
CRITICAL,CLOCK_MANAGER,"System reference clock lost entirely, cannot recover.","CLOCK_MANAGER System reference clock lost entirely, cannot recover.",0
CRITICAL,FIFO_BUF,Critical data loss due to FIFO corruption,FIFO_BUF Critical data loss due to FIFO corruption,5
ERROR,POWER_CTRL,Voltage regulator power good signal de-asserted,POWER_CTRL Voltage regulator power good signal de-asserted,-1
WARNING,DDR_CTRL,DDR ZQ calibration pending,DDR_CTRL DDR ZQ calibration pending,1
ERROR,DMA_ENGINE,DMA transfer timeout detected,DMA_ENGINE DMA transfer timeout detected,3
INFO,POWER_CTRL,System entered into deep sleep state,POWER_CTRL System entered into deep sleep state,4
WARNING,PCIE_CTRL,PCIe transaction layer packet (TLP) buffer almost full,PCIE_CTRL PCIe transaction layer packet (TLP) buffer almost full,6
WARNING,DMA_ENGINE,DMA channel 3 has pending transactions for too long,DMA_ENGINE DMA channel 3 has pending transactions for too long,3
ERROR,CACHE_CTRL,"Cache Way X enabled illegally, configuration error.","CACHE_CTRL Cache Way X enabled illegally, configuration error.",1
WARNING,MEM_CTRL,Memory page fault rate exceeding threshold,MEM_CTRL Memory page fault rate exceeding threshold,1
WARNING,DDR_CTRL,DDR controller reported a read data integrity warning,DDR_CTRL DDR controller reported a read data integrity warning,1
CRITICAL,DDR_CTRL,DDR training sequence failed (unrecoverable),DDR_CTRL DDR training sequence failed (unrecoverable),1
ERROR,INTERRUPT_CTRL,Interrupt vector mismatch detected for IRQ 31.,INTERRUPT_CTRL Interrupt vector mismatch detected for IRQ 31.,1
ERROR,PCIE_CTRL,PCIe TLP integrity check failure,PCIE_CTRL PCIe TLP integrity check failure,6
INFO,PCIE_CTRL,PCIe device configuration completed,PCIE_CTRL PCIe device configuration completed,6
ERROR,AXI_CTRL,AXI read burst alignment violation.,AXI_CTRL AXI read burst alignment violation.,2
WARNING,MEM_CTRL,Memory address range 0x20000000-0x200FFFFF experiencing high access rate,MEM_CTRL Memory address range 0x20000000-0x200FFFFF experiencing high access rate,1
ERROR,DDR_CTRL,Memory address alignment fault on DDR access.,DDR_CTRL Memory address alignment fault on DDR access.,1
WARNING,CACHE_CTRL,Cache writeback buffer nearly full,CACHE_CTRL Cache writeback buffer nearly full,1
WARNING,INTERRUPT_CTRL,Pending interrupt count high for module X.,INTERRUPT_CTRL Pending interrupt count high for module X.,1
CRITICAL,DDR_CTRL,DDR memory data strobe (DQS) failure,DDR_CTRL DDR memory data strobe (DQS) failure,-1
WARNING,FIFO_BUF,FIFO depth threshold for 'almost_full' reached,FIFO_BUF FIFO depth threshold for 'almost_full' reached,5
ERROR,POWER_CTRL,Power sequencing controller timeout during power-down phase,POWER_CTRL Power sequencing controller timeout during power-down phase,4
ERROR,CLOCK_MANAGER,Frequency deviation detected on critical clock,CLOCK_MANAGER Frequency deviation detected on critical clock,0
CRITICAL,DDR_CTRL,DDR initialization sequence failed to complete,DDR_CTRL DDR initialization sequence failed to complete,1
ERROR,MEM_CTRL,Memory address decoding error at 0xDEADBEEF,MEM_CTRL Memory address decoding error at 0xDEADBEEF,1
CRITICAL,CLOCK_MANAGER,Clock network redundancy failure,CLOCK_MANAGER Clock network redundancy failure,0
INFO,CACHE_CTRL,Cache access permission table updated,CACHE_CTRL Cache access permission table updated,-1
CRITICAL,PCIE_CTRL,PCIe root complex communication lost,PCIE_CTRL PCIe root complex communication lost,6
INFO,DDR_CTRL,DDR controller frequency scaled down,DDR_CTRL DDR controller frequency scaled down,1
WARNING,DDR_CTRL,DDR controller read data FIFO overflow,DDR_CTRL DDR controller read data FIFO overflow,1
WARNING,FIFO_BUF,FIFO read latency increasing significantly,FIFO_BUF FIFO read latency increasing significantly,5
ERROR,INTERRUPT_CTRL,"Interrupt masking error detected, incorrect configuration.","INTERRUPT_CTRL Interrupt masking error detected, incorrect configuration.",1
INFO,FIFO_BUF,"Write operation successful, FIFO fill level 0x20","FIFO_BUF Write operation successful, FIFO fill level 0x20",5
ERROR,POWER_CTRL,Voltage sensor calibration out of range,POWER_CTRL Voltage sensor calibration out of range,7
CRITICAL,CACHE_CTRL,Critical cache deadlock detected during M-state transition,CACHE_CTRL Critical cache deadlock detected during M-state transition,1
ERROR,AXI_CTRL,AXI atomic operation failed to complete,AXI_CTRL AXI atomic operation failed to complete,2
INFO,AXI_CTRL,AXI burst transfer completed with expected beats,AXI_CTRL AXI burst transfer completed with expected beats,2
INFO,DDR_CTRL,DDR burst length set to 8,DDR_CTRL DDR burst length set to 8,1
ERROR,DDR_CTRL,DDR row active time violation,DDR_CTRL DDR row active time violation,1
WARNING,CLOCK_MANAGER,Clock domain crossing setup time warning,CLOCK_MANAGER Clock domain crossing setup time warning,0
WARNING,CLOCK_MANAGER,Reference clock frequency deviation detected,CLOCK_MANAGER Reference clock frequency deviation detected,0
WARNING,POWER_CTRL,Core voltage rail minor droop observed,POWER_CTRL Core voltage rail minor droop observed,4
INFO,MEM_CTRL,Data read from memory at 0x1000 successfully,MEM_CTRL Data read from memory at 0x1000 successfully,1
CRITICAL,CLOCK_MANAGER,"CRITICAL: Clock generation PLL lock lost, all system clocks unstable.","CLOCK_MANAGER CRITICAL: Clock generation PLL lock lost, all system clocks unstable.",0
ERROR,PCIE_CTRL,PCIe configuration space access violation,PCIE_CTRL PCIe configuration space access violation,6
CRITICAL,POWER_CTRL,Power rail voltage critical drop detected below safe margin,POWER_CTRL Power rail voltage critical drop detected below safe margin,4
CRITICAL,AXI_CTRL,AXI interconnect asserted system-level error response,AXI_CTRL AXI interconnect asserted system-level error response,2
CRITICAL,CACHE_CTRL,Uncorrectable cache memory ECC error,CACHE_CTRL Uncorrectable cache memory ECC error,1
INFO,DMA_ENGINE,DMA transfer initiated for 2KB block,DMA_ENGINE DMA transfer initiated for 2KB block,3
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal stuck low,INTERRUPT_CTRL Interrupt acknowledge signal stuck low,1
CRITICAL,CLOCK_MANAGER,"PLL permanent unlock, system clock unstable.","CLOCK_MANAGER PLL permanent unlock, system clock unstable.",0
WARNING,CACHE_CTRL,Cache tag RAM nearing capacity,CACHE_CTRL Cache tag RAM nearing capacity,1
WARNING,AXI_CTRL,AXI slave experiencing heavy backpressure,AXI_CTRL AXI slave experiencing heavy backpressure,2
INFO,PCIE_CTRL,PCIe link speed negotiated to Gen4 x8,PCIE_CTRL PCIe link speed negotiated to Gen4 x8,6
INFO,PCIE_CTRL,PCIe link established at target speed,PCIE_CTRL PCIe link established at target speed,6
INFO,AXI_CTRL,AXI read burst completed on channel X.,AXI_CTRL AXI read burst completed on channel X.,2
CRITICAL,PCIE_CTRL,"PCIe fabric link layer fatal error, system isolation","PCIE_CTRL PCIe fabric link layer fatal error, system isolation",-1
INFO,CLOCK_MANAGER,Clock frequency scaling to 1.5GHz successful,CLOCK_MANAGER Clock frequency scaling to 1.5GHz successful,0
WARNING,PCIE_CTRL,PCIE_CTRL resource allocation nearing limit (88% utilized).,PCIE_CTRL PCIE_CTRL resource allocation nearing limit (88% utilized).,6
ERROR,CACHE_CTRL,"Cache tag parity error detected, data invalid","CACHE_CTRL Cache tag parity error detected, data invalid",1
WARNING,DDR_CTRL,Self-refresh exit latency high,DDR_CTRL Self-refresh exit latency high,1
ERROR,PCIE_CTRL,Endpoint reported 'Unsupported Request' TLP,PCIE_CTRL Endpoint reported 'Unsupported Request' TLP,6
ERROR,CACHE_CTRL,Cache coherency violation on shared line,CACHE_CTRL Cache coherency violation on shared line,1
WARNING,DDR_CTRL,DDR memory module temperature exceeding normal operating range,DDR_CTRL DDR memory module temperature exceeding normal operating range,1
CRITICAL,CACHE_CTRL,"Cache directory coherence protocol violation, potential data loss","CACHE_CTRL Cache directory coherence protocol violation, potential data loss",1
ERROR,DDR_CTRL,DDR DQS to DQ timing skew out of bounds,DDR_CTRL DDR DQS to DQ timing skew out of bounds,-1
INFO,DMA_ENGINE,DMA transfer of 512 bytes started on channel 24,DMA_ENGINE DMA transfer of 512 bytes started on channel 24,3
INFO,CLOCK_MANAGER,Clock distribution network integrity check passed,CLOCK_MANAGER Clock distribution network integrity check passed,0
INFO,INTERRUPT_CTRL,Interrupt handler for IRQ_TIMER completed,INTERRUPT_CTRL Interrupt handler for IRQ_TIMER completed,1
INFO,AXI_CTRL,AXI slave at address 0x1000 responded,AXI_CTRL AXI slave at address 0x1000 responded,2
ERROR,INTERRUPT_CTRL,Interrupt service routine timeout,INTERRUPT_CTRL Interrupt service routine timeout,1
INFO,DMA_ENGINE,Debug status collected for DMA_ENGINE.,DMA_ENGINE Debug status collected for DMA_ENGINE.,3
CRITICAL,MEM_CTRL,Memory controller power cycle required,MEM_CTRL Memory controller power cycle required,1
CRITICAL,FIFO_BUF,FIFO internal pointer logic stuck,FIFO_BUF FIFO internal pointer logic stuck,5
INFO,POWER_CTRL,Low power mode entry sequence initiated.,POWER_CTRL Low power mode entry sequence initiated.,4
INFO,FIFO_BUF,"FIFO read operation completed successfully, occupancy decreased","FIFO_BUF FIFO read operation completed successfully, occupancy decreased",5
CRITICAL,AXI_CTRL,"AXI_CTRL: Catastrophic bus contention, requiring system reset. (drive conflict on bus)","AXI_CTRL AXI_CTRL: Catastrophic bus contention, requiring system reset. (drive conflict on bus)",2
ERROR,POWER_CTRL,"Power gate logic error, state machine fault.","POWER_CTRL Power gate logic error, state machine fault.",4
ERROR,AXI_CTRL,AXI write response mismatch detected for ID 0x9,AXI_CTRL AXI write response mismatch detected for ID 0x9,2
CRITICAL,INTERRUPT_CTRL,Interrupt controller fatal internal bus error,INTERRUPT_CTRL Interrupt controller fatal internal bus error,1
CRITICAL,POWER_CTRL,System thermal shutdown initiated due to critical temperature,POWER_CTRL System thermal shutdown initiated due to critical temperature,4
ERROR,DMA_ENGINE,"DMA channel arbitration failure detected, bus contention.","DMA_ENGINE DMA channel arbitration failure detected, bus contention.",3
WARNING,INTERRUPT_CTRL,Interrupt handler latency exceeding benchmark,INTERRUPT_CTRL Interrupt handler latency exceeding benchmark,1
ERROR,INTERRUPT_CTRL,Interrupt controller state machine entered an unrecoverable state,INTERRUPT_CTRL Interrupt controller state machine entered an unrecoverable state,1
CRITICAL,POWER_CTRL,Power rail short circuit detected,POWER_CTRL Power rail short circuit detected,-1
INFO,INTERRUPT_CTRL,Interrupt controller in lowest power state,INTERRUPT_CTRL Interrupt controller in lowest power state,-1
INFO,CLOCK_MANAGER,Clock gate X enabled.,CLOCK_MANAGER Clock gate X enabled.,0
WARNING,POWER_CTRL,"Power consumption exceeding expected idle levels (idle 1W, actual 2W)","POWER_CTRL Power consumption exceeding expected idle levels (idle 1W, actual 2W)",4
WARNING,CACHE_CTRL,Cache tag array parity error corrected,CACHE_CTRL Cache tag array parity error corrected,1
WARNING,CLOCK_MANAGER,Clock domain crossing path delay marginal,CLOCK_MANAGER Clock domain crossing path delay marginal,0
WARNING,DMA_ENGINE,DMA status register access failed,DMA_ENGINE DMA status register access failed,3
INFO,CACHE_CTRL,Cache line writeback completed for address 0xd653f5f3.,CACHE_CTRL Cache line writeback completed for address 0xd653f5f3.,1
INFO,INTERRUPT_CTRL,ISR entered for device 0x1A,INTERRUPT_CTRL ISR entered for device 0x1A,-1
ERROR,INTERRUPT_CTRL,"Interrupt vector mismatch, ISR for ID 10 points to invalid address","INTERRUPT_CTRL Interrupt vector mismatch, ISR for ID 10 points to invalid address",1
INFO,AXI_CTRL,AXI read transaction completed with full burst,AXI_CTRL AXI read transaction completed with full burst,2
ERROR,PCIE_CTRL,PCIe lane synchronization lost on lane 0,PCIE_CTRL PCIe lane synchronization lost on lane 0,6
ERROR,FIFO_BUF,FIFO reset sequence detected unexpected behavior,FIFO_BUF FIFO reset sequence detected unexpected behavior,5
INFO,MEM_CTRL,Memory bank configured,MEM_CTRL Memory bank configured,1
INFO,PCIE_CTRL,PCIe endpoint BAR configuration complete,PCIE_CTRL PCIe endpoint BAR configuration complete,6
INFO,MEM_CTRL,Memory ECC scrubbing cycle initiated,MEM_CTRL Memory ECC scrubbing cycle initiated,1
INFO,FIFO_BUF,FIFO_ETH_RX buffer 50% full,FIFO_BUF FIFO_ETH_RX buffer 50% full,5
INFO,MEM_CTRL,Memory read data integrity check passed,MEM_CTRL Memory read data integrity check passed,1
WARNING,CACHE_CTRL,Cache way X replacement policy under stress,CACHE_CTRL Cache way X replacement policy under stress,1
INFO,FIFO_BUF,FIFO depth configured to 1024 entries,FIFO_BUF FIFO depth configured to 1024 entries,5
ERROR,CACHE_CTRL,Cache invalidation broadcast failure,CACHE_CTRL Cache invalidation broadcast failure,1
ERROR,CLOCK_MANAGER,Input clock signal lost briefly,CLOCK_MANAGER Input clock signal lost briefly,0
INFO,PCIE_CTRL,PCIe hot-plug successfully detected and initialized,PCIE_CTRL PCIe hot-plug successfully detected and initialized,6
INFO,DMA_ENGINE,Interrupt mask updated in DMA_ENGINE.,DMA_ENGINE Interrupt mask updated in DMA_ENGINE.,3
ERROR,DDR_CTRL,DDR command bus contention detected,DDR_CTRL DDR command bus contention detected,1
CRITICAL,PCIE_CTRL,"PCIe lane 3 synchronization lost, unrecoverable link degradation.","PCIE_CTRL PCIe lane 3 synchronization lost, unrecoverable link degradation.",6
INFO,PCIE_CTRL,Link width negotiated to x16,PCIE_CTRL Link width negotiated to x16,6
ERROR,AXI_CTRL,AXI master detected unexpected RRESP value,AXI_CTRL AXI master detected unexpected RRESP value,2
ERROR,AXI_CTRL,AXI read burst alignment violation detected.,AXI_CTRL AXI read burst alignment violation detected.,2
INFO,CACHE_CTRL,Cache coherence unit idle,CACHE_CTRL Cache coherence unit idle,1
CRITICAL,POWER_CTRL,Over-current protection trip detected.,POWER_CTRL Over-current protection trip detected.,4
CRITICAL,CLOCK_MANAGER,Clock generation hardware fault,CLOCK_MANAGER Clock generation hardware fault,0
CRITICAL,PCIE_CTRL,PCIe physical layer link re-establishment failed after multiple attempts,PCIE_CTRL PCIe physical layer link re-establishment failed after multiple attempts,6
INFO,AXI_CTRL,AXI interconnect configured,AXI_CTRL AXI interconnect configured,2
WARNING,CACHE_CTRL,Cache prefetch buffer nearing capacity,CACHE_CTRL Cache prefetch buffer nearing capacity,1
WARNING,DMA_ENGINE,DMA descriptor queue depth at 80% capacity,DMA_ENGINE DMA descriptor queue depth at 80% capacity,3
WARNING,AXI_CTRL,AXI handshake delay approaching threshold (137 cycles).,AXI_CTRL AXI handshake delay approaching threshold (137 cycles).,2
ERROR,AXI_CTRL,"AXI write response mismatch, expected OKAY but got DECERR","AXI_CTRL AXI write response mismatch, expected OKAY but got DECERR",2
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal state machine hung,INTERRUPT_CTRL Interrupt controller internal state machine hung,1
ERROR,DMA_ENGINE,DMA engine internal state machine error at state 0xAB.,DMA_ENGINE DMA engine internal state machine error at state 0xAB.,3
INFO,DMA_ENGINE,DMA controller reset asserted,DMA_ENGINE DMA controller reset asserted,3
ERROR,DMA_ENGINE,DMA access to protected region,DMA_ENGINE DMA access to protected region,3
WARNING,FIFO_BUF,FIFO latency spikes detected during burst writes,FIFO_BUF FIFO latency spikes detected during burst writes,5
WARNING,FIFO_BUF,"FIFO nearly empty, read potentially stalled","FIFO_BUF FIFO nearly empty, read potentially stalled",5
WARNING,POWER_CTRL,Core rail voltage slightly under nominal,POWER_CTRL Core rail voltage slightly under nominal,4
WARNING,CACHE_CTRL,Cache eviction queue nearing capacity,CACHE_CTRL Cache eviction queue nearing capacity,1
ERROR,AXI_CTRL,AXI read data channel RLAST asserted incorrectly,AXI_CTRL AXI read data channel RLAST asserted incorrectly,2
ERROR,PCIE_CTRL,PCIe hot-plug event detected with invalid configuration,PCIE_CTRL PCIe hot-plug event detected with invalid configuration,6
INFO,CACHE_CTRL,Cache flushed successfully.,CACHE_CTRL Cache flushed successfully.,1
ERROR,MEM_CTRL,Memory controller queue full for writes,MEM_CTRL Memory controller queue full for writes,1
INFO,MEM_CTRL,Memory controller statistics reset,MEM_CTRL Memory controller statistics reset,1
INFO,CACHE_CTRL,Cache hit rate optimized,CACHE_CTRL Cache hit rate optimized,1
ERROR,CLOCK_MANAGER,Clock domain crossing synchronizer reset error,CLOCK_MANAGER Clock domain crossing synchronizer reset error,0
ERROR,CACHE_CTRL,Cache snoop response timeout detected for remote request,CACHE_CTRL Cache snoop response timeout detected for remote request,1
ERROR,CACHE_CTRL,Cache controller FSM entered invalid state 0x5,CACHE_CTRL Cache controller FSM entered invalid state 0x5,1
WARNING,MEM_CTRL,Memory write data parity error predicted,MEM_CTRL Memory write data parity error predicted,1
ERROR,POWER_CTRL,Thermal sensor over-temperature alert,POWER_CTRL Thermal sensor over-temperature alert,4
INFO,DMA_ENGINE,DMA channel 3 configured for peripheral-to-memory,DMA_ENGINE DMA channel 3 configured for peripheral-to-memory,3
WARNING,INTERRUPT_CTRL,Interrupt enable register read as unexpected value,INTERRUPT_CTRL Interrupt enable register read as unexpected value,1
WARNING,AXI_CTRL,AXI write data channel backpressure rising,AXI_CTRL AXI write data channel backpressure rising,2
WARNING,PCIE_CTRL,PCIe link error rate (LER) increasing,PCIE_CTRL PCIe link error rate (LER) increasing,6
INFO,AXI_CTRL,AXI transaction completed for ID 0x3,AXI_CTRL AXI transaction completed for ID 0x3,2
CRITICAL,FIFO_BUF,Unrecoverable FIFO corruption detected.,FIFO_BUF Unrecoverable FIFO corruption detected.,5
INFO,DDR_CTRL,DDR power-up sequence initiated.,DDR_CTRL DDR power-up sequence initiated.,1
CRITICAL,CACHE_CTRL,Cache controller entered an invalid state during snoop transaction.,CACHE_CTRL Cache controller entered an invalid state during snoop transaction.,1
INFO,DDR_CTRL,DDR memory interface calibrated,DDR_CTRL DDR memory interface calibrated,1
ERROR,MEM_CTRL,Memory address alignment fault during access to 0x4864A,MEM_CTRL Memory address alignment fault during access to 0x4864A,1
CRITICAL,MEM_CTRL,Memory controller state machine stuck in 'busy',MEM_CTRL Memory controller state machine stuck in 'busy',1
ERROR,DMA_ENGINE,DMA descriptor memory access timeout,DMA_ENGINE DMA descriptor memory access timeout,3
WARNING,POWER_CTRL,Voltage regulator output ripple exceeding tolerance,POWER_CTRL Voltage regulator output ripple exceeding tolerance,4
INFO,CLOCK_MANAGER,Clock gating for idle module AXI_CTRL applied,CLOCK_MANAGER Clock gating for idle module AXI_CTRL applied,0
WARNING,DMA_ENGINE,DMA channel 0 transaction re-submitted due to error,DMA_ENGINE DMA channel 0 transaction re-submitted due to error,3
INFO,INTERRUPT_CTRL,Interrupt mask updated.,INTERRUPT_CTRL Interrupt mask updated.,1
WARNING,CACHE_CTRL,Cache access stalls due to contention,CACHE_CTRL Cache access stalls due to contention,1
INFO,POWER_CTRL,Power management unit enters low power mode,POWER_CTRL Power management unit enters low power mode,4
WARNING,AXI_CTRL,AXI write channel backpressure asserted for extended period,AXI_CTRL AXI write channel backpressure asserted for extended period,2
ERROR,PCIE_CTRL,PCIe upstream port detected fatal error,PCIE_CTRL PCIe upstream port detected fatal error,6
ERROR,PCIE_CTRL,PCIe root complex transaction layer protocol violation,PCIE_CTRL PCIe root complex transaction layer protocol violation,6
WARNING,POWER_CTRL,Voltage regulator response time observed to be slow,POWER_CTRL Voltage regulator response time observed to be slow,4
ERROR,INTERRUPT_CTRL,"Multiple interrupts asserted simultaneously with same priority (IRQs 0x0, 0x1)","INTERRUPT_CTRL Multiple interrupts asserted simultaneously with same priority (IRQs 0x0, 0x1)",1
ERROR,POWER_CTRL,"Brownout detected on 1.2V rail, potential data loss","POWER_CTRL Brownout detected on 1.2V rail, potential data loss",4
CRITICAL,DMA_ENGINE,"DMA engine internal state machine stuck, requiring system reset","DMA_ENGINE DMA engine internal state machine stuck, requiring system reset",3
WARNING,AXI_CTRL,AXI master request queue depth increasing,AXI_CTRL AXI master request queue depth increasing,2
CRITICAL,POWER_CTRL,"Power supply unit instability detected, immediate shutdown advised","POWER_CTRL Power supply unit instability detected, immediate shutdown advised",4
WARNING,MEM_CTRL,"Memory refresh interval approaching limit, refresh pending","MEM_CTRL Memory refresh interval approaching limit, refresh pending",1
WARNING,MEM_CTRL,Memory controller refresh interval approaching boundary,MEM_CTRL Memory controller refresh interval approaching boundary,1
CRITICAL,FIFO_BUF,FIFO internal state machine entered invalid state,FIFO_BUF FIFO internal state machine entered invalid state,5
WARNING,PCIE_CTRL,PCIe completion timeout threshold approaching,PCIE_CTRL PCIe completion timeout threshold approaching,6
INFO,PCIE_CTRL,PCIe device ID 0x10DE:0x1340 enumerated.,PCIE_CTRL PCIe device ID 0x10DE:0x1340 enumerated.,6
CRITICAL,POWER_CTRL,Voltage monitor circuit failure,POWER_CTRL Voltage monitor circuit failure,-1
ERROR,POWER_CTRL,Power-on reset de-assertion timing violation,POWER_CTRL Power-on reset de-assertion timing violation,4
INFO,DMA_ENGINE,DMA scatter-gather list processing completed,DMA_ENGINE DMA scatter-gather list processing completed,3
CRITICAL,POWER_CTRL,System reset asserted due to critical power supply failure.,POWER_CTRL System reset asserted due to critical power supply failure.,4
INFO,INTERRUPT_CTRL,Interrupt source unmasked,INTERRUPT_CTRL Interrupt source unmasked,1
WARNING,DMA_ENGINE,DMA scatter-gather list parsing error,DMA_ENGINE DMA scatter-gather list parsing error,3
WARNING,AXI_CTRL,AXI read address channel backpressure applied,AXI_CTRL AXI read address channel backpressure applied,2
CRITICAL,PCIE_CTRL,PCIe hot-reset assertion failed to propagate,PCIE_CTRL PCIe hot-reset assertion failed to propagate,6
WARNING,INTERRUPT_CTRL,Interrupt acknowledge signal observed without pending request,INTERRUPT_CTRL Interrupt acknowledge signal observed without pending request,1
WARNING,AXI_CTRL,AXI transaction backlog accumulating in interconnect,AXI_CTRL AXI transaction backlog accumulating in interconnect,-1
CRITICAL,PCIE_CTRL,PCIe lane synchronization lost during link retraining,PCIE_CTRL PCIe lane synchronization lost during link retraining,6
ERROR,AXI_CTRL,AXI address decode failure for address 0xFFFFFFFF,AXI_CTRL AXI address decode failure for address 0xFFFFFFFF,2
ERROR,CACHE_CTRL,Cache directory entry invalidation failure,CACHE_CTRL Cache directory entry invalidation failure,1
WARNING,DDR_CTRL,DDR timing parameters at boundary conditions,DDR_CTRL DDR timing parameters at boundary conditions,1
ERROR,AXI_CTRL,AXI transaction timeout detected (ID=11).,AXI_CTRL AXI transaction timeout detected (ID=11).,2
INFO,AXI_CTRL,AXI interconnect configuration applied,AXI_CTRL AXI interconnect configuration applied,2
ERROR,DDR_CTRL,DDR training sequence failed to lock DQ-DQS phase,DDR_CTRL DDR training sequence failed to lock DQ-DQS phase,1
ERROR,CACHE_CTRL,Cache tag comparison logic error,CACHE_CTRL Cache tag comparison logic error,1
ERROR,DMA_ENGINE,Invalid DMA descriptor format encountered,DMA_ENGINE Invalid DMA descriptor format encountered,3
INFO,CACHE_CTRL,Cache prefetcher engaged for sequential access,CACHE_CTRL Cache prefetcher engaged for sequential access,1
WARNING,MEM_CTRL,Memory access latency high,MEM_CTRL Memory access latency high,1
CRITICAL,AXI_CTRL,"Global AXI bus matrix arbitration failure, system hung","AXI_CTRL Global AXI bus matrix arbitration failure, system hung",2
ERROR,CACHE_CTRL,"Data corruption in cache line 0x1234, integrity check failed","CACHE_CTRL Data corruption in cache line 0x1234, integrity check failed",1
CRITICAL,DDR_CTRL,DDR memory read/write path corrupted,DDR_CTRL DDR memory read/write path corrupted,1
ERROR,MEM_CTRL,Memory ECC correction threshold exceeded,MEM_CTRL Memory ECC correction threshold exceeded,1
WARNING,AXI_CTRL,AXI ID tags nearing saturation on interconnect,AXI_CTRL AXI ID tags nearing saturation on interconnect,-1
INFO,POWER_CTRL,Voltage rail 1.8V stable,POWER_CTRL Voltage rail 1.8V stable,4
INFO,DDR_CTRL,DDR memory clock frequency locked,DDR_CTRL DDR memory clock frequency locked,1
WARNING,FIFO_BUF,"FIFO watermark high, approaching overflow","FIFO_BUF FIFO watermark high, approaching overflow",5
WARNING,AXI_CTRL,AXI ID signal collision detected,AXI_CTRL AXI ID signal collision detected,2
CRITICAL,DDR_CTRL,DDR memory subsystem unresponsive,DDR_CTRL DDR memory subsystem unresponsive,1
INFO,INTERRUPT_CTRL,Interrupt service routine for vector Y entered,INTERRUPT_CTRL Interrupt service routine for vector Y entered,1
INFO,AXI_CTRL,AXI write transaction completed with EXOKAY,AXI_CTRL AXI write transaction completed with EXOKAY,2
WARNING,PCIE_CTRL,PCIe retransmission buffer utilization high (78%).,PCIE_CTRL PCIe retransmission buffer utilization high (78%).,6
ERROR,AXI_CTRL,AXI transaction timeout detected (ID=10).,AXI_CTRL AXI transaction timeout detected (ID=10).,2
ERROR,FIFO_BUF,FIFO input data corrupted during write,FIFO_BUF FIFO input data corrupted during write,5
INFO,MEM_CTRL,ECC parity mismatch detected in memory bank,MEM_CTRL ECC parity mismatch detected in memory bank,1
ERROR,DMA_ENGINE,DMA read channel data corruption,DMA_ENGINE DMA read channel data corruption,3
INFO,POWER_CTRL,Firmware successfully loaded into POWER_CTRL control registers.,POWER_CTRL Firmware successfully loaded into POWER_CTRL control registers.,-1
WARNING,PCIE_CTRL,Root complex reported unexpected completion timeout,PCIE_CTRL Root complex reported unexpected completion timeout,6
INFO,AXI_CTRL,AXI burst write of 32 bytes to 0x1000 completed,AXI_CTRL AXI burst write of 32 bytes to 0x1000 completed,2
WARNING,DDR_CTRL,DDR power-down entry timing violation,DDR_CTRL DDR power-down entry timing violation,1
ERROR,CLOCK_MANAGER,Clock network buffer output glitch,CLOCK_MANAGER Clock network buffer output glitch,0
WARNING,AXI_CTRL,AXI read transaction retry limit reached,AXI_CTRL AXI read transaction retry limit reached,2
CRITICAL,CLOCK_MANAGER,"Clock MUX selection error, invalid clock routed","CLOCK_MANAGER Clock MUX selection error, invalid clock routed",0
INFO,FIFO_BUF,Read pointer incremented,FIFO_BUF Read pointer incremented,5
ERROR,CACHE_CTRL,Cache coherence invalidate operation failed for address 0xDEAD0000,CACHE_CTRL Cache coherence invalidate operation failed for address 0xDEAD0000,1
CRITICAL,POWER_CTRL,"Voltage regulator failure on VDD_MEM, memory corruption imminent.","POWER_CTRL Voltage regulator failure on VDD_MEM, memory corruption imminent.",4
INFO,FIFO_BUF,FIFO almost empty status asserted,FIFO_BUF FIFO almost empty status asserted,5
INFO,FIFO_BUF,FIFO status register cleared,FIFO_BUF FIFO status register cleared,5
INFO,CLOCK_MANAGER,Main system clock configuration updated successfully,CLOCK_MANAGER Main system clock configuration updated successfully,0
WARNING,CLOCK_MANAGER,Jitter on output clock 'clk_out_0' increased,CLOCK_MANAGER Jitter on output clock 'clk_out_0' increased,0
INFO,FIFO_BUF,FIFO_ID 0x1A reset sequence initiated,FIFO_BUF FIFO_ID 0x1A reset sequence initiated,5
ERROR,AXI_CTRL,AXI read data width mismatch,AXI_CTRL AXI read data width mismatch,2
WARNING,CACHE_CTRL,Cache eviction policy causing thrashing,CACHE_CTRL Cache eviction policy causing thrashing,1
WARNING,POWER_CTRL,Core voltage droop detected under heavy load,POWER_CTRL Core voltage droop detected under heavy load,4
INFO,CLOCK_MANAGER,Clock source selected: internal RC oscillator.,CLOCK_MANAGER Clock source selected: internal RC oscillator.,0
ERROR,MEM_CTRL,Data bus parity error detected on memory read.,MEM_CTRL Data bus parity error detected on memory read.,1
WARNING,DDR_CTRL,DDR read data integrity check threshold exceeded,DDR_CTRL DDR read data integrity check threshold exceeded,1
CRITICAL,MEM_CTRL,Memory data bus stuck-at fault detected,MEM_CTRL Memory data bus stuck-at fault detected,1
CRITICAL,FIFO_BUF,FIFO internal read/write pointer out of bounds,FIFO_BUF FIFO internal read/write pointer out of bounds,5
WARNING,POWER_CTRL,Power domain transition delay detected for SYS_PD,POWER_CTRL Power domain transition delay detected for SYS_PD,4
INFO,FIFO_BUF,"FIFO write operation successful, X entries free","FIFO_BUF FIFO write operation successful, X entries free",5
INFO,POWER_CTRL,Power domain VDD_SENSORS enabled.,POWER_CTRL Power domain VDD_SENSORS enabled.,-1
CRITICAL,FIFO_BUF,Critical FIFO data integrity error detected.,FIFO_BUF Critical FIFO data integrity error detected.,5
ERROR,CLOCK_MANAGER,"Input clock source unstable, exceeding phase noise limits.","CLOCK_MANAGER Input clock source unstable, exceeding phase noise limits.",0
ERROR,MEM_CTRL,Write after read hazard detected by memory controller at address 0xABCD1234,MEM_CTRL Write after read hazard detected by memory controller at address 0xABCD1234,1
INFO,POWER_CTRL,Voltage regulator configured for 1.2V,POWER_CTRL Voltage regulator configured for 1.2V,4
INFO,CLOCK_MANAGER,Clock Gating unit enabled for module Z.,CLOCK_MANAGER Clock Gating unit enabled for module Z.,0
ERROR,POWER_CTRL,POWER_CTRL: state machine fault - control logic sequence error detected.,POWER_CTRL POWER_CTRL: state machine fault - control logic sequence error detected.,4
ERROR,CACHE_CTRL,Cache line locked by an invalid agent,CACHE_CTRL Cache line locked by an invalid agent,1
CRITICAL,CACHE_CTRL,Cache way 7 data parity failure,CACHE_CTRL Cache way 7 data parity failure,1
CRITICAL,POWER_CTRL,VCORE power-on reset sequence failed,POWER_CTRL VCORE power-on reset sequence failed,4
WARNING,PCIE_CTRL,PCIe link bandwidth utilization high.,PCIE_CTRL PCIe link bandwidth utilization high.,6
ERROR,MEM_CTRL,Memory controller detected a critical data path stall,MEM_CTRL Memory controller detected a critical data path stall,1
INFO,DMA_ENGINE,DMA transfer queued on channel 7,DMA_ENGINE DMA transfer queued on channel 7,3
INFO,FIFO_BUF,FIFO_STATUS empty,FIFO_BUF FIFO_STATUS empty,5
ERROR,PCIE_CTRL,"PCIe Posted Request queue reached maximum capacity, dropping TLPs","PCIE_CTRL PCIe Posted Request queue reached maximum capacity, dropping TLPs",6
CRITICAL,POWER_CTRL,Uncontrolled system shutdown detected due to power failure,POWER_CTRL Uncontrolled system shutdown detected due to power failure,4
WARNING,CACHE_CTRL,Cache write buffer flush delayed,CACHE_CTRL Cache write buffer flush delayed,1
CRITICAL,AXI_CTRL,AXI bus contention deadlock detected,AXI_CTRL AXI bus contention deadlock detected,2
INFO,FIFO_BUF,FIFO flush complete,FIFO_BUF FIFO flush complete,5
INFO,INTERRUPT_CTRL,Interrupt source registered to handler,INTERRUPT_CTRL Interrupt source registered to handler,1
INFO,DDR_CTRL,DDR memory temperature within nominal range,DDR_CTRL DDR memory temperature within nominal range,1
ERROR,MEM_CTRL,Invalid memory access attempt to protected region 0x27993,MEM_CTRL Invalid memory access attempt to protected region 0x27993,1
WARNING,CACHE_CTRL,Cache eviction queue approaching full,CACHE_CTRL Cache eviction queue approaching full,1
WARNING,FIFO_BUF,FIFO write pointer crossing read pointer without wrap,FIFO_BUF FIFO write pointer crossing read pointer without wrap,5
ERROR,POWER_CTRL,Brown-out event detected,POWER_CTRL Brown-out event detected,4
INFO,POWER_CTRL,Power sequencing complete,POWER_CTRL Power sequencing complete,4
WARNING,DDR_CTRL,DDR controller temperature exceeding threshold.,DDR_CTRL DDR controller temperature exceeding threshold.,1
ERROR,DDR_CTRL,DDR write timing parameters not met,DDR_CTRL DDR write timing parameters not met,1
WARNING,DDR_CTRL,DDR read eye margin below safe limit for rank 0,DDR_CTRL DDR read eye margin below safe limit for rank 0,1
INFO,FIFO_BUF,FIFO almost_empty asserted,FIFO_BUF FIFO almost_empty asserted,5
WARNING,AXI_CTRL,AXI write data transfer latency variance observed,AXI_CTRL AXI write data transfer latency variance observed,2
INFO,MEM_CTRL,ECC correction feature enabled.,MEM_CTRL ECC correction feature enabled.,1
ERROR,AXI_CTRL,AXI address decoding logic output an unmapped address,AXI_CTRL AXI address decoding logic output an unmapped address,2
INFO,CACHE_CTRL,Data prefetch initiated,CACHE_CTRL Data prefetch initiated,1
INFO,CACHE_CTRL,Cache line replaced by new data,CACHE_CTRL Cache line replaced by new data,1
ERROR,PCIE_CTRL,PCIe flow control credit timeout,PCIE_CTRL PCIe flow control credit timeout,6
ERROR,MEM_CTRL,Memory controller command queue deadlock,MEM_CTRL Memory controller command queue deadlock,1
INFO,MEM_CTRL,Memory refresh cycle performed successfully,MEM_CTRL Memory refresh cycle performed successfully,1
INFO,CLOCK_MANAGER,Clock domain power-gating enabled,CLOCK_MANAGER Clock domain power-gating enabled,-1
ERROR,AXI_CTRL,"AXI_CTRL encountered an unexpected protocol mismatch event (unrecognized command). (Master ID: 7, AXI ID: 9)","AXI_CTRL AXI_CTRL encountered an unexpected protocol mismatch event (unrecognized command). (Master ID: 7, AXI ID: 9)",2
INFO,AXI_CTRL,AXI master granted bus ownership,AXI_CTRL AXI master granted bus ownership,2
WARNING,DMA_ENGINE,DMA transfer completion interrupted,DMA_ENGINE DMA transfer completion interrupted,3
ERROR,MEM_CTRL,Memory address range violation,MEM_CTRL Memory address range violation,1
ERROR,PCIE_CTRL,PCIe device function level reset (FLR) failed,PCIE_CTRL PCIe device function level reset (FLR) failed,6
ERROR,MEM_CTRL,Memory write data mismatch detected after ECC,MEM_CTRL Memory write data mismatch detected after ECC,1
ERROR,MEM_CTRL,Memory write data parity error from AXI master,MEM_CTRL Memory write data parity error from AXI master,1
WARNING,CLOCK_MANAGER,Clock domain crossing path showing increased setup time slack,CLOCK_MANAGER Clock domain crossing path showing increased setup time slack,0
ERROR,AXI_CTRL,"AXI outstanding transaction count exceeded, bus stalled.","AXI_CTRL AXI outstanding transaction count exceeded, bus stalled.",2
INFO,INTERRUPT_CTRL,Interrupt service routine started,INTERRUPT_CTRL Interrupt service routine started,1
ERROR,INTERRUPT_CTRL,Interrupt controller unable to clear pending IRQ,INTERRUPT_CTRL Interrupt controller unable to clear pending IRQ,1
INFO,INTERRUPT_CTRL,Interrupt enable register updated,INTERRUPT_CTRL Interrupt enable register updated,1
ERROR,DDR_CTRL,DDR command timing violation detected,DDR_CTRL DDR command timing violation detected,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller deadlock,INTERRUPT_CTRL Interrupt controller deadlock,1
INFO,MEM_CTRL,Memory access latency metrics collected,MEM_CTRL Memory access latency metrics collected,1
INFO,CACHE_CTRL,Cache write-back buffer flushed,CACHE_CTRL Cache write-back buffer flushed,1
ERROR,PCIE_CTRL,PCIe hot-plug controller reported an unexpected device removal,PCIE_CTRL PCIe hot-plug controller reported an unexpected device removal,6
ERROR,POWER_CTRL,Power-on reset (POR) de-assertion delayed,POWER_CTRL Power-on reset (POR) de-assertion delayed,4
INFO,CACHE_CTRL,Tag updated,CACHE_CTRL Tag updated,1
WARNING,DDR_CTRL,DDR training sequence for DQS failed to converge.,DDR_CTRL DDR training sequence for DQS failed to converge.,1
INFO,MEM_CTRL,Memory data bus width detected: 64-bit,MEM_CTRL Memory data bus width detected: 64-bit,1
INFO,MEM_CTRL,Memory access granted,MEM_CTRL Memory access granted,1
INFO,INTERRUPT_CTRL,Interrupt coalescing feature enabled,INTERRUPT_CTRL Interrupt coalescing feature enabled,1
ERROR,CACHE_CTRL,Cache coherency protocol violation on shared data,CACHE_CTRL Cache coherency protocol violation on shared data,1
INFO,MEM_CTRL,Memory controller entered low-power idle state,MEM_CTRL Memory controller entered low-power idle state,1
INFO,FIFO_BUF,FIFO data available for reading,FIFO_BUF FIFO data available for reading,5
INFO,POWER_CTRL,Core voltage rail configured to nominal,POWER_CTRL Core voltage rail configured to nominal,4
INFO,PCIE_CTRL,PCIe link established at Gen3 x8,PCIE_CTRL PCIe link established at Gen3 x8,6
CRITICAL,DDR_CTRL,"DDR controller entered critical error state, system memory unavailable","DDR_CTRL DDR controller entered critical error state, system memory unavailable",1
INFO,POWER_CTRL,Power rail self-test initiated,POWER_CTRL Power rail self-test initiated,4
ERROR,MEM_CTRL,Memory address out of bounds access,MEM_CTRL Memory address out of bounds access,1
INFO,CACHE_CTRL,Cache hit detected,CACHE_CTRL Cache hit detected,1
INFO,POWER_CTRL,Power state transition to active initiated,POWER_CTRL Power state transition to active initiated,4
WARNING,CLOCK_MANAGER,Clock jitter variance high,CLOCK_MANAGER Clock jitter variance high,0
WARNING,POWER_CTRL,Temperature sensor nearing high threshold,POWER_CTRL Temperature sensor nearing high threshold,4
INFO,CACHE_CTRL,Cache line invalidation requested by snooping master,CACHE_CTRL Cache line invalidation requested by snooping master,1
INFO,FIFO_BUF,FIFO data available indication asserted,FIFO_BUF FIFO data available indication asserted,5
ERROR,CLOCK_MANAGER,Clock domain crossing failure detected (metastability),CLOCK_MANAGER Clock domain crossing failure detected (metastability),0
WARNING,CACHE_CTRL,Cache write-through buffer nearing saturation,CACHE_CTRL Cache write-through buffer nearing saturation,1
INFO,DMA_ENGINE,DMA channel CH0 configured for burst transfer.,DMA_ENGINE DMA channel CH0 configured for burst transfer.,3
CRITICAL,CLOCK_MANAGER,System clock input signal lost,CLOCK_MANAGER System clock input signal lost,0
ERROR,DMA_ENGINE,DMA channel 4 transfer size mismatch,DMA_ENGINE DMA channel 4 transfer size mismatch,3
CRITICAL,POWER_CTRL,Voltage regulator VDD_RAM not responding to control,POWER_CTRL Voltage regulator VDD_RAM not responding to control,4
ERROR,DDR_CTRL,DDR refresh operation failed to complete,DDR_CTRL DDR refresh operation failed to complete,1
CRITICAL,CLOCK_MANAGER,Clock generation PLL critical failure,CLOCK_MANAGER Clock generation PLL critical failure,0
WARNING,CLOCK_MANAGER,Clock jitter exceeding specification (150ps observed),CLOCK_MANAGER Clock jitter exceeding specification (150ps observed),0
ERROR,FIFO_BUF,FIFO full status not asserted when full,FIFO_BUF FIFO full status not asserted when full,5
ERROR,DDR_CTRL,DDR command queue arbitration starvation detected,DDR_CTRL DDR command queue arbitration starvation detected,1
WARNING,DMA_ENGINE,Backpressure asserted by DMA_ENGINE for extended period.,DMA_ENGINE Backpressure asserted by DMA_ENGINE for extended period.,3
WARNING,CACHE_CTRL,Cache dirty bit not set for modified line,CACHE_CTRL Cache dirty bit not set for modified line,1
CRITICAL,POWER_CTRL,"Power rail instability detected on critical core voltage, system shutdown.","POWER_CTRL Power rail instability detected on critical core voltage, system shutdown.",4
INFO,CLOCK_MANAGER,Clock enable signal propagated correctly,CLOCK_MANAGER Clock enable signal propagated correctly,0
INFO,CLOCK_MANAGER,Clock gating enabled for idle units,CLOCK_MANAGER Clock gating enabled for idle units,0
CRITICAL,CACHE_CTRL,Cache controller internal state machine deadlock,CACHE_CTRL Cache controller internal state machine deadlock,1
ERROR,FIFO_BUF,"FIFO underflow detected, read from empty FIFO. (buffer underflow)","FIFO_BUF FIFO underflow detected, read from empty FIFO. (buffer underflow)",5
WARNING,POWER_CTRL,Brownout detection circuit triggered,POWER_CTRL Brownout detection circuit triggered,4
WARNING,PCIE_CTRL,PCIe upstream receive buffer nearing capacity.,PCIE_CTRL PCIe upstream receive buffer nearing capacity.,6
WARNING,AXI_CTRL,AXI write backpressure detected,AXI_CTRL AXI write backpressure detected,2
WARNING,PCIE_CTRL,PCIe link error rate exceeding threshold for retries,PCIE_CTRL PCIe link error rate exceeding threshold for retries,6
WARNING,FIFO_BUF,FIFO nearing full capacity (96%).,FIFO_BUF FIFO nearing full capacity (96%).,5
ERROR,MEM_CTRL,Memory controller detected an invalid state transition,MEM_CTRL Memory controller detected an invalid state transition,1
INFO,FIFO_BUF,FIFO 'status_queue' peek operation successful,FIFO_BUF FIFO 'status_queue' peek operation successful,5
INFO,FIFO_BUF,Read operation completed with valid data.,FIFO_BUF Read operation completed with valid data.,5
INFO,MEM_CTRL,Memory page marked as accessible,MEM_CTRL Memory page marked as accessible,1
CRITICAL,DDR_CTRL,Double-bit ECC error on critical DDR memory region.,DDR_CTRL Double-bit ECC error on critical DDR memory region.,1
INFO,POWER_CTRL,Low power mode entry success,POWER_CTRL Low power mode entry success,4
CRITICAL,PCIE_CTRL,PCIe hot reset asserted due to fatal error,PCIE_CTRL PCIe hot reset asserted due to fatal error,6
WARNING,DDR_CTRL,DDR ECC scrub rate below target,DDR_CTRL DDR ECC scrub rate below target,-1
INFO,CACHE_CTRL,L1 instruction cache flushed,CACHE_CTRL L1 instruction cache flushed,1
ERROR,PCIE_CTRL,PCIe upstream bridge state machine fault.,PCIE_CTRL PCIe upstream bridge state machine fault.,6
WARNING,AXI_CTRL,AXI response channel latency increased,AXI_CTRL AXI response channel latency increased,2
ERROR,POWER_CTRL,Power rail X voltage droop exceeded tolerance,POWER_CTRL Power rail X voltage droop exceeded tolerance,4
WARNING,CACHE_CTRL,Cache coherence snooping delay observed (20 cycles),CACHE_CTRL Cache coherence snooping delay observed (20 cycles),1
WARNING,POWER_CTRL,Thermal sensor reading approaching critical limit,POWER_CTRL Thermal sensor reading approaching critical limit,4
ERROR,PCIE_CTRL,PCIe ECRC error detected on received TLP.,PCIE_CTRL PCIe ECRC error detected on received TLP.,6
WARNING,CLOCK_MANAGER,Clock buffer output skew detected,CLOCK_MANAGER Clock buffer output skew detected,0
INFO,CACHE_CTRL,Cache line invalidate for address 0x1000 completed,CACHE_CTRL Cache line invalidate for address 0x1000 completed,1
INFO,CACHE_CTRL,Cache line '0x1234' evicted successfully,CACHE_CTRL Cache line '0x1234' evicted successfully,1
CRITICAL,CLOCK_MANAGER,Clock generation PLL lock lost for system clock.,CLOCK_MANAGER Clock generation PLL lock lost for system clock.,0
ERROR,INTERRUPT_CTRL,Interrupt controller registers corrupted,INTERRUPT_CTRL Interrupt controller registers corrupted,1
WARNING,CACHE_CTRL,Shared cache line contention observed,CACHE_CTRL Shared cache line contention observed,1
CRITICAL,AXI_CTRL,AXI interconnect asserted system-level deadlock,AXI_CTRL AXI interconnect asserted system-level deadlock,2
ERROR,POWER_CTRL,Voltage regulator output current limit exceeded,POWER_CTRL Voltage regulator output current limit exceeded,4
ERROR,PCIE_CTRL,PCIe lane synchronization lost.,PCIE_CTRL PCIe lane synchronization lost.,6
CRITICAL,FIFO_BUF,Critical FIFO data path failure,FIFO_BUF Critical FIFO data path failure,5
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for IRQ 4.,INTERRUPT_CTRL Interrupt dispatch completed for IRQ 4.,1
ERROR,POWER_CTRL,Power rail instability detected on VDD_MEM,POWER_CTRL Power rail instability detected on VDD_MEM,4
ERROR,MEM_CTRL,Memory protection violation for write operation,MEM_CTRL Memory protection violation for write operation,1
ERROR,DMA_ENGINE,"DMA descriptor fetch failed, internal FSM error.","DMA_ENGINE DMA descriptor fetch failed, internal FSM error.",3
ERROR,DDR_CTRL,Memory refresh command issued prematurely.,DDR_CTRL Memory refresh command issued prematurely.,1
WARNING,AXI_CTRL,AXI transaction to slave S3 received AXI_DECERR,AXI_CTRL AXI transaction to slave S3 received AXI_DECERR,2
ERROR,AXI_CTRL,AXI protocol violation: RREADY asserted without RVALID,AXI_CTRL AXI protocol violation: RREADY asserted without RVALID,2
INFO,PCIE_CTRL,PCIe configuration space read successful for device ID 0x1234,PCIE_CTRL PCIe configuration space read successful for device ID 0x1234,6
WARNING,DDR_CTRL,DDR command queue depth elevated,DDR_CTRL DDR command queue depth elevated,1
ERROR,DMA_ENGINE,"DMA configuration error detected, channel disabled","DMA_ENGINE DMA configuration error detected, channel disabled",3
WARNING,DDR_CTRL,DDR memory refresh rate not meeting minimum requirement,DDR_CTRL DDR memory refresh rate not meeting minimum requirement,1
INFO,POWER_CTRL,Power domain transition to 'active' state successful,POWER_CTRL Power domain transition to 'active' state successful,4
INFO,DMA_ENGINE,DMA configuration loaded,DMA_ENGINE DMA configuration loaded,3
INFO,PCIE_CTRL,PCIe bridge configuration successful,PCIE_CTRL PCIe bridge configuration successful,6
ERROR,PCIE_CTRL,PCIe lane synchronization lost on lane 3,PCIE_CTRL PCIe lane synchronization lost on lane 3,6
WARNING,FIFO_BUF,FIFO_EVENTS_LOG latency exceeding 50 cycles for consecutive reads.,FIFO_BUF FIFO_EVENTS_LOG latency exceeding 50 cycles for consecutive reads.,5
INFO,PCIE_CTRL,PCIe PME (Power Management Event) assertion detected,PCIE_CTRL PCIe PME (Power Management Event) assertion detected,6
ERROR,PCIE_CTRL,PCIe endpoint configuration space access error,PCIE_CTRL PCIe endpoint configuration space access error,6
ERROR,DMA_ENGINE,DMA transfer aborted due to bus error,DMA_ENGINE DMA transfer aborted due to bus error,3
CRITICAL,INTERRUPT_CTRL,Interrupt controller logic detected a functional deadlock.,INTERRUPT_CTRL Interrupt controller logic detected a functional deadlock.,1
CRITICAL,CACHE_CTRL,Cache data array parity error detected on read.,CACHE_CTRL Cache data array parity error detected on read.,1
INFO,CACHE_CTRL,Cache preload operation completed,CACHE_CTRL Cache preload operation completed,1
ERROR,DDR_CTRL,"DDR bank conflict detected, performance impact","DDR_CTRL DDR bank conflict detected, performance impact",1
CRITICAL,POWER_CTRL,Power rail instability detected on VCC_CORE,POWER_CTRL Power rail instability detected on VCC_CORE,4
WARNING,PCIE_CTRL,PCIe link error rate exceeding threshold.,PCIE_CTRL PCIe link error rate exceeding threshold.,6
ERROR,CACHE_CTRL,Cache Way Select logic error,CACHE_CTRL Cache Way Select logic error,1
ERROR,PCIE_CTRL,PCIe upstream receive buffer overflow,PCIE_CTRL PCIe upstream receive buffer overflow,6
INFO,DMA_ENGINE,DMA transfer completed successfully for block X,DMA_ENGINE DMA transfer completed successfully for block X,3
INFO,FIFO_BUF,"FIFO high watermark reached, no overflow","FIFO_BUF FIFO high watermark reached, no overflow",5
CRITICAL,CACHE_CTRL,"Cache directory tag array parity error, unrecoverable","CACHE_CTRL Cache directory tag array parity error, unrecoverable",1
WARNING,INTERRUPT_CTRL,Interrupt disable duration exceeding threshold,INTERRUPT_CTRL Interrupt disable duration exceeding threshold,1
CRITICAL,AXI_CTRL,AXI master 1 issued an invalid write command,AXI_CTRL AXI master 1 issued an invalid write command,2
WARNING,DDR_CTRL,DDR access latency exceeding typical range,DDR_CTRL DDR access latency exceeding typical range,1
CRITICAL,MEM_CTRL,Memory bank controller permanent fault,MEM_CTRL Memory bank controller permanent fault,1
INFO,MEM_CTRL,Memory BIST (Built-In Self-Test) completed without errors,MEM_CTRL Memory BIST (Built-In Self-Test) completed without errors,1
ERROR,DMA_ENGINE,DMA completion status not updated,DMA_ENGINE DMA completion status not updated,3
ERROR,CLOCK_MANAGER,Clock domain crossing FIFO overflow during data transfer.,CLOCK_MANAGER Clock domain crossing FIFO overflow during data transfer.,0
ERROR,FIFO_BUF,FIFO buffer corrupted during reset,FIFO_BUF FIFO buffer corrupted during reset,5
ERROR,MEM_CTRL,Memory address decoder output mismatch,MEM_CTRL Memory address decoder output mismatch,1
WARNING,DMA_ENGINE,DMA_ENGINE observed higher than expected transaction latency (TxID: 158).,DMA_ENGINE DMA_ENGINE observed higher than expected transaction latency (TxID: 158).,3
WARNING,INTERRUPT_CTRL,Interrupt queue approaching saturation,INTERRUPT_CTRL Interrupt queue approaching saturation,1
ERROR,AXI_CTRL,AXI write data channel WSTRB signal asserted incorrectly.,AXI_CTRL AXI write data channel WSTRB signal asserted incorrectly.,-1
ERROR,DMA_ENGINE,DMA source address register parity error,DMA_ENGINE DMA source address register parity error,3
INFO,CLOCK_MANAGER,System clock configured to 500MHz,CLOCK_MANAGER System clock configured to 500MHz,0
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, potential underflow (delta 0x2)","FIFO_BUF FIFO read pointer approaching write pointer, potential underflow (delta 0x2)",5
CRITICAL,MEM_CTRL,"ECC parity mismatch detected, memory data integrity compromised","MEM_CTRL ECC parity mismatch detected, memory data integrity compromised",1
WARNING,FIFO_BUF,FIFO almost empty condition for extended duration.,FIFO_BUF FIFO almost empty condition for extended duration.,5
WARNING,PCIE_CTRL,PCIe device 'GPU' reported multiple recoverable errors,PCIE_CTRL PCIe device 'GPU' reported multiple recoverable errors,6
WARNING,DDR_CTRL,DDR read latency increasing on specific bank,DDR_CTRL DDR read latency increasing on specific bank,1
INFO,CLOCK_MANAGER,Clock tree rebuilt,CLOCK_MANAGER Clock tree rebuilt,0
INFO,FIFO_BUF,FIFO fill level reported as 25%,FIFO_BUF FIFO fill level reported as 25%,5
WARNING,PCIE_CTRL,PCIe TLP latency exceeding expected threshold.,PCIE_CTRL PCIe TLP latency exceeding expected threshold.,6
WARNING,CLOCK_MANAGER,Clock gater for module Y showing excessive delay in enabling clock.,CLOCK_MANAGER Clock gater for module Y showing excessive delay in enabling clock.,0
ERROR,CACHE_CTRL,Cache coherency message dropped,CACHE_CTRL Cache coherency message dropped,1
CRITICAL,MEM_CTRL,Memory controller arbitration deadlock,MEM_CTRL Memory controller arbitration deadlock,1
WARNING,CACHE_CTRL,Cache coherence protocol deadlock potential identified.,CACHE_CTRL Cache coherence protocol deadlock potential identified.,1
INFO,CACHE_CTRL,Cache line fill from DDR memory completed,CACHE_CTRL Cache line fill from DDR memory completed,1
INFO,MEM_CTRL,Memory read cycle executed,MEM_CTRL Memory read cycle executed,1
INFO,INTERRUPT_CTRL,Interrupt controller enabled,INTERRUPT_CTRL Interrupt controller enabled,1
WARNING,MEM_CTRL,Memory utilization approaching high water mark,MEM_CTRL Memory utilization approaching high water mark,1
CRITICAL,DDR_CTRL,DDR memory channel initialization fatal error,DDR_CTRL DDR memory channel initialization fatal error,1
INFO,INTERRUPT_CTRL,Interrupt latency measured at 120 cycles,INTERRUPT_CTRL Interrupt latency measured at 120 cycles,1
CRITICAL,CLOCK_MANAGER,Primary clock source failure detected,CLOCK_MANAGER Primary clock source failure detected,0
INFO,MEM_CTRL,Memory data prefetcher enabled,MEM_CTRL Memory data prefetcher enabled,1
ERROR,PCIE_CTRL,PCIe unsupported request detected,PCIE_CTRL PCIe unsupported request detected,6
WARNING,AXI_CTRL,AXI master 0 stalled on write address channel,AXI_CTRL AXI master 0 stalled on write address channel,2
WARNING,CLOCK_MANAGER,PLL lock time extended beyond expected window,CLOCK_MANAGER PLL lock time extended beyond expected window,0
INFO,POWER_CTRL,Power management unit active,POWER_CTRL Power management unit active,4
CRITICAL,AXI_CTRL,AXI interconnect suffered a fatal deadlock on address '0xDEADBEEF',AXI_CTRL AXI interconnect suffered a fatal deadlock on address '0xDEADBEEF',2
INFO,MEM_CTRL,Memory scrub operation initiated,MEM_CTRL Memory scrub operation initiated,1
CRITICAL,CACHE_CTRL,Cache tag comparison logic failure,CACHE_CTRL Cache tag comparison logic failure,1
CRITICAL,AXI_CTRL,AXI interconnect fatal error,AXI_CTRL AXI interconnect fatal error,2
INFO,DMA_ENGINE,DMA channel N configured for fixed address mode,DMA_ENGINE DMA channel N configured for fixed address mode,3
WARNING,DDR_CTRL,DDR refresh rate adjusted due to temperature increase.,DDR_CTRL DDR refresh rate adjusted due to temperature increase.,1
WARNING,DDR_CTRL,DDR controller refresh logic stalled,DDR_CTRL DDR controller refresh logic stalled,1
WARNING,INTERRUPT_CTRL,Interrupt controller internal state register inconsistencies,INTERRUPT_CTRL Interrupt controller internal state register inconsistencies,1
ERROR,MEM_CTRL,Memory controller FSM stuck in transient state,MEM_CTRL Memory controller FSM stuck in transient state,1
INFO,PCIE_CTRL,PCIe link speed downgraded to recover,PCIE_CTRL PCIe link speed downgraded to recover,6
ERROR,CLOCK_MANAGER,PLL frequency acquisition failure,CLOCK_MANAGER PLL frequency acquisition failure,0
WARNING,DMA_ENGINE,"DMA channel arbitration failure detected, retry initiated","DMA_ENGINE DMA channel arbitration failure detected, retry initiated",3
WARNING,CLOCK_MANAGER,Clock generator PLL fractional N divider not settling,CLOCK_MANAGER Clock generator PLL fractional N divider not settling,-1
INFO,AXI_CTRL,AXI read data received and validated,AXI_CTRL AXI read data received and validated,2
INFO,CACHE_CTRL,Cache line writeback completed for address.,CACHE_CTRL Cache line writeback completed for address.,1
WARNING,INTERRUPT_CTRL,Interrupt latency exceeded maximum allowed.,INTERRUPT_CTRL Interrupt latency exceeded maximum allowed.,1
ERROR,MEM_CTRL,Memory refresh address counter desynchronized,MEM_CTRL Memory refresh address counter desynchronized,1
ERROR,DMA_ENGINE,DMA descriptor fetch failed due to invalid address,DMA_ENGINE DMA descriptor fetch failed due to invalid address,3
CRITICAL,CACHE_CTRL,Multi-cache line corruption detected across several ways,CACHE_CTRL Multi-cache line corruption detected across several ways,1
ERROR,DMA_ENGINE,DMA destination address 0x0119e7a8 out of bounds.,DMA_ENGINE DMA destination address 0x0119e7a8 out of bounds.,3
ERROR,CACHE_CTRL,Cache data parity error detected,CACHE_CTRL Cache data parity error detected,1
ERROR,FIFO_BUF,FIFO reset failed to clear all internal pointers,FIFO_BUF FIFO reset failed to clear all internal pointers,5
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range.,CLOCK_MANAGER Clock skew approaching unsafe range.,0
WARNING,PCIE_CTRL,PCIe link re-training initiated due to minor errors.,PCIE_CTRL PCIe link re-training initiated due to minor errors.,6
WARNING,DMA_ENGINE,DMA engine internal register access failure,DMA_ENGINE DMA engine internal register access failure,3
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance (233ps peak-to-peak).,CLOCK_MANAGER Clock jitter exceeding tolerance (233ps peak-to-peak).,0
INFO,CACHE_CTRL,L1 instruction cache prefetch enabled,CACHE_CTRL L1 instruction cache prefetch enabled,1
INFO,POWER_CTRL,Power rail voltage stable at 0.9V,POWER_CTRL Power rail voltage stable at 0.9V,4
ERROR,CACHE_CTRL,Cache coherence violation during RMW operation,CACHE_CTRL Cache coherence violation during RMW operation,1
WARNING,FIFO_BUF,FIFO data width mismatch detected,FIFO_BUF FIFO data width mismatch detected,5
INFO,AXI_CTRL,AXI write request queued for ID 0x0A.,AXI_CTRL AXI write request queued for ID 0x0A.,2
WARNING,AXI_CTRL,AXI write response channel congested,AXI_CTRL AXI write response channel congested,2
ERROR,CLOCK_MANAGER,Clock tree buffer drive strength warning,CLOCK_MANAGER Clock tree buffer drive strength warning,0
ERROR,PCIE_CTRL,"PCIe link established successfully, but at reduced speed","PCIE_CTRL PCIe link established successfully, but at reduced speed",6
INFO,CACHE_CTRL,Cache line write-back for address 0x3000 completed,CACHE_CTRL Cache line write-back for address 0x3000 completed,1
WARNING,INTERRUPT_CTRL,Interrupt controller internal buffer filling up,INTERRUPT_CTRL Interrupt controller internal buffer filling up,1
ERROR,PCIE_CTRL,PCIe completion timeout detected for request ID 0x1234,PCIE_CTRL PCIe completion timeout detected for request ID 0x1234,6
ERROR,POWER_CTRL,Power management unit internal registers corrupted,POWER_CTRL Power management unit internal registers corrupted,4
WARNING,CLOCK_MANAGER,Clock input frequency drift detected,CLOCK_MANAGER Clock input frequency drift detected,0
WARNING,DDR_CTRL,Training parameters drift detected,DDR_CTRL Training parameters drift detected,1
INFO,CACHE_CTRL,CACHE_CTRL configuration update applied.,CACHE_CTRL CACHE_CTRL configuration update applied.,1
WARNING,DMA_ENGINE,DMA transfer completion not acknowledged,DMA_ENGINE DMA transfer completion not acknowledged,3
CRITICAL,POWER_CTRL,Power sequencing failure leading to bricked state,POWER_CTRL Power sequencing failure leading to bricked state,4
ERROR,CLOCK_MANAGER,PLL reference clock source instability,CLOCK_MANAGER PLL reference clock source instability,0
WARNING,POWER_CTRL,Dynamic voltage and frequency scaling (DVFS) transition failed,POWER_CTRL Dynamic voltage and frequency scaling (DVFS) transition failed,9
INFO,FIFO_BUF,FIFO empty condition asserted,FIFO_BUF FIFO empty condition asserted,5
INFO,DDR_CTRL,DDR read data burst completed,DDR_CTRL DDR read data burst completed,1
CRITICAL,DDR_CTRL,DDR training sequence failed repeatedly,DDR_CTRL DDR training sequence failed repeatedly,1
INFO,INTERRUPT_CTRL,Interrupt enable/disable toggled,INTERRUPT_CTRL Interrupt enable/disable toggled,1
CRITICAL,AXI_CTRL,AXI coherent interconnect assertion failure,AXI_CTRL AXI coherent interconnect assertion failure,2
ERROR,PCIE_CTRL,PCIe received TLP with incorrect length field,PCIE_CTRL PCIe received TLP with incorrect length field,6
CRITICAL,CACHE_CTRL,Cache controller internal data path error,CACHE_CTRL Cache controller internal data path error,1
ERROR,FIFO_BUF,FIFO depth configuration mismatch,FIFO_BUF FIFO depth configuration mismatch,5
CRITICAL,PCIE_CTRL,PCIe root complex unable to enumerate endpoint,PCIE_CTRL PCIe root complex unable to enumerate endpoint,6
INFO,FIFO_BUF,FIFO depth configured to 256 entries,FIFO_BUF FIFO depth configured to 256 entries,5
WARNING,DMA_ENGINE,DMA request queue depth nearing critical level,DMA_ENGINE DMA request queue depth nearing critical level,3
WARNING,PCIE_CTRL,PCIe receive buffer experiencing backpressure,PCIE_CTRL PCIe receive buffer experiencing backpressure,6
ERROR,AXI_CTRL,AXI slave 0x07 asserted SLVERR for a valid transaction.,AXI_CTRL AXI slave 0x07 asserted SLVERR for a valid transaction.,2
INFO,CACHE_CTRL,Cache hit on L1 for address 0xABCDEF00,CACHE_CTRL Cache hit on L1 for address 0xABCDEF00,1
CRITICAL,DDR_CTRL,"DDR initialization sequence failed, stuck in reset","DDR_CTRL DDR initialization sequence failed, stuck in reset",1
INFO,FIFO_BUF,Data successfully enqueued to FIFO,FIFO_BUF Data successfully enqueued to FIFO,5
ERROR,DDR_CTRL,DDR ZQ calibration failure,DDR_CTRL DDR ZQ calibration failure,1
INFO,INTERRUPT_CTRL,Interrupt controller unmasked device 11,INTERRUPT_CTRL Interrupt controller unmasked device 11,-1
ERROR,CLOCK_MANAGER,CLOCK_MANAGER detected a severe timing violation: clock period violation.,CLOCK_MANAGER CLOCK_MANAGER detected a severe timing violation: clock period violation.,0
CRITICAL,FIFO_BUF,"FIFO integrity check failed, data loss imminent","FIFO_BUF FIFO integrity check failed, data loss imminent",5
WARNING,CACHE_CTRL,Cache line fill buffer full,CACHE_CTRL Cache line fill buffer full,1
ERROR,AXI_CTRL,AXI protocol violation: AWVALID asserted without AWREADY,AXI_CTRL AXI protocol violation: AWVALID asserted without AWREADY,2
ERROR,CLOCK_MANAGER,Clock domain crossing path setup time violation,CLOCK_MANAGER Clock domain crossing path setup time violation,0
ERROR,POWER_CTRL,Thermal shutdown initiated due to critical temperature (105C),POWER_CTRL Thermal shutdown initiated due to critical temperature (105C),4
CRITICAL,INTERRUPT_CTRL,CRITICAL: System integrity compromised by unhandled critical interrupt 31.,INTERRUPT_CTRL CRITICAL: System integrity compromised by unhandled critical interrupt 31.,1
WARNING,AXI_CTRL,AXI outstanding transaction limit nearing capacity,AXI_CTRL AXI outstanding transaction limit nearing capacity,2
WARNING,MEM_CTRL,Memory refresh cycle delayed,MEM_CTRL Memory refresh cycle delayed,1
INFO,POWER_CTRL,Core power domain re-enabled after idle state,POWER_CTRL Core power domain re-enabled after idle state,4
WARNING,FIFO_BUF,"FIFO almost full, but no backpressure asserted.","FIFO_BUF FIFO almost full, but no backpressure asserted.",5
WARNING,DDR_CTRL,DDR refresh sequence interrupted,DDR_CTRL DDR refresh sequence interrupted,1
WARNING,INTERRUPT_CTRL,Interrupt controller queue depth exceeding threshold,INTERRUPT_CTRL Interrupt controller queue depth exceeding threshold,1
WARNING,AXI_CTRL,AXI read channel wait states increasing,AXI_CTRL AXI read channel wait states increasing,2
CRITICAL,FIFO_BUF,FIFO buffer hardware fault detected,FIFO_BUF FIFO buffer hardware fault detected,5
CRITICAL,DMA_ENGINE,DMA engine experienced a permanent internal deadlock,DMA_ENGINE DMA engine experienced a permanent internal deadlock,3
ERROR,INTERRUPT_CTRL,Pending interrupt queue overflow,INTERRUPT_CTRL Pending interrupt queue overflow,1
INFO,DDR_CTRL,DDR memory training sequence successful,DDR_CTRL DDR memory training sequence successful,1
CRITICAL,CLOCK_MANAGER,Internal oscillator failure,CLOCK_MANAGER Internal oscillator failure,0
CRITICAL,AXI_CTRL,AXI bus error response (SLVERR) from critical peripheral,AXI_CTRL AXI bus error response (SLVERR) from critical peripheral,-1
ERROR,FIFO_BUF,FIFO pointer corruption detected.,FIFO_BUF FIFO pointer corruption detected.,5
INFO,PCIE_CTRL,PCIe re-training successful at current link speed,PCIE_CTRL PCIe re-training successful at current link speed,6
INFO,AXI_CTRL,AXI write completion acknowledged.,AXI_CTRL AXI write completion acknowledged.,2
ERROR,DDR_CTRL,Memory rank scheduling conflict detected,DDR_CTRL Memory rank scheduling conflict detected,1
INFO,MEM_CTRL,Memory address range 0x1000-0x1FFF protected,MEM_CTRL Memory address range 0x1000-0x1FFF protected,1
WARNING,INTERRUPT_CTRL,Interrupt controller configuration mismatch,INTERRUPT_CTRL Interrupt controller configuration mismatch,1
ERROR,CACHE_CTRL,Cache line prefetch request fetched invalid data,CACHE_CTRL Cache line prefetch request fetched invalid data,1
INFO,INTERRUPT_CTRL,Interrupt 'TIMER0' successfully processed,INTERRUPT_CTRL Interrupt 'TIMER0' successfully processed,1
WARNING,DMA_ENGINE,DMA source address invalid,DMA_ENGINE DMA source address invalid,3
CRITICAL,PCIE_CTRL,PCIe configuration space locked by faulty device,PCIE_CTRL PCIe configuration space locked by faulty device,6
CRITICAL,DDR_CTRL,"Persistent DDR command timeout, memory unresponsive","DDR_CTRL Persistent DDR command timeout, memory unresponsive",1
INFO,INTERRUPT_CTRL,Interrupt 'GPIO_INT' pending flag set,INTERRUPT_CTRL Interrupt 'GPIO_INT' pending flag set,1
INFO,PCIE_CTRL,PCIe link width negotiated to x8.,PCIE_CTRL PCIe link width negotiated to x8.,6
ERROR,FIFO_BUF,FIFO 'control_pipe' suffered pointer corruption,FIFO_BUF FIFO 'control_pipe' suffered pointer corruption,5
CRITICAL,POWER_CTRL,Power-on reset (POR) signal asserted spuriously.,POWER_CTRL Power-on reset (POR) signal asserted spuriously.,4
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold for high-priority data,FIFO_BUF FIFO latency exceeding expected threshold for high-priority data,5
ERROR,AXI_CTRL,AXI outstanding transaction ID mismatch,AXI_CTRL AXI outstanding transaction ID mismatch,2
CRITICAL,MEM_CTRL,Memory controller entered catastrophic failure mode.,MEM_CTRL Memory controller entered catastrophic failure mode.,1
WARNING,INTERRUPT_CTRL,Interrupt mask register modified unexpectedly by software,INTERRUPT_CTRL Interrupt mask register modified unexpectedly by software,1
ERROR,DDR_CTRL,DDR precharge timing violation detected,DDR_CTRL DDR precharge timing violation detected,1
INFO,INTERRUPT_CTRL,Interrupt controller reset completed,INTERRUPT_CTRL Interrupt controller reset completed,1
ERROR,FIFO_BUF,"FIFO read operation failed, internal buffer empty.","FIFO_BUF FIFO read operation failed, internal buffer empty.",5
ERROR,FIFO_BUF,FIFO 'pkt_header' write pointer unexpectedly reset,FIFO_BUF FIFO 'pkt_header' write pointer unexpectedly reset,5
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on 'ctrl_signal_A',CLOCK_MANAGER Clock domain crossing synchronization failure on 'ctrl_signal_A',0
ERROR,DMA_ENGINE,DMA channel 3 arbitration conflict detected with channel 4.,DMA_ENGINE DMA channel 3 arbitration conflict detected with channel 4.,3
CRITICAL,AXI_CTRL,"AXI interconnect deadlock detected, system stalled. (deadlock detected)","AXI_CTRL AXI interconnect deadlock detected, system stalled. (deadlock detected)",2
INFO,INTERRUPT_CTRL,Interrupt delivery mechanism verified,INTERRUPT_CTRL Interrupt delivery mechanism verified,1
CRITICAL,AXI_CTRL,AXI transaction timeout detected after 1000 cycles,AXI_CTRL AXI transaction timeout detected after 1000 cycles,2
INFO,CACHE_CTRL,Cache line invalidated from L2,CACHE_CTRL Cache line invalidated from L2,1
WARNING,DMA_ENGINE,DMA engine internal command queue fill level at 80%.,DMA_ENGINE DMA engine internal command queue fill level at 80%.,3
WARNING,DMA_ENGINE,DMA channel paused awaiting semaphore,DMA_ENGINE DMA channel paused awaiting semaphore,3
CRITICAL,DDR_CTRL,DDR controller unable to issue any commands,DDR_CTRL DDR controller unable to issue any commands,1
CRITICAL,DMA_ENGINE,DMA engine unable to recover from error,DMA_ENGINE DMA engine unable to recover from error,3
ERROR,DDR_CTRL,DDR chip select timing violation,DDR_CTRL DDR chip select timing violation,1
WARNING,CACHE_CTRL,Cache data retention issues during low power mode,CACHE_CTRL Cache data retention issues during low power mode,-1
WARNING,PCIE_CTRL,PCIe completion timeout approaching,PCIE_CTRL PCIe completion timeout approaching,6
WARNING,DDR_CTRL,DDR temperature approaching critical limit,DDR_CTRL DDR temperature approaching critical limit,1
ERROR,DMA_ENGINE,DMA channel 3 descriptor access timeout,DMA_ENGINE DMA channel 3 descriptor access timeout,3
WARNING,CACHE_CTRL,Cache coherency probe latency high,CACHE_CTRL Cache coherency probe latency high,1
CRITICAL,PCIE_CTRL,"PCIe link down, fatal error detected","PCIE_CTRL PCIe link down, fatal error detected",6
ERROR,CLOCK_MANAGER,Clock domain crossing control signal metastability,CLOCK_MANAGER Clock domain crossing control signal metastability,0
INFO,PCIE_CTRL,PCIe link up with negotiated speed,PCIE_CTRL PCIe link up with negotiated speed,6
CRITICAL,CACHE_CTRL,Cache tag SRAM uncorrectable ECC error,CACHE_CTRL Cache tag SRAM uncorrectable ECC error,1
ERROR,PCIE_CTRL,PCIe device hot-plug detection failed,PCIE_CTRL PCIe device hot-plug detection failed,6
INFO,INTERRUPT_CTRL,Interrupt vector mismatch detection disabled,INTERRUPT_CTRL Interrupt vector mismatch detection disabled,1
ERROR,CACHE_CTRL,Cache tag RAM read/write error,CACHE_CTRL Cache tag RAM read/write error,1
ERROR,PCIE_CTRL,PCIe Completion Timeout (CTO) detected.,PCIE_CTRL PCIe Completion Timeout (CTO) detected.,6
INFO,POWER_CTRL,Power consumption metrics logged,POWER_CTRL Power consumption metrics logged,4
INFO,DMA_ENGINE,DMA engine stopped,DMA_ENGINE DMA engine stopped,3
CRITICAL,DMA_ENGINE,DMA engine register file corruption,DMA_ENGINE DMA engine register file corruption,3
ERROR,CLOCK_MANAGER,Clock domain crossing handshake failure in synchronizer,CLOCK_MANAGER Clock domain crossing handshake failure in synchronizer,0
CRITICAL,PCIE_CTRL,PCIe Root Complex communication failure,PCIE_CTRL PCIe Root Complex communication failure,6
INFO,AXI_CTRL,AXI read channel 'master_0' granted access,AXI_CTRL AXI read channel 'master_0' granted access,2
INFO,PCIE_CTRL,PCIe completion timeout disabled,PCIE_CTRL PCIe completion timeout disabled,6
ERROR,INTERRUPT_CTRL,Interrupt vector address translation fault,INTERRUPT_CTRL Interrupt vector address translation fault,1
CRITICAL,MEM_CTRL,Memory controller address path corruption,MEM_CTRL Memory controller address path corruption,1
WARNING,POWER_CTRL,Power domain transition to D3 taking longer than expected,POWER_CTRL Power domain transition to D3 taking longer than expected,4
WARNING,FIFO_BUF,FIFO read data valid but not consumed for multiple cycles,FIFO_BUF FIFO read data valid but not consumed for multiple cycles,5
INFO,DDR_CTRL,DDR calibration completed successfully (mode ZQ_CAL).,DDR_CTRL DDR calibration completed successfully (mode ZQ_CAL).,1
ERROR,CACHE_CTRL,Cache directory entry corruption detected.,CACHE_CTRL Cache directory entry corruption detected.,1
WARNING,DDR_CTRL,"DDR refresh pending, read access temporarily delayed","DDR_CTRL DDR refresh pending, read access temporarily delayed",1
CRITICAL,PCIE_CTRL,"PCIe training sequence failed, link stuck in L0s","PCIE_CTRL PCIe training sequence failed, link stuck in L0s",6
ERROR,DMA_ENGINE,DMA transfer completion interrupt not asserted,DMA_ENGINE DMA transfer completion interrupt not asserted,3
INFO,INTERRUPT_CTRL,Interrupt line 3 deasserted,INTERRUPT_CTRL Interrupt line 3 deasserted,1
INFO,CACHE_CTRL,Cache line written back with no issues,CACHE_CTRL Cache line written back with no issues,1
CRITICAL,DMA_ENGINE,"DMA engine system bus error, critical data path affected","DMA_ENGINE DMA engine system bus error, critical data path affected",3
CRITICAL,DMA_ENGINE,"DMA engine unable to complete any transfers, functional failure","DMA_ENGINE DMA engine unable to complete any transfers, functional failure",3
WARNING,MEM_CTRL,DRAM refresh rate set to minimum,MEM_CTRL DRAM refresh rate set to minimum,1
WARNING,FIFO_BUF,FIFO 'debug_trace' latency exceeding expected threshold,FIFO_BUF FIFO 'debug_trace' latency exceeding expected threshold,5
WARNING,PCIE_CTRL,PCIe replay buffer approaching capacity after errors,PCIE_CTRL PCIe replay buffer approaching capacity after errors,6
ERROR,FIFO_BUF,FIFO pointer corruption: read_ptr > write_ptr unexpectedly,FIFO_BUF FIFO pointer corruption: read_ptr > write_ptr unexpectedly,5
WARNING,DDR_CTRL,DDR clock gating instability detected,DDR_CTRL DDR clock gating instability detected,1
CRITICAL,FIFO_BUF,FIFO buffer memory unrecoverable error,FIFO_BUF FIFO buffer memory unrecoverable error,5
INFO,INTERRUPT_CTRL,Interrupt controller enabled and ready.,INTERRUPT_CTRL Interrupt controller enabled and ready.,1
WARNING,FIFO_BUF,"FIFO nearing capacity, potential for buffer overflow.","FIFO_BUF FIFO nearing capacity, potential for buffer overflow.",5
INFO,CLOCK_MANAGER,Clock domain crossing bridge reset synchronized,CLOCK_MANAGER Clock domain crossing bridge reset synchronized,0
INFO,DMA_ENGINE,DMA channel idle.,DMA_ENGINE DMA channel idle.,3
WARNING,DDR_CTRL,DDR memory utilization at high levels,DDR_CTRL DDR memory utilization at high levels,1
WARNING,FIFO_BUF,"FIFO reset in progress, data loss possible","FIFO_BUF FIFO reset in progress, data loss possible",5
INFO,MEM_CTRL,Memory controller initialized for 7691MB.,MEM_CTRL Memory controller initialized for 7691MB.,1
ERROR,AXI_CTRL,AXI burst length violation (unexpected length) detected for read transaction,AXI_CTRL AXI burst length violation (unexpected length) detected for read transaction,2
ERROR,MEM_CTRL,Data bus single bit error detected and corrected,MEM_CTRL Data bus single bit error detected and corrected,1
WARNING,CLOCK_MANAGER,Clock frequency drift detected from target,CLOCK_MANAGER Clock frequency drift detected from target,0
INFO,CACHE_CTRL,Cache line write-through policy enabled,CACHE_CTRL Cache line write-through policy enabled,1
INFO,FIFO_BUF,FIFO bypass mode disengaged,FIFO_BUF FIFO bypass mode disengaged,-1
WARNING,AXI_CTRL,AXI BVALID asserted without BREADY on write channel,AXI_CTRL AXI BVALID asserted without BREADY on write channel,2
ERROR,CLOCK_MANAGER,Clock domain crossing FIFO underflow detected,CLOCK_MANAGER Clock domain crossing FIFO underflow detected,0
WARNING,PCIE_CTRL,PCIe internal error counter incremented (non-fatal),PCIE_CTRL PCIe internal error counter incremented (non-fatal),6
INFO,DMA_ENGINE,Transfer count updated,DMA_ENGINE Transfer count updated,3
INFO,DDR_CTRL,DDR controller power-down mode entered,DDR_CTRL DDR controller power-down mode entered,1
WARNING,POWER_CTRL,Auxiliary power rail slightly above nominal,POWER_CTRL Auxiliary power rail slightly above nominal,4
ERROR,CACHE_CTRL,Cache tag parity error detected for entry 16.,CACHE_CTRL Cache tag parity error detected for entry 16.,1
WARNING,AXI_CTRL,AXI write channel starvation observed,AXI_CTRL AXI write channel starvation observed,2
WARNING,CLOCK_MANAGER,Clock tree synthesis detected minor timing violations,CLOCK_MANAGER Clock tree synthesis detected minor timing violations,0
ERROR,AXI_CTRL,AXI read burst alignment violation,AXI_CTRL AXI read burst alignment violation,2
WARNING,DDR_CTRL,DDR ZQ calibration due,DDR_CTRL DDR ZQ calibration due,1
ERROR,FIFO_BUF,FIFO empty flag deasserted prematurely,FIFO_BUF FIFO empty flag deasserted prematurely,5
CRITICAL,POWER_CTRL,System power plane short circuit detected,POWER_CTRL System power plane short circuit detected,-1
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout from CPU,INTERRUPT_CTRL Interrupt acknowledge timeout from CPU,1
INFO,MEM_CTRL,Memory refresh cycle initiated,MEM_CTRL Memory refresh cycle initiated,1
ERROR,AXI_CTRL,AXI address channel deadlock,AXI_CTRL AXI address channel deadlock,2
INFO,MEM_CTRL,Memory controller in low power mode,MEM_CTRL Memory controller in low power mode,1
WARNING,DMA_ENGINE,DMA transfer completion interrupt pending,DMA_ENGINE DMA transfer completion interrupt pending,3
WARNING,AXI_CTRL,AXI bus contention detected for shared resource,AXI_CTRL AXI bus contention detected for shared resource,2
WARNING,FIFO_BUF,Input data rate consistently exceeding output rate.,FIFO_BUF Input data rate consistently exceeding output rate.,5
CRITICAL,CLOCK_MANAGER,Clock tree integrity check failed post-reset,CLOCK_MANAGER Clock tree integrity check failed post-reset,0
CRITICAL,AXI_CTRL,AXI read channel deadlock due to RREADY assertion,AXI_CTRL AXI read channel deadlock due to RREADY assertion,2
ERROR,PCIE_CTRL,PCIe packet framing error detected on lane 1.,PCIE_CTRL PCIe packet framing error detected on lane 1.,6
ERROR,AXI_CTRL,AXI address decoding error on read channel,AXI_CTRL AXI address decoding error on read channel,2
ERROR,MEM_CTRL,Memory controller address decoder misrouted access,MEM_CTRL Memory controller address decoder misrouted access,1
ERROR,AXI_CTRL,"Transaction to AXI_CTRL experienced transaction timeout (outstanding request expired, TxID: 0x22). (Master ID: 6, AXI ID: 0)","AXI_CTRL Transaction to AXI_CTRL experienced transaction timeout (outstanding request expired, TxID: 0x22). (Master ID: 6, AXI ID: 0)",2
ERROR,CLOCK_MANAGER,Clock signal integrity degradation detected,CLOCK_MANAGER Clock signal integrity degradation detected,0
CRITICAL,CACHE_CTRL,Cache hierarchy coherence deadlock detected between L1 and L2,CACHE_CTRL Cache hierarchy coherence deadlock detected between L1 and L2,1
INFO,CACHE_CTRL,Cache hit on dirty line,CACHE_CTRL Cache hit on dirty line,1
INFO,DDR_CTRL,Write leveling completed,DDR_CTRL Write leveling completed,1
INFO,CACHE_CTRL,Cache hit detected for address 0xD12D4,CACHE_CTRL Cache hit detected for address 0xD12D4,1
WARNING,MEM_CTRL,Memory access permissions misconfigured for region '0x20000000',MEM_CTRL Memory access permissions misconfigured for region '0x20000000',1
WARNING,AXI_CTRL,AXI write channel starvation detected,AXI_CTRL AXI write channel starvation detected,2
INFO,PCIE_CTRL,PCIe configuration read access successful,PCIE_CTRL PCIe configuration read access successful,6
WARNING,DMA_ENGINE,DMA channel status register indicates pending error,DMA_ENGINE DMA channel status register indicates pending error,3
ERROR,DDR_CTRL,DDR memory page open error,DDR_CTRL DDR memory page open error,1
INFO,INTERRUPT_CTRL,Interrupt vector table updated,INTERRUPT_CTRL Interrupt vector table updated,1
INFO,PCIE_CTRL,PCIe device enumerated successfully,PCIE_CTRL PCIe device enumerated successfully,6
ERROR,CLOCK_MANAGER,Global clock buffer output stuck low,CLOCK_MANAGER Global clock buffer output stuck low,0
WARNING,FIFO_BUF,FIFO read operation stalled due to empty condition,FIFO_BUF FIFO read operation stalled due to empty condition,5
WARNING,MEM_CTRL,Memory controller arbitration delays increasing,MEM_CTRL Memory controller arbitration delays increasing,1
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold (500ns),FIFO_BUF FIFO latency exceeding expected threshold (500ns),5
CRITICAL,AXI_CTRL,AXI bus arbitration logic entered a starvation state,AXI_CTRL AXI bus arbitration logic entered a starvation state,2
INFO,POWER_CTRL,Power management controller debug mode enabled,POWER_CTRL Power management controller debug mode enabled,-1
CRITICAL,PCIE_CTRL,"PCIe link training timeout, x0 link speed","PCIE_CTRL PCIe link training timeout, x0 link speed",6
ERROR,DDR_CTRL,"DDR_CTRL: timing violation - asynchronous path timing error detected. (Command: WRITE, Bank: 2)","DDR_CTRL DDR_CTRL: timing violation - asynchronous path timing error detected. (Command: WRITE, Bank: 2)",1
CRITICAL,PCIE_CTRL,PCIe root complex internal error,PCIE_CTRL PCIe root complex internal error,6
WARNING,AXI_CTRL,AXI handshake delay approaching threshold on read channel,AXI_CTRL AXI handshake delay approaching threshold on read channel,2
ERROR,MEM_CTRL,Memory address alignment fault on write operation,MEM_CTRL Memory address alignment fault on write operation,1
CRITICAL,MEM_CTRL,System bus deadlock involving memory controller.,MEM_CTRL System bus deadlock involving memory controller.,1
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance for clock Core.,CLOCK_MANAGER Clock jitter exceeding tolerance for clock Core.,0
INFO,MEM_CTRL,Memory write buffer flushed.,MEM_CTRL Memory write buffer flushed.,1
WARNING,PCIE_CTRL,PCIe Lane 0 symbol error rate increasing,PCIE_CTRL PCIe Lane 0 symbol error rate increasing,6
INFO,DDR_CTRL,DDR controller configured for 1T timing,DDR_CTRL DDR controller configured for 1T timing,1
CRITICAL,DDR_CTRL,DDR memory power sequencing invalid state,DDR_CTRL DDR memory power sequencing invalid state,1
ERROR,CACHE_CTRL,Cache tag array mismatch during lookup,CACHE_CTRL Cache tag array mismatch during lookup,1
INFO,AXI_CTRL,AXI response channel detected valid response,AXI_CTRL AXI response channel detected valid response,2
WARNING,FIFO_BUF,FIFO_LOG_CHANNEL has accumulated 95% of its log capacity.,FIFO_BUF FIFO_LOG_CHANNEL has accumulated 95% of its log capacity.,5
CRITICAL,MEM_CTRL,Uncorrectable ECC error in data path,MEM_CTRL Uncorrectable ECC error in data path,1
ERROR,CLOCK_MANAGER,Primary clock source instability detected,CLOCK_MANAGER Primary clock source instability detected,0
ERROR,DDR_CTRL,DRAM refresh counter corruption detected,DDR_CTRL DRAM refresh counter corruption detected,1
ERROR,AXI_CTRL,AXI address channel ID mismatch,AXI_CTRL AXI address channel ID mismatch,2
ERROR,MEM_CTRL,Memory address translation fault detected,MEM_CTRL Memory address translation fault detected,1
INFO,PCIE_CTRL,PCIe enumeration successful,PCIE_CTRL PCIe enumeration successful,6
WARNING,PCIE_CTRL,PCIe virtual channel buffer usage high,PCIE_CTRL PCIe virtual channel buffer usage high,6
ERROR,AXI_CTRL,"AXI write response mismatch detected (expected DECERR, got SLVERR).","AXI_CTRL AXI write response mismatch detected (expected DECERR, got SLVERR).",2
CRITICAL,FIFO_BUF,FIFO internal state machine entered unrecoverable error,FIFO_BUF FIFO internal state machine entered unrecoverable error,5
ERROR,MEM_CTRL,Memory parity error detected at 0x550a26d7 during read.,MEM_CTRL Memory parity error detected at 0x550a26d7 during read.,1
ERROR,MEM_CTRL,Memory access timeout detected for peripheral 'UART',MEM_CTRL Memory access timeout detected for peripheral 'UART',1
ERROR,DMA_ENGINE,Invalid DMA descriptor format detected,DMA_ENGINE Invalid DMA descriptor format detected,3
ERROR,MEM_CTRL,Memory read-after-write data inconsistency,MEM_CTRL Memory read-after-write data inconsistency,1
INFO,AXI_CTRL,Write response received for outstanding burst.,AXI_CTRL Write response received for outstanding burst.,2
WARNING,PCIE_CTRL,"Credit buffer low, potential for stalls","PCIE_CTRL Credit buffer low, potential for stalls",6
INFO,MEM_CTRL,Memory region protection enabled,MEM_CTRL Memory region protection enabled,1
INFO,MEM_CTRL,"Memory scrub operation completed successfully, 1 single-bit error corrected","MEM_CTRL Memory scrub operation completed successfully, 1 single-bit error corrected",1
CRITICAL,POWER_CTRL,"Thermal runaway detected, immediate shutdown","POWER_CTRL Thermal runaway detected, immediate shutdown",4
WARNING,POWER_CTRL,Brown-out detection circuit triggered momentarily,POWER_CTRL Brown-out detection circuit triggered momentarily,4
INFO,MEM_CTRL,Memory controller debug registers accessed,MEM_CTRL Memory controller debug registers accessed,1
CRITICAL,MEM_CTRL,Uncorrectable multi-bit ECC error detected,MEM_CTRL Uncorrectable multi-bit ECC error detected,1
INFO,DMA_ENGINE,DMA completion callback registered,DMA_ENGINE DMA completion callback registered,3
ERROR,POWER_CTRL,Voltage sensor reports instability on 'VDD_IO' rail,POWER_CTRL Voltage sensor reports instability on 'VDD_IO' rail,4
CRITICAL,POWER_CTRL,Main system voltage regulator unresponsive,POWER_CTRL Main system voltage regulator unresponsive,4
WARNING,POWER_CTRL,Power domain X current draw exceeding budgeted limit,POWER_CTRL Power domain X current draw exceeding budgeted limit,4
INFO,CLOCK_MANAGER,Clock network scan completed,CLOCK_MANAGER Clock network scan completed,-1
WARNING,INTERRUPT_CTRL,Spurious interrupt detected (ignored),INTERRUPT_CTRL Spurious interrupt detected (ignored),1
INFO,AXI_CTRL,AXI bus master released,AXI_CTRL AXI bus master released,2
ERROR,PCIE_CTRL,PCIe Completion Timeout (CTO) on downstream device,PCIE_CTRL PCIe Completion Timeout (CTO) on downstream device,6
ERROR,MEM_CTRL,Memory controller internal state machine fault,MEM_CTRL Memory controller internal state machine fault,1
WARNING,DDR_CTRL,DDR command queue fullness nearing critical level,DDR_CTRL DDR command queue fullness nearing critical level,1
INFO,CACHE_CTRL,Cache invalidate command issued for core 1.,CACHE_CTRL Cache invalidate command issued for core 1.,1
ERROR,AXI_CTRL,AXI write response channel observed unexpected data.,AXI_CTRL AXI write response channel observed unexpected data.,2
WARNING,FIFO_BUF,FIFO watermark exceeded,FIFO_BUF FIFO watermark exceeded,5
INFO,PCIE_CTRL,PCIe transaction completed with ECRC check passed,PCIE_CTRL PCIe transaction completed with ECRC check passed,6
INFO,FIFO_BUF,FIFO_REQUEST_QUEUE write operation successful.,FIFO_BUF FIFO_REQUEST_QUEUE write operation successful.,5
CRITICAL,DDR_CTRL,DDR training sequence failed repeatedly (DDR training sequence failed),DDR_CTRL DDR training sequence failed repeatedly (DDR training sequence failed),1
WARNING,AXI_CTRL,AXI write data received with unexpected delay,AXI_CTRL AXI write data received with unexpected delay,2
WARNING,PCIE_CTRL,PCIe outbound transaction buffer 80% full,PCIE_CTRL PCIe outbound transaction buffer 80% full,6
ERROR,CACHE_CTRL,Cache directory lookup returned stale entry,CACHE_CTRL Cache directory lookup returned stale entry,1
INFO,PCIE_CTRL,PCIe link state changed to L0.,PCIE_CTRL PCIe link state changed to L0.,6
CRITICAL,PCIE_CTRL,PCIe lane synchronization lost on multiple lanes simultaneously,PCIE_CTRL PCIe lane synchronization lost on multiple lanes simultaneously,6
CRITICAL,DMA_ENGINE,"DMA engine hung in critical state, unable to complete transfers","DMA_ENGINE DMA engine hung in critical state, unable to complete transfers",3
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal register corruption,INTERRUPT_CTRL Interrupt controller internal register corruption,1
ERROR,CLOCK_MANAGER,Main system clock power rail instability,CLOCK_MANAGER Main system clock power rail instability,0
CRITICAL,POWER_CTRL,Core voltage rail collapsed,POWER_CTRL Core voltage rail collapsed,4
ERROR,MEM_CTRL,Memory controller write data parity error,MEM_CTRL Memory controller write data parity error,1
ERROR,DDR_CTRL,DDR bank activate timing violation.,DDR_CTRL DDR bank activate timing violation.,1
INFO,INTERRUPT_CTRL,Interrupt controller re-armed for next event,INTERRUPT_CTRL Interrupt controller re-armed for next event,1
WARNING,DDR_CTRL,"DDR command queue depth unusual (8 pending), potential stalls","DDR_CTRL DDR command queue depth unusual (8 pending), potential stalls",1
WARNING,PCIE_CTRL,PCIe egress queue depth consistently high,PCIE_CTRL PCIe egress queue depth consistently high,6
WARNING,CLOCK_MANAGER,"Clock domain crossing FIFO nearly full, potential buffer overflow.","CLOCK_MANAGER Clock domain crossing FIFO nearly full, potential buffer overflow.",0
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for source 'TIMER'.,INTERRUPT_CTRL Interrupt dispatch completed for source 'TIMER'.,1
ERROR,POWER_CTRL,Power sequencing FSM in deadlock state,POWER_CTRL Power sequencing FSM in deadlock state,-1
WARNING,INTERRUPT_CTRL,Interrupt pending count exceeds software processing rate,INTERRUPT_CTRL Interrupt pending count exceeds software processing rate,1
INFO,CACHE_CTRL,Cache tag RAM initialized to default state,CACHE_CTRL Cache tag RAM initialized to default state,1
CRITICAL,CLOCK_MANAGER,"Clock input signal quality degradation detected, unrecoverable.","CLOCK_MANAGER Clock input signal quality degradation detected, unrecoverable.",0
CRITICAL,MEM_CTRL,Memory address translation unit (MMU) fault,MEM_CTRL Memory address translation unit (MMU) fault,1
ERROR,PCIE_CTRL,"PCIe poisoned TLP received, potential data corruption","PCIE_CTRL PCIe poisoned TLP received, potential data corruption",6
ERROR,AXI_CTRL,AXI read data phase error detected,AXI_CTRL AXI read data phase error detected,2
ERROR,INTERRUPT_CTRL,Interrupt service routine not invoked for pending interrupt,INTERRUPT_CTRL Interrupt service routine not invoked for pending interrupt,1
INFO,PCIE_CTRL,PCIe link operating in Gen4 x16 mode,PCIE_CTRL PCIe link operating in Gen4 x16 mode,6
ERROR,CLOCK_MANAGER,Clock gate enable timing violation,CLOCK_MANAGER Clock gate enable timing violation,0
ERROR,PCIE_CTRL,PCIe received TLP with bad CRC.,PCIE_CTRL PCIe received TLP with bad CRC.,6
CRITICAL,MEM_CTRL,Memory address mapping unit (MMU) configuration error,MEM_CTRL Memory address mapping unit (MMU) configuration error,1
CRITICAL,MEM_CTRL,Memory access forbidden region violation,MEM_CTRL Memory access forbidden region violation,1
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lock lost, switching to backup oscillator","CLOCK_MANAGER Clock generation PLL lock lost, switching to backup oscillator",0
WARNING,DMA_ENGINE,DMA buffer not aligned to cache line boundary,DMA_ENGINE DMA buffer not aligned to cache line boundary,-1
WARNING,CLOCK_MANAGER,Clock recovery circuit instability,CLOCK_MANAGER Clock recovery circuit instability,0
CRITICAL,CLOCK_MANAGER,System reset generated by clock monitor circuit,CLOCK_MANAGER System reset generated by clock monitor circuit,0
CRITICAL,POWER_CTRL,"Fatal power sequence failure, unrecoverable","POWER_CTRL Fatal power sequence failure, unrecoverable",4
INFO,PCIE_CTRL,PCIe transaction layer packet sent,PCIE_CTRL PCIe transaction layer packet sent,6
INFO,INTERRUPT_CTRL,Non-maskable interrupt received,INTERRUPT_CTRL Non-maskable interrupt received,1
ERROR,INTERRUPT_CTRL,"Spurious interrupt detected, unexpected vector","INTERRUPT_CTRL Spurious interrupt detected, unexpected vector",1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller deadlock, system unresponsive","INTERRUPT_CTRL Interrupt controller deadlock, system unresponsive",1
WARNING,INTERRUPT_CTRL,Interrupt queue approaching limit: 39/59 entries used,INTERRUPT_CTRL Interrupt queue approaching limit: 39/59 entries used,1
WARNING,DDR_CTRL,DDR read latency variation exceeding expected range,DDR_CTRL DDR read latency variation exceeding expected range,1
INFO,CLOCK_MANAGER,Clock generator output enabled.,CLOCK_MANAGER Clock generator output enabled.,0
INFO,FIFO_BUF,FIFO configuration register write successful,FIFO_BUF FIFO configuration register write successful,5
CRITICAL,MEM_CTRL,Memory controller internal bus contention led to data loss,MEM_CTRL Memory controller internal bus contention led to data loss,1
WARNING,DDR_CTRL,DDR precharge command delayed,DDR_CTRL DDR precharge command delayed,1
ERROR,PCIE_CTRL,"PCIe hot-plug event detected, but device unresponsive","PCIE_CTRL PCIe hot-plug event detected, but device unresponsive",6
ERROR,INTERRUPT_CTRL,Interrupt controller internal logic error,INTERRUPT_CTRL Interrupt controller internal logic error,1
INFO,AXI_CTRL,AXI bus granted to master ID 14,AXI_CTRL AXI bus granted to master ID 14,2
ERROR,CACHE_CTRL,L3 cache data integrity check failed,CACHE_CTRL L3 cache data integrity check failed,1
WARNING,AXI_CTRL,AXI write outstanding count nearing maximum limit,AXI_CTRL AXI write outstanding count nearing maximum limit,2
WARNING,CLOCK_MANAGER,PLL jitter exceeding acceptable limits,CLOCK_MANAGER PLL jitter exceeding acceptable limits,0
WARNING,CACHE_CTRL,Cache eviction queue nearing capacity (50 entries).,CACHE_CTRL Cache eviction queue nearing capacity (50 entries).,1
ERROR,INTERRUPT_CTRL,Interrupt priority inversion detected in dispatch logic.,INTERRUPT_CTRL Interrupt priority inversion detected in dispatch logic.,1
WARNING,PCIE_CTRL,PCIe transaction layer packet retry count high.,PCIE_CTRL PCIe transaction layer packet retry count high.,6
INFO,POWER_CTRL,Power state reporting enabled,POWER_CTRL Power state reporting enabled,4
CRITICAL,PCIE_CTRL,PCIe physical layer link training state machine stuck,PCIE_CTRL PCIe physical layer link training state machine stuck,6
CRITICAL,CLOCK_MANAGER,"Main PLL lost lock, system clock generation halted","CLOCK_MANAGER Main PLL lost lock, system clock generation halted",0
CRITICAL,MEM_CTRL,Memory controller bus contention deadlock,MEM_CTRL Memory controller bus contention deadlock,1
INFO,AXI_CTRL,AXI write transaction acknowledged,AXI_CTRL AXI write transaction acknowledged,2
ERROR,INTERRUPT_CTRL,Interrupt priority level configured incorrectly,INTERRUPT_CTRL Interrupt priority level configured incorrectly,1
CRITICAL,POWER_CTRL,Critical voltage supply failure on 1.0V.,POWER_CTRL Critical voltage supply failure on 1.0V.,4
WARNING,CACHE_CTRL,Cache line prefetch abort,CACHE_CTRL Cache line prefetch abort,1
ERROR,AXI_CTRL,AXI slave response timeout on read operation,AXI_CTRL AXI slave response timeout on read operation,2
ERROR,DMA_ENGINE,DMA address translation fault for virtual address 0x80000000,DMA_ENGINE DMA address translation fault for virtual address 0x80000000,3
INFO,FIFO_BUF,Write operation successful.,FIFO_BUF Write operation successful.,5
INFO,MEM_CTRL,Memory controller idle state entered.,MEM_CTRL Memory controller idle state entered.,1
WARNING,PCIE_CTRL,PCIe replay buffer nearing capacity,PCIE_CTRL PCIe replay buffer nearing capacity,6
INFO,DDR_CTRL,DDR auto-calibration cycle initiated,DDR_CTRL DDR auto-calibration cycle initiated,1
INFO,FIFO_BUF,FIFO write operation accepted,FIFO_BUF FIFO write operation accepted,5
WARNING,INTERRUPT_CTRL,Interrupt priority level 3 backlog detected,INTERRUPT_CTRL Interrupt priority level 3 backlog detected,1
WARNING,CACHE_CTRL,Cache L2 miss rate showing upward trend,CACHE_CTRL Cache L2 miss rate showing upward trend,1
WARNING,DDR_CTRL,"ZQ calibration pending, potential accuracy degradation","DDR_CTRL ZQ calibration pending, potential accuracy degradation",1
INFO,CLOCK_MANAGER,Auxiliary clock source enabled,CLOCK_MANAGER Auxiliary clock source enabled,0
CRITICAL,DDR_CTRL,DDR training sequence failed to find valid timing parameters.,DDR_CTRL DDR training sequence failed to find valid timing parameters.,1
ERROR,AXI_CTRL,AXI interconnect asserted illegal read address,AXI_CTRL AXI interconnect asserted illegal read address,2
WARNING,DMA_ENGINE,DMA channel 2 data underrun warning,DMA_ENGINE DMA channel 2 data underrun warning,3
INFO,PCIE_CTRL,PCIe power state transition to D1 completed.,PCIE_CTRL PCIe power state transition to D1 completed.,6
INFO,INTERRUPT_CTRL,Interrupt line for GPIO controller asserted,INTERRUPT_CTRL Interrupt line for GPIO controller asserted,1
WARNING,DDR_CTRL,DDR temperature sensor reading elevated,DDR_CTRL DDR temperature sensor reading elevated,1
INFO,CLOCK_MANAGER,PLL re-locked after transient event,CLOCK_MANAGER PLL re-locked after transient event,0
CRITICAL,CLOCK_MANAGER,Global clock tree integrity compromised.,CLOCK_MANAGER Global clock tree integrity compromised.,0
INFO,MEM_CTRL,Memory address translation successful,MEM_CTRL Memory address translation successful,1
CRITICAL,MEM_CTRL,Multiple-bit ECC error on memory region 0x10000000,MEM_CTRL Multiple-bit ECC error on memory region 0x10000000,1
INFO,CACHE_CTRL,Cache line read from main memory,CACHE_CTRL Cache line read from main memory,1
INFO,DMA_ENGINE,DMA descriptor chain processing for channel 0,DMA_ENGINE DMA descriptor chain processing for channel 0,3
CRITICAL,POWER_CTRL,Voltage rail exceeds maximum ripple specification,POWER_CTRL Voltage rail exceeds maximum ripple specification,4
INFO,MEM_CTRL,Memory page 0x100000 locked successfully for exclusive access,MEM_CTRL Memory page 0x100000 locked successfully for exclusive access,1
CRITICAL,MEM_CTRL,Memory controller arbitration logic failure,MEM_CTRL Memory controller arbitration logic failure,1
WARNING,DDR_CTRL,DDR self-refresh entry/exit latency degradation,DDR_CTRL DDR self-refresh entry/exit latency degradation,1
WARNING,POWER_CTRL,Power domain voltage overshoot detected,POWER_CTRL Power domain voltage overshoot detected,-1
CRITICAL,MEM_CTRL,Memory controller internal protocol mismatch.,MEM_CTRL Memory controller internal protocol mismatch.,1
INFO,CACHE_CTRL,Cache line marked clean,CACHE_CTRL Cache line marked clean,1
INFO,POWER_CTRL,All power domains confirmed operational,POWER_CTRL All power domains confirmed operational,4
ERROR,DMA_ENGINE,Scatter-gather list error,DMA_ENGINE Scatter-gather list error,3
WARNING,DDR_CTRL,DDR command scheduling conflicts detected,DDR_CTRL DDR command scheduling conflicts detected,1
ERROR,PCIE_CTRL,PCIe upstream port detected invalid TLP sequence number,PCIE_CTRL PCIe upstream port detected invalid TLP sequence number,6
ERROR,DMA_ENGINE,DMA configuration register corruption,DMA_ENGINE DMA configuration register corruption,3
ERROR,DMA_ENGINE,DMA transfer burst length violation,DMA_ENGINE DMA transfer burst length violation,3
ERROR,PCIE_CTRL,PCIe physical layer (PHY) training failure,PCIE_CTRL PCIe physical layer (PHY) training failure,6
INFO,INTERRUPT_CTRL,Interrupt controller entered idle state.,INTERRUPT_CTRL Interrupt controller entered idle state.,1
WARNING,CLOCK_MANAGER,Clock frequency instability observed during DVFS,CLOCK_MANAGER Clock frequency instability observed during DVFS,-1
CRITICAL,DDR_CTRL,DDR interface logic reset asserted unexpectedly,DDR_CTRL DDR interface logic reset asserted unexpectedly,1
ERROR,MEM_CTRL,Memory scrub engine encountered an uncorrectable ECC error,MEM_CTRL Memory scrub engine encountered an uncorrectable ECC error,1
ERROR,FIFO_BUF,"FIFO pointer comparison logic error, incorrect full/empty","FIFO_BUF FIFO pointer comparison logic error, incorrect full/empty",5
ERROR,POWER_CTRL,Voltage regulator thermal shutdown,POWER_CTRL Voltage regulator thermal shutdown,4
ERROR,CACHE_CTRL,Cache line invalidation sequence failure,CACHE_CTRL Cache line invalidation sequence failure,1
CRITICAL,POWER_CTRL,"Core power rail completely collapsed, system failure","POWER_CTRL Core power rail completely collapsed, system failure",4
ERROR,CLOCK_MANAGER,Clock domain crossing bridge internal error,CLOCK_MANAGER Clock domain crossing bridge internal error,0
WARNING,DMA_ENGINE,DMA channel maximum transfer size exceeded,DMA_ENGINE DMA channel maximum transfer size exceeded,3
INFO,FIFO_BUF,FIFO reset pulse successfully applied,FIFO_BUF FIFO reset pulse successfully applied,5
CRITICAL,PCIE_CTRL,"PCIe lane synchronization lost, link down (lane 7).","PCIE_CTRL PCIe lane synchronization lost, link down (lane 7).",6
ERROR,MEM_CTRL,"Memory byte lane read error, data '0x00' instead of '0xFF'","MEM_CTRL Memory byte lane read error, data '0x00' instead of '0xFF'",1
ERROR,DDR_CTRL,DDR initialization parameter mismatch,DDR_CTRL DDR initialization parameter mismatch,1
WARNING,CLOCK_MANAGER,Clock source Y stability degrading.,CLOCK_MANAGER Clock source Y stability degrading.,0
WARNING,CLOCK_MANAGER,Clock frequency slightly below target,CLOCK_MANAGER Clock frequency slightly below target,0
CRITICAL,MEM_CTRL,"Memory controller state machine entered an unexpected, unrecoverable state.","MEM_CTRL Memory controller state machine entered an unexpected, unrecoverable state.",1
ERROR,DDR_CTRL,DDR controller detected a refresh cycle miss.,DDR_CTRL DDR controller detected a refresh cycle miss.,1
INFO,INTERRUPT_CTRL,Interrupt acknowledge signal issued,INTERRUPT_CTRL Interrupt acknowledge signal issued,1
CRITICAL,DMA_ENGINE,"Global DMA engine failure, no data movement possible","DMA_ENGINE Global DMA engine failure, no data movement possible",3
ERROR,FIFO_BUF,FIFO reset not observed on all elements,FIFO_BUF FIFO reset not observed on all elements,5
WARNING,DMA_ENGINE,DMA channel busy status unexpectedly deasserted,DMA_ENGINE DMA channel busy status unexpectedly deasserted,3
CRITICAL,FIFO_BUF,"FIFO buffer corruption detected, system halt imminent","FIFO_BUF FIFO buffer corruption detected, system halt imminent",5
CRITICAL,PCIE_CTRL,PCIe link training failure during system boot,PCIE_CTRL PCIe link training failure during system boot,6
CRITICAL,CLOCK_MANAGER,"Global clock halted unexpectedly, fatal timing violation.","CLOCK_MANAGER Global clock halted unexpectedly, fatal timing violation.",0
WARNING,POWER_CTRL,Power sequence state machine stalled at 'power_on_reset',POWER_CTRL Power sequence state machine stalled at 'power_on_reset',4
WARNING,DMA_ENGINE,DMA transfer paused due to external throttle,DMA_ENGINE DMA transfer paused due to external throttle,3
ERROR,MEM_CTRL,Memory read data mismatch detected.,MEM_CTRL Memory read data mismatch detected.,1
WARNING,DDR_CTRL,DDR memory bank conflict rate exceeding threshold,DDR_CTRL DDR memory bank conflict rate exceeding threshold,1
ERROR,POWER_CTRL,Power domain reset sequence failure,POWER_CTRL Power domain reset sequence failure,4
CRITICAL,POWER_CTRL,Redundant power supply rail failure detected,POWER_CTRL Redundant power supply rail failure detected,4
ERROR,PCIE_CTRL,PCIe AER (Advanced Error Reporting) fatal error reported,PCIE_CTRL PCIe AER (Advanced Error Reporting) fatal error reported,6
INFO,INTERRUPT_CTRL,Interrupt 7 successfully masked by software,INTERRUPT_CTRL Interrupt 7 successfully masked by software,1
WARNING,DDR_CTRL,DDR ZQ calibration due soon,DDR_CTRL DDR ZQ calibration due soon,1
INFO,FIFO_BUF,"FIFO write operation successful, available space decreasing","FIFO_BUF FIFO write operation successful, available space decreasing",5
CRITICAL,POWER_CTRL,Power rail instability detected on 1.0V rail.,POWER_CTRL Power rail instability detected on 1.0V rail.,4
INFO,DMA_ENGINE,DMA channel 0 transfer initiated for 1024 bytes,DMA_ENGINE DMA channel 0 transfer initiated for 1024 bytes,3
WARNING,CLOCK_MANAGER,Clock skew measured beyond design intent,CLOCK_MANAGER Clock skew measured beyond design intent,0
INFO,FIFO_BUF,Write operation committed to internal buffer,FIFO_BUF Write operation committed to internal buffer,5
ERROR,MEM_CTRL,Memory page fault for unmapped address region.,MEM_CTRL Memory page fault for unmapped address region.,1
WARNING,CLOCK_MANAGER,PLL lock time exceeding expected range,CLOCK_MANAGER PLL lock time exceeding expected range,0
ERROR,POWER_CTRL,"Current sensor detected overcurrent event, power cycle recommended.","POWER_CTRL Current sensor detected overcurrent event, power cycle recommended.",-1
INFO,CACHE_CTRL,Cache invalidate-all operation completed,CACHE_CTRL Cache invalidate-all operation completed,1
CRITICAL,AXI_CTRL,AXI outstanding transaction count exceeded fatal limit,AXI_CTRL AXI outstanding transaction count exceeded fatal limit,2
WARNING,CLOCK_MANAGER,Clock jitter spike detected,CLOCK_MANAGER Clock jitter spike detected,0
CRITICAL,MEM_CTRL,Memory bus arbitration failure leading to system deadlock,MEM_CTRL Memory bus arbitration failure leading to system deadlock,1
CRITICAL,DMA_ENGINE,DMA engine deadlock detected,DMA_ENGINE DMA engine deadlock detected,3
ERROR,CACHE_CTRL,L2 cache line invalidation failed to propagate,CACHE_CTRL L2 cache line invalidation failed to propagate,1
WARNING,INTERRUPT_CTRL,Interrupt priority level 5 requests continuously.,INTERRUPT_CTRL Interrupt priority level 5 requests continuously.,1
WARNING,MEM_CTRL,High memory access latency detected,MEM_CTRL High memory access latency detected,1
WARNING,DDR_CTRL,DDR command bus utilization high,DDR_CTRL DDR command bus utilization high,1
ERROR,MEM_CTRL,Memory controller arbitration logic deadlock,MEM_CTRL Memory controller arbitration logic deadlock,1
ERROR,FIFO_BUF,"FIFO nearly full, write rejected","FIFO_BUF FIFO nearly full, write rejected",5
WARNING,CACHE_CTRL,"Cache write buffer full, stalls occurring","CACHE_CTRL Cache write buffer full, stalls occurring",1
WARNING,CLOCK_MANAGER,Clock frequency deviation exceeding limits,CLOCK_MANAGER Clock frequency deviation exceeding limits,0
WARNING,DDR_CTRL,DDR refresh cycle delayed (674 cycles).,DDR_CTRL DDR refresh cycle delayed (674 cycles).,1
INFO,FIFO_BUF,"Data pushed to FIFO, write operation successful.","FIFO_BUF Data pushed to FIFO, write operation successful.",5
INFO,DDR_CTRL,DDR refresh rate adjusted,DDR_CTRL DDR refresh rate adjusted,1
ERROR,INTERRUPT_CTRL,Interrupt priority inversion detected in dispatcher,INTERRUPT_CTRL Interrupt priority inversion detected in dispatcher,1
INFO,AXI_CTRL,AXI write transaction initiated,AXI_CTRL AXI write transaction initiated,2
INFO,POWER_CTRL,Power domain GFX_PD successfully entered D3 state,POWER_CTRL Power domain GFX_PD successfully entered D3 state,4
WARNING,POWER_CTRL,Power-off sequence initiated with active rails,POWER_CTRL Power-off sequence initiated with active rails,4
INFO,POWER_CTRL,Power domain Z successfully transitioned to active state.,POWER_CTRL Power domain Z successfully transitioned to active state.,4
WARNING,DMA_ENGINE,DMA channel X timeout for external handshake,DMA_ENGINE DMA channel X timeout for external handshake,3
CRITICAL,MEM_CTRL,ECC multiple bit error on memory bus,MEM_CTRL ECC multiple bit error on memory bus,1
ERROR,DDR_CTRL,DDR refresh command skipped,DDR_CTRL DDR refresh command skipped,1
INFO,POWER_CTRL,Power domain CPU activated,POWER_CTRL Power domain CPU activated,4
WARNING,INTERRUPT_CTRL,Interrupt dispatcher latency increased,INTERRUPT_CTRL Interrupt dispatcher latency increased,1
INFO,CLOCK_MANAGER,Clock output buffer enabled for module 'X',CLOCK_MANAGER Clock output buffer enabled for module 'X',0
WARNING,AXI_CTRL,AXI slave 'ethernet_mac' response time becoming erratic,AXI_CTRL AXI slave 'ethernet_mac' response time becoming erratic,2
INFO,MEM_CTRL,Memory controller standby mode entered,MEM_CTRL Memory controller standby mode entered,1
INFO,DMA_ENGINE,DMA channel 4 started a new transfer,DMA_ENGINE DMA channel 4 started a new transfer,3
INFO,CLOCK_MANAGER,Secondary clock path engaged,CLOCK_MANAGER Secondary clock path engaged,0
INFO,FIFO_BUF,FIFO read pointer decremented,FIFO_BUF FIFO read pointer decremented,5
INFO,POWER_CTRL,Power domain VDD_SRAM disabled.,POWER_CTRL Power domain VDD_SRAM disabled.,-1
ERROR,CLOCK_MANAGER,Clock enable assertion timing violation for clock System.,CLOCK_MANAGER Clock enable assertion timing violation for clock System.,0
WARNING,AXI_CTRL,Bus contention detected,AXI_CTRL Bus contention detected,2
ERROR,DMA_ENGINE,DMA channel security violation detected,DMA_ENGINE DMA channel security violation detected,3
WARNING,FIFO_BUF,FIFO latency spikes detected during peak load.,FIFO_BUF FIFO latency spikes detected during peak load.,5
CRITICAL,AXI_CTRL,AXI master asserted transaction to unmapped address,AXI_CTRL AXI master asserted transaction to unmapped address,2
WARNING,CLOCK_MANAGER,System clock frequency deviation detected,CLOCK_MANAGER System clock frequency deviation detected,0
CRITICAL,MEM_CTRL,Memory ECC logic self-test failed,MEM_CTRL Memory ECC logic self-test failed,1
ERROR,CLOCK_MANAGER,Clock generation PLL lock lost,CLOCK_MANAGER Clock generation PLL lock lost,0
ERROR,DDR_CTRL,DDR command bus arbitration conflict,DDR_CTRL DDR command bus arbitration conflict,1
ERROR,CACHE_CTRL,Cache tag comparison mismatch on critical section access,CACHE_CTRL Cache tag comparison mismatch on critical section access,1
INFO,AXI_CTRL,AXI read transaction completed successfully with OKAY response,AXI_CTRL AXI read transaction completed successfully with OKAY response,2
WARNING,DMA_ENGINE,DMA engine 'AUDIO' exhibiting degraded throughput.,DMA_ENGINE DMA engine 'AUDIO' exhibiting degraded throughput.,3
ERROR,FIFO_BUF,"FIFO underflow detected, read from empty buffer.","FIFO_BUF FIFO underflow detected, read from empty buffer.",5
CRITICAL,FIFO_BUF,Critical FIFO overflow leading to system memory corruption.,FIFO_BUF Critical FIFO overflow leading to system memory corruption.,5
WARNING,POWER_CTRL,Temperature sensor for PMIC reporting high values,POWER_CTRL Temperature sensor for PMIC reporting high values,4
INFO,AXI_CTRL,AXI bus idle for 1000 cycles,AXI_CTRL AXI bus idle for 1000 cycles,2
INFO,CACHE_CTRL,Data loaded into L2 cache successfully,CACHE_CTRL Data loaded into L2 cache successfully,1
ERROR,CLOCK_MANAGER,Clock gating logic error,CLOCK_MANAGER Clock gating logic error,0
ERROR,DMA_ENGINE,DMA descriptor fetch failed for entry 0 on channel CH0.,DMA_ENGINE DMA descriptor fetch failed for entry 0 on channel CH0.,3
CRITICAL,INTERRUPT_CTRL,"Interrupt controller deadlock detected, system unresponsive.","INTERRUPT_CTRL Interrupt controller deadlock detected, system unresponsive.",1
INFO,POWER_CTRL,System power consumption nominal,POWER_CTRL System power consumption nominal,4
INFO,AXI_CTRL,AXI ID mapping updated,AXI_CTRL AXI ID mapping updated,2
CRITICAL,DMA_ENGINE,"DMA request queue overflow, requests dropped.","DMA_ENGINE DMA request queue overflow, requests dropped.",3
ERROR,DDR_CTRL,DDR memory address alignment fault during byte lane write,DDR_CTRL DDR memory address alignment fault during byte lane write,1
CRITICAL,DMA_ENGINE,DMA controller state machine entered an unrecoverable state,DMA_ENGINE DMA controller state machine entered an unrecoverable state,3
INFO,CACHE_CTRL,Cache way allocation optimized,CACHE_CTRL Cache way allocation optimized,1
ERROR,INTERRUPT_CTRL,Interrupt controller internal bus error,INTERRUPT_CTRL Interrupt controller internal bus error,1
ERROR,PCIE_CTRL,PCIe link CRC error detected on received packet,PCIE_CTRL PCIe link CRC error detected on received packet,6
INFO,INTERRUPT_CTRL,ISR started for vector 0x0C,INTERRUPT_CTRL ISR started for vector 0x0C,1
CRITICAL,AXI_CTRL,AXI system bus deadlock detected.,AXI_CTRL AXI system bus deadlock detected.,2
INFO,POWER_CTRL,System voltage regulators confirmed operational,POWER_CTRL System voltage regulators confirmed operational,4
WARNING,PCIE_CTRL,PCIe replay buffer approaching full,PCIE_CTRL PCIe replay buffer approaching full,6
INFO,CLOCK_MANAGER,PLL locked successfully (4382MHz).,CLOCK_MANAGER PLL locked successfully (4382MHz).,0
CRITICAL,PCIE_CTRL,PCIe internal PHY clock lost lock.,PCIE_CTRL PCIe internal PHY clock lost lock.,-1
ERROR,MEM_CTRL,Unaligned memory access fault at address 0xDEADBEEF,MEM_CTRL Unaligned memory access fault at address 0xDEADBEEF,1
ERROR,DMA_ENGINE,DMA buffer pointer corruption detected on channel 12,DMA_ENGINE DMA buffer pointer corruption detected on channel 12,3
WARNING,DMA_ENGINE,DMA burst size negotiation ongoing,DMA_ENGINE DMA burst size negotiation ongoing,3
ERROR,INTERRUPT_CTRL,Interrupt acknowledge timeout detected for pending IRQ,INTERRUPT_CTRL Interrupt acknowledge timeout detected for pending IRQ,1
ERROR,CACHE_CTRL,"Cache coherence violation detected, stale data read","CACHE_CTRL Cache coherence violation detected, stale data read",1
ERROR,POWER_CTRL,Power rail 1.8V out of tolerance.,POWER_CTRL Power rail 1.8V out of tolerance.,4
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal state corruption,INTERRUPT_CTRL Interrupt controller internal state corruption,1
WARNING,FIFO_BUF,FIFO backpressure assertion prolonged,FIFO_BUF FIFO backpressure assertion prolonged,5
WARNING,CLOCK_MANAGER,Clock phase detection failed during transition,CLOCK_MANAGER Clock phase detection failed during transition,-1
WARNING,FIFO_BUF,FIFO read clock and write clock phase mismatch,FIFO_BUF FIFO read clock and write clock phase mismatch,5
ERROR,DDR_CTRL,DDR refresh command issued out of specification,DDR_CTRL DDR refresh command issued out of specification,1
WARNING,INTERRUPT_CTRL,Interrupt queue depth 75% full,INTERRUPT_CTRL Interrupt queue depth 75% full,1
INFO,MEM_CTRL,Memory controller performing background refresh,MEM_CTRL Memory controller performing background refresh,1
INFO,DDR_CTRL,DDR memory module ID detected,DDR_CTRL DDR memory module ID detected,1
CRITICAL,DMA_ENGINE,DMA channel 2 H/W assertion failure: invalid address,DMA_ENGINE DMA channel 2 H/W assertion failure: invalid address,3
WARNING,FIFO_BUF,FIFO empty state not propagated correctly,FIFO_BUF FIFO empty state not propagated correctly,5
WARNING,CLOCK_MANAGER,Clock tree power consumption exceeding budget,CLOCK_MANAGER Clock tree power consumption exceeding budget,-1
INFO,FIFO_BUF,FIFO 'output_buffer' fill level within optimal range,FIFO_BUF FIFO 'output_buffer' fill level within optimal range,5
CRITICAL,CACHE_CTRL,"Cache line dirty bit corruption, potential data loss on writeback","CACHE_CTRL Cache line dirty bit corruption, potential data loss on writeback",1
WARNING,AXI_CTRL,AXI exclusive access failed due to external master,AXI_CTRL AXI exclusive access failed due to external master,2
INFO,INTERRUPT_CTRL,Interrupt controller version read: v2.1,INTERRUPT_CTRL Interrupt controller version read: v2.1,1
CRITICAL,DMA_ENGINE,CRITICAL: DMA descriptor ring buffer corruption preventing all transfers.,DMA_ENGINE CRITICAL: DMA descriptor ring buffer corruption preventing all transfers.,3
ERROR,INTERRUPT_CTRL,Interrupt pending bit stuck,INTERRUPT_CTRL Interrupt pending bit stuck,1
WARNING,AXI_CTRL,AXI response channel stall detected for too long,AXI_CTRL AXI response channel stall detected for too long,2
ERROR,PCIE_CTRL,PCIe link state machine invalid transition,PCIE_CTRL PCIe link state machine invalid transition,6
CRITICAL,CACHE_CTRL,Unrecoverable cache tag error,CACHE_CTRL Unrecoverable cache tag error,1
ERROR,MEM_CTRL,Memory write data bit error detected on bus,MEM_CTRL Memory write data bit error detected on bus,1
CRITICAL,POWER_CTRL,Power rail monitoring system offline,POWER_CTRL Power rail monitoring system offline,-1
CRITICAL,POWER_CTRL,"Power rail instability detected on 1.8V, system shutdown.","POWER_CTRL Power rail instability detected on 1.8V, system shutdown.",4
WARNING,AXI_CTRL,AXI outstanding transaction limit nearing capacity.,AXI_CTRL AXI outstanding transaction limit nearing capacity.,2
INFO,PCIE_CTRL,PCIe speed negotiation completed at Gen4 x8,PCIE_CTRL PCIe speed negotiation completed at Gen4 x8,6
ERROR,PCIE_CTRL,PCIe Downstream Port receive buffer overflow,PCIE_CTRL PCIe Downstream Port receive buffer overflow,6
ERROR,DMA_ENGINE,DMA descriptor read error,DMA_ENGINE DMA descriptor read error,3
WARNING,INTERRUPT_CTRL,Interrupt pending counter overflow,INTERRUPT_CTRL Interrupt pending counter overflow,1
ERROR,FIFO_BUF,"FIFO underflow detected, read from empty queue","FIFO_BUF FIFO underflow detected, read from empty queue",5
WARNING,MEM_CTRL,Soft ECC error detected (single bit flip) at 0x48e42f63.,MEM_CTRL Soft ECC error detected (single bit flip) at 0x48e42f63.,1
ERROR,POWER_CTRL,Voltage regulator output outside nominal range,POWER_CTRL Voltage regulator output outside nominal range,4
INFO,PCIE_CTRL,PCIe device hot-plug detection,PCIE_CTRL PCIe device hot-plug detection,6
WARNING,INTERRUPT_CTRL,Interrupt priority inversion detected,INTERRUPT_CTRL Interrupt priority inversion detected,1
CRITICAL,PCIE_CTRL,PCIe link entered permanent error state (DL_Down),PCIE_CTRL PCIe link entered permanent error state (DL_Down),6
INFO,DDR_CTRL,DDR memory configured for burst of 8,DDR_CTRL DDR memory configured for burst of 8,1
INFO,INTERRUPT_CTRL,Pending interrupt cleared for CPU core 0.,INTERRUPT_CTRL Pending interrupt cleared for CPU core 0.,1
ERROR,DMA_ENGINE,DMA internal state machine entered an illegal state,DMA_ENGINE DMA internal state machine entered an illegal state,3
WARNING,AXI_CTRL,AXI write burst with non-incremental address observed,AXI_CTRL AXI write burst with non-incremental address observed,2
INFO,FIFO_BUF,"Read operation successful, FIFO depth now X","FIFO_BUF Read operation successful, FIFO depth now X",5
WARNING,FIFO_BUF,FIFO read threshold approaching critical level,FIFO_BUF FIFO read threshold approaching critical level,5
ERROR,INTERRUPT_CTRL,Interrupt masking register corruption,INTERRUPT_CTRL Interrupt masking register corruption,1
INFO,DMA_ENGINE,DMA channel 11 configured for new transfer,DMA_ENGINE DMA channel 11 configured for new transfer,3
INFO,CACHE_CTRL,Cache coherence update processed,CACHE_CTRL Cache coherence update processed,1
INFO,MEM_CTRL,Memory region 0x2000-0x3000 released,MEM_CTRL Memory region 0x2000-0x3000 released,1
INFO,CLOCK_MANAGER,Clock frequency scaled down successfully,CLOCK_MANAGER Clock frequency scaled down successfully,0
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding maximum threshold,INTERRUPT_CTRL Interrupt latency exceeding maximum threshold,1
INFO,POWER_CTRL,Power-on reset sequence completed,POWER_CTRL Power-on reset sequence completed,4
ERROR,INTERRUPT_CTRL,Interrupt controller failed to clear pending status,INTERRUPT_CTRL Interrupt controller failed to clear pending status,1
ERROR,MEM_CTRL,ECC uncorrectable error detected,MEM_CTRL ECC uncorrectable error detected,1
ERROR,AXI_CTRL,"AXI_CTRL: bus contention - bus arbitration failure detected. (Master ID: 4, AXI ID: 15)","AXI_CTRL AXI_CTRL: bus contention - bus arbitration failure detected. (Master ID: 4, AXI ID: 15)",2
INFO,FIFO_BUF,"FIFO write operation successful, 32 entries free","FIFO_BUF FIFO write operation successful, 32 entries free",5
INFO,MEM_CTRL,Memory scrub operation completed,MEM_CTRL Memory scrub operation completed,1
CRITICAL,PCIE_CTRL,"PCIe root complex communication failure, device isolated","PCIE_CTRL PCIe root complex communication failure, device isolated",6
INFO,CLOCK_MANAGER,Clock phase detection successful,CLOCK_MANAGER Clock phase detection successful,0
WARNING,DDR_CTRL,DDR refresh interval approaching maximum allowed limit.,DDR_CTRL DDR refresh interval approaching maximum allowed limit.,1
ERROR,MEM_CTRL,"Memory ECC error count threshold exceeded, forcing shutdown","MEM_CTRL Memory ECC error count threshold exceeded, forcing shutdown",1
CRITICAL,DDR_CTRL,DDR memory channel initialization timeout,DDR_CTRL DDR memory channel initialization timeout,1
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure between CPU_DOMAIN and DDR_DOMAIN.,CLOCK_MANAGER Clock domain crossing synchronization failure between CPU_DOMAIN and DDR_DOMAIN.,0
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, high latency risk","FIFO_BUF FIFO read pointer approaching write pointer, high latency risk",5
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal watchdog timeout,INTERRUPT_CTRL Interrupt controller internal watchdog timeout,1
INFO,CACHE_CTRL,Data cache line invalidated by M-state change,CACHE_CTRL Data cache line invalidated by M-state change,1
INFO,MEM_CTRL,Memory protection unit disabled,MEM_CTRL Memory protection unit disabled,1
ERROR,FIFO_BUF,FIFO read data corruption detected,FIFO_BUF FIFO read data corruption detected,5
INFO,CLOCK_MANAGER,Clock spread spectrum modulation enabled,CLOCK_MANAGER Clock spread spectrum modulation enabled,-1
INFO,INTERRUPT_CTRL,Interrupt handler execution completed,INTERRUPT_CTRL Interrupt handler execution completed,1
ERROR,CLOCK_MANAGER,Clock domain crossing bridge 'SYS_TO_PERIPH' asserted error,CLOCK_MANAGER Clock domain crossing bridge 'SYS_TO_PERIPH' asserted error,0
WARNING,DMA_ENGINE,DMA buffer fill level approaching saturation,DMA_ENGINE DMA buffer fill level approaching saturation,3
WARNING,CACHE_CTRL,Cache write-through policy causing performance degradation,CACHE_CTRL Cache write-through policy causing performance degradation,1
WARNING,FIFO_BUF,FIFO 'debug_log' write pointer lagging significantly behind expected,FIFO_BUF FIFO 'debug_log' write pointer lagging significantly behind expected,5
ERROR,MEM_CTRL,Memory access detected out of bounds,MEM_CTRL Memory access detected out of bounds,1
INFO,AXI_CTRL,AXI read burst completed with OKAY response.,AXI_CTRL AXI read burst completed with OKAY response.,2
INFO,PCIE_CTRL,PCIe configuration space read successful.,PCIE_CTRL PCIe configuration space read successful.,6
ERROR,AXI_CTRL,AXI read data integrity check failed,AXI_CTRL AXI read data integrity check failed,2
CRITICAL,PCIE_CTRL,"PCIe endpoint response timeout, link down","PCIE_CTRL PCIe endpoint response timeout, link down",6
INFO,DMA_ENGINE,DMA engine idle state entered,DMA_ENGINE DMA engine idle state entered,3
WARNING,AXI_CTRL,AXI slave burst transaction reordering detected,AXI_CTRL AXI slave burst transaction reordering detected,2
CRITICAL,AXI_CTRL,"AXI bridge FSM entered unrecoverable state, invalid state transition.","AXI_CTRL AXI bridge FSM entered unrecoverable state, invalid state transition.",-1
ERROR,DDR_CTRL,DDR row hammer detection triggered,DDR_CTRL DDR row hammer detection triggered,-1
CRITICAL,MEM_CTRL,"Memory controller state machine entered invalid state, system unresponsive","MEM_CTRL Memory controller state machine entered invalid state, system unresponsive",1
WARNING,FIFO_BUF,FIFO output data parity error detected,FIFO_BUF FIFO output data parity error detected,5
INFO,MEM_CTRL,Memory access to boot ROM,MEM_CTRL Memory access to boot ROM,1
CRITICAL,FIFO_BUF,FIFO control FSM in permanent deadlock.,FIFO_BUF FIFO control FSM in permanent deadlock.,5
INFO,DDR_CTRL,Read latency optimized for current operating frequency,DDR_CTRL Read latency optimized for current operating frequency,1
ERROR,CACHE_CTRL,Cache tag parity error detected for set 121.,CACHE_CTRL Cache tag parity error detected for set 121.,1
INFO,FIFO_BUF,FIFO ID 0x3B configured for asynchronous operation,FIFO_BUF FIFO ID 0x3B configured for asynchronous operation,5
WARNING,PCIE_CTRL,Flow control update pending,PCIE_CTRL Flow control update pending,6
ERROR,INTERRUPT_CTRL,Multiple interrupt sources asserting same vector unexpectedly.,INTERRUPT_CTRL Multiple interrupt sources asserting same vector unexpectedly.,1
INFO,AXI_CTRL,Slave 0x1000 acknowledged write transaction,AXI_CTRL Slave 0x1000 acknowledged write transaction,2
WARNING,DDR_CTRL,DDR self-refresh entry/exit timing margin reduced,DDR_CTRL DDR self-refresh entry/exit timing margin reduced,1
ERROR,MEM_CTRL,Memory read data corruption,MEM_CTRL Memory read data corruption,1
WARNING,MEM_CTRL,Memory scrubbing cycle initiated.,MEM_CTRL Memory scrubbing cycle initiated.,1
INFO,MEM_CTRL,Memory map established,MEM_CTRL Memory map established,1
WARNING,DMA_ENGINE,"DMA channel blocked, awaiting resources","DMA_ENGINE DMA channel blocked, awaiting resources",3
INFO,AXI_CTRL,AXI write response channel status `OKAY`,AXI_CTRL AXI write response channel status `OKAY`,2
INFO,CACHE_CTRL,Cache line de-allocated,CACHE_CTRL Cache line de-allocated,1
ERROR,POWER_CTRL,Voltage monitoring unit detected overcurrent on main rail,POWER_CTRL Voltage monitoring unit detected overcurrent on main rail,4
CRITICAL,DDR_CTRL,DDR initialization sequence timeout,DDR_CTRL DDR initialization sequence timeout,1
WARNING,MEM_CTRL,Memory write latency exceeding specification,MEM_CTRL Memory write latency exceeding specification,1
ERROR,CACHE_CTRL,CACHE_CTRL: protocol mismatch - invalid handshake sequence detected.,CACHE_CTRL CACHE_CTRL: protocol mismatch - invalid handshake sequence detected.,1
WARNING,CACHE_CTRL,Cache line writeback queue nearly full.,CACHE_CTRL Cache line writeback queue nearly full.,1
WARNING,AXI_CTRL,AXI outstanding write requests nearing saturation,AXI_CTRL AXI outstanding write requests nearing saturation,2
ERROR,CACHE_CTRL,Cache tag RAM data corruption detected,CACHE_CTRL Cache tag RAM data corruption detected,1
INFO,CACHE_CTRL,Cache line eviction policy set to LRU,CACHE_CTRL Cache line eviction policy set to LRU,1
WARNING,DDR_CTRL,DDR training eye margin reduced,DDR_CTRL DDR training eye margin reduced,1
WARNING,FIFO_BUF,FIFO programmable almost full threshold reached,FIFO_BUF FIFO programmable almost full threshold reached,5
WARNING,PCIE_CTRL,PCIe completion with unexpected requester ID,PCIE_CTRL PCIe completion with unexpected requester ID,6
WARNING,DMA_ENGINE,"DMA channel X bandwidth saturation detected, bus contention.","DMA_ENGINE DMA channel X bandwidth saturation detected, bus contention.",3
ERROR,FIFO_BUF,FIFO status register corruption,FIFO_BUF FIFO status register corruption,5
WARNING,CLOCK_MANAGER,Clock domain crossing path setup violation margin low,CLOCK_MANAGER Clock domain crossing path setup violation margin low,0
INFO,POWER_CTRL,Core voltage rail ramped up successfully,POWER_CTRL Core voltage rail ramped up successfully,4
ERROR,DMA_ENGINE,DMA transfer completion error reported,DMA_ENGINE DMA transfer completion error reported,3
ERROR,POWER_CTRL,Voltage regulator 'VCC_IO' output voltage outside tolerance,POWER_CTRL Voltage regulator 'VCC_IO' output voltage outside tolerance,4
ERROR,DDR_CTRL,Memory controller arbitration conflict,DDR_CTRL Memory controller arbitration conflict,1
ERROR,INTERRUPT_CTRL,Interrupt source ID mismatch detected,INTERRUPT_CTRL Interrupt source ID mismatch detected,1
CRITICAL,POWER_CTRL,System thermal shutdown initiated,POWER_CTRL System thermal shutdown initiated,4
ERROR,FIFO_BUF,FIFO full flag not deasserted after read,FIFO_BUF FIFO full flag not deasserted after read,5
ERROR,PCIE_CTRL,PCIe configuration space access error for device GPU at 0xABCDEF01.,PCIE_CTRL PCIe configuration space access error for device GPU at 0xABCDEF01.,6
INFO,MEM_CTRL,Memory region 0x0-0xFFF cleared,MEM_CTRL Memory region 0x0-0xFFF cleared,1
WARNING,DMA_ENGINE,DMA channel 9 burst data read completion delayed,DMA_ENGINE DMA channel 9 burst data read completion delayed,3
INFO,INTERRUPT_CTRL,All pending interrupts serviced,INTERRUPT_CTRL All pending interrupts serviced,1
INFO,CLOCK_MANAGER,Secondary clock domain enabled.,CLOCK_MANAGER Secondary clock domain enabled.,0
WARNING,DDR_CTRL,DDR low-power state entry delay,DDR_CTRL DDR low-power state entry delay,1
WARNING,CLOCK_MANAGER,"Clock domain crossing detected, potential metastability hazard","CLOCK_MANAGER Clock domain crossing detected, potential metastability hazard",0
WARNING,CACHE_CTRL,"Cache eviction queue nearing capacity, potential performance impact","CACHE_CTRL Cache eviction queue nearing capacity, potential performance impact",1
ERROR,INTERRUPT_CTRL,Interrupt controller internal register corruption,INTERRUPT_CTRL Interrupt controller internal register corruption,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller core logic unresponsive,INTERRUPT_CTRL Interrupt controller core logic unresponsive,1
WARNING,FIFO_BUF,"FIFO fill level at 85%, approaching full","FIFO_BUF FIFO fill level at 85%, approaching full",5
WARNING,CACHE_CTRL,Cache pollution detected from non-cached region,CACHE_CTRL Cache pollution detected from non-cached region,1
ERROR,CACHE_CTRL,Cache set 7 replacement policy failure,CACHE_CTRL Cache set 7 replacement policy failure,1
WARNING,DMA_ENGINE,DMA control register write pending,DMA_ENGINE DMA control register write pending,3
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lost lock, system reset pending","CLOCK_MANAGER Clock generation PLL lost lock, system reset pending",0
CRITICAL,DMA_ENGINE,"DMA channel 10 enters unrecoverable error state, system impact","DMA_ENGINE DMA channel 10 enters unrecoverable error state, system impact",3
ERROR,PCIE_CTRL,PCIe link retraining failed multiple times,PCIE_CTRL PCIe link retraining failed multiple times,6
ERROR,DDR_CTRL,DDR MR4 register write failed (temperature sensor read),DDR_CTRL DDR MR4 register write failed (temperature sensor read),-1
INFO,DDR_CTRL,DDR_CTRL module initialized.,DDR_CTRL DDR_CTRL module initialized.,1
ERROR,CLOCK_MANAGER,Clock domain isolation register mismatch,CLOCK_MANAGER Clock domain isolation register mismatch,-1
WARNING,MEM_CTRL,"Parity error detected during memory read, single bit corrected","MEM_CTRL Parity error detected during memory read, single bit corrected",1
WARNING,CACHE_CTRL,Cache write buffer accumulating entries,CACHE_CTRL Cache write buffer accumulating entries,1
INFO,AXI_CTRL,AXI interconnect configuration loaded successfully.,AXI_CTRL AXI interconnect configuration loaded successfully.,2
INFO,CLOCK_MANAGER,Oscillator enabled,CLOCK_MANAGER Oscillator enabled,0
INFO,MEM_CTRL,Memory block 0x2000-0x2FFF cleared.,MEM_CTRL Memory block 0x2000-0x2FFF cleared.,1
CRITICAL,AXI_CTRL,AXI interconnect deadlock detected on read channel,AXI_CTRL AXI interconnect deadlock detected on read channel,2
INFO,MEM_CTRL,Memory arbitration granted to core 1,MEM_CTRL Memory arbitration granted to core 1,1
ERROR,DMA_ENGINE,DMA completion status register error,DMA_ENGINE DMA completion status register error,3
INFO,CACHE_CTRL,Cache flush operation completed for address range.,CACHE_CTRL Cache flush operation completed for address range.,1
CRITICAL,DMA_ENGINE,"DMA engine register access deadlock, programming frozen","DMA_ENGINE DMA engine register access deadlock, programming frozen",3
WARNING,PCIE_CTRL,PCIe internal error counter incremented,PCIE_CTRL PCIe internal error counter incremented,6
ERROR,PCIE_CTRL,PCIe Link Down status persisted,PCIE_CTRL PCIe Link Down status persisted,6
WARNING,CLOCK_MANAGER,Clock integrity monitor reporting minor glitches,CLOCK_MANAGER Clock integrity monitor reporting minor glitches,0
CRITICAL,AXI_CTRL,AXI coherency protocol violation,AXI_CTRL AXI coherency protocol violation,2
CRITICAL,MEM_CTRL,Uncorrectable cache data corruption,MEM_CTRL Uncorrectable cache data corruption,1
INFO,MEM_CTRL,Memory bank 0 initialized to default values,MEM_CTRL Memory bank 0 initialized to default values,1
CRITICAL,CACHE_CTRL,Cache hierarchy coherence failure,CACHE_CTRL Cache hierarchy coherence failure,1
CRITICAL,CLOCK_MANAGER,CLOCK_MANAGER: System-level clock domain crossing failure detected. Unrecoverable hardware state. (asynchronous bridge synchronization failure),CLOCK_MANAGER CLOCK_MANAGER: System-level clock domain crossing failure detected. Unrecoverable hardware state. (asynchronous bridge synchronization failure),0
ERROR,FIFO_BUF,FIFO pointer comparison error,FIFO_BUF FIFO pointer comparison error,5
WARNING,PCIE_CTRL,PCIe message signaled interrupt queue nearing capacity,PCIE_CTRL PCIe message signaled interrupt queue nearing capacity,6
WARNING,DDR_CTRL,DDR read data CRC mismatch,DDR_CTRL DDR read data CRC mismatch,1
INFO,CLOCK_MANAGER,Clock gate enable signal stuck,CLOCK_MANAGER Clock gate enable signal stuck,0
WARNING,CLOCK_MANAGER,Reference clock input stability degraded,CLOCK_MANAGER Reference clock input stability degraded,0
CRITICAL,AXI_CTRL,AXI bus matrix arbitration deadlock detected,AXI_CTRL AXI bus matrix arbitration deadlock detected,2
INFO,CACHE_CTRL,Cache line clean operation completed,CACHE_CTRL Cache line clean operation completed,1
CRITICAL,MEM_CTRL,"Memory bus deadlock detected, unrecoverable.","MEM_CTRL Memory bus deadlock detected, unrecoverable.",1
ERROR,MEM_CTRL,Memory read-modify-write atomic operation failed,MEM_CTRL Memory read-modify-write atomic operation failed,1
INFO,POWER_CTRL,Low power entry sequence completed successfully,POWER_CTRL Low power entry sequence completed successfully,4
ERROR,PCIE_CTRL,Invalid Vendor ID read,PCIE_CTRL Invalid Vendor ID read,6
WARNING,AXI_CTRL,AXI read data channel ready assertion delayed,AXI_CTRL AXI read data channel ready assertion delayed,2
ERROR,MEM_CTRL,Memory address bus signal integrity issue,MEM_CTRL Memory address bus signal integrity issue,1
WARNING,FIFO_BUF,FIFO write operation nearing timeout,FIFO_BUF FIFO write operation nearing timeout,5
INFO,MEM_CTRL,Memory region deallocated successfully,MEM_CTRL Memory region deallocated successfully,1
INFO,CLOCK_MANAGER,Clock domain crossing bridge synchronization confirmed,CLOCK_MANAGER Clock domain crossing bridge synchronization confirmed,0
ERROR,INTERRUPT_CTRL,Interrupt service routine pointer corrupted,INTERRUPT_CTRL Interrupt service routine pointer corrupted,1
CRITICAL,FIFO_BUF,FIFO internal FSM stuck in intermediate state,FIFO_BUF FIFO internal FSM stuck in intermediate state,5
CRITICAL,CLOCK_MANAGER,Clock tree synthesis mismatch detected,CLOCK_MANAGER Clock tree synthesis mismatch detected,0
INFO,CLOCK_MANAGER,Clock skew measured within tolerance,CLOCK_MANAGER Clock skew measured within tolerance,0
WARNING,AXI_CTRL,AXI slave response delay exceeding verification limits,AXI_CTRL AXI slave response delay exceeding verification limits,2
INFO,POWER_CTRL,Voltage scaling successfully applied to VDD_GPU,POWER_CTRL Voltage scaling successfully applied to VDD_GPU,4
WARNING,PCIE_CTRL,PCIe lane 0 signal integrity degraded.,PCIE_CTRL PCIe lane 0 signal integrity degraded.,6
INFO,CACHE_CTRL,L1 data cache invalidation request processed,CACHE_CTRL L1 data cache invalidation request processed,1
WARNING,PCIE_CTRL,PCIe receive buffer nearing overflow,PCIE_CTRL PCIe receive buffer nearing overflow,6
INFO,POWER_CTRL,Power domain isolation successful,POWER_CTRL Power domain isolation successful,4
CRITICAL,MEM_CTRL,"Double bit ECC corruption detected, unrecoverable data loss at 0x933D72B9","MEM_CTRL Double bit ECC corruption detected, unrecoverable data loss at 0x933D72B9",1
CRITICAL,FIFO_BUF,FIFO control logic entered an undefined state,FIFO_BUF FIFO control logic entered an undefined state,5
ERROR,DMA_ENGINE,DMA control FSM in invalid state,DMA_ENGINE DMA control FSM in invalid state,3
WARNING,CACHE_CTRL,Cache directory write contention,CACHE_CTRL Cache directory write contention,1
INFO,DDR_CTRL,DDR memory initialization sequence completed.,DDR_CTRL DDR memory initialization sequence completed.,1
INFO,DMA_ENGINE,Engine idle,DMA_ENGINE Engine idle,3
CRITICAL,DMA_ENGINE,Unrecoverable DMA transfer error.,DMA_ENGINE Unrecoverable DMA transfer error.,3
CRITICAL,CACHE_CTRL,Cache controller state machine entered invalid state.,CACHE_CTRL Cache controller state machine entered invalid state.,1
INFO,FIFO_BUF,FIFO_BUF_18 read operation successful,FIFO_BUF FIFO_BUF_18 read operation successful,5
ERROR,POWER_CTRL,Power domain Core failed to power up.,POWER_CTRL Power domain Core failed to power up.,4
WARNING,CLOCK_MANAGER,Clock input stability marginal,CLOCK_MANAGER Clock input stability marginal,0
INFO,CLOCK_MANAGER,Clock buffer bypass enabled,CLOCK_MANAGER Clock buffer bypass enabled,0
INFO,INTERRUPT_CTRL,Pending interrupt detected and queued,INTERRUPT_CTRL Pending interrupt detected and queued,1
INFO,DMA_ENGINE,DMA descriptor queue head updated,DMA_ENGINE DMA descriptor queue head updated,3
CRITICAL,AXI_CTRL,AXI deadlock detected on crossbar interconnect,AXI_CTRL AXI deadlock detected on crossbar interconnect,2
ERROR,POWER_CTRL,Thermal shutdown due to temperature threshold exceedance,POWER_CTRL Thermal shutdown due to temperature threshold exceedance,4
CRITICAL,AXI_CTRL,AXI interconnect permanent deadlock detected,AXI_CTRL AXI interconnect permanent deadlock detected,2
WARNING,DMA_ENGINE,Channel busy for extended duration,DMA_ENGINE Channel busy for extended duration,3
INFO,DDR_CTRL,Memory refresh cycle executed successfully,DDR_CTRL Memory refresh cycle executed successfully,1
WARNING,PCIE_CTRL,PCIe transaction retry count increasing,PCIE_CTRL PCIe transaction retry count increasing,6
INFO,AXI_CTRL,AXI slave 0x2 reporting no errors,AXI_CTRL AXI slave 0x2 reporting no errors,2
WARNING,DMA_ENGINE,DMA transaction timeout on read from peripheral.,DMA_ENGINE DMA transaction timeout on read from peripheral.,3
INFO,FIFO_BUF,"Read operation successful, FIFO now at 50% capacity","FIFO_BUF Read operation successful, FIFO now at 50% capacity",5
WARNING,POWER_CTRL,Power domain isolation register write access attempted by unauthorized module,POWER_CTRL Power domain isolation register write access attempted by unauthorized module,4
ERROR,PCIE_CTRL,PCIe transaction layer packet (TLP) header parity error,PCIE_CTRL PCIe transaction layer packet (TLP) header parity error,6
CRITICAL,PCIE_CTRL,PCIe configuration space corruption,PCIE_CTRL PCIe configuration space corruption,6
CRITICAL,PCIE_CTRL,PCIe link synchronization lost after several retries,PCIE_CTRL PCIe link synchronization lost after several retries,6
INFO,CLOCK_MANAGER,PLL lock acquired successfully,CLOCK_MANAGER PLL lock acquired successfully,0
INFO,PCIE_CTRL,PCIe device BAR configuration completed.,PCIE_CTRL PCIe device BAR configuration completed.,6
ERROR,PCIE_CTRL,PCIe Lane skew detected,PCIE_CTRL PCIe Lane skew detected,6
INFO,DMA_ENGINE,DMA engine idle after completing all transfers.,DMA_ENGINE DMA engine idle after completing all transfers.,3
INFO,PCIE_CTRL,PCIe link up with full functionality and speed,PCIE_CTRL PCIe link up with full functionality and speed,6
ERROR,DDR_CTRL,DDR memory controller detected illegal bank command sequence.,DDR_CTRL DDR memory controller detected illegal bank command sequence.,1
ERROR,FIFO_BUF,FIFO data corruption detected during read,FIFO_BUF FIFO data corruption detected during read,5
WARNING,PCIE_CTRL,PCIe retry buffer utilization above 70%,PCIE_CTRL PCIe retry buffer utilization above 70%,6
ERROR,DMA_ENGINE,"DMA descriptor fetch failed from memory, descriptor corrupted","DMA_ENGINE DMA descriptor fetch failed from memory, descriptor corrupted",3
INFO,CACHE_CTRL,CACHE_CTRL self-test sequence completed.,CACHE_CTRL CACHE_CTRL self-test sequence completed.,-1
ERROR,CACHE_CTRL,Directory lookup failure,CACHE_CTRL Directory lookup failure,1
INFO,DMA_ENGINE,DMA burst length configured to 16 beats,DMA_ENGINE DMA burst length configured to 16 beats,3
INFO,DMA_ENGINE,DMA descriptor queue flushed for channel 5,DMA_ENGINE DMA descriptor queue flushed for channel 5,3
INFO,AXI_CTRL,AXI transaction ID 0x123 completed.,AXI_CTRL AXI transaction ID 0x123 completed.,2
CRITICAL,CLOCK_MANAGER,"System clock integrity compromised, critical hardware error.","CLOCK_MANAGER System clock integrity compromised, critical hardware error.",0
WARNING,DMA_ENGINE,"Scatter-gather list parsing warning, potential descriptor skip","DMA_ENGINE Scatter-gather list parsing warning, potential descriptor skip",3
WARNING,FIFO_BUF,"FIFO almost empty threshold reached, requesting more data","FIFO_BUF FIFO almost empty threshold reached, requesting more data",5
INFO,PCIE_CTRL,PCIe device reset sequence completed,PCIE_CTRL PCIe device reset sequence completed,6
ERROR,INTERRUPT_CTRL,Interrupt priority inversion detected for IRQ 8,INTERRUPT_CTRL Interrupt priority inversion detected for IRQ 8,1
WARNING,CACHE_CTRL,"Cache eviction queue nearing capacity, thrashing risk","CACHE_CTRL Cache eviction queue nearing capacity, thrashing risk",1
ERROR,PCIE_CTRL,PCIe hot reset detected,PCIE_CTRL PCIe hot reset detected,6
CRITICAL,DDR_CTRL,"DDR calibration failed, memory unusable","DDR_CTRL DDR calibration failed, memory unusable",1
ERROR,DMA_ENGINE,DMA buffer descriptor invalid address,DMA_ENGINE DMA buffer descriptor invalid address,3
ERROR,DMA_ENGINE,DMA descriptor checksum mismatch,DMA_ENGINE DMA descriptor checksum mismatch,3
CRITICAL,MEM_CTRL,Persistent multi-bit ECC error on memory bank 2,MEM_CTRL Persistent multi-bit ECC error on memory bank 2,1
WARNING,DDR_CTRL,DDR temperature sensor reporting elevated levels,DDR_CTRL DDR temperature sensor reporting elevated levels,1
WARNING,POWER_CTRL,Voltage rail ripple observed,POWER_CTRL Voltage rail ripple observed,4
CRITICAL,POWER_CTRL,System power-on reset sequence stalled,POWER_CTRL System power-on reset sequence stalled,4
WARNING,CACHE_CTRL,Cache write buffer nearly full,CACHE_CTRL Cache write buffer nearly full,1
WARNING,DDR_CTRL,DDR memory refresh cycle delayed due to high traffic,DDR_CTRL DDR memory refresh cycle delayed due to high traffic,1
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold of 20 cycles.,FIFO_BUF FIFO latency exceeding expected threshold of 20 cycles.,5
ERROR,AXI_CTRL,AXI slave response invalid on read transaction,AXI_CTRL AXI slave response invalid on read transaction,2
CRITICAL,DDR_CTRL,DDR memory module 0 reports critical temperature,DDR_CTRL DDR memory module 0 reports critical temperature,1
WARNING,DMA_ENGINE,DMA_ENGINE resource allocation nearing limit (86% utilized).,DMA_ENGINE DMA_ENGINE resource allocation nearing limit (86% utilized).,3
WARNING,CACHE_CTRL,Dirty line count high,CACHE_CTRL Dirty line count high,1
ERROR,CLOCK_MANAGER,PLL feedback path open loop detected,CLOCK_MANAGER PLL feedback path open loop detected,0
INFO,POWER_CTRL,Voltage regulator output within spec.,POWER_CTRL Voltage regulator output within spec.,4
CRITICAL,MEM_CTRL,"CRITICAL: Multi-bit ECC uncorrectable error, memory integrity compromised at 0xDEADBEEF.","MEM_CTRL CRITICAL: Multi-bit ECC uncorrectable error, memory integrity compromised at 0xDEADBEEF.",1
CRITICAL,AXI_CTRL,AXI interconnect bridge deadlock,AXI_CTRL AXI interconnect bridge deadlock,2
ERROR,AXI_CTRL,AXI AW channel handshake timeout,AXI_CTRL AXI AW channel handshake timeout,2
INFO,FIFO_BUF,FIFO_BUF debug status collected.,FIFO_BUF FIFO_BUF debug status collected.,5
CRITICAL,CLOCK_MANAGER,Clock generation PLL lock lost.,CLOCK_MANAGER Clock generation PLL lock lost.,0
CRITICAL,PCIE_CTRL,PCIe internal clock recovery unit lock lost,PCIE_CTRL PCIe internal clock recovery unit lock lost,-1
INFO,AXI_CTRL,AXI master completed all pending transactions,AXI_CTRL AXI master completed all pending transactions,2
WARNING,DMA_ENGINE,DMA channel priority not correctly honored,DMA_ENGINE DMA channel priority not correctly honored,3
WARNING,AXI_CTRL,AXI read burst completion delayed,AXI_CTRL AXI read burst completion delayed,2
CRITICAL,MEM_CTRL,"Critical memory corruption detected, system integrity compromised.","MEM_CTRL Critical memory corruption detected, system integrity compromised.",1
CRITICAL,CLOCK_MANAGER,"Main system PLL lost lock, clock unstable","CLOCK_MANAGER Main system PLL lost lock, clock unstable",0
ERROR,MEM_CTRL,Memory protection unit violation detected,MEM_CTRL Memory protection unit violation detected,1
INFO,INTERRUPT_CTRL,Interrupt controller peripheral ID read successful,INTERRUPT_CTRL Interrupt controller peripheral ID read successful,1
ERROR,DMA_ENGINE,DMA descriptor ring buffer overflow,DMA_ENGINE DMA descriptor ring buffer overflow,3
ERROR,DDR_CTRL,DDR read data CRC mismatch detected,DDR_CTRL DDR read data CRC mismatch detected,1
ERROR,DMA_ENGINE,DMA destination address out of bounds,DMA_ENGINE DMA destination address out of bounds,3
INFO,POWER_CTRL,Voltage rail stable,POWER_CTRL Voltage rail stable,4
ERROR,DDR_CTRL,DDR read data capture timing error,DDR_CTRL DDR read data capture timing error,1
CRITICAL,FIFO_BUF,FIFO clock domain crossing bridge failure,FIFO_BUF FIFO clock domain crossing bridge failure,5
WARNING,FIFO_BUF,Excessive read latency detected,FIFO_BUF Excessive read latency detected,5
ERROR,CLOCK_MANAGER,Clock enable signal glitch detected,CLOCK_MANAGER Clock enable signal glitch detected,0
INFO,DMA_ENGINE,Operation on DMA_ENGINE completed successfully.,DMA_ENGINE Operation on DMA_ENGINE completed successfully.,3
CRITICAL,DDR_CTRL,"DDR controller entered critical error state, memory access halted.","DDR_CTRL DDR controller entered critical error state, memory access halted.",1
INFO,AXI_CTRL,AXI read transaction completed,AXI_CTRL AXI read transaction completed,2
CRITICAL,PCIE_CTRL,"PCIe link training failed repeatedly, permanent link down","PCIE_CTRL PCIe link training failed repeatedly, permanent link down",6
CRITICAL,FIFO_BUF,FIFO internal pointer addresses out of bounds,FIFO_BUF FIFO internal pointer addresses out of bounds,5
ERROR,CACHE_CTRL,"Cache eviction queue full, unable to evict","CACHE_CTRL Cache eviction queue full, unable to evict",1
INFO,DDR_CTRL,DDR memory entered low-power mode,DDR_CTRL DDR memory entered low-power mode,1
ERROR,MEM_CTRL,Memory controller state machine entered an unexpected 'IDLE_WAIT' state,MEM_CTRL Memory controller state machine entered an unexpected 'IDLE_WAIT' state,1
INFO,MEM_CTRL,Memory bank 0x3 opened successfully.,MEM_CTRL Memory bank 0x3 opened successfully.,1
INFO,DDR_CTRL,DDR memory integrity check passed,DDR_CTRL DDR memory integrity check passed,1
CRITICAL,MEM_CTRL,Uncorrectable memory data error.,MEM_CTRL Uncorrectable memory data error.,1
CRITICAL,MEM_CTRL,Memory controller state machine entered invalid state (ACTIVE -> INVALID).,MEM_CTRL Memory controller state machine entered invalid state (ACTIVE -> INVALID).,1
CRITICAL,POWER_CTRL,Voltage regulator X reported catastrophic failure,POWER_CTRL Voltage regulator X reported catastrophic failure,4
INFO,DMA_ENGINE,Memory-to-memory transfer 0x2000 to 0x3000 completed,DMA_ENGINE Memory-to-memory transfer 0x2000 to 0x3000 completed,-1
ERROR,CACHE_CTRL,Cache data array corruption detected,CACHE_CTRL Cache data array corruption detected,1
WARNING,CACHE_CTRL,Cache coherence messages experiencing delay,CACHE_CTRL Cache coherence messages experiencing delay,1
INFO,INTERRUPT_CTRL,Interrupt controller in low-power mode,INTERRUPT_CTRL Interrupt controller in low-power mode,-1
WARNING,AXI_CTRL,AXI outstanding transactions exceeding threshold (69/119),AXI_CTRL AXI outstanding transactions exceeding threshold (69/119),2
INFO,POWER_CTRL,Voltage regulator VDD_LOGIC output stable at 1.05V,POWER_CTRL Voltage regulator VDD_LOGIC output stable at 1.05V,4
INFO,CACHE_CTRL,Cache tag RAM initialization complete,CACHE_CTRL Cache tag RAM initialization complete,1
CRITICAL,CLOCK_MANAGER,Primary system clock signal lost,CLOCK_MANAGER Primary system clock signal lost,0
WARNING,PCIE_CTRL,PCIe transaction layer packet (TLP) error rate increasing,PCIE_CTRL PCIe transaction layer packet (TLP) error rate increasing,6
CRITICAL,DDR_CTRL,DDR command queue became unresponsive,DDR_CTRL DDR command queue became unresponsive,1
INFO,FIFO_BUF,FIFO read operation acknowledged,FIFO_BUF FIFO read operation acknowledged,5
INFO,DMA_ENGINE,Descriptor processed,DMA_ENGINE Descriptor processed,3
CRITICAL,MEM_CTRL,Memory BIST (Built-In Self-Test) failed at address 0xDEADBEEF,MEM_CTRL Memory BIST (Built-In Self-Test) failed at address 0xDEADBEEF,1
INFO,FIFO_BUF,FIFO read operation completed,FIFO_BUF FIFO read operation completed,5
CRITICAL,CLOCK_MANAGER,Global clock tree routing error,CLOCK_MANAGER Global clock tree routing error,0
ERROR,MEM_CTRL,"Single bit error corrected by ECC, threshold reached","MEM_CTRL Single bit error corrected by ECC, threshold reached",1
WARNING,FIFO_BUF,"Output FIFO almost empty, potential underflow risk","FIFO_BUF Output FIFO almost empty, potential underflow risk",5
WARNING,PCIE_CTRL,"PCIe link degradation detected, falling back to lower speed","PCIE_CTRL PCIe link degradation detected, falling back to lower speed",6
ERROR,AXI_CTRL,Decode error (DECERR) on address,AXI_CTRL Decode error (DECERR) on address,2
INFO,POWER_CTRL,Power state transition completed.,POWER_CTRL Power state transition completed.,4
INFO,DDR_CTRL,DDR memory rank configuration applied,DDR_CTRL DDR memory rank configuration applied,1
WARNING,PCIE_CTRL,PCIe endpoint device not responding to enumeration,PCIE_CTRL PCIe endpoint device not responding to enumeration,6
WARNING,PCIE_CTRL,PCIe receiver buffer nearing overflow,PCIE_CTRL PCIe receiver buffer nearing overflow,6
ERROR,PCIE_CTRL,PCIe TLP (Transaction Layer Packet) format error,PCIE_CTRL PCIe TLP (Transaction Layer Packet) format error,6
ERROR,PCIE_CTRL,PCIe completion timeout for request 0x1234,PCIE_CTRL PCIe completion timeout for request 0x1234,6
INFO,INTERRUPT_CTRL,Software interrupt (SWI) generated,INTERRUPT_CTRL Software interrupt (SWI) generated,1
CRITICAL,AXI_CTRL,AXI protocol violation: AWVALID/WVALID asserted without ARREADY,AXI_CTRL AXI protocol violation: AWVALID/WVALID asserted without ARREADY,2
INFO,MEM_CTRL,Memory bank 0 refresh completed,MEM_CTRL Memory bank 0 refresh completed,1
INFO,CLOCK_MANAGER,System clock output re-enabled.,CLOCK_MANAGER System clock output re-enabled.,0
ERROR,POWER_CTRL,Power-up sequence failure: core voltage not stable,POWER_CTRL Power-up sequence failure: core voltage not stable,4
ERROR,INTERRUPT_CTRL,Interrupt vector mismatch for acknowledged IRQ,INTERRUPT_CTRL Interrupt vector mismatch for acknowledged IRQ,1
WARNING,FIFO_BUF,FIFO fill level consistently high,FIFO_BUF FIFO fill level consistently high,5
CRITICAL,MEM_CTRL,Memory controller internal register corruption,MEM_CTRL Memory controller internal register corruption,1
INFO,CLOCK_MANAGER,Clock monitoring unit active,CLOCK_MANAGER Clock monitoring unit active,0
ERROR,CLOCK_MANAGER,"Clock synchronizer ""sync_reg_1"" metastability detected","CLOCK_MANAGER Clock synchronizer ""sync_reg_1"" metastability detected",0
WARNING,DDR_CTRL,"DDR command queue build-up, latency increasing (avg 20 cycles)","DDR_CTRL DDR command queue build-up, latency increasing (avg 20 cycles)",1
INFO,AXI_CTRL,AXI transaction successfully completed,AXI_CTRL AXI transaction successfully completed,2
WARNING,INTERRUPT_CTRL,Interrupt queue depth exceeded 70%,INTERRUPT_CTRL Interrupt queue depth exceeded 70%,1
CRITICAL,DDR_CTRL,DDR controller state machine entered invalid state.,DDR_CTRL DDR controller state machine entered invalid state.,1
INFO,CACHE_CTRL,Cache line invalidated at address 0x1000C000.,CACHE_CTRL Cache line invalidated at address 0x1000C000.,1
WARNING,PCIE_CTRL,PCIe message signaled interrupt (MSI) delivery delayed,PCIE_CTRL PCIe message signaled interrupt (MSI) delivery delayed,6
WARNING,POWER_CTRL,Voltage drop detected on GFX rail,POWER_CTRL Voltage drop detected on GFX rail,4
CRITICAL,MEM_CTRL,Memory controller reported multiple ECC errors in single memory word,MEM_CTRL Memory controller reported multiple ECC errors in single memory word,1
INFO,POWER_CTRL,Power sequence controller advancing to next state,POWER_CTRL Power sequence controller advancing to next state,4
CRITICAL,INTERRUPT_CTRL,Interrupt controller power rail instability detected.,INTERRUPT_CTRL Interrupt controller power rail instability detected.,4
WARNING,DMA_ENGINE,DMA descriptor fetch latency high,DMA_ENGINE DMA descriptor fetch latency high,3
INFO,MEM_CTRL,Single-bit ECC correction applied to read data.,MEM_CTRL Single-bit ECC correction applied to read data.,1
INFO,CACHE_CTRL,Cache clean operation completed,CACHE_CTRL Cache clean operation completed,1
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on peripheral bridge,CLOCK_MANAGER Clock domain crossing synchronization failure on peripheral bridge,0
ERROR,MEM_CTRL,"Memory controller ECC single bit error on address 0x12345678, corrected","MEM_CTRL Memory controller ECC single bit error on address 0x12345678, corrected",1
INFO,POWER_CTRL,Power state transition to D0 (Full Power) completed,POWER_CTRL Power state transition to D0 (Full Power) completed,4
WARNING,DDR_CTRL,DDR command re-ordering latency significant,DDR_CTRL DDR command re-ordering latency significant,1
ERROR,AXI_CTRL,AXI write response channel 'BVALID' de-asserted prematurely,AXI_CTRL AXI write response channel 'BVALID' de-asserted prematurely,2
CRITICAL,DMA_ENGINE,"DMA engine fatal error, unrecoverable state","DMA_ENGINE DMA engine fatal error, unrecoverable state",3
CRITICAL,MEM_CTRL,Memory controller state machine entered an unknown state,MEM_CTRL Memory controller state machine entered an unknown state,1
INFO,DDR_CTRL,DDR command scheduler operating normally,DDR_CTRL DDR command scheduler operating normally,1
ERROR,FIFO_BUF,FIFO data corruption detected during read operation,FIFO_BUF FIFO data corruption detected during read operation,5
CRITICAL,PCIE_CTRL,"PCIe root complex unrecoverable error, device communication lost.","PCIE_CTRL PCIe root complex unrecoverable error, device communication lost.",6
ERROR,POWER_CTRL,Power supply unit (PSU) reporting fault.,POWER_CTRL Power supply unit (PSU) reporting fault.,4
WARNING,FIFO_BUF,FIFO input stream showing bursts exceeding expected rate,FIFO_BUF FIFO input stream showing bursts exceeding expected rate,5
ERROR,MEM_CTRL,Memory page fault detected.,MEM_CTRL Memory page fault detected.,1
INFO,FIFO_BUF,Data flow re-established,FIFO_BUF Data flow re-established,5
ERROR,POWER_CTRL,System PMIC (Power Management IC) communication error,POWER_CTRL System PMIC (Power Management IC) communication error,4
INFO,INTERRUPT_CTRL,Interrupt source ID 15 currently masked,INTERRUPT_CTRL Interrupt source ID 15 currently masked,1
ERROR,PCIE_CTRL,PCIe configuration transaction error,PCIE_CTRL PCIe configuration transaction error,6
WARNING,MEM_CTRL,Memory wear-leveling algorithm reporting high cell wear,MEM_CTRL Memory wear-leveling algorithm reporting high cell wear,-1
INFO,DMA_ENGINE,DMA transfer paused for debug purposes,DMA_ENGINE DMA transfer paused for debug purposes,3
INFO,INTERRUPT_CTRL,External interrupt received,INTERRUPT_CTRL External interrupt received,1
ERROR,CLOCK_MANAGER,PLL frequency deviation detected,CLOCK_MANAGER PLL frequency deviation detected,0
ERROR,CACHE_CTRL,"Cache tag entry parity error on way 2, index 0x100","CACHE_CTRL Cache tag entry parity error on way 2, index 0x100",1
WARNING,FIFO_BUF,Output FIFO 'tx_fifo' fill level below low watermark,FIFO_BUF Output FIFO 'tx_fifo' fill level below low watermark,5
ERROR,DMA_ENGINE,DMA scatter-gather list parsing error,DMA_ENGINE DMA scatter-gather list parsing error,3
ERROR,CLOCK_MANAGER,Reset synchronizer for module X detected an asynchronous input,CLOCK_MANAGER Reset synchronizer for module X detected an asynchronous input,-1
ERROR,PCIE_CTRL,PCIe Poisoned TLP detected,PCIE_CTRL PCIe Poisoned TLP detected,6
INFO,FIFO_BUF,Data successfully popped from FIFO,FIFO_BUF Data successfully popped from FIFO,5
WARNING,DDR_CTRL,DDR memory controller arbitration fairness issue,DDR_CTRL DDR memory controller arbitration fairness issue,1
WARNING,AXI_CTRL,AXI slave response delay exceeds specification,AXI_CTRL AXI slave response delay exceeds specification,2
ERROR,PCIE_CTRL,PCIe link CRC error rate above acceptable limit,PCIE_CTRL PCIe link CRC error rate above acceptable limit,6
WARNING,POWER_CTRL,Core voltage rail VDD_CORE showing minor fluctuations,POWER_CTRL Core voltage rail VDD_CORE showing minor fluctuations,4
INFO,FIFO_BUF,"Write operation successful, FIFO occupancy 30%","FIFO_BUF Write operation successful, FIFO occupancy 30%",5
ERROR,AXI_CTRL,AXI read response timeout,AXI_CTRL AXI read response timeout,2
CRITICAL,DMA_ENGINE,DMA descriptor fetching hardware became unresponsive,DMA_ENGINE DMA descriptor fetching hardware became unresponsive,3
ERROR,AXI_CTRL,"AXI_CTRL: bus contention - bus arbitration failure detected. (Master ID: 6, AXI ID: 0)","AXI_CTRL AXI_CTRL: bus contention - bus arbitration failure detected. (Master ID: 6, AXI ID: 0)",2
INFO,POWER_CTRL,Core voltage rail enabled,POWER_CTRL Core voltage rail enabled,4
ERROR,AXI_CTRL,AXI read address and write address channels observed to be in deadlock,AXI_CTRL AXI read address and write address channels observed to be in deadlock,2
ERROR,FIFO_BUF,FIFO synchronization across clock domains failed,FIFO_BUF FIFO synchronization across clock domains failed,5
ERROR,CLOCK_MANAGER,"Clock reset sequence failed, internal error.","CLOCK_MANAGER Clock reset sequence failed, internal error.",0
INFO,CACHE_CTRL,Cache line 0xFF0000 marked dirty,CACHE_CTRL Cache line 0xFF0000 marked dirty,1
WARNING,PCIE_CTRL,PCIe link state fluctuating between L0 and L1,PCIE_CTRL PCIe link state fluctuating between L0 and L1,6
ERROR,MEM_CTRL,Double-bit ECC corruption detected in memory bank 0.,MEM_CTRL Double-bit ECC corruption detected in memory bank 0.,1
INFO,CACHE_CTRL,Cache invalidated for process ID.,CACHE_CTRL Cache invalidated for process ID.,-1
ERROR,INTERRUPT_CTRL,Interrupt mask register value self-modified,INTERRUPT_CTRL Interrupt mask register value self-modified,1
WARNING,POWER_CTRL,Brownout detection circuit triggered momentarily,POWER_CTRL Brownout detection circuit triggered momentarily,4
ERROR,FIFO_BUF,FIFO boundary check failed on write,FIFO_BUF FIFO boundary check failed on write,5
INFO,POWER_CTRL,Power state D0 entered,POWER_CTRL Power state D0 entered,4
WARNING,CLOCK_MANAGER,Clock network skew increasing,CLOCK_MANAGER Clock network skew increasing,0
ERROR,CLOCK_MANAGER,Gated clock output glitch detected for peripheral,CLOCK_MANAGER Gated clock output glitch detected for peripheral,0
ERROR,CACHE_CTRL,Cache line invalidation not propagated to all agents,CACHE_CTRL Cache line invalidation not propagated to all agents,1
INFO,DDR_CTRL,DDR bank activate command successful,DDR_CTRL DDR bank activate command successful,1
WARNING,DMA_ENGINE,DMA transfer completion status pending for too long,DMA_ENGINE DMA transfer completion status pending for too long,3
WARNING,DDR_CTRL,DDR timing margin low.,DDR_CTRL DDR timing margin low.,1
ERROR,FIFO_BUF,FIFO read data path corruption,FIFO_BUF FIFO read data path corruption,5
ERROR,FIFO_BUF,FIFO_DEBUG_IN synchronization error,FIFO_BUF FIFO_DEBUG_IN synchronization error,5
WARNING,DDR_CTRL,DDR access latency exceeding specification,DDR_CTRL DDR access latency exceeding specification,1
WARNING,MEM_CTRL,Memory write buffer nearing full,MEM_CTRL Memory write buffer nearing full,1
CRITICAL,CLOCK_MANAGER,Clock manager detected unrecoverable clock tree error,CLOCK_MANAGER Clock manager detected unrecoverable clock tree error,0
ERROR,MEM_CTRL,MEM_CTRL: parity error - data bus parity mismatch detected.,MEM_CTRL MEM_CTRL: parity error - data bus parity mismatch detected.,1
CRITICAL,POWER_CTRL,Power rail ripple exceeding 20% of nominal voltage,POWER_CTRL Power rail ripple exceeding 20% of nominal voltage,4
CRITICAL,POWER_CTRL,"Power rail instability detected, critical voltage drop","POWER_CTRL Power rail instability detected, critical voltage drop",4
ERROR,DMA_ENGINE,DMA channel descriptor buffer overflow,DMA_ENGINE DMA channel descriptor buffer overflow,3
ERROR,PCIE_CTRL,PCIe hot-reset asserted,PCIE_CTRL PCIe hot-reset asserted,6
INFO,MEM_CTRL,Memory controller self-test passed,MEM_CTRL Memory controller self-test passed,1
INFO,CACHE_CTRL,Cache controller reset to clean state,CACHE_CTRL Cache controller reset to clean state,1
WARNING,POWER_CTRL,Core rail voltage slightly below nominal,POWER_CTRL Core rail voltage slightly below nominal,4
ERROR,AXI_CTRL,AXI read data phase timing violation detected on slave 'S0',AXI_CTRL AXI read data phase timing violation detected on slave 'S0',2
WARNING,POWER_CTRL,Voltage rail VDD_IO marginally out of range (1.27V),POWER_CTRL Voltage rail VDD_IO marginally out of range (1.27V),-1
ERROR,PCIE_CTRL,PCIe packet framing error detected on lane 4.,PCIE_CTRL PCIe packet framing error detected on lane 4.,6
WARNING,CLOCK_MANAGER,Clock domain crossing buffer nearing overflow,CLOCK_MANAGER Clock domain crossing buffer nearing overflow,0
CRITICAL,DDR_CTRL,"DDR memory controller deadlock, memory access impossible","DDR_CTRL DDR memory controller deadlock, memory access impossible",1
INFO,POWER_CTRL,Power-on reset sequence complete,POWER_CTRL Power-on reset sequence complete,4
WARNING,INTERRUPT_CTRL,"Spurious interrupt detected, vector lookup failure","INTERRUPT_CTRL Spurious interrupt detected, vector lookup failure",1
WARNING,AXI_CTRL,AXI_CTRL interface handshake with AXI_CTRL showing sporadic delays.,AXI_CTRL AXI_CTRL interface handshake with AXI_CTRL showing sporadic delays.,2
WARNING,CLOCK_MANAGER,Clock domain crossing FIFO_CTRL_01 nearing overflow.,CLOCK_MANAGER Clock domain crossing FIFO_CTRL_01 nearing overflow.,0
CRITICAL,POWER_CTRL,"Power-on sequence failure, system unresponsive","POWER_CTRL Power-on sequence failure, system unresponsive",4
ERROR,CLOCK_MANAGER,PLL output frequency out of spec,CLOCK_MANAGER PLL output frequency out of spec,0
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range between domains Y and Z.,CLOCK_MANAGER Clock skew approaching unsafe range between domains Y and Z.,0
ERROR,CACHE_CTRL,Cache line '0xABCD' marked dirty but data doesn't match memory,CACHE_CTRL Cache line '0xABCD' marked dirty but data doesn't match memory,1
INFO,FIFO_BUF,Write pointer updated,FIFO_BUF Write pointer updated,5
INFO,DDR_CTRL,DDR burst length configured to 8,DDR_CTRL DDR burst length configured to 8,1
INFO,POWER_CTRL,Power state C1 entered,POWER_CTRL Power state C1 entered,4
INFO,FIFO_BUF,FIFO depth reconfigured to 128 entries,FIFO_BUF FIFO depth reconfigured to 128 entries,5
WARNING,DMA_ENGINE,DMA transfer completion delayed on channel 1,DMA_ENGINE DMA transfer completion delayed on channel 1,3
WARNING,CLOCK_MANAGER,Clock tree buffer output drive strength degradation,CLOCK_MANAGER Clock tree buffer output drive strength degradation,0
WARNING,DMA_ENGINE,DMA channel 3 pending transfers exceeding target,DMA_ENGINE DMA channel 3 pending transfers exceeding target,3
WARNING,INTERRUPT_CTRL,Interrupt handler for vector 0x20 is taking too long.,INTERRUPT_CTRL Interrupt handler for vector 0x20 is taking too long.,1
CRITICAL,DMA_ENGINE,DMA engine detected a data integrity failure during buffer transfer,DMA_ENGINE DMA engine detected a data integrity failure during buffer transfer,3
INFO,POWER_CTRL,Power sequencing logic initialized,POWER_CTRL Power sequencing logic initialized,4
INFO,CLOCK_MANAGER,Clock gating enabled for module,CLOCK_MANAGER Clock gating enabled for module,0
WARNING,DMA_ENGINE,DMA transfer rate below expected performance,DMA_ENGINE DMA transfer rate below expected performance,3
CRITICAL,INTERRUPT_CTRL,Interrupt controller internal bus contention deadlock,INTERRUPT_CTRL Interrupt controller internal bus contention deadlock,1
ERROR,PCIE_CTRL,PCIe configuration space write error,PCIE_CTRL PCIe configuration space write error,6
INFO,AXI_CTRL,AXI handshake completed (ARVALID/ARREADY),AXI_CTRL AXI handshake completed (ARVALID/ARREADY),2
INFO,MEM_CTRL,Memory controller initialized successfully,MEM_CTRL Memory controller initialized successfully,1
CRITICAL,POWER_CTRL,Overcurrent condition detected on 12V rail,POWER_CTRL Overcurrent condition detected on 12V rail,4
ERROR,PCIE_CTRL,PCIe TLP CRC error detected on ingress,PCIE_CTRL PCIe TLP CRC error detected on ingress,6
CRITICAL,DMA_ENGINE,DMA engine internal state corruption detected,DMA_ENGINE DMA engine internal state corruption detected,3
CRITICAL,PCIE_CTRL,PCIe TLP header corruption leading to link instability,PCIE_CTRL PCIe TLP header corruption leading to link instability,6
INFO,CACHE_CTRL,Cache line invalidated for address 0x2000,CACHE_CTRL Cache line invalidated for address 0x2000,1
WARNING,CLOCK_MANAGER,Clock propagation delay variation observed during mode change,CLOCK_MANAGER Clock propagation delay variation observed during mode change,-1
INFO,POWER_CTRL,Voltage rail 'VDD_CORE' stable at 0.9V,POWER_CTRL Voltage rail 'VDD_CORE' stable at 0.9V,4
INFO,DMA_ENGINE,DMA channel 16 configured to high priority,DMA_ENGINE DMA channel 16 configured to high priority,3
WARNING,AXI_CTRL,AXI write data channel FIFO nearing capacity,AXI_CTRL AXI write data channel FIFO nearing capacity,2
ERROR,CLOCK_MANAGER,Internal oscillator output unstable,CLOCK_MANAGER Internal oscillator output unstable,0
ERROR,CLOCK_MANAGER,Clock gate logic anomaly detected,CLOCK_MANAGER Clock gate logic anomaly detected,0
INFO,FIFO_BUF,Data written to FIFO at address 0x10,FIFO_BUF Data written to FIFO at address 0x10,5
INFO,CACHE_CTRL,Cache line fill buffer active,CACHE_CTRL Cache line fill buffer active,1
INFO,CACHE_CTRL,Cache line invalidated,CACHE_CTRL Cache line invalidated,1
ERROR,AXI_CTRL,Write transaction ID mismatch detected on AXI interconnect,AXI_CTRL Write transaction ID mismatch detected on AXI interconnect,2
WARNING,INTERRUPT_CTRL,Interrupt queue approaching limit: 67/103 entries used,INTERRUPT_CTRL Interrupt queue approaching limit: 67/103 entries used,1
INFO,POWER_CTRL,Low power mode enabled,POWER_CTRL Low power mode enabled,4
WARNING,PCIE_CTRL,PCIe error reporting mechanism triggered,PCIE_CTRL PCIe error reporting mechanism triggered,6
ERROR,CACHE_CTRL,Cache way invalidation failure,CACHE_CTRL Cache way invalidation failure,1
CRITICAL,MEM_CTRL,"ECC parity mismatch detected, memory data integrity compromised at 0x933D72B9","MEM_CTRL ECC parity mismatch detected, memory data integrity compromised at 0x933D72B9",1
INFO,INTERRUPT_CTRL,Interrupt enable for watchdog timer asserted,INTERRUPT_CTRL Interrupt enable for watchdog timer asserted,-1
WARNING,AXI_CTRL,AXI read burst alignment violation on slave 0x3,AXI_CTRL AXI read burst alignment violation on slave 0x3,2
CRITICAL,PCIE_CTRL,Link training sequence permanently failed,PCIE_CTRL Link training sequence permanently failed,6
INFO,DDR_CTRL,DDR training sequence complete,DDR_CTRL DDR training sequence complete,1
WARNING,DDR_CTRL,DDR read latency percentile exceeding 99th percentile,DDR_CTRL DDR read latency percentile exceeding 99th percentile,1
CRITICAL,PCIE_CTRL,"PCIe lane synchronization lost, physical link down","PCIE_CTRL PCIe lane synchronization lost, physical link down",6
ERROR,PCIE_CTRL,"PCIe hot-plug event detected, but device not recognized","PCIE_CTRL PCIe hot-plug event detected, but device not recognized",6
ERROR,DDR_CTRL,DDR memory address alignment violation,DDR_CTRL DDR memory address alignment violation,1
WARNING,CLOCK_MANAGER,"Clock jitter exceeding tolerance, timing violation detected.","CLOCK_MANAGER Clock jitter exceeding tolerance, timing violation detected.",0
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold (15%) for CPU_0,CACHE_CTRL Cache miss rate exceeding expected threshold (15%) for CPU_0,1
INFO,DDR_CTRL,DDR memory clock 1.2V rail stable,DDR_CTRL DDR memory clock 1.2V rail stable,1
WARNING,PCIE_CTRL,PCIe device ID mismatch during enumeration,PCIE_CTRL PCIe device ID mismatch during enumeration,6
WARNING,FIFO_BUF,FIFO write pointer approaching read pointer after wrap,FIFO_BUF FIFO write pointer approaching read pointer after wrap,5
ERROR,DDR_CTRL,Memory refresh command not acknowledged,DDR_CTRL Memory refresh command not acknowledged,1
INFO,CLOCK_MANAGER,PLL lock re-acquired after brief instability,CLOCK_MANAGER PLL lock re-acquired after brief instability,0
CRITICAL,MEM_CTRL,"Memory protection unit (MPU) violation detected, unauthorized access","MEM_CTRL Memory protection unit (MPU) violation detected, unauthorized access",1
WARNING,CACHE_CTRL,Cache dirty line count exceeding 90% of total.,CACHE_CTRL Cache dirty line count exceeding 90% of total.,1
WARNING,PCIE_CTRL,PCIe device hot-reset initiated,PCIE_CTRL PCIe device hot-reset initiated,6
CRITICAL,POWER_CTRL,Core power rail oscillating rapidly,POWER_CTRL Core power rail oscillating rapidly,4
INFO,FIFO_BUF,FIFO watermark level 1 reached,FIFO_BUF FIFO watermark level 1 reached,5
WARNING,CACHE_CTRL,Cache eviction rate exceeding expected threshold,CACHE_CTRL Cache eviction rate exceeding expected threshold,1
ERROR,INTERRUPT_CTRL,"Interrupt pending status corruption, protocol mismatch.","INTERRUPT_CTRL Interrupt pending status corruption, protocol mismatch.",1
CRITICAL,DDR_CTRL,DDR memory controller initialization aborted,DDR_CTRL DDR memory controller initialization aborted,1
ERROR,INTERRUPT_CTRL,"Stale interrupt pending after acknowledgement, checking for race condition","INTERRUPT_CTRL Stale interrupt pending after acknowledgement, checking for race condition",1
ERROR,PCIE_CTRL,PCIe device power state transition error,PCIE_CTRL PCIe device power state transition error,6
WARNING,CLOCK_MANAGER,PLL lock time exceeding nominal,CLOCK_MANAGER PLL lock time exceeding nominal,0
INFO,CACHE_CTRL,Cache line eviction completed for address 0xABCD,CACHE_CTRL Cache line eviction completed for address 0xABCD,1
WARNING,AXI_CTRL,AXI write channel experiencing increased latency,AXI_CTRL AXI write channel experiencing increased latency,2
WARNING,INTERRUPT_CTRL,Interrupt service routine execution time warning,INTERRUPT_CTRL Interrupt service routine execution time warning,1
INFO,MEM_CTRL,Memory access granted to debug unit,MEM_CTRL Memory access granted to debug unit,1
WARNING,CACHE_CTRL,Cache tag directory full,CACHE_CTRL Cache tag directory full,1
INFO,INTERRUPT_CTRL,Interrupt pending register cleared,INTERRUPT_CTRL Interrupt pending register cleared,1
INFO,INTERRUPT_CTRL,Interrupt handler registered successfully,INTERRUPT_CTRL Interrupt handler registered successfully,1
ERROR,DMA_ENGINE,DMA channel 11 descriptor fetch timeout,DMA_ENGINE DMA channel 11 descriptor fetch timeout,3
CRITICAL,POWER_CTRL,"System power loss detected, unrecoverable state","POWER_CTRL System power loss detected, unrecoverable state",4
ERROR,PCIE_CTRL,"PCIe Data Link Layer CRC error on received TLP, retry initiated","PCIE_CTRL PCIe Data Link Layer CRC error on received TLP, retry initiated",6
ERROR,CLOCK_MANAGER,CLOCK_MANAGER encountered an unexpected state machine fault event (state machine logic inconsistency).,CLOCK_MANAGER CLOCK_MANAGER encountered an unexpected state machine fault event (state machine logic inconsistency).,0
WARNING,AXI_CTRL,"AXI slave response timeout for ID 0x03, retrying transaction","AXI_CTRL AXI slave response timeout for ID 0x03, retrying transaction",2
ERROR,CLOCK_MANAGER,Clock skew detected on critical path,CLOCK_MANAGER Clock skew detected on critical path,0
WARNING,PCIE_CTRL,PCIe message signaled interrupt queue depth nearing limit,PCIE_CTRL PCIe message signaled interrupt queue depth nearing limit,6
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for IRQ 3,INTERRUPT_CTRL Interrupt dispatch completed for IRQ 3,1
ERROR,DDR_CTRL,DDR memory training sequence timeout,DDR_CTRL DDR memory training sequence timeout,1
INFO,DMA_ENGINE,DMA descriptor pre-fetch enabled,DMA_ENGINE DMA descriptor pre-fetch enabled,3
WARNING,INTERRUPT_CTRL,Spurious interrupt detected from module XYZ,INTERRUPT_CTRL Spurious interrupt detected from module XYZ,1
ERROR,MEM_CTRL,"Single-bit ECC correction failed for bank 1, data corrupted","MEM_CTRL Single-bit ECC correction failed for bank 1, data corrupted",1
WARNING,CLOCK_MANAGER,Clock source switching warning,CLOCK_MANAGER Clock source switching warning,0
WARNING,DMA_ENGINE,DMA descriptor fetching rate slowing down,DMA_ENGINE DMA descriptor fetching rate slowing down,3
INFO,CLOCK_MANAGER,PLL re-locked after minor drift.,CLOCK_MANAGER PLL re-locked after minor drift.,0
WARNING,AXI_CTRL,AXI write response delay from slave,AXI_CTRL AXI write response delay from slave,2
INFO,FIFO_BUF,"FIFO write pointer at 0x10, current fill level 16","FIFO_BUF FIFO write pointer at 0x10, current fill level 16",5
CRITICAL,MEM_CTRL,Memory address lines stuck at value X,MEM_CTRL Memory address lines stuck at value X,1
ERROR,MEM_CTRL,Memory controller state machine entered illegal state,MEM_CTRL Memory controller state machine entered illegal state,1
WARNING,MEM_CTRL,"Memory controller queue full for writes, delaying CPU","MEM_CTRL Memory controller queue full for writes, delaying CPU",1
WARNING,AXI_CTRL,AXI outstanding transaction count nearing threshold,AXI_CTRL AXI outstanding transaction count nearing threshold,2
ERROR,CLOCK_MANAGER,Clock domain crossing bridge for Control Path C-D detected data corruption.,CLOCK_MANAGER Clock domain crossing bridge for Control Path C-D detected data corruption.,0
CRITICAL,MEM_CTRL,Memory bank 0 data corruption detected,MEM_CTRL Memory bank 0 data corruption detected,1
WARNING,CLOCK_MANAGER,System clock phase noise exceeding specification,CLOCK_MANAGER System clock phase noise exceeding specification,0
ERROR,CLOCK_MANAGER,Clock generator state machine fault.,CLOCK_MANAGER Clock generator state machine fault.,0
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance on peripheral clock,CLOCK_MANAGER Clock jitter exceeding tolerance on peripheral clock,0
ERROR,DMA_ENGINE,DMA descriptor fetch address alignment violation detected,DMA_ENGINE DMA descriptor fetch address alignment violation detected,3
WARNING,POWER_CTRL,Current draw exceeding soft limit,POWER_CTRL Current draw exceeding soft limit,4
WARNING,CLOCK_MANAGER,Clock source switching detected,CLOCK_MANAGER Clock source switching detected,0
WARNING,FIFO_BUF,Input FIFO buffer occupancy at 90%,FIFO_BUF Input FIFO buffer occupancy at 90%,5
WARNING,CLOCK_MANAGER,Clock source health monitor indicating degradation,CLOCK_MANAGER Clock source health monitor indicating degradation,0
CRITICAL,FIFO_BUF,Persistent FIFO pointer corruption leading to data integrity loss,FIFO_BUF Persistent FIFO pointer corruption leading to data integrity loss,5
WARNING,PCIE_CTRL,PCIe link status register reporting minor errors,PCIE_CTRL PCIe link status register reporting minor errors,6
WARNING,DMA_ENGINE,DMA descriptor ring buffer nearly full,DMA_ENGINE DMA descriptor ring buffer nearly full,3
WARNING,INTERRUPT_CTRL,Interrupt controller register read-modify-write failure,INTERRUPT_CTRL Interrupt controller register read-modify-write failure,1
WARNING,CLOCK_MANAGER,Clock domain crossing FIFO 'sync_data' approaching full,CLOCK_MANAGER Clock domain crossing FIFO 'sync_data' approaching full,0
CRITICAL,DDR_CTRL,"DDR initialization timeout, DRAM unresponsive","DDR_CTRL DDR initialization timeout, DRAM unresponsive",1
INFO,FIFO_BUF,FIFO_BUF entered idle state.,FIFO_BUF FIFO_BUF entered idle state.,-1
INFO,INTERRUPT_CTRL,Global interrupt enable set.,INTERRUPT_CTRL Global interrupt enable set.,1
WARNING,FIFO_BUF,"FIFO almost empty, asserting underflow warning","FIFO_BUF FIFO almost empty, asserting underflow warning",5
INFO,FIFO_BUF,FIFO 'rx_status' has 5 entries,FIFO_BUF FIFO 'rx_status' has 5 entries,-1
CRITICAL,MEM_CTRL,Memory controller encountered a permanent bus error response,MEM_CTRL Memory controller encountered a permanent bus error response,1
WARNING,AXI_CTRL,AXI master 0x01 burst request exceeded maximum allowed length,AXI_CTRL AXI master 0x01 burst request exceeded maximum allowed length,2
INFO,INTERRUPT_CTRL,Interrupt acknowledge signal asserted,INTERRUPT_CTRL Interrupt acknowledge signal asserted,1
ERROR,DDR_CTRL,DDR memory refresh failed to execute within critical window,DDR_CTRL DDR memory refresh failed to execute within critical window,1
INFO,INTERRUPT_CTRL,INTERRUPT_CTRL self-test passed.,INTERRUPT_CTRL INTERRUPT_CTRL self-test passed.,-1
ERROR,PCIE_CTRL,PCIe device hot-reset failure,PCIE_CTRL PCIe device hot-reset failure,6
WARNING,DMA_ENGINE,DMA channel resource contention,DMA_ENGINE DMA channel resource contention,3
ERROR,FIFO_BUF,FIFO_BUF detected a severe buffer overflow: write past end of buffer. (FIFO 'FIFO_BUF' Depth: 196),FIFO_BUF FIFO_BUF detected a severe buffer overflow: write past end of buffer. (FIFO 'FIFO_BUF' Depth: 196),5
WARNING,PCIE_CTRL,PCIe transaction layer retry count incrementing rapidly,PCIE_CTRL PCIe transaction layer retry count incrementing rapidly,6
CRITICAL,CLOCK_MANAGER,Critical clock MUX selected invalid input,CLOCK_MANAGER Critical clock MUX selected invalid input,0
CRITICAL,MEM_CTRL,Unrecoverable memory access stall.,MEM_CTRL Unrecoverable memory access stall.,1
CRITICAL,AXI_CTRL,AXI master detected unexpected RRESP for read transaction,AXI_CTRL AXI master detected unexpected RRESP for read transaction,2
WARNING,MEM_CTRL,Memory bank conflict detected.,MEM_CTRL Memory bank conflict detected.,1
ERROR,CACHE_CTRL,Cache tag RAM data mismatch,CACHE_CTRL Cache tag RAM data mismatch,1
ERROR,FIFO_BUF,FIFO empty flag stuck deasserted,FIFO_BUF FIFO empty flag stuck deasserted,5
CRITICAL,MEM_CTRL,Memory ECC logic reported uncorrectable multi-bit error,MEM_CTRL Memory ECC logic reported uncorrectable multi-bit error,1
INFO,POWER_CTRL,System power state transitioned to active,POWER_CTRL System power state transitioned to active,4
CRITICAL,CLOCK_MANAGER,"Critical clock domain unrecoverable, system cannot operate","CLOCK_MANAGER Critical clock domain unrecoverable, system cannot operate",0
CRITICAL,POWER_CTRL,Power management unit enters fatal error state,POWER_CTRL Power management unit enters fatal error state,4
WARNING,AXI_CTRL,AXI write channel stall due to slave ready de-assertion,AXI_CTRL AXI write channel stall due to slave ready de-assertion,2
CRITICAL,CACHE_CTRL,Cache power domain corruption detected.,CACHE_CTRL Cache power domain corruption detected.,-1
INFO,AXI_CTRL,AXI slave 'PERIPH_01' responded with SLVERR for a write transaction,AXI_CTRL AXI slave 'PERIPH_01' responded with SLVERR for a write transaction,2
WARNING,DDR_CTRL,DDR refresh command issued late,DDR_CTRL DDR refresh command issued late,1
ERROR,AXI_CTRL,AXI slave response error (SLVERR),AXI_CTRL AXI slave response error (SLVERR),2
WARNING,CLOCK_MANAGER,Reference clock frequency deviation,CLOCK_MANAGER Reference clock frequency deviation,0
CRITICAL,DDR_CTRL,DDR memory controller internal bus deadlock,DDR_CTRL DDR memory controller internal bus deadlock,1
WARNING,INTERRUPT_CTRL,ISR execution time exceeding threshold,INTERRUPT_CTRL ISR execution time exceeding threshold,1
ERROR,CLOCK_MANAGER,Clock synchronizer for 'GPIO' module detected metastability,CLOCK_MANAGER Clock synchronizer for 'GPIO' module detected metastability,0
ERROR,INTERRUPT_CTRL,Interrupt clear signal ignored by pending request,INTERRUPT_CTRL Interrupt clear signal ignored by pending request,1
WARNING,INTERRUPT_CTRL,Interrupt request input chattering,INTERRUPT_CTRL Interrupt request input chattering,1
INFO,POWER_CTRL,Power state transition to low-power successful,POWER_CTRL Power state transition to low-power successful,4
WARNING,PCIE_CTRL,"PCIe link re-training event occurred, performance impact","PCIE_CTRL PCIe link re-training event occurred, performance impact",6
ERROR,AXI_CTRL,AXI response channel stall detected,AXI_CTRL AXI response channel stall detected,2
ERROR,PCIE_CTRL,"PCIe hot-plug event detected, but configuration failed","PCIE_CTRL PCIe hot-plug event detected, but configuration failed",6
WARNING,INTERRUPT_CTRL,Interrupt vector table checksum mismatch,INTERRUPT_CTRL Interrupt vector table checksum mismatch,1
CRITICAL,MEM_CTRL,Memory controller state machine stuck in illegal state,MEM_CTRL Memory controller state machine stuck in illegal state,1
WARNING,AXI_CTRL,AXI master response `EXOKAY` but expected `OKAY`,AXI_CTRL AXI master response `EXOKAY` but expected `OKAY`,-1
INFO,AXI_CTRL,AXI interconnect bandwidth utilization report generated,AXI_CTRL AXI interconnect bandwidth utilization report generated,-1
INFO,MEM_CTRL,Memory writeback buffer flushed,MEM_CTRL Memory writeback buffer flushed,1
WARNING,POWER_CTRL,Thermal sensor reporting elevated temperatures,POWER_CTRL Thermal sensor reporting elevated temperatures,4
ERROR,CLOCK_MANAGER,Clock source integrity check failed,CLOCK_MANAGER Clock source integrity check failed,0
CRITICAL,CLOCK_MANAGER,System clock integrity alarm triggered,CLOCK_MANAGER System clock integrity alarm triggered,0
INFO,MEM_CTRL,Memory bank power-up sequence complete,MEM_CTRL Memory bank power-up sequence complete,1
INFO,CACHE_CTRL,Performance counters for CACHE_CTRL reset.,CACHE_CTRL Performance counters for CACHE_CTRL reset.,1
INFO,POWER_CTRL,All rails reporting nominal voltage,POWER_CTRL All rails reporting nominal voltage,4
ERROR,DDR_CTRL,DDR training sequence failed (stage 3).,DDR_CTRL DDR training sequence failed (stage 3).,1
WARNING,DDR_CTRL,DDR refresh rate temporarily increased for stability,DDR_CTRL DDR refresh rate temporarily increased for stability,1
ERROR,AXI_CTRL,AXI write data channel protocol error,AXI_CTRL AXI write data channel protocol error,2
ERROR,CACHE_CTRL,"Cache coherence protocol violation, potential stale data","CACHE_CTRL Cache coherence protocol violation, potential stale data",1
ERROR,POWER_CTRL,Power rail voltage regulator current limit hit,POWER_CTRL Power rail voltage regulator current limit hit,4
INFO,DMA_ENGINE,"DMA channel 3 paused, awaiting external event","DMA_ENGINE DMA channel 3 paused, awaiting external event",3
CRITICAL,CACHE_CTRL,Fatal cache controller internal error,CACHE_CTRL Fatal cache controller internal error,1
INFO,POWER_CTRL,Voltage monitoring unit self-test passed,POWER_CTRL Voltage monitoring unit self-test passed,4
INFO,POWER_CTRL,Power domain X successfully isolated.,POWER_CTRL Power domain X successfully isolated.,4
ERROR,POWER_CTRL,POWER_CTRL detected a severe invalid state transition: unexpected state change.,POWER_CTRL POWER_CTRL detected a severe invalid state transition: unexpected state change.,4
WARNING,FIFO_BUF,FIFO_LOG latency exceeding expected threshold,FIFO_BUF FIFO_LOG latency exceeding expected threshold,5
WARNING,POWER_CTRL,"Voltage rail marginal, potential droop.","POWER_CTRL Voltage rail marginal, potential droop.",4
WARNING,INTERRUPT_CTRL,Interrupt controller internal register corruption detected,INTERRUPT_CTRL Interrupt controller internal register corruption detected,1
INFO,AXI_CTRL,AXI B channel ready.,AXI_CTRL AXI B channel ready.,2
WARNING,AXI_CTRL,AXI master issuing invalid transaction IDs,AXI_CTRL AXI master issuing invalid transaction IDs,2
WARNING,DMA_ENGINE,DMA target address alignment warning,DMA_ENGINE DMA target address alignment warning,3
WARNING,CACHE_CTRL,Cache dirty lines pending writeback.,CACHE_CTRL Cache dirty lines pending writeback.,1
ERROR,FIFO_BUF,FIFO write enable asserted while full,FIFO_BUF FIFO write enable asserted while full,5
INFO,PCIE_CTRL,PCIe device enumeration successful for 4 devices,PCIE_CTRL PCIe device enumeration successful for 4 devices,6
WARNING,CACHE_CTRL,Cache L2 miss rate approaching critical threshold,CACHE_CTRL Cache L2 miss rate approaching critical threshold,1
ERROR,DDR_CTRL,DDR memory chip select timing violation,DDR_CTRL DDR memory chip select timing violation,1
ERROR,DMA_ENGINE,DMA channel arbitration failure detected for 1.,DMA_ENGINE DMA channel arbitration failure detected for 1.,3
INFO,DMA_ENGINE,DMA channel 4 idle,DMA_ENGINE DMA channel 4 idle,3
INFO,AXI_CTRL,AXI master configured for new transfer,AXI_CTRL AXI master configured for new transfer,2
WARNING,INTERRUPT_CTRL,Interrupt source 12 asserted at high frequency,INTERRUPT_CTRL Interrupt source 12 asserted at high frequency,1
ERROR,FIFO_BUF,FIFO write access while full detected,FIFO_BUF FIFO write access while full detected,5
WARNING,DDR_CTRL,DDR precharge power down timing violation approaching,DDR_CTRL DDR precharge power down timing violation approaching,1
WARNING,MEM_CTRL,Memory read-modify-write operation stalled,MEM_CTRL Memory read-modify-write operation stalled,1
WARNING,DDR_CTRL,DDR read latency variation exceeding expected limits,DDR_CTRL DDR read latency variation exceeding expected limits,1
WARNING,POWER_CTRL,POWER_CTRL internal buffer approaching capacity (80% full).,POWER_CTRL POWER_CTRL internal buffer approaching capacity (80% full).,-1
INFO,AXI_CTRL,Register write to AXI_CTRL successful (Addr: 0x30).,AXI_CTRL Register write to AXI_CTRL successful (Addr: 0x30).,2
ERROR,FIFO_BUF,"FIFO overflow condition detected, data lost","FIFO_BUF FIFO overflow condition detected, data lost",5
ERROR,PCIE_CTRL,PCIe hot-reset failed,PCIE_CTRL PCIe hot-reset failed,6
WARNING,PCIE_CTRL,PCIe completion queue experiencing backpressure,PCIE_CTRL PCIe completion queue experiencing backpressure,6
ERROR,CACHE_CTRL,Cache tag comparison error for address 0x12345678,CACHE_CTRL Cache tag comparison error for address 0x12345678,1
ERROR,AXI_CTRL,"AXI burst length violation detected (length=38, max 104).","AXI_CTRL AXI burst length violation detected (length=38, max 104).",2
WARNING,CLOCK_MANAGER,Secondary clock source drift detected,CLOCK_MANAGER Secondary clock source drift detected,0
CRITICAL,CLOCK_MANAGER,"Main PLL lock lost, system clock unstable","CLOCK_MANAGER Main PLL lock lost, system clock unstable",0
WARNING,CACHE_CTRL,"Cache write buffer nearly full, causing stalls","CACHE_CTRL Cache write buffer nearly full, causing stalls",1
WARNING,CACHE_CTRL,Cache miss due to thrashing suspected,CACHE_CTRL Cache miss due to thrashing suspected,1
CRITICAL,FIFO_BUF,FIFO data corruption detected during internal transfer,FIFO_BUF FIFO data corruption detected during internal transfer,5
CRITICAL,DDR_CTRL,DDR memory rank 2 initialization failure,DDR_CTRL DDR memory rank 2 initialization failure,1
ERROR,DDR_CTRL,DDR memory rank calibration failed,DDR_CTRL DDR memory rank calibration failed,1
INFO,FIFO_BUF,"FIFO write operation successful, occupancy increased","FIFO_BUF FIFO write operation successful, occupancy increased",5
CRITICAL,POWER_CTRL,System power management unit (PMU) unresponsive,POWER_CTRL System power management unit (PMU) unresponsive,4
CRITICAL,MEM_CTRL,Memory access violation: unprivileged write to protected region,MEM_CTRL Memory access violation: unprivileged write to protected region,1
CRITICAL,DMA_ENGINE,DMA engine internal parity error detected,DMA_ENGINE DMA engine internal parity error detected,3
WARNING,DMA_ENGINE,DMA channel paused due to external throttle,DMA_ENGINE DMA channel paused due to external throttle,3
INFO,FIFO_BUF,"Write operation successful, data enqueued","FIFO_BUF Write operation successful, data enqueued",5
INFO,MEM_CTRL,Memory controller re-initialized,MEM_CTRL Memory controller re-initialized,1
WARNING,DDR_CTRL,DDR bank activate command latency high,DDR_CTRL DDR bank activate command latency high,1
CRITICAL,FIFO_BUF,Internal FIFO memory parity error detected.,FIFO_BUF Internal FIFO memory parity error detected.,5
CRITICAL,PCIE_CTRL,PCIe physical layer unrecoverable error.,PCIE_CTRL PCIe physical layer unrecoverable error.,6
ERROR,AXI_CTRL,AXI write transaction dropped due to slave timeout,AXI_CTRL AXI write transaction dropped due to slave timeout,2
CRITICAL,MEM_CTRL,Memory address bus high-impedance state detected,MEM_CTRL Memory address bus high-impedance state detected,1
INFO,CACHE_CTRL,Cache directory update completed.,CACHE_CTRL Cache directory update completed.,1
WARNING,DDR_CTRL,DDR memory temperature sensor reports 85C,DDR_CTRL DDR memory temperature sensor reports 85C,1
ERROR,INTERRUPT_CTRL,Interrupt masking register corruption detected,INTERRUPT_CTRL Interrupt masking register corruption detected,1
INFO,CACHE_CTRL,Cache line allocated in L1 instruction cache,CACHE_CTRL Cache line allocated in L1 instruction cache,1
WARNING,DDR_CTRL,DRAM page hit rate lower than expected,DDR_CTRL DRAM page hit rate lower than expected,1
INFO,AXI_CTRL,AXI debug monitor enabled,AXI_CTRL AXI debug monitor enabled,-1
INFO,MEM_CTRL,Memory power-down mode entered for unused region.,MEM_CTRL Memory power-down mode entered for unused region.,1
INFO,DMA_ENGINE,DMA channel enabled successfully,DMA_ENGINE DMA channel enabled successfully,3
INFO,POWER_CTRL,Dynamic Voltage and Frequency Scaling (DVFS) applied,POWER_CTRL Dynamic Voltage and Frequency Scaling (DVFS) applied,9
CRITICAL,CACHE_CTRL,Cache way invalidation command failed,CACHE_CTRL Cache way invalidation command failed,1
WARNING,PCIE_CTRL,PCIe replay buffer full,PCIE_CTRL PCIe replay buffer full,6
ERROR,CACHE_CTRL,Cache tag parity error detected on invalidation,CACHE_CTRL Cache tag parity error detected on invalidation,1
WARNING,CLOCK_MANAGER,Clock tree branch critical path nearing delay budget,CLOCK_MANAGER Clock tree branch critical path nearing delay budget,-1
INFO,DDR_CTRL,Write to address 0x100 completed successfully,DDR_CTRL Write to address 0x100 completed successfully,1
ERROR,DDR_CTRL,DDR command sequence error detected,DDR_CTRL DDR command sequence error detected,1
INFO,INTERRUPT_CTRL,Interrupt acknowledge for ID 7 received,INTERRUPT_CTRL Interrupt acknowledge for ID 7 received,1
INFO,PCIE_CTRL,PCIe Transaction Layer Packet (TLP) generated,PCIE_CTRL PCIe Transaction Layer Packet (TLP) generated,6
ERROR,AXI_CTRL,AXI protocol violation: illegal burst length (17) detected,AXI_CTRL AXI protocol violation: illegal burst length (17) detected,2
WARNING,AXI_CTRL,"AXI read wait states increasing, performance degradation likely","AXI_CTRL AXI read wait states increasing, performance degradation likely",2
ERROR,POWER_CTRL,Core rail power state transition stalled,POWER_CTRL Core rail power state transition stalled,4
ERROR,DMA_ENGINE,DMA read address out of bounds,DMA_ENGINE DMA read address out of bounds,3
WARNING,CLOCK_MANAGER,Clock synthesis output phase deviation detected,CLOCK_MANAGER Clock synthesis output phase deviation detected,0
INFO,AXI_CTRL,AXI write data transfer successful,AXI_CTRL AXI write data transfer successful,2
WARNING,MEM_CTRL,Memory controller pipeline stall detected,MEM_CTRL Memory controller pipeline stall detected,1
INFO,CACHE_CTRL,Cache data prefetching active,CACHE_CTRL Cache data prefetching active,1
INFO,AXI_CTRL,AXI write burst completed successfully,AXI_CTRL AXI write burst completed successfully,2
WARNING,FIFO_BUF,"FIFO read underflow hazard detected, pipeline stall","FIFO_BUF FIFO read underflow hazard detected, pipeline stall",5
WARNING,INTERRUPT_CTRL,Interrupt queue approaching limit for high priority interrupts,INTERRUPT_CTRL Interrupt queue approaching limit for high priority interrupts,1
INFO,POWER_CTRL,Voltage regulator output within tolerance,POWER_CTRL Voltage regulator output within tolerance,4
ERROR,AXI_CTRL,AXI response with unexpected CPLD status,AXI_CTRL AXI response with unexpected CPLD status,2
ERROR,FIFO_BUF,FIFO output data corruption detected,FIFO_BUF FIFO output data corruption detected,5
INFO,POWER_CTRL,Low power mode exit sequence completed,POWER_CTRL Low power mode exit sequence completed,4
INFO,INTERRUPT_CTRL,Interrupt controller in idle state,INTERRUPT_CTRL Interrupt controller in idle state,1
WARNING,FIFO_BUF,FIFO read operation stalled due to backpressure,FIFO_BUF FIFO read operation stalled due to backpressure,5
INFO,FIFO_BUF,"FIFO underflow detected and handled, consumer was idle","FIFO_BUF FIFO underflow detected and handled, consumer was idle",5
INFO,CACHE_CTRL,Cache line written back to memory successfully,CACHE_CTRL Cache line written back to memory successfully,1
CRITICAL,MEM_CTRL,Memory array initialization failed,MEM_CTRL Memory array initialization failed,1
INFO,AXI_CTRL,AXI transaction timeout for master 0x0 was cleared,AXI_CTRL AXI transaction timeout for master 0x0 was cleared,2
INFO,DMA_ENGINE,DMA_ENGINE module initialized.,DMA_ENGINE DMA_ENGINE module initialized.,3
INFO,POWER_CTRL,Power domain isolation logic active,POWER_CTRL Power domain isolation logic active,4
INFO,CACHE_CTRL,Cache hit detected for address.,CACHE_CTRL Cache hit detected for address.,1
ERROR,MEM_CTRL,Memory controller hardware ECC failure detected,MEM_CTRL Memory controller hardware ECC failure detected,1
ERROR,FIFO_BUF,Input FIFO 'cmd_in' underflow during critical operation,FIFO_BUF Input FIFO 'cmd_in' underflow during critical operation,5
CRITICAL,INTERRUPT_CTRL,Interrupt controller fatal error,INTERRUPT_CTRL Interrupt controller fatal error,1
INFO,FIFO_BUF,FIFO empty threshold reached,FIFO_BUF FIFO empty threshold reached,5
CRITICAL,FIFO_BUF,FIFO 'critical_data' experienced unrecoverable overflow,FIFO_BUF FIFO 'critical_data' experienced unrecoverable overflow,5
ERROR,CACHE_CTRL,Cache line state transition failure,CACHE_CTRL Cache line state transition failure,1
ERROR,POWER_CTRL,Power domain VDD_AUDIO failed to power up.,POWER_CTRL Power domain VDD_AUDIO failed to power up.,-1
WARNING,CACHE_CTRL,Cache dirty eviction pipeline stalled,CACHE_CTRL Cache dirty eviction pipeline stalled,1
ERROR,PCIE_CTRL,PCIe uncorrectable error reported from endpoint.,PCIE_CTRL PCIe uncorrectable error reported from endpoint.,6
INFO,DMA_ENGINE,"DMA transfer completed, 1024 bytes moved","DMA_ENGINE DMA transfer completed, 1024 bytes moved",3
INFO,FIFO_BUF,"FIFO status queried: Not Empty, Not Full","FIFO_BUF FIFO status queried: Not Empty, Not Full",5
CRITICAL,CACHE_CTRL,Cache coherency protocol violation across masters,CACHE_CTRL Cache coherency protocol violation across masters,1
CRITICAL,MEM_CTRL,"Memory access violation detected, protection fault","MEM_CTRL Memory access violation detected, protection fault",1
CRITICAL,AXI_CTRL,AXI interconnect deadlock detected on global ID 0x55.,AXI_CTRL AXI interconnect deadlock detected on global ID 0x55.,2
CRITICAL,MEM_CTRL,Memory address decoder output became metastable.,MEM_CTRL Memory address decoder output became metastable.,1
ERROR,CACHE_CTRL,"Cache tag parity error detected, data corruption.","CACHE_CTRL Cache tag parity error detected, data corruption.",1
WARNING,CLOCK_MANAGER,Clock distribution network delay variation detected.,CLOCK_MANAGER Clock distribution network delay variation detected.,-1
INFO,CACHE_CTRL,Cache 'L1D' prefetcher enabled,CACHE_CTRL Cache 'L1D' prefetcher enabled,1
WARNING,CLOCK_MANAGER,Clock distribution network temperature rising,CLOCK_MANAGER Clock distribution network temperature rising,-1
ERROR,CLOCK_MANAGER,Clock domain crossing synchronization failure on 'RESET_N',CLOCK_MANAGER Clock domain crossing synchronization failure on 'RESET_N',0
CRITICAL,CACHE_CTRL,Cache controller deadlock detected,CACHE_CTRL Cache controller deadlock detected,1
INFO,FIFO_BUF,FIFO buffer status polled,FIFO_BUF FIFO buffer status polled,5
INFO,PCIE_CTRL,PCIe TLP received and acknowledged,PCIE_CTRL PCIe TLP received and acknowledged,6
INFO,DDR_CTRL,DDR memory capacity detected as 8GB,DDR_CTRL DDR memory capacity detected as 8GB,1
ERROR,CLOCK_MANAGER,Clock glitch detected on critical clock Main.,CLOCK_MANAGER Clock glitch detected on critical clock Main.,0
CRITICAL,PCIE_CTRL,PCIe fatal error detected on bus,PCIE_CTRL PCIe fatal error detected on bus,6
CRITICAL,CACHE_CTRL,Cache coherence protocol deadlock detected.,CACHE_CTRL Cache coherence protocol deadlock detected.,1
INFO,DDR_CTRL,"DDR power-up sequence complete, all ranks accessible","DDR_CTRL DDR power-up sequence complete, all ranks accessible",1
WARNING,DMA_ENGINE,Pending operations queue in DMA_ENGINE growing (count: 12).,DMA_ENGINE Pending operations queue in DMA_ENGINE growing (count: 12).,3
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance of 468 ps,CLOCK_MANAGER Clock jitter exceeding tolerance of 468 ps,0
WARNING,DDR_CTRL,DDR calibration detected excessive clock jitter.,DDR_CTRL DDR calibration detected excessive clock jitter.,1
WARNING,DMA_ENGINE,DMA descriptor fetch latency exceeding expected threshold,DMA_ENGINE DMA descriptor fetch latency exceeding expected threshold,3
CRITICAL,MEM_CTRL,Memory data bus contention detected,MEM_CTRL Memory data bus contention detected,1
CRITICAL,DMA_ENGINE,DMA internal bus arbitration deadlock.,DMA_ENGINE DMA internal bus arbitration deadlock.,3
ERROR,MEM_CTRL,Critical parity error in MEM_CTRL preventing further operation: control signal parity error.,MEM_CTRL Critical parity error in MEM_CTRL preventing further operation: control signal parity error.,1
CRITICAL,MEM_CTRL,Memory controller entered a protection fault state,MEM_CTRL Memory controller entered a protection fault state,1
CRITICAL,MEM_CTRL,Double bit ECC corruption detected in critical data region,MEM_CTRL Double bit ECC corruption detected in critical data region,1
INFO,INTERRUPT_CTRL,Interrupt controller reset procedure initiated,INTERRUPT_CTRL Interrupt controller reset procedure initiated,1
WARNING,DDR_CTRL,DDR memory rank 0 data integrity check pending,DDR_CTRL DDR memory rank 0 data integrity check pending,1
INFO,INTERRUPT_CTRL,Interrupt mask updated successfully,INTERRUPT_CTRL Interrupt mask updated successfully,1
INFO,DMA_ENGINE,DMA channel 22 transfer completed without errors,DMA_ENGINE DMA channel 22 transfer completed without errors,3
WARNING,CACHE_CTRL,"Cache eviction queue nearing capacity, potential performance degradation.","CACHE_CTRL Cache eviction queue nearing capacity, potential performance degradation.",1
INFO,PCIE_CTRL,PCIe hot reset sequence initiated successfully,PCIE_CTRL PCIe hot reset sequence initiated successfully,6
ERROR,CLOCK_MANAGER,Clock source selection mux glitch,CLOCK_MANAGER Clock source selection mux glitch,0
ERROR,DMA_ENGINE,DMA scatter-gather list corruption,DMA_ENGINE DMA scatter-gather list corruption,3
CRITICAL,CACHE_CTRL,"Cache directory corruption detected, cache data unreliable","CACHE_CTRL Cache directory corruption detected, cache data unreliable",1
INFO,CACHE_CTRL,Cache invalidate-all command completed,CACHE_CTRL Cache invalidate-all command completed,1
ERROR,DDR_CTRL,DDR controller detected a spurious RAS signal,DDR_CTRL DDR controller detected a spurious RAS signal,-1
ERROR,POWER_CTRL,Battery-backed RAM voltage unstable,POWER_CTRL Battery-backed RAM voltage unstable,4
WARNING,AXI_CTRL,AXI protocol violation: AWLEN/ARLEN mismatch with burst type,AXI_CTRL AXI protocol violation: AWLEN/ARLEN mismatch with burst type,2
WARNING,DMA_ENGINE,DMA queue nearing saturation,DMA_ENGINE DMA queue nearing saturation,3
INFO,CACHE_CTRL,Cache prefetcher disabled,CACHE_CTRL Cache prefetcher disabled,1
INFO,AXI_CTRL,AXI interconnect arbitration complete for all pending masters,AXI_CTRL AXI interconnect arbitration complete for all pending masters,2
ERROR,DMA_ENGINE,DMA channel control path deadlock,DMA_ENGINE DMA channel control path deadlock,3
CRITICAL,DDR_CTRL,DDR controller internal state machine deadlock,DDR_CTRL DDR controller internal state machine deadlock,1
CRITICAL,FIFO_BUF,"FIFO state machine entered unrecoverable error state, system impact","FIFO_BUF FIFO state machine entered unrecoverable error state, system impact",5
ERROR,AXI_CTRL,AXI write data channel (W) with incorrect WSTRB bits,AXI_CTRL AXI write data channel (W) with incorrect WSTRB bits,2
INFO,INTERRUPT_CTRL,Interrupt controller unmasked source ID Y,INTERRUPT_CTRL Interrupt controller unmasked source ID Y,1
ERROR,AXI_CTRL,AXI transaction ID collision detected,AXI_CTRL AXI transaction ID collision detected,2
ERROR,MEM_CTRL,Memory address alignment violation on write access,MEM_CTRL Memory address alignment violation on write access,1
INFO,PCIE_CTRL,Configuration space accessed,PCIE_CTRL Configuration space accessed,6
INFO,DMA_ENGINE,DMA engine initialized and channels enabled.,DMA_ENGINE DMA engine initialized and channels enabled.,3
WARNING,CACHE_CTRL,Cache miss rate exceeds performance target,CACHE_CTRL Cache miss rate exceeds performance target,1
INFO,MEM_CTRL,Memory controller state reset completed.,MEM_CTRL Memory controller state reset completed.,1
INFO,DDR_CTRL,DDR calibration fine-tuning complete,DDR_CTRL DDR calibration fine-tuning complete,1
INFO,PCIE_CTRL,PCIe hot-reset completed successfully.,PCIE_CTRL PCIe hot-reset completed successfully.,6
ERROR,PCIE_CTRL,PCIe configuration space access failed (vendor ID mismatch),PCIE_CTRL PCIe configuration space access failed (vendor ID mismatch),6
ERROR,DDR_CTRL,DDR memory 'DIMM_B' ECC reporting enabled but no ECC bits,DDR_CTRL DDR memory 'DIMM_B' ECC reporting enabled but no ECC bits,1
WARNING,FIFO_BUF,FIFO_NETWORK_RX_BUFFER approaching high watermark.,FIFO_BUF FIFO_NETWORK_RX_BUFFER approaching high watermark.,5
ERROR,PCIE_CTRL,"PCIe fatal error detected, link down","PCIE_CTRL PCIe fatal error detected, link down",6
ERROR,INTERRUPT_CTRL,Interrupt controller internal timeout for critical interrupt,INTERRUPT_CTRL Interrupt controller internal timeout for critical interrupt,1
WARNING,POWER_CTRL,Power domain isolation test failed,POWER_CTRL Power domain isolation test failed,4
CRITICAL,POWER_CTRL,External voltage monitor reports out-of-spec voltage,POWER_CTRL External voltage monitor reports out-of-spec voltage,4
ERROR,POWER_CTRL,Power sequence state machine entered illegal state,POWER_CTRL Power sequence state machine entered illegal state,4
INFO,PCIE_CTRL,PCIe link training completed successfully,PCIE_CTRL PCIe link training completed successfully,6
WARNING,FIFO_BUF,FIFO output data valid asserted too long,FIFO_BUF FIFO output data valid asserted too long,5
WARNING,AXI_CTRL,AXI read address channel asserting same address multiple times,AXI_CTRL AXI read address channel asserting same address multiple times,2
CRITICAL,MEM_CTRL,Memory controller state machine entered an unreachable state,MEM_CTRL Memory controller state machine entered an unreachable state,1
ERROR,FIFO_BUF,FIFO underflow condition detected on read attempt,FIFO_BUF FIFO underflow condition detected on read attempt,5
ERROR,FIFO_BUF,FIFO 'CONFIG' register corruption,FIFO_BUF FIFO 'CONFIG' register corruption,5
ERROR,CACHE_CTRL,Cache directory update failure.,CACHE_CTRL Cache directory update failure.,1
CRITICAL,MEM_CTRL,Memory protection unit detected access violation,MEM_CTRL Memory protection unit detected access violation,1
WARNING,DDR_CTRL,DDR command queue high latency for critical operations,DDR_CTRL DDR command queue high latency for critical operations,1
WARNING,PCIE_CTRL,Retransmission buffer nearing capacity due to link errors,PCIE_CTRL Retransmission buffer nearing capacity due to link errors,6
CRITICAL,CLOCK_MANAGER,"System clock absent, core logic powered down","CLOCK_MANAGER System clock absent, core logic powered down",-1
CRITICAL,MEM_CTRL,Memory initialization sequence failed,MEM_CTRL Memory initialization sequence failed,1
ERROR,DMA_ENGINE,DMA channel 11 descriptor pointer wrap-around detected,DMA_ENGINE DMA channel 11 descriptor pointer wrap-around detected,3
CRITICAL,INTERRUPT_CTRL,Interrupt controller watchdog failed to kick,INTERRUPT_CTRL Interrupt controller watchdog failed to kick,1
WARNING,FIFO_BUF,"Read buffer nearing empty (level: 10%), potential underflow","FIFO_BUF Read buffer nearing empty (level: 10%), potential underflow",5
CRITICAL,DMA_ENGINE,DMA unrecoverable channel error,DMA_ENGINE DMA unrecoverable channel error,3
INFO,INTERRUPT_CTRL,Interrupt controller initialized,INTERRUPT_CTRL Interrupt controller initialized,1
WARNING,CLOCK_MANAGER,CLOCK_MANAGER power domain transition taking longer than nominal.,CLOCK_MANAGER CLOCK_MANAGER power domain transition taking longer than nominal.,-1
CRITICAL,AXI_CTRL,AXI system bus reset assertion required,AXI_CTRL AXI system bus reset assertion required,2
CRITICAL,AXI_CTRL,AXI system bus deadlock detected between masters,AXI_CTRL AXI system bus deadlock detected between masters,2
CRITICAL,AXI_CTRL,AXI bus protocol violation causing system halt,AXI_CTRL AXI bus protocol violation causing system halt,2
ERROR,AXI_CTRL,AXI protection bits timing violation.,AXI_CTRL AXI protection bits timing violation.,2
CRITICAL,AXI_CTRL,AXI bus deadlock detected between master and slave,AXI_CTRL AXI bus deadlock detected between master and slave,2
CRITICAL,POWER_CTRL,Critical voltage regulator instability,POWER_CTRL Critical voltage regulator instability,4
CRITICAL,PCIE_CTRL,PCIe Physical Layer fatal error detected,PCIE_CTRL PCIe Physical Layer fatal error detected,6
INFO,MEM_CTRL,Memory refresh interval approaching critical limit,MEM_CTRL Memory refresh interval approaching critical limit,1
WARNING,PCIE_CTRL,PCIe upstream receive buffer nearing capacity,PCIE_CTRL PCIe upstream receive buffer nearing capacity,6
CRITICAL,CACHE_CTRL,Cache coherence arbiter stuck in wait state,CACHE_CTRL Cache coherence arbiter stuck in wait state,-1
ERROR,AXI_CTRL,"AXI burst length violation detected (actual 128, expected 8).","AXI_CTRL AXI burst length violation detected (actual 128, expected 8).",2
CRITICAL,POWER_CTRL,"Power rail collapse detected, immediate shutdown","POWER_CTRL Power rail collapse detected, immediate shutdown",4
ERROR,DDR_CTRL,DDR memory power-up sequence verification failed,DDR_CTRL DDR memory power-up sequence verification failed,1
CRITICAL,DDR_CTRL,DDR Vref calibration failed to meet setup/hold requirements.,DDR_CTRL DDR Vref calibration failed to meet setup/hold requirements.,1
ERROR,POWER_CTRL,Power sequencing controller stuck,POWER_CTRL Power sequencing controller stuck,4
WARNING,DDR_CTRL,DDR memory controller queue stalled intermittently,DDR_CTRL DDR memory controller queue stalled intermittently,1
ERROR,DMA_ENGINE,DMA access to protected memory region,DMA_ENGINE DMA access to protected memory region,3
ERROR,FIFO_BUF,FIFO 'message_queue' input data rate exceeding output rate,FIFO_BUF FIFO 'message_queue' input data rate exceeding output rate,5
WARNING,POWER_CTRL,Power domain transition delay detected for GPU_PD,POWER_CTRL Power domain transition delay detected for GPU_PD,4
ERROR,FIFO_BUF,FIFO read data mismatch due to internal corruption,FIFO_BUF FIFO read data mismatch due to internal corruption,5
INFO,POWER_CTRL,Power domain VDD_GRAPHICS is now active.,POWER_CTRL Power domain VDD_GRAPHICS is now active.,4
ERROR,DDR_CTRL,DDR DQS training failed to converge,DDR_CTRL DDR DQS training failed to converge,1
CRITICAL,POWER_CTRL,Critical power rail voltage sag detected,POWER_CTRL Critical power rail voltage sag detected,4
INFO,CLOCK_MANAGER,Clock reset propagation confirmed.,CLOCK_MANAGER Clock reset propagation confirmed.,0
WARNING,INTERRUPT_CTRL,Software interrupt pending,INTERRUPT_CTRL Software interrupt pending,1
CRITICAL,MEM_CTRL,Memory address decoding error leading to system crash,MEM_CTRL Memory address decoding error leading to system crash,1
WARNING,CACHE_CTRL,Cache 'L1D' eviction rate too high,CACHE_CTRL Cache 'L1D' eviction rate too high,1
CRITICAL,FIFO_BUF,FIFO control logic state machine reached an illegal state,FIFO_BUF FIFO control logic state machine reached an illegal state,5
CRITICAL,MEM_CTRL,"System memory corruption detected, unrecoverable","MEM_CTRL System memory corruption detected, unrecoverable",1
CRITICAL,POWER_CTRL,Catastrophic voltage rail collapse detected on 'VCC_CORE',POWER_CTRL Catastrophic voltage rail collapse detected on 'VCC_CORE',4
CRITICAL,PCIE_CTRL,PCIe link state machine reached permanent hot-reset state,PCIE_CTRL PCIe link state machine reached permanent hot-reset state,6
WARNING,DMA_ENGINE,DMA channel 2 pending transfers queue growing,DMA_ENGINE DMA channel 2 pending transfers queue growing,3
CRITICAL,CLOCK_MANAGER,System clock input lost,CLOCK_MANAGER System clock input lost,0
CRITICAL,PCIE_CTRL,PCIe PHY layer unrecoverable timing violation.,PCIE_CTRL PCIe PHY layer unrecoverable timing violation.,6
ERROR,POWER_CTRL,"Brown-out detection asserted unexpectedly, timing violation.","POWER_CTRL Brown-out detection asserted unexpectedly, timing violation.",4
INFO,MEM_CTRL,Memory read initiated at address 0xABCDEF00,MEM_CTRL Memory read initiated at address 0xABCDEF00,1
ERROR,DDR_CTRL,DDR write data byte lane strobe timing violation,DDR_CTRL DDR write data byte lane strobe timing violation,1
INFO,DMA_ENGINE,DMA channel 0 transfer of 4KB completed,DMA_ENGINE DMA channel 0 transfer of 4KB completed,3
ERROR,CACHE_CTRL,Cache line state transition protocol error,CACHE_CTRL Cache line state transition protocol error,1
CRITICAL,POWER_CTRL,Main power rail dropped below minimum operating voltage,POWER_CTRL Main power rail dropped below minimum operating voltage,4
ERROR,AXI_CTRL,"AXI burst length violation detected, protocol mismatch.","AXI_CTRL AXI burst length violation detected, protocol mismatch.",2
INFO,CLOCK_MANAGER,Dynamic frequency scaling applied,CLOCK_MANAGER Dynamic frequency scaling applied,0
WARNING,DMA_ENGINE,"DMA channel busy status prolonged, exceeding timeout","DMA_ENGINE DMA channel busy status prolonged, exceeding timeout",3
ERROR,POWER_CTRL,Power rail voltage surge detected,POWER_CTRL Power rail voltage surge detected,4
ERROR,MEM_CTRL,Memory refresh cycle skipped multiple times,MEM_CTRL Memory refresh cycle skipped multiple times,1
ERROR,DMA_ENGINE,DMA buffer descriptor invalid configuration,DMA_ENGINE DMA buffer descriptor invalid configuration,3
WARNING,CLOCK_MANAGER,Clock jitter exceeding tolerance of 157 ps,CLOCK_MANAGER Clock jitter exceeding tolerance of 157 ps,0
ERROR,CLOCK_MANAGER,Clock domain crossing data corruption detected on bridge X,CLOCK_MANAGER Clock domain crossing data corruption detected on bridge X,0
WARNING,MEM_CTRL,MEM_CTRL resource allocation nearing limit (90% utilized).,MEM_CTRL MEM_CTRL resource allocation nearing limit (90% utilized).,1
CRITICAL,POWER_CTRL,PMIC communication loss,POWER_CTRL PMIC communication loss,4
CRITICAL,CACHE_CTRL,"Cache controller internal state corruption, data loss imminent.","CACHE_CTRL Cache controller internal state corruption, data loss imminent.",1
INFO,CACHE_CTRL,Cache invalidate-single-line completed,CACHE_CTRL Cache invalidate-single-line completed,1
CRITICAL,CACHE_CTRL,Cache controller deadlock.,CACHE_CTRL Cache controller deadlock.,1
INFO,CLOCK_MANAGER,Clock propagation delay calibrated,CLOCK_MANAGER Clock propagation delay calibrated,-1
WARNING,CLOCK_MANAGER,JTAG clock bypass circuit engaged,CLOCK_MANAGER JTAG clock bypass circuit engaged,-1
INFO,CACHE_CTRL,Cache 'L2' data array scrub completed without errors,CACHE_CTRL Cache 'L2' data array scrub completed without errors,1
WARNING,FIFO_BUF,"FIFO write pointer at maximum, blocking further writes.","FIFO_BUF FIFO write pointer at maximum, blocking further writes.",5
ERROR,DDR_CTRL,DDR command timing violation detected for READ command,DDR_CTRL DDR command timing violation detected for READ command,1
CRITICAL,MEM_CTRL,Memory controller asserted system fatal error due to ECC failure,MEM_CTRL Memory controller asserted system fatal error due to ECC failure,1
CRITICAL,DMA_ENGINE,DMA engine unrecoverable data corruption.,DMA_ENGINE DMA engine unrecoverable data corruption.,3
ERROR,PCIE_CTRL,PCIe link layer protocol violation (ordered set),PCIE_CTRL PCIe link layer protocol violation (ordered set),6
ERROR,INTERRUPT_CTRL,Interrupt controller watchdog timeout for pending IRQ,INTERRUPT_CTRL Interrupt controller watchdog timeout for pending IRQ,1
WARNING,AXI_CTRL,AXI read transaction latency increased,AXI_CTRL AXI read transaction latency increased,2
CRITICAL,MEM_CTRL,Memory controller state machine entered fatal invalid state,MEM_CTRL Memory controller state machine entered fatal invalid state,1
INFO,CLOCK_MANAGER,Clock source selected from internal oscillator,CLOCK_MANAGER Clock source selected from internal oscillator,0
WARNING,INTERRUPT_CTRL,Interrupt debounce logic warning,INTERRUPT_CTRL Interrupt debounce logic warning,-1
INFO,CLOCK_MANAGER,Clock source switched to external crystal,CLOCK_MANAGER Clock source switched to external crystal,0
WARNING,PCIE_CTRL,PCIe outbound retry buffer utilization reaching 75%.,PCIE_CTRL PCIe outbound retry buffer utilization reaching 75%.,6
WARNING,CLOCK_MANAGER,Clock jitter on primary PLL output exceeding tolerance.,CLOCK_MANAGER Clock jitter on primary PLL output exceeding tolerance.,0
WARNING,DMA_ENGINE,DMA transfer progress slower than expected,DMA_ENGINE DMA transfer progress slower than expected,3
WARNING,DDR_CTRL,DDR read latency exceeding specified limits,DDR_CTRL DDR read latency exceeding specified limits,1
INFO,CLOCK_MANAGER,Clock domain crossing (CDC) synchronizers verified,CLOCK_MANAGER Clock domain crossing (CDC) synchronizers verified,0
INFO,CACHE_CTRL,Cache invalidation command issued for region 0x1000,CACHE_CTRL Cache invalidation command issued for region 0x1000,1
INFO,CACHE_CTRL,Cache line hit on address 0x20000000,CACHE_CTRL Cache line hit on address 0x20000000,1
WARNING,INTERRUPT_CTRL,Interrupt 'WDT_INT' pending for extended period,INTERRUPT_CTRL Interrupt 'WDT_INT' pending for extended period,1
WARNING,CACHE_CTRL,Cache line eviction rate increasing rapidly,CACHE_CTRL Cache line eviction rate increasing rapidly,1
INFO,DDR_CTRL,DDR memory row activation completed,DDR_CTRL DDR memory row activation completed,1
CRITICAL,PCIE_CTRL,"PCIe device hot-reset failed, device remains in error state","PCIE_CTRL PCIe device hot-reset failed, device remains in error state",6
WARNING,AXI_CTRL,AXI slave `DECERR` responses increasing,AXI_CTRL AXI slave `DECERR` responses increasing,2
CRITICAL,CACHE_CTRL,Cache tag directory corruption,CACHE_CTRL Cache tag directory corruption,1
CRITICAL,POWER_CTRL,System voltage monitor reports critical undervoltage,POWER_CTRL System voltage monitor reports critical undervoltage,4
INFO,INTERRUPT_CTRL,Interrupt priority level adjusted for ID P,INTERRUPT_CTRL Interrupt priority level adjusted for ID P,1
WARNING,POWER_CTRL,Power domain transition delay detected,POWER_CTRL Power domain transition delay detected,4
ERROR,INTERRUPT_CTRL,Interrupt enable register corrupted,INTERRUPT_CTRL Interrupt enable register corrupted,1
INFO,DDR_CTRL,Memory refresh burst completed,DDR_CTRL Memory refresh burst completed,1
ERROR,DMA_ENGINE,DMA descriptor fetch failed for entry 16 on channel CH0.,DMA_ENGINE DMA descriptor fetch failed for entry 16 on channel CH0.,3
WARNING,DDR_CTRL,DDR memory temperature approaching maximum operating limit,DDR_CTRL DDR memory temperature approaching maximum operating limit,1
INFO,POWER_CTRL,Power-up sequence complete for system.,POWER_CTRL Power-up sequence complete for system.,4
ERROR,AXI_CTRL,"AXI bus contention detected, multiple masters attempting to drive AXI_READY.","AXI_CTRL AXI bus contention detected, multiple masters attempting to drive AXI_READY.",2
CRITICAL,MEM_CTRL,Memory controller read data CRC mismatch detected,MEM_CTRL Memory controller read data CRC mismatch detected,1
ERROR,PCIE_CTRL,PCIe link retrain initiated due to severe errors,PCIE_CTRL PCIe link retrain initiated due to severe errors,6
CRITICAL,DDR_CTRL,DDR controller internal deadlock detected.,DDR_CTRL DDR controller internal deadlock detected.,1
ERROR,DMA_ENGINE,DMA engine unable to obtain bus mastership,DMA_ENGINE DMA engine unable to obtain bus mastership,3
WARNING,AXI_CTRL,AXI_CTRL observed higher than expected transaction latency (TxID: 15).,AXI_CTRL AXI_CTRL observed higher than expected transaction latency (TxID: 15).,2
CRITICAL,MEM_CTRL,Memory controller internal bus error,MEM_CTRL Memory controller internal bus error,1
INFO,PCIE_CTRL,PCIe upstream link status OK,PCIE_CTRL PCIe upstream link status OK,6
ERROR,POWER_CTRL,Power rail voltage drop below minimum threshold,POWER_CTRL Power rail voltage drop below minimum threshold,4
ERROR,PCIE_CTRL,PCIe TLP CRC error detected,PCIE_CTRL PCIe TLP CRC error detected,6
ERROR,FIFO_BUF,Asynchronous clock domain crossing FIFO underflow during burst.,FIFO_BUF Asynchronous clock domain crossing FIFO underflow during burst.,5
ERROR,MEM_CTRL,Memory ECC single-bit error detected and corrected at 0x1000C000,MEM_CTRL Memory ECC single-bit error detected and corrected at 0x1000C000,1
ERROR,CLOCK_MANAGER,Clock manager state machine entered unexpected state RESET.,CLOCK_MANAGER Clock manager state machine entered unexpected state RESET.,0
WARNING,DMA_ENGINE,"DMA descriptor fetch latency high, average 16 cycles","DMA_ENGINE DMA descriptor fetch latency high, average 16 cycles",3
ERROR,INTERRUPT_CTRL,Interrupt priority inversion detected for IRQ 3.,INTERRUPT_CTRL Interrupt priority inversion detected for IRQ 3.,1
INFO,CLOCK_MANAGER,Clock gating for peripheral disabled,CLOCK_MANAGER Clock gating for peripheral disabled,0
ERROR,MEM_CTRL,Multi-bit ECC error detected and uncorrectable,MEM_CTRL Multi-bit ECC error detected and uncorrectable,1
CRITICAL,DMA_ENGINE,"Descriptor ring buffer corruption, unrecoverable DMA failure","DMA_ENGINE Descriptor ring buffer corruption, unrecoverable DMA failure",3
WARNING,AXI_CTRL,"AXI write outstanding limit reached, stalling transactions","AXI_CTRL AXI write outstanding limit reached, stalling transactions",2
INFO,FIFO_BUF,Write operation successful on 'output_buffer',FIFO_BUF Write operation successful on 'output_buffer',5
CRITICAL,AXI_CTRL,"AXI system bus error, critical transaction halted.","AXI_CTRL AXI system bus error, critical transaction halted.",2
ERROR,CACHE_CTRL,Cache access permission fault,CACHE_CTRL Cache access permission fault,1
CRITICAL,POWER_CTRL,Power sequencing logic halted unexpectedly,POWER_CTRL Power sequencing logic halted unexpectedly,4
ERROR,CACHE_CTRL,MSI protocol violation,CACHE_CTRL MSI protocol violation,-1
ERROR,FIFO_BUF,"FIFO pointer corruption detected, inconsistent read/write pointers.","FIFO_BUF FIFO pointer corruption detected, inconsistent read/write pointers.",5
ERROR,AXI_CTRL,AXI write data channel backpressure timeout,AXI_CTRL AXI write data channel backpressure timeout,2
INFO,AXI_CTRL,AXI arbitration granted to master 14.,AXI_CTRL AXI arbitration granted to master 14.,2
WARNING,DDR_CTRL,DDR training eye margin for write leveling is narrow,DDR_CTRL DDR training eye margin for write leveling is narrow,1
INFO,DDR_CTRL,Command issued to SDRAM bank 0,DDR_CTRL Command issued to SDRAM bank 0,-1
WARNING,INTERRUPT_CTRL,Interrupt mask register contention.,INTERRUPT_CTRL Interrupt mask register contention.,1
CRITICAL,CACHE_CTRL,Cache snoop filter reported fatal inconsistency,CACHE_CTRL Cache snoop filter reported fatal inconsistency,1
INFO,CACHE_CTRL,Directory entry updated for physical address 0xABCDEF00.,CACHE_CTRL Directory entry updated for physical address 0xABCDEF00.,1
CRITICAL,AXI_CTRL,AXI crossbar arbiter state machine entered an illegal state.,AXI_CTRL AXI crossbar arbiter state machine entered an illegal state.,-1
INFO,CACHE_CTRL,Data served from L1 cache (cache hit),CACHE_CTRL Data served from L1 cache (cache hit),1
INFO,CLOCK_MANAGER,System clock source switched to external crystal.,CLOCK_MANAGER System clock source switched to external crystal.,0
CRITICAL,DMA_ENGINE,DMA channel configuration registers became corrupted,DMA_ENGINE DMA channel configuration registers became corrupted,3
CRITICAL,PCIE_CTRL,PCIe link state transition failed after hot reset,PCIE_CTRL PCIe link state transition failed after hot reset,6
ERROR,MEM_CTRL,Memory page table entry corruption detected,MEM_CTRL Memory page table entry corruption detected,1
CRITICAL,DMA_ENGINE,DMA engine self-test failed critically,DMA_ENGINE DMA engine self-test failed critically,3
CRITICAL,FIFO_BUF,"Dual-port FIFO internal state inconsistency, data corruption","FIFO_BUF Dual-port FIFO internal state inconsistency, data corruption",5
ERROR,CLOCK_MANAGER,Clock domain crossing bridge logic fault,CLOCK_MANAGER Clock domain crossing bridge logic fault,0
ERROR,POWER_CTRL,Power-on reset (POR) deassertion sequence error.,POWER_CTRL Power-on reset (POR) deassertion sequence error.,4
WARNING,CLOCK_MANAGER,Clock source output drive strength degraded,CLOCK_MANAGER Clock source output drive strength degraded,0
CRITICAL,FIFO_BUF,FIFO power domain isolation failure,FIFO_BUF FIFO power domain isolation failure,-1
ERROR,INTERRUPT_CTRL,Unexpected interrupt controller reset,INTERRUPT_CTRL Unexpected interrupt controller reset,1
INFO,DDR_CTRL,DDR controller self-test passed,DDR_CTRL DDR controller self-test passed,1
INFO,DDR_CTRL,DDR initialization sequence passed.,DDR_CTRL DDR initialization sequence passed.,1
ERROR,POWER_CTRL,Voltage monitoring unit reports under-voltage,POWER_CTRL Voltage monitoring unit reports under-voltage,4
WARNING,CACHE_CTRL,Cache fill buffer nearing capacity,CACHE_CTRL Cache fill buffer nearing capacity,1
WARNING,DMA_ENGINE,DMA channel busy status unexpectedly asserted,DMA_ENGINE DMA channel busy status unexpectedly asserted,3
ERROR,DDR_CTRL,DDR initialization sequence stalled at phase 2.,DDR_CTRL DDR initialization sequence stalled at phase 2.,1
ERROR,MEM_CTRL,Address translation unit reported an access fault,MEM_CTRL Address translation unit reported an access fault,1
CRITICAL,PCIE_CTRL,PCIe hot-reset command failed to propagate to endpoint,PCIE_CTRL PCIe hot-reset command failed to propagate to endpoint,6
ERROR,DMA_ENGINE,DMA descriptor format error detected for channel 0.,DMA_ENGINE DMA descriptor format error detected for channel 0.,3
INFO,DDR_CTRL,DDR memory operating at full speed,DDR_CTRL DDR memory operating at full speed,1
CRITICAL,MEM_CTRL,Memory data bus arbitration deadlock,MEM_CTRL Memory data bus arbitration deadlock,1
WARNING,CACHE_CTRL,Cache line fill rate exceeding threshold,CACHE_CTRL Cache line fill rate exceeding threshold,1
ERROR,INTERRUPT_CTRL,Interrupt mask register value unexpected,INTERRUPT_CTRL Interrupt mask register value unexpected,1
CRITICAL,AXI_CTRL,"AXI bridge internal state machine crashed, unresponsive.","AXI_CTRL AXI bridge internal state machine crashed, unresponsive.",-1
WARNING,POWER_CTRL,"Voltage regulator output ripple detected, within spec on VDD_IO","POWER_CTRL Voltage regulator output ripple detected, within spec on VDD_IO",4
INFO,CLOCK_MANAGER,Clock propagation delay optimized,CLOCK_MANAGER Clock propagation delay optimized,-1
ERROR,CLOCK_MANAGER,Clock generator output frequency drift detected,CLOCK_MANAGER Clock generator output frequency drift detected,0
WARNING,DDR_CTRL,DDR controller temperature exceeding limits,DDR_CTRL DDR controller temperature exceeding limits,1
INFO,DDR_CTRL,DDR memory clock frequency switched to 800MHz,DDR_CTRL DDR memory clock frequency switched to 800MHz,1
INFO,FIFO_BUF,"Data written to FIFO, available space reduced","FIFO_BUF Data written to FIFO, available space reduced",5
ERROR,AXI_CTRL,AXI Read Data (RDATA) received but RRESP was not OKAY.,AXI_CTRL AXI Read Data (RDATA) received but RRESP was not OKAY.,2
ERROR,MEM_CTRL,Memory address decoding error,MEM_CTRL Memory address decoding error,1
WARNING,FIFO_BUF,FIFO pointer comparison logic error,FIFO_BUF FIFO pointer comparison logic error,5
CRITICAL,DDR_CTRL,DDR controller internal state machine critical failure,DDR_CTRL DDR controller internal state machine critical failure,1
CRITICAL,AXI_CTRL,AXI bus deadlock detected,AXI_CTRL AXI bus deadlock detected,2
ERROR,POWER_CTRL,Voltage regulator V_AUDIO response timeout,POWER_CTRL Voltage regulator V_AUDIO response timeout,4
WARNING,FIFO_BUF,FIFO queue depth approaching saturation (at 75% capacity).,FIFO_BUF FIFO queue depth approaching saturation (at 75% capacity).,5
WARNING,DMA_ENGINE,DMA queue saturation detected for channel 0x7,DMA_ENGINE DMA queue saturation detected for channel 0x7,3
INFO,AXI_CTRL,AXI burst write completed for address range,AXI_CTRL AXI burst write completed for address range,2
ERROR,FIFO_BUF,FIFO_VIDEO_IN overflow detected,FIFO_BUF FIFO_VIDEO_IN overflow detected,5
INFO,INTERRUPT_CTRL,Interrupt dispatch completed,INTERRUPT_CTRL Interrupt dispatch completed,1
INFO,AXI_CTRL,AXI bus idle for 100 cycles,AXI_CTRL AXI bus idle for 100 cycles,2
INFO,FIFO_BUF,All FIFO buffers empty,FIFO_BUF All FIFO buffers empty,5
WARNING,PCIE_CTRL,PCIe receiver buffer empty during expected data burst,PCIE_CTRL PCIe receiver buffer empty during expected data burst,6
WARNING,AXI_CTRL,"AXI outstanding read transactions high, potential bottleneck","AXI_CTRL AXI outstanding read transactions high, potential bottleneck",2
WARNING,INTERRUPT_CTRL,Interrupt service routine (ISR) execution time exceeding threshold,INTERRUPT_CTRL Interrupt service routine (ISR) execution time exceeding threshold,1
CRITICAL,AXI_CTRL,"AXI fabric deadlock detected, no further transactions progressing","AXI_CTRL AXI fabric deadlock detected, no further transactions progressing",2
ERROR,DMA_ENGINE,DMA channel 7 arbitration priority inversion,DMA_ENGINE DMA channel 7 arbitration priority inversion,3
ERROR,CLOCK_MANAGER,Clock stability issue,CLOCK_MANAGER Clock stability issue,0
ERROR,CACHE_CTRL,Cache access permission denied,CACHE_CTRL Cache access permission denied,-1
WARNING,CLOCK_MANAGER,Frequency deviation detected on secondary clock source.,CLOCK_MANAGER Frequency deviation detected on secondary clock source.,0
CRITICAL,MEM_CTRL,Memory controller assertion failure at reset,MEM_CTRL Memory controller assertion failure at reset,1
WARNING,CLOCK_MANAGER,Clock skew approaching unsafe range between domains Y and Secondary.,CLOCK_MANAGER Clock skew approaching unsafe range between domains Y and Secondary.,0
CRITICAL,PCIE_CTRL,PCIe lane synchronization lost,PCIE_CTRL PCIe lane synchronization lost,6
ERROR,INTERRUPT_CTRL,Interrupt controller internal state machine error,INTERRUPT_CTRL Interrupt controller internal state machine error,1
ERROR,PCIE_CTRL,PCIe completion timeout detected for device ID 0x1234,PCIE_CTRL PCIe completion timeout detected for device ID 0x1234,6
CRITICAL,PCIE_CTRL,PCIe link state machine stuck in detect state,PCIE_CTRL PCIe link state machine stuck in detect state,6
INFO,DDR_CTRL,Scheduled maintenance routine executed for DDR_CTRL.,DDR_CTRL Scheduled maintenance routine executed for DDR_CTRL.,-1
WARNING,DDR_CTRL,DDR controller latency spike observed,DDR_CTRL DDR controller latency spike observed,1
WARNING,DDR_CTRL,Refresh rate deviation,DDR_CTRL Refresh rate deviation,1
WARNING,PCIE_CTRL,PCIe error reported on AER (Advanced Error Reporting) capability,PCIE_CTRL PCIe error reported on AER (Advanced Error Reporting) capability,6
CRITICAL,MEM_CTRL,Memory controller state machine entered illegal state (invalid state transition),MEM_CTRL Memory controller state machine entered illegal state (invalid state transition),1
WARNING,CLOCK_MANAGER,CLOCK_MANAGER backpressure asserted by CLOCK_MANAGER for extended period.,CLOCK_MANAGER CLOCK_MANAGER backpressure asserted by CLOCK_MANAGER for extended period.,-1
ERROR,CACHE_CTRL,Cache dirty bit corruption.,CACHE_CTRL Cache dirty bit corruption.,1
WARNING,AXI_CTRL,"AXI write data channel backpressure detected, potential stall.","AXI_CTRL AXI write data channel backpressure detected, potential stall.",2
ERROR,AXI_CTRL,AXI burst size negotiation failure,AXI_CTRL AXI burst size negotiation failure,2
ERROR,AXI_CTRL,AXI decode error (DECERR) detected,AXI_CTRL AXI decode error (DECERR) detected,2
INFO,CACHE_CTRL,Cache line clean state asserted,CACHE_CTRL Cache line clean state asserted,1
WARNING,MEM_CTRL,Memory write queue depth high.,MEM_CTRL Memory write queue depth high.,1
INFO,DMA_ENGINE,DMA channel 0 configured for high priority,DMA_ENGINE DMA channel 0 configured for high priority,3
CRITICAL,AXI_CTRL,AXI protocol bridge deadlock,AXI_CTRL AXI protocol bridge deadlock,2
CRITICAL,POWER_CTRL,System power-off initiated due to critical timing violation.,POWER_CTRL System power-off initiated due to critical timing violation.,4
INFO,POWER_CTRL,"Voltage regulator response timeout detected, but recovered","POWER_CTRL Voltage regulator response timeout detected, but recovered",4
ERROR,POWER_CTRL,Voltage drop detected on core rail (VDD_CORE < 1.13V),POWER_CTRL Voltage drop detected on core rail (VDD_CORE < 1.13V),4
ERROR,PCIE_CTRL,PCIe hotplug event detected without proper device enumeration,PCIE_CTRL PCIe hotplug event detected without proper device enumeration,6
CRITICAL,DDR_CTRL,DDR PHY training sequence failure detected,DDR_CTRL DDR PHY training sequence failure detected,1
CRITICAL,MEM_CTRL,Memory bank access deadlock detected,MEM_CTRL Memory bank access deadlock detected,1
CRITICAL,DDR_CTRL,"DDR memory subsystem unrecoverable error, DIMM replacement advised","DDR_CTRL DDR memory subsystem unrecoverable error, DIMM replacement advised",1
INFO,FIFO_BUF,FIFO 'EVENT' data written successfully,FIFO_BUF FIFO 'EVENT' data written successfully,5
CRITICAL,PCIE_CTRL,PCIe core internal state machine entered invalid state,PCIE_CTRL PCIe core internal state machine entered invalid state,6
INFO,PCIE_CTRL,PCIe physical layer link re-established.,PCIE_CTRL PCIe physical layer link re-established.,6
WARNING,FIFO_BUF,Write operation blocked due to full FIFO.,FIFO_BUF Write operation blocked due to full FIFO.,5
CRITICAL,DMA_ENGINE,DMA controller arbitration deadlock detected,DMA_ENGINE DMA controller arbitration deadlock detected,3
ERROR,DMA_ENGINE,DMA control register access invalid state transition.,DMA_ENGINE DMA control register access invalid state transition.,3
INFO,AXI_CTRL,AXI transaction ID 0x12 successfully completed.,AXI_CTRL AXI transaction ID 0x12 successfully completed.,2
INFO,PCIE_CTRL,PCIe root complex link negotiation completed,PCIE_CTRL PCIe root complex link negotiation completed,6
ERROR,FIFO_BUF,FIFO read operation failed due to invalid pointer,FIFO_BUF FIFO read operation failed due to invalid pointer,5
ERROR,CACHE_CTRL,Coherence protocol violation (MESI),CACHE_CTRL Coherence protocol violation (MESI),1
CRITICAL,MEM_CTRL,Memory controller command queue deadlock,MEM_CTRL Memory controller command queue deadlock,1
WARNING,CACHE_CTRL,Cache eviction queue for L2 cache is 90% full.,CACHE_CTRL Cache eviction queue for L2 cache is 90% full.,1
INFO,DMA_ENGINE,DMA transfer completed successfully.,DMA_ENGINE DMA transfer completed successfully.,3
WARNING,AXI_CTRL,AXI master 'cpu_core' making multiple consecutive stalled requests,AXI_CTRL AXI master 'cpu_core' making multiple consecutive stalled requests,-1
ERROR,AXI_CTRL,AXI transaction timeout detected,AXI_CTRL AXI transaction timeout detected,2
WARNING,AXI_CTRL,AXI master outstanding transaction count nearing limit for slave ID 0x05.,AXI_CTRL AXI master outstanding transaction count nearing limit for slave ID 0x05.,2
ERROR,PCIE_CTRL,"PCIe device hot-plug event detected, but configuration failed","PCIE_CTRL PCIe device hot-plug event detected, but configuration failed",6
ERROR,FIFO_BUF,FIFO data path gate stuck closed during read,FIFO_BUF FIFO data path gate stuck closed during read,5
INFO,CLOCK_MANAGER,PLL Y locked successfully.,CLOCK_MANAGER PLL Y locked successfully.,0
ERROR,POWER_CTRL,Core voltage rail stability issue,POWER_CTRL Core voltage rail stability issue,4
INFO,DDR_CTRL,DDR power-down mode exited,DDR_CTRL DDR power-down mode exited,1
WARNING,DMA_ENGINE,DMA channel 7 arbitration priority contention,DMA_ENGINE DMA channel 7 arbitration priority contention,3
CRITICAL,CLOCK_MANAGER,"Primary clock source failure, system unable to operate.","CLOCK_MANAGER Primary clock source failure, system unable to operate.",0
CRITICAL,POWER_CTRL,Critical voltage rail dropped below threshold,POWER_CTRL Critical voltage rail dropped below threshold,4
ERROR,MEM_CTRL,Memory protection violation for access type 'write',MEM_CTRL Memory protection violation for access type 'write',1
INFO,CACHE_CTRL,Cache set associative policy configured,CACHE_CTRL Cache set associative policy configured,1
CRITICAL,PCIE_CTRL,"PCIe lane synchronization lost, fatal physical layer error.","PCIE_CTRL PCIe lane synchronization lost, fatal physical layer error.",6
WARNING,CLOCK_MANAGER,Clock domain crossing logic experiencing high metastability rate,CLOCK_MANAGER Clock domain crossing logic experiencing high metastability rate,0
WARNING,AXI_CTRL,AXI write data channel underflow,AXI_CTRL AXI write data channel underflow,2
INFO,PCIE_CTRL,PCIe link credit updated.,PCIE_CTRL PCIe link credit updated.,6
CRITICAL,MEM_CTRL,Uncorrectable ECC error on critical memory region,MEM_CTRL Uncorrectable ECC error on critical memory region,1
INFO,POWER_CTRL,Regulator V_DDR activated,POWER_CTRL Regulator V_DDR activated,4
INFO,CLOCK_MANAGER,Clock generator output stable,CLOCK_MANAGER Clock generator output stable,0
CRITICAL,CLOCK_MANAGER,"System reference clock lost, halting all clock generation.","CLOCK_MANAGER System reference clock lost, halting all clock generation.",0
ERROR,CLOCK_MANAGER,CLOCK_MANAGER: clock domain crossing failure - asynchronous bridge synchronization failure detected.,CLOCK_MANAGER CLOCK_MANAGER: clock domain crossing failure - asynchronous bridge synchronization failure detected.,0
ERROR,MEM_CTRL,Memory read-modify-write operation failed,MEM_CTRL Memory read-modify-write operation failed,1
ERROR,CACHE_CTRL,Cache tag comparison failed for address 0x12345678,CACHE_CTRL Cache tag comparison failed for address 0x12345678,1
WARNING,MEM_CTRL,Memory bus write latency approaching critical path,MEM_CTRL Memory bus write latency approaching critical path,1
CRITICAL,MEM_CTRL,Memory controller internal state machine entered invalid state,MEM_CTRL Memory controller internal state machine entered invalid state,1
WARNING,PCIE_CTRL,PCIe device error reporting disabled,PCIE_CTRL PCIe device error reporting disabled,6
ERROR,CACHE_CTRL,Cache way miss prediction resulting in pipeline stall,CACHE_CTRL Cache way miss prediction resulting in pipeline stall,-1
ERROR,CACHE_CTRL,Cache entry invalidation logic fault,CACHE_CTRL Cache entry invalidation logic fault,1
ERROR,FIFO_BUF,Invalid read access attempt on empty FIFO,FIFO_BUF Invalid read access attempt on empty FIFO,5
ERROR,POWER_CTRL,Over-current condition detected on peripheral power rail,POWER_CTRL Over-current condition detected on peripheral power rail,4
INFO,PCIE_CTRL,PCIe device functional reset completed,PCIE_CTRL PCIe device functional reset completed,6
INFO,DMA_ENGINE,DMA transfer from memory to peripheral completed,DMA_ENGINE DMA transfer from memory to peripheral completed,3
ERROR,DDR_CTRL,DDR CAS latency violation detected,DDR_CTRL DDR CAS latency violation detected,1
WARNING,AXI_CTRL,AXI master issuing transactions with incorrect memory type,AXI_CTRL AXI master issuing transactions with incorrect memory type,2
ERROR,DMA_ENGINE,DMA descriptor chain pointer invalid,DMA_ENGINE DMA descriptor chain pointer invalid,3
INFO,POWER_CTRL,Core power rail initialized successfully,POWER_CTRL Core power rail initialized successfully,4
INFO,CLOCK_MANAGER,Clock domain crossing (CDC) analysis completed,CLOCK_MANAGER Clock domain crossing (CDC) analysis completed,0
CRITICAL,PCIE_CTRL,PCIe Physical Layer reset timeout,PCIE_CTRL PCIe Physical Layer reset timeout,6
CRITICAL,POWER_CTRL,System power-on reset circuit failed,POWER_CTRL System power-on reset circuit failed,4
WARNING,DMA_ENGINE,DMA descriptor fetch latency increasing.,DMA_ENGINE DMA descriptor fetch latency increasing.,3
WARNING,DMA_ENGINE,DMA channel request starvation detected,DMA_ENGINE DMA channel request starvation detected,3
CRITICAL,CACHE_CTRL,"Cache data array ECC uncorrectable error, critical data loss","CACHE_CTRL Cache data array ECC uncorrectable error, critical data loss",1
WARNING,CACHE_CTRL,Cache eviction policy triggered frequently,CACHE_CTRL Cache eviction policy triggered frequently,1
INFO,FIFO_BUF,FIFO depth reconfigured to 64.,FIFO_BUF FIFO depth reconfigured to 64.,5
ERROR,CACHE_CTRL,Cache line write-back failure to main memory.,CACHE_CTRL Cache line write-back failure to main memory.,1
INFO,FIFO_BUF,FIFO almost full flag cleared,FIFO_BUF FIFO almost full flag cleared,5
CRITICAL,MEM_CTRL,Memory address decoding logic output an invalid address,MEM_CTRL Memory address decoding logic output an invalid address,1
ERROR,FIFO_BUF,FIFO control path stuck-at fault,FIFO_BUF FIFO control path stuck-at fault,5
INFO,DDR_CTRL,DDR controller in normal operation mode,DDR_CTRL DDR controller in normal operation mode,1
ERROR,AXI_CTRL,AXI bus arbitration failure,AXI_CTRL AXI bus arbitration failure,2
ERROR,PCIE_CTRL,PCIe Data Link Layer Packet (DLLP) sequence number mismatch,PCIE_CTRL PCIe Data Link Layer Packet (DLLP) sequence number mismatch,6
WARNING,FIFO_BUF,Input FIFO depth approaching 75% capacity,FIFO_BUF Input FIFO depth approaching 75% capacity,5
WARNING,AXI_CTRL,AXI interconnect congestion detected on shared resource,AXI_CTRL AXI interconnect congestion detected on shared resource,2
CRITICAL,POWER_CTRL,Power controller internal bus contention leading to system hang.,POWER_CTRL Power controller internal bus contention leading to system hang.,-1
INFO,PCIE_CTRL,PCIe device BARs successfully configured,PCIE_CTRL PCIe device BARs successfully configured,6
CRITICAL,MEM_CTRL,Critical memory access deadlock,MEM_CTRL Critical memory access deadlock,1
INFO,POWER_CTRL,Power-off sequence initiated for system,POWER_CTRL Power-off sequence initiated for system,4
INFO,INTERRUPT_CTRL,Interrupt aggregation enabled,INTERRUPT_CTRL Interrupt aggregation enabled,-1
CRITICAL,PCIE_CTRL,PCIe configuration space access deadlocked,PCIE_CTRL PCIe configuration space access deadlocked,6
CRITICAL,PCIE_CTRL,PCIe Endpoint power fault detected,PCIE_CTRL PCIe Endpoint power fault detected,6
INFO,PCIE_CTRL,PCIe hot-plug remove event detected,PCIE_CTRL PCIe hot-plug remove event detected,6
CRITICAL,MEM_CTRL,Memory ECC scrubber detected a pattern of single-bit errors indicating future failure,MEM_CTRL Memory ECC scrubber detected a pattern of single-bit errors indicating future failure,1
ERROR,PCIE_CTRL,PCIe symbol decoding error on lane 2,PCIE_CTRL PCIe symbol decoding error on lane 2,6
ERROR,INTERRUPT_CTRL,Interrupt controller internal state machine entered invalid state.,INTERRUPT_CTRL Interrupt controller internal state machine entered invalid state.,1
CRITICAL,DDR_CTRL,DDR interface I/O buffer stuck-at-low,DDR_CTRL DDR interface I/O buffer stuck-at-low,-1
INFO,MEM_CTRL,Memory controller entered low-power self-refresh mode.,MEM_CTRL Memory controller entered low-power self-refresh mode.,1
ERROR,POWER_CTRL,Voltage monitor self-test failed,POWER_CTRL Voltage monitor self-test failed,4
ERROR,FIFO_BUF,FIFO 'transaction_log' detected data corruption during write,FIFO_BUF FIFO 'transaction_log' detected data corruption during write,5
INFO,PCIE_CTRL,PCIe configuration space read completed.,PCIE_CTRL PCIe configuration space read completed.,6
INFO,DDR_CTRL,DDR power-up sequence completed,DDR_CTRL DDR power-up sequence completed,1
INFO,CLOCK_MANAGER,Clock source selected: internal,CLOCK_MANAGER Clock source selected: internal,0
WARNING,INTERRUPT_CTRL,INTERRUPT_CTRL expected response delay exceeding threshold (current: 12 cycles).,INTERRUPT_CTRL INTERRUPT_CTRL expected response delay exceeding threshold (current: 12 cycles).,1
ERROR,MEM_CTRL,Single bit ECC error corrected at address 0xABCDEF00,MEM_CTRL Single bit ECC error corrected at address 0xABCDEF00,1
CRITICAL,DDR_CTRL,"DDR interface initialization failure, memory not usable","DDR_CTRL DDR interface initialization failure, memory not usable",1
INFO,DMA_ENGINE,Data path reset for DMA_ENGINE completed.,DMA_ENGINE Data path reset for DMA_ENGINE completed.,3
ERROR,CLOCK_MANAGER,PLL lock time extended beyond specification,CLOCK_MANAGER PLL lock time extended beyond specification,0
CRITICAL,MEM_CTRL,Memory controller internal self-test failure,MEM_CTRL Memory controller internal self-test failure,1
WARNING,FIFO_BUF,FIFO depth usage at 90% during stress test,FIFO_BUF FIFO depth usage at 90% during stress test,5
CRITICAL,POWER_CTRL,System power-off sequence failed,POWER_CTRL System power-off sequence failed,4
WARNING,DMA_ENGINE,"DMA channel 7 stalled, waiting for bus access.","DMA_ENGINE DMA channel 7 stalled, waiting for bus access.",3
WARNING,CLOCK_MANAGER,Frequency deviation detected on 1076MHz clock.,CLOCK_MANAGER Frequency deviation detected on 1076MHz clock.,0
WARNING,DDR_CTRL,ZQ calibration warning,DDR_CTRL ZQ calibration warning,1
INFO,FIFO_BUF,"Write operation successful, data committed.","FIFO_BUF Write operation successful, data committed.",5
INFO,PCIE_CTRL,PCIe link up at Gen4 x16 speed,PCIE_CTRL PCIe link up at Gen4 x16 speed,6
ERROR,FIFO_BUF,FIFO empty status detected prematurely,FIFO_BUF FIFO empty status detected prematurely,5
INFO,PCIE_CTRL,PCIe link up and stable at Gen4 x4,PCIE_CTRL PCIe link up and stable at Gen4 x4,6
INFO,POWER_CTRL,Power domain enabled for peripheral block,POWER_CTRL Power domain enabled for peripheral block,4
WARNING,MEM_CTRL,Memory retention voltage marginal during standby,MEM_CTRL Memory retention voltage marginal during standby,1
ERROR,MEM_CTRL,Write data verification error after memory write,MEM_CTRL Write data verification error after memory write,1
INFO,POWER_CTRL,System Power-on reset sequence completed,POWER_CTRL System Power-on reset sequence completed,4
CRITICAL,CLOCK_MANAGER,"Primary system clock halted, recovery initiated","CLOCK_MANAGER Primary system clock halted, recovery initiated",0
ERROR,PCIE_CTRL,PCIe transaction layer header corruption,PCIE_CTRL PCIe transaction layer header corruption,6
INFO,DMA_ENGINE,DMA transfer to memory region X completed,DMA_ENGINE DMA transfer to memory region X completed,3
INFO,POWER_CTRL,Low-power mode entry sequence initiated,POWER_CTRL Low-power mode entry sequence initiated,4
INFO,CLOCK_MANAGER,Main system clock successfully switched to backup oscillator,CLOCK_MANAGER Main system clock successfully switched to backup oscillator,0
INFO,DMA_ENGINE,DMA transfer to peripheral 'SPI0' initiated,DMA_ENGINE DMA transfer to peripheral 'SPI0' initiated,3
WARNING,POWER_CTRL,Power rail current spikes detected during high load,POWER_CTRL Power rail current spikes detected during high load,4
INFO,CLOCK_MANAGER,System clock source switched to external crystal,CLOCK_MANAGER System clock source switched to external crystal,0
INFO,MEM_CTRL,Memory refresh rate configured,MEM_CTRL Memory refresh rate configured,1
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding expected threshold of 285 cycles,INTERRUPT_CTRL Interrupt latency exceeding expected threshold of 285 cycles,1
WARNING,DMA_ENGINE,DMA channel 1 completion status delayed,DMA_ENGINE DMA channel 1 completion status delayed,3
INFO,POWER_CTRL,Power state transition 'active' to 'idle' completed,POWER_CTRL Power state transition 'active' to 'idle' completed,4
ERROR,PCIE_CTRL,PCIe device driver reports fatal error,PCIE_CTRL PCIe device driver reports fatal error,6
WARNING,FIFO_BUF,FIFO threshold for almost full reached,FIFO_BUF FIFO threshold for almost full reached,5
CRITICAL,CACHE_CTRL,Unrecoverable cache memory array error,CACHE_CTRL Unrecoverable cache memory array error,1
WARNING,PCIE_CTRL,PCIe link retraining initiated due to CRC errors,PCIE_CTRL PCIe link retraining initiated due to CRC errors,6
WARNING,DMA_ENGINE,DMA channel paused due to external event,DMA_ENGINE DMA channel paused due to external event,3
ERROR,MEM_CTRL,Memory controller state machine transition invalid,MEM_CTRL Memory controller state machine transition invalid,1
INFO,INTERRUPT_CTRL,Interrupt handler invoked for ID 5,INTERRUPT_CTRL Interrupt handler invoked for ID 5,1
CRITICAL,MEM_CTRL,Double-bit error detected by ECC on critical system data at 0xABCDEF00.,MEM_CTRL Double-bit error detected by ECC on critical system data at 0xABCDEF00.,1
WARNING,CACHE_CTRL,Cache coherence snooping delay observed,CACHE_CTRL Cache coherence snooping delay observed,1
INFO,DMA_ENGINE,DMA channel 3 configured successfully for scatter-gather transfer,DMA_ENGINE DMA channel 3 configured successfully for scatter-gather transfer,3
WARNING,FIFO_BUF,FIFO data integrity check reporting minor discrepancies,FIFO_BUF FIFO data integrity check reporting minor discrepancies,5
ERROR,PCIE_CTRL,"PCIe link training failure detected, link down","PCIE_CTRL PCIe link training failure detected, link down",6
WARNING,AXI_CTRL,AXI write response buffer overfill warning,AXI_CTRL AXI write response buffer overfill warning,2
ERROR,PCIE_CTRL,PCIe root complex received malformed TLP header.,PCIE_CTRL PCIe root complex received malformed TLP header.,6
ERROR,POWER_CTRL,Core power domain unable to power up,POWER_CTRL Core power domain unable to power up,4
CRITICAL,DMA_ENGINE,DMA engine unable to complete any transfers,DMA_ENGINE DMA engine unable to complete any transfers,3
INFO,INTERRUPT_CTRL,Interrupt source acknowledged,INTERRUPT_CTRL Interrupt source acknowledged,1
ERROR,DMA_ENGINE,DMA engine arbiter granted access to inactive channel,DMA_ENGINE DMA engine arbiter granted access to inactive channel,3
INFO,FIFO_BUF,FIFO data available,FIFO_BUF FIFO data available,5
ERROR,DDR_CTRL,DDR memory 'DIMM_C' detected high number of bit errors,DDR_CTRL DDR memory 'DIMM_C' detected high number of bit errors,1
WARNING,PCIE_CTRL,CRC error rate elevated,PCIE_CTRL CRC error rate elevated,6
WARNING,MEM_CTRL,"Memory write buffer nearing capacity, could cause stalls.","MEM_CTRL Memory write buffer nearing capacity, could cause stalls.",1
WARNING,CACHE_CTRL,Cache tag parity error detected in L2,CACHE_CTRL Cache tag parity error detected in L2,1
CRITICAL,MEM_CTRL,Internal memory data path stuck-at fault,MEM_CTRL Internal memory data path stuck-at fault,1
WARNING,DDR_CTRL,DDR memory access frequency high,DDR_CTRL DDR memory access frequency high,1
ERROR,DMA_ENGINE,DMA channel 14 encountered bus error during transfer,DMA_ENGINE DMA channel 14 encountered bus error during transfer,3
ERROR,FIFO_BUF,FIFO write enable asserted when full,FIFO_BUF FIFO write enable asserted when full,5
CRITICAL,DDR_CTRL,DDR calibration sequence failed due to timing,DDR_CTRL DDR calibration sequence failed due to timing,1
ERROR,AXI_CTRL,AXI protocol violation: AWVALID without AWREADY timeout,AXI_CTRL AXI protocol violation: AWVALID without AWREADY timeout,2
WARNING,FIFO_BUF,FIFO bypass path engaged due to high latency,FIFO_BUF FIFO bypass path engaged due to high latency,5
INFO,FIFO_BUF,FIFO_BUF_14 ready to accept new data,FIFO_BUF FIFO_BUF_14 ready to accept new data,5
CRITICAL,MEM_CTRL,Memory module initialization failed.,MEM_CTRL Memory module initialization failed.,1
INFO,AXI_CTRL,AXI QoS settings applied,AXI_CTRL AXI QoS settings applied,-1
ERROR,POWER_CTRL,Voltage regulator enters unsafe operating mode,POWER_CTRL Voltage regulator enters unsafe operating mode,-1
CRITICAL,FIFO_BUF,"CRITICAL: Unrecoverable FIFO state detected, requires hard reset.","FIFO_BUF CRITICAL: Unrecoverable FIFO state detected, requires hard reset.",5
ERROR,DDR_CTRL,DDR training sequence failed.,DDR_CTRL DDR training sequence failed.,1
ERROR,AXI_CTRL,AXI transaction timeout detected for read address channel,AXI_CTRL AXI transaction timeout detected for read address channel,2
INFO,POWER_CTRL,Power domain isolation test passed,POWER_CTRL Power domain isolation test passed,4
ERROR,DDR_CTRL,DDR command queue overflowed during high traffic,DDR_CTRL DDR command queue overflowed during high traffic,1
CRITICAL,AXI_CTRL,CRITICAL: AXI bridge control logic entered unrecoverable state 0xAB.,AXI_CTRL CRITICAL: AXI bridge control logic entered unrecoverable state 0xAB.,2
INFO,FIFO_BUF,Buffer cleared,FIFO_BUF Buffer cleared,5
WARNING,AXI_CTRL,AXI slave not responding to `AWVALID`,AXI_CTRL AXI slave not responding to `AWVALID`,2
WARNING,DDR_CTRL,"DDR timing parameters marginally stable, check system margins","DDR_CTRL DDR timing parameters marginally stable, check system margins",1
WARNING,DMA_ENGINE,DMA channel 10 completion interrupt not asserted for 500us,DMA_ENGINE DMA channel 10 completion interrupt not asserted for 500us,3
ERROR,FIFO_BUF,FIFO output enable stuck low,FIFO_BUF FIFO output enable stuck low,5
WARNING,INTERRUPT_CTRL,"Interrupt queue approaching saturation, potential for dropped interrupts.","INTERRUPT_CTRL Interrupt queue approaching saturation, potential for dropped interrupts.",1
ERROR,AXI_CTRL,AXI bus contention detected on shared interconnect,AXI_CTRL AXI bus contention detected on shared interconnect,2
ERROR,CLOCK_MANAGER,Gated clock glitch detected,CLOCK_MANAGER Gated clock glitch detected,0
WARNING,DMA_ENGINE,DMA scatter-gather list parsing error count incrementing,DMA_ENGINE DMA scatter-gather list parsing error count incrementing,3
WARNING,CLOCK_MANAGER,Clock enable glitch detected during mode switch,CLOCK_MANAGER Clock enable glitch detected during mode switch,0
INFO,INTERRUPT_CTRL,Interrupt controller configured for edge triggered IRQs,INTERRUPT_CTRL Interrupt controller configured for edge triggered IRQs,1
ERROR,DMA_ENGINE,DMA transfer completed with wrong byte count,DMA_ENGINE DMA transfer completed with wrong byte count,3
CRITICAL,MEM_CTRL,Memory read data returned with incorrect byte enables.,MEM_CTRL Memory read data returned with incorrect byte enables.,1
ERROR,INTERRUPT_CTRL,Interrupt controller internal state inconsistent,INTERRUPT_CTRL Interrupt controller internal state inconsistent,1
INFO,CLOCK_MANAGER,Clock divider configuration updated successfully,CLOCK_MANAGER Clock divider configuration updated successfully,0
INFO,PCIE_CTRL,PCIe PME event successfully sent,PCIE_CTRL PCIe PME event successfully sent,6
WARNING,FIFO_BUF,FIFO almost empty,FIFO_BUF FIFO almost empty,5
WARNING,POWER_CTRL,Dynamic voltage and frequency scaling (DVFS) transition pending.,POWER_CTRL Dynamic voltage and frequency scaling (DVFS) transition pending.,9
INFO,AXI_CTRL,AXI channel configured for burst access,AXI_CTRL AXI channel configured for burst access,2
ERROR,DDR_CTRL,DRAM initialization sequence error,DDR_CTRL DRAM initialization sequence error,1
WARNING,FIFO_BUF,"FIFO write pointer approaching read pointer, potential overflow","FIFO_BUF FIFO write pointer approaching read pointer, potential overflow",5
WARNING,INTERRUPT_CTRL,Interrupt latency increasing for high-priority IRQs,INTERRUPT_CTRL Interrupt latency increasing for high-priority IRQs,1
WARNING,CACHE_CTRL,L1 cache miss rate above acceptable threshold.,CACHE_CTRL L1 cache miss rate above acceptable threshold.,1
WARNING,AXI_CTRL,"AXI handshake delay approaching threshold, potential timing violation.","AXI_CTRL AXI handshake delay approaching threshold, potential timing violation.",2
CRITICAL,POWER_CTRL,Redundant power supply failure,POWER_CTRL Redundant power supply failure,-1
INFO,INTERRUPT_CTRL,Interrupt handler for IRQ_0 invoked,INTERRUPT_CTRL Interrupt handler for IRQ_0 invoked,1
WARNING,PCIE_CTRL,PCIe device capability register conflict,PCIE_CTRL PCIe device capability register conflict,6
ERROR,CACHE_CTRL,Cache dirty bit logic fault,CACHE_CTRL Cache dirty bit logic fault,1
INFO,PCIE_CTRL,"PCIe hot-plug event detected, device added","PCIE_CTRL PCIe hot-plug event detected, device added",6
WARNING,FIFO_BUF,FIFO read operation returning stale data,FIFO_BUF FIFO read operation returning stale data,5
INFO,DMA_ENGINE,DMA channel 1 transfer rate optimized,DMA_ENGINE DMA channel 1 transfer rate optimized,3
INFO,DMA_ENGINE,DMA transfer ID 0xABCD completed with no errors.,DMA_ENGINE DMA transfer ID 0xABCD completed with no errors.,3
ERROR,CLOCK_MANAGER,Gated clock signal showing glitches,CLOCK_MANAGER Gated clock signal showing glitches,0
ERROR,AXI_CTRL,AXI master 0x1A issued an invalid burst length (0xF),AXI_CTRL AXI master 0x1A issued an invalid burst length (0xF),2
ERROR,CACHE_CTRL,Cache tag RAM address corruption,CACHE_CTRL Cache tag RAM address corruption,1
CRITICAL,INTERRUPT_CTRL,Unmaskable interrupt storm detected,INTERRUPT_CTRL Unmaskable interrupt storm detected,1
WARNING,AXI_CTRL,AXI read data phase unexpected termination,AXI_CTRL AXI read data phase unexpected termination,2
ERROR,DMA_ENGINE,DMA channel 0 detected a data integrity error on bus,DMA_ENGINE DMA channel 0 detected a data integrity error on bus,3
INFO,DDR_CTRL,DDR write latency measured,DDR_CTRL DDR write latency measured,1
INFO,FIFO_BUF,Data entry X written to FIFO,FIFO_BUF Data entry X written to FIFO,5
ERROR,FIFO_BUF,FIFO synchronization logic failure,FIFO_BUF FIFO synchronization logic failure,5
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, potential stall","FIFO_BUF FIFO read pointer approaching write pointer, potential stall",5
WARNING,CLOCK_MANAGER,Clock spread spectrum modulation disabled unexpectedly,CLOCK_MANAGER Clock spread spectrum modulation disabled unexpectedly,-1
WARNING,INTERRUPT_CTRL,Interrupt controller queue backpressure asserted,INTERRUPT_CTRL Interrupt controller queue backpressure asserted,-1
WARNING,DMA_ENGINE,DMA control register read returned unexpected value,DMA_ENGINE DMA control register read returned unexpected value,3
WARNING,CACHE_CTRL,Cache fill buffer nearing capacity.,CACHE_CTRL Cache fill buffer nearing capacity.,1
CRITICAL,PCIE_CTRL,PCIe receiver equalization failure across multiple lanes,PCIE_CTRL PCIe receiver equalization failure across multiple lanes,6
CRITICAL,POWER_CTRL,Uncontrolled power cycle detected on main SoC,POWER_CTRL Uncontrolled power cycle detected on main SoC,-1
ERROR,CLOCK_MANAGER,Clock generation logic output stuck at high,CLOCK_MANAGER Clock generation logic output stuck at high,0
INFO,DDR_CTRL,DDR bus training completed successfully,DDR_CTRL DDR bus training completed successfully,1
ERROR,DMA_ENGINE,DMA descriptor fetch loop detected,DMA_ENGINE DMA descriptor fetch loop detected,3
WARNING,DMA_ENGINE,DMA channel in high-priority mode too long,DMA_ENGINE DMA channel in high-priority mode too long,3
WARNING,CLOCK_MANAGER,PLL frequency offset detected from target,CLOCK_MANAGER PLL frequency offset detected from target,0
ERROR,INTERRUPT_CTRL,"Interrupt controller internal deadlock, IRQs unresponsive","INTERRUPT_CTRL Interrupt controller internal deadlock, IRQs unresponsive",1
ERROR,AXI_CTRL,AXI write response mismatch detected for ID 0x05,AXI_CTRL AXI write response mismatch detected for ID 0x05,2
ERROR,DDR_CTRL,DDR DRAM chip select glitch detected,DDR_CTRL DDR DRAM chip select glitch detected,8
ERROR,PCIE_CTRL,PCIe hot-plug event caused link instability.,PCIE_CTRL PCIe hot-plug event caused link instability.,6
INFO,CACHE_CTRL,Cache line invalidate for address 0xFF00,CACHE_CTRL Cache line invalidate for address 0xFF00,1
INFO,MEM_CTRL,Memory controller entered low-power mode,MEM_CTRL Memory controller entered low-power mode,1
CRITICAL,INTERRUPT_CTRL,Interrupt controller priority encoder logic failed,INTERRUPT_CTRL Interrupt controller priority encoder logic failed,1
ERROR,POWER_CTRL,Voltage regulator VDD_RAM reported instability,POWER_CTRL Voltage regulator VDD_RAM reported instability,4
INFO,PCIE_CTRL,PCIe device 'USB_HOST' configuration successfully verified,PCIE_CTRL PCIe device 'USB_HOST' configuration successfully verified,6
INFO,DDR_CTRL,DDR memory initialized to default state.,DDR_CTRL DDR memory initialized to default state.,1
WARNING,CACHE_CTRL,CACHE_CTRL internal buffer approaching capacity (90% full).,CACHE_CTRL CACHE_CTRL internal buffer approaching capacity (90% full).,1
ERROR,AXI_CTRL,AXI read address channel protocol mismatch,AXI_CTRL AXI read address channel protocol mismatch,2
WARNING,DMA_ENGINE,DMA channel re-arbitration count high,DMA_ENGINE DMA channel re-arbitration count high,3
INFO,DMA_ENGINE,DMA channel 15 configured for new transfer,DMA_ENGINE DMA channel 15 configured for new transfer,3
ERROR,PCIE_CTRL,PCIE_CTRL: arbitration conflict - fairness algorithm failure detected.,PCIE_CTRL PCIE_CTRL: arbitration conflict - fairness algorithm failure detected.,-1
ERROR,DDR_CTRL,DDR DQ-DQS misalignment detected.,DDR_CTRL DDR DQ-DQS misalignment detected.,-1
INFO,CLOCK_MANAGER,PLL locked successfully,CLOCK_MANAGER PLL locked successfully,0
WARNING,AXI_CTRL,AXI protocol violation: unsupported transaction type,AXI_CTRL AXI protocol violation: unsupported transaction type,2
WARNING,CACHE_CTRL,Cache line fill buffer nearing capacity,CACHE_CTRL Cache line fill buffer nearing capacity,1
CRITICAL,DDR_CTRL,DDR memory calibration data invalid,DDR_CTRL DDR memory calibration data invalid,1
INFO,FIFO_BUF,FIFO 'rx_queue' reported 32 entries available for read,FIFO_BUF FIFO 'rx_queue' reported 32 entries available for read,-1
INFO,INTERRUPT_CTRL,Interrupt controller debug mode enabled,INTERRUPT_CTRL Interrupt controller debug mode enabled,1
INFO,FIFO_BUF,FIFO 'TX_DATA' cleared,FIFO_BUF FIFO 'TX_DATA' cleared,5
WARNING,DMA_ENGINE,DMA scatter-gather descriptor list corrupted,DMA_ENGINE DMA scatter-gather descriptor list corrupted,3
WARNING,DDR_CTRL,DDR command timing violation detected during burst read,DDR_CTRL DDR command timing violation detected during burst read,1
INFO,FIFO_BUF,"FIFO reset completed, all pointers cleared","FIFO_BUF FIFO reset completed, all pointers cleared",5
CRITICAL,DDR_CTRL,DDR memory controller unable to arbitrate between requests,DDR_CTRL DDR memory controller unable to arbitrate between requests,1
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold,CACHE_CTRL Cache miss rate exceeding expected threshold,1
WARNING,AXI_CTRL,AXI transaction ID reuse detected without full completion,AXI_CTRL AXI transaction ID reuse detected without full completion,2
WARNING,DMA_ENGINE,DMA channel maximum burst length exceeded,DMA_ENGINE DMA channel maximum burst length exceeded,3
WARNING,MEM_CTRL,Memory BIST failed on specific address range,MEM_CTRL Memory BIST failed on specific address range,1
ERROR,DDR_CTRL,DDR read latency violation,DDR_CTRL DDR read latency violation,1
WARNING,AXI_CTRL,AXI read burst length too short for request,AXI_CTRL AXI read burst length too short for request,2
INFO,FIFO_BUF,FIFO data written: 0xDEADBEEF,FIFO_BUF FIFO data written: 0xDEADBEEF,5
CRITICAL,POWER_CTRL,Persistent voltage instability causing unpredictable behavior,POWER_CTRL Persistent voltage instability causing unpredictable behavior,4
ERROR,CLOCK_MANAGER,Clock source switching transient detected,CLOCK_MANAGER Clock source switching transient detected,0
CRITICAL,POWER_CTRL,Power rail instability detected on 'VCC_SOC',POWER_CTRL Power rail instability detected on 'VCC_SOC',4
ERROR,CACHE_CTRL,"Cache eviction queue overflow, blocking new evictions","CACHE_CTRL Cache eviction queue overflow, blocking new evictions",1
ERROR,DMA_ENGINE,DMA channel doorbell register error,DMA_ENGINE DMA channel doorbell register error,3
WARNING,FIFO_BUF,FIFO_BUF internal buffer approaching capacity (84% full).,FIFO_BUF FIFO_BUF internal buffer approaching capacity (84% full).,5
CRITICAL,MEM_CTRL,Memory controller power cycling required,MEM_CTRL Memory controller power cycling required,1
WARNING,AXI_CTRL,AXI interconnect arbitration latency increasing,AXI_CTRL AXI interconnect arbitration latency increasing,2
WARNING,FIFO_BUF,FIFO latency exceeding expected threshold (180ns).,FIFO_BUF FIFO latency exceeding expected threshold (180ns).,5
CRITICAL,CLOCK_MANAGER,Entire clock tree for 'graphics_subsystem' unstable,CLOCK_MANAGER Entire clock tree for 'graphics_subsystem' unstable,-1
INFO,INTERRUPT_CTRL,Interrupt 15 successfully acknowledged.,INTERRUPT_CTRL Interrupt 15 successfully acknowledged.,1
WARNING,PCIE_CTRL,PCIe device driver timeout,PCIE_CTRL PCIe device driver timeout,6
WARNING,POWER_CTRL,Power consumption spike detected during load increase.,POWER_CTRL Power consumption spike detected during load increase.,4
CRITICAL,AXI_CTRL,"AXI bus master detected as rogue, system shutdown","AXI_CTRL AXI bus master detected as rogue, system shutdown",-1
INFO,DDR_CTRL,DDR channel 0 memory mapped successfully,DDR_CTRL DDR channel 0 memory mapped successfully,1
CRITICAL,CLOCK_MANAGER,"PLL output frequency out of specification range, fatal","CLOCK_MANAGER PLL output frequency out of specification range, fatal",0
WARNING,DMA_ENGINE,DMA buffer descriptor queue full,DMA_ENGINE DMA buffer descriptor queue full,3
ERROR,CACHE_CTRL,"Cache data array bit flip detected, ECC error.","CACHE_CTRL Cache data array bit flip detected, ECC error.",1
WARNING,CLOCK_MANAGER,Clock domain crossing bridge experiencing excessive latency,CLOCK_MANAGER Clock domain crossing bridge experiencing excessive latency,0
CRITICAL,POWER_CTRL,System PMU unresponsive,POWER_CTRL System PMU unresponsive,4
ERROR,PCIE_CTRL,PCIe link state machine stuck in recovery,PCIE_CTRL PCIe link state machine stuck in recovery,6
ERROR,INTERRUPT_CTRL,Interrupt acknowledge signal held too long,INTERRUPT_CTRL Interrupt acknowledge signal held too long,1
INFO,FIFO_BUF,"FIFO flush successful, 0 entries remaining","FIFO_BUF FIFO flush successful, 0 entries remaining",5
INFO,MEM_CTRL,"Write buffer emptied, data flushed to memory","MEM_CTRL Write buffer emptied, data flushed to memory",1
CRITICAL,DMA_ENGINE,"DMA channel 12 descriptor fetch deadlock detected, channel stuck","DMA_ENGINE DMA channel 12 descriptor fetch deadlock detected, channel stuck",3
INFO,INTERRUPT_CTRL,Interrupt priority update successful,INTERRUPT_CTRL Interrupt priority update successful,1
WARNING,CACHE_CTRL,Cache way prediction miss rate increasing,CACHE_CTRL Cache way prediction miss rate increasing,1
ERROR,AXI_CTRL,"AXI read channel deadlock detected, AR/R channels stalled","AXI_CTRL AXI read channel deadlock detected, AR/R channels stalled",2
ERROR,FIFO_BUF,FIFO_BUF detected a severe buffer underflow: starvation detected. (FIFO 'FIFO_BUF' Depth: 140),FIFO_BUF FIFO_BUF detected a severe buffer underflow: starvation detected. (FIFO 'FIFO_BUF' Depth: 140),5
CRITICAL,CACHE_CTRL,Data cache flush operation failed to complete,CACHE_CTRL Data cache flush operation failed to complete,1
ERROR,PCIE_CTRL,Vendor-specific PCIe error detected,PCIE_CTRL Vendor-specific PCIe error detected,6
WARNING,CLOCK_MANAGER,Jitter on main system clock increasing,CLOCK_MANAGER Jitter on main system clock increasing,0
WARNING,PCIE_CTRL,PCIe transaction layer detected multiple retry events,PCIE_CTRL PCIe transaction layer detected multiple retry events,6
WARNING,CACHE_CTRL,Cache access latency showing variability,CACHE_CTRL Cache access latency showing variability,1
ERROR,POWER_CTRL,Power regulator output unstable,POWER_CTRL Power regulator output unstable,4
WARNING,INTERRUPT_CTRL,Interrupt controller software configuration mismatch with hardware mask Y.,INTERRUPT_CTRL Interrupt controller software configuration mismatch with hardware mask Y.,1
CRITICAL,CACHE_CTRL,Cache tag lookup returned invalid entry,CACHE_CTRL Cache tag lookup returned invalid entry,1
INFO,AXI_CTRL,AXI response received for previous transaction,AXI_CTRL AXI response received for previous transaction,2
INFO,PCIE_CTRL,PCIe device ID 0x1A2B enabled.,PCIE_CTRL PCIe device ID 0x1A2B enabled.,6
WARNING,CACHE_CTRL,Cache snoop filter miss rate high,CACHE_CTRL Cache snoop filter miss rate high,1
CRITICAL,CLOCK_MANAGER,System halt due to unrecoverable clock tree corruption,CLOCK_MANAGER System halt due to unrecoverable clock tree corruption,0
ERROR,DMA_ENGINE,DMA transfer aborted due to address protection violation,DMA_ENGINE DMA transfer aborted due to address protection violation,3
WARNING,DDR_CTRL,DDR command queue fullness reaching critical level,DDR_CTRL DDR command queue fullness reaching critical level,1
INFO,CACHE_CTRL,Cache invalidation broadcast initiated,CACHE_CTRL Cache invalidation broadcast initiated,1
WARNING,POWER_CTRL,Power consumption nearing limit,POWER_CTRL Power consumption nearing limit,4
INFO,CLOCK_MANAGER,Clock gate enabled for module.,CLOCK_MANAGER Clock gate enabled for module.,0
ERROR,PCIE_CTRL,PCIe link state machine entered illegal state,PCIE_CTRL PCIe link state machine entered illegal state,6
ERROR,MEM_CTRL,Memory ECC single bit error corrected but too frequent,MEM_CTRL Memory ECC single bit error corrected but too frequent,1
CRITICAL,PCIE_CTRL,PCIe configuration space permanently inaccessible,PCIE_CTRL PCIe configuration space permanently inaccessible,6
WARNING,DMA_ENGINE,DMA channel 1 burst size not optimized,DMA_ENGINE DMA channel 1 burst size not optimized,3
CRITICAL,DDR_CTRL,DDR memory module unrecoverable error,DDR_CTRL DDR memory module unrecoverable error,1
INFO,MEM_CTRL,Memory bank activation successful,MEM_CTRL Memory bank activation successful,1
ERROR,FIFO_BUF,FIFO synchronization error detected between domains,FIFO_BUF FIFO synchronization error detected between domains,5
CRITICAL,AXI_CTRL,AXI transaction timeout on critical boot ROM access,AXI_CTRL AXI transaction timeout on critical boot ROM access,2
CRITICAL,CLOCK_MANAGER,Global reset pulse width out of spec,CLOCK_MANAGER Global reset pulse width out of spec,-1
CRITICAL,MEM_CTRL,Uncorrectable ECC error detected on main memory,MEM_CTRL Uncorrectable ECC error detected on main memory,1
ERROR,AXI_CTRL,AXI read address channel ARID mismatch between master and slave,AXI_CTRL AXI read address channel ARID mismatch between master and slave,2
CRITICAL,INTERRUPT_CTRL,"Unmaskable interrupt storm detected, system halt imminent","INTERRUPT_CTRL Unmaskable interrupt storm detected, system halt imminent",1
ERROR,AXI_CTRL,AXI protocol violation: RLAST not asserted for last beat.,AXI_CTRL AXI protocol violation: RLAST not asserted for last beat.,-1
ERROR,POWER_CTRL,Overcurrent detected on power rail,POWER_CTRL Overcurrent detected on power rail,4
INFO,PCIE_CTRL,PCIe configuration read successful.,PCIE_CTRL PCIe configuration read successful.,6
INFO,DDR_CTRL,DDR memory initialized for 16-bit data width,DDR_CTRL DDR memory initialized for 16-bit data width,1
INFO,MEM_CTRL,"Memory block 0, region 1, initialized to zero","MEM_CTRL Memory block 0, region 1, initialized to zero",1
WARNING,DMA_ENGINE,DMA control register access timeout,DMA_ENGINE DMA control register access timeout,3
ERROR,CACHE_CTRL,Cache coherence protocol violation on specific line,CACHE_CTRL Cache coherence protocol violation on specific line,1
INFO,DMA_ENGINE,"DMA channel 0 transfer completed, 1024 bytes moved","DMA_ENGINE DMA channel 0 transfer completed, 1024 bytes moved",3
WARNING,CLOCK_MANAGER,Clock source switching in progress for critical clock,CLOCK_MANAGER Clock source switching in progress for critical clock,0
ERROR,CACHE_CTRL,Cache replacement policy logic error detected,CACHE_CTRL Cache replacement policy logic error detected,1
CRITICAL,DMA_ENGINE,DMA channel 3 descriptor chain invalid state.,DMA_ENGINE DMA channel 3 descriptor chain invalid state.,3
ERROR,POWER_CTRL,Voltage regulator response timeout detected on 1.4V rail.,POWER_CTRL Voltage regulator response timeout detected on 1.4V rail.,4
ERROR,DDR_CTRL,DDR burst access to unaligned address boundary detected.,DDR_CTRL DDR burst access to unaligned address boundary detected.,1
ERROR,CACHE_CTRL,Cache invalidation broadcast failed to reach all coherence agents.,CACHE_CTRL Cache invalidation broadcast failed to reach all coherence agents.,1
CRITICAL,POWER_CTRL,"Power rail instability detected, fatal power supply issue.","POWER_CTRL Power rail instability detected, fatal power supply issue.",4
ERROR,FIFO_BUF,FIFO read of empty buffer attempted,FIFO_BUF FIFO read of empty buffer attempted,5
INFO,FIFO_BUF,FIFO_BUF resource allocation successful.,FIFO_BUF FIFO_BUF resource allocation successful.,5
WARNING,DDR_CTRL,DDR power-down entry delayed,DDR_CTRL DDR power-down entry delayed,1
ERROR,AXI_CTRL,AXI read data issued without prior read address,AXI_CTRL AXI read data issued without prior read address,2
INFO,AXI_CTRL,AXI transaction ID allocation successful,AXI_CTRL AXI transaction ID allocation successful,2
CRITICAL,DDR_CTRL,DDR memory chip selection failure,DDR_CTRL DDR memory chip selection failure,1
ERROR,MEM_CTRL,Memory address decoding fault,MEM_CTRL Memory address decoding fault,1
WARNING,PCIE_CTRL,PCIe receiver equalization warning,PCIE_CTRL PCIe receiver equalization warning,6
INFO,DMA_ENGINE,DMA channel 21 transfer completed with errors,DMA_ENGINE DMA channel 21 transfer completed with errors,3
WARNING,FIFO_BUF,FIFO occupancy exceeding warning threshold,FIFO_BUF FIFO occupancy exceeding warning threshold,5
WARNING,DDR_CTRL,DDR command queue depth frequently at maximum,DDR_CTRL DDR command queue depth frequently at maximum,1
CRITICAL,CLOCK_MANAGER,Clock generation PLL lock lost,CLOCK_MANAGER Clock generation PLL lock lost,0
ERROR,DDR_CTRL,DDR training sequence failure for rank 0,DDR_CTRL DDR training sequence failure for rank 0,1
WARNING,AXI_CTRL,AXI write data channel backpressure observed,AXI_CTRL AXI write data channel backpressure observed,2
CRITICAL,POWER_CTRL,System power rail collapse detected,POWER_CTRL System power rail collapse detected,4
INFO,AXI_CTRL,Outstanding transactions cleared,AXI_CTRL Outstanding transactions cleared,2
ERROR,PCIE_CTRL,PCIe Hot-Plug event not handled,PCIE_CTRL PCIe Hot-Plug event not handled,6
WARNING,MEM_CTRL,Soft ECC error detected (single bit flip) at 0x4f15d7f7.,MEM_CTRL Soft ECC error detected (single bit flip) at 0x4f15d7f7.,1
WARNING,DMA_ENGINE,DMA transfer completion signal delayed,DMA_ENGINE DMA transfer completion signal delayed,3
INFO,CACHE_CTRL,Cache writeback completed for address 0x6789,CACHE_CTRL Cache writeback completed for address 0x6789,1
INFO,PCIE_CTRL,PCIe link established successfully at Gen2 speed,PCIE_CTRL PCIe link established successfully at Gen2 speed,6
WARNING,INTERRUPT_CTRL,Interrupt handler latency exceeding acceptable bounds,INTERRUPT_CTRL Interrupt handler latency exceeding acceptable bounds,1
INFO,CACHE_CTRL,Cache line eviction count increased,CACHE_CTRL Cache line eviction count increased,1
CRITICAL,CLOCK_MANAGER,Main oscillator output unstable,CLOCK_MANAGER Main oscillator output unstable,0
INFO,CACHE_CTRL,Firmware successfully loaded into CACHE_CTRL control registers.,CACHE_CTRL Firmware successfully loaded into CACHE_CTRL control registers.,-1
INFO,FIFO_BUF,FIFO occupancy 10%,FIFO_BUF FIFO occupancy 10%,5
ERROR,POWER_CTRL,Voltage regulator output ripple exceeding specification,POWER_CTRL Voltage regulator output ripple exceeding specification,4
ERROR,CLOCK_MANAGER,Global clock enable signal stuck high,CLOCK_MANAGER Global clock enable signal stuck high,0
INFO,DMA_ENGINE,DMA channel 2 transfer completed successfully,DMA_ENGINE DMA channel 2 transfer completed successfully,3
ERROR,POWER_CTRL,Power state transition to ACTIVE failed,POWER_CTRL Power state transition to ACTIVE failed,4
ERROR,CLOCK_MANAGER,Clock gating logic for module X stuck open,CLOCK_MANAGER Clock gating logic for module X stuck open,0
ERROR,FIFO_BUF,FIFO write pointer overran the buffer boundary,FIFO_BUF FIFO write pointer overran the buffer boundary,5
ERROR,CLOCK_MANAGER,Clock frequency change request denied by FSM,CLOCK_MANAGER Clock frequency change request denied by FSM,-1
WARNING,AXI_CTRL,AXI handshake delay approaching threshold,AXI_CTRL AXI handshake delay approaching threshold,2
INFO,CACHE_CTRL,Cache directory updated,CACHE_CTRL Cache directory updated,1
CRITICAL,PCIE_CTRL,PCIe link re-negotiation failure,PCIE_CTRL PCIe link re-negotiation failure,6
ERROR,FIFO_BUF,FIFO 'data_out_buffer' experienced an underflow condition,FIFO_BUF FIFO 'data_out_buffer' experienced an underflow condition,5
ERROR,CLOCK_MANAGER,Clock source jitter spike detected,CLOCK_MANAGER Clock source jitter spike detected,0
INFO,PCIE_CTRL,PCIe device 0x6D power management state changed.,PCIE_CTRL PCIe device 0x6D power management state changed.,6
ERROR,DDR_CTRL,DDR rank disable detected,DDR_CTRL DDR rank disable detected,1
WARNING,DMA_ENGINE,DMA channel 0 paused due to external flow control,DMA_ENGINE DMA channel 0 paused due to external flow control,3
CRITICAL,FIFO_BUF,FIFO head/tail pointer deadlock detected,FIFO_BUF FIFO head/tail pointer deadlock detected,5
INFO,DMA_ENGINE,DMA completion interrupt generated,DMA_ENGINE DMA completion interrupt generated,3
WARNING,CACHE_CTRL,MSHR entries nearing capacity,CACHE_CTRL MSHR entries nearing capacity,-1
CRITICAL,INTERRUPT_CTRL,"Interrupt controller FSM entered unexpected state, system unrecoverable","INTERRUPT_CTRL Interrupt controller FSM entered unexpected state, system unrecoverable",1
ERROR,CACHE_CTRL,Cache instruction fetch miss rate exceeding threshold,CACHE_CTRL Cache instruction fetch miss rate exceeding threshold,1
CRITICAL,POWER_CTRL,"System PMIC reported critical over-current event, initiated shutdown","POWER_CTRL System PMIC reported critical over-current event, initiated shutdown",4
INFO,AXI_CTRL,AXI interconnect configuration validated,AXI_CTRL AXI interconnect configuration validated,2
INFO,DMA_ENGINE,DMA descriptor prefetch enabled,DMA_ENGINE DMA descriptor prefetch enabled,3
WARNING,FIFO_BUF,Almost full threshold reached,FIFO_BUF Almost full threshold reached,5
INFO,DDR_CTRL,DDR controller operating in low power mode,DDR_CTRL DDR controller operating in low power mode,1
CRITICAL,FIFO_BUF,FIFO state machine entered an unrecoverable invalid state.,FIFO_BUF FIFO state machine entered an unrecoverable invalid state.,5
CRITICAL,CACHE_CTRL,"Cache integrity check failed across multiple blocks, data corruption.","CACHE_CTRL Cache integrity check failed across multiple blocks, data corruption.",1
WARNING,CACHE_CTRL,Cache line invalidation pending for multiple cores,CACHE_CTRL Cache line invalidation pending for multiple cores,1
ERROR,POWER_CTRL,Power monitor reporting excessive ripple,POWER_CTRL Power monitor reporting excessive ripple,4
WARNING,DDR_CTRL,DDR controller write data FIFO backpressure,DDR_CTRL DDR controller write data FIFO backpressure,-1
CRITICAL,FIFO_BUF,FIFO controller in unrecoverable state.,FIFO_BUF FIFO controller in unrecoverable state.,5
ERROR,FIFO_BUF,FIFO synchronization error detected on asynchronous FIFO boundary,FIFO_BUF FIFO synchronization error detected on asynchronous FIFO boundary,5
INFO,DDR_CTRL,DDR memory mode register configured,DDR_CTRL DDR memory mode register configured,1
INFO,AXI_CTRL,AXI write transaction completed successfully with SLVERR response,AXI_CTRL AXI write transaction completed successfully with SLVERR response,2
INFO,DMA_ENGINE,DMA channel configured.,DMA_ENGINE DMA channel configured.,3
INFO,INTERRUPT_CTRL,Interrupt routing table updated,INTERRUPT_CTRL Interrupt routing table updated,1
INFO,DMA_ENGINE,DMA channel 6 transfer request acknowledged,DMA_ENGINE DMA channel 6 transfer request acknowledged,3
WARNING,PCIE_CTRL,PCIe link speed degradation detected,PCIE_CTRL PCIe link speed degradation detected,6
CRITICAL,DDR_CTRL,DRAM device unrecoverable error,DDR_CTRL DRAM device unrecoverable error,1
WARNING,FIFO_BUF,FIFO high watermark threshold reached.,FIFO_BUF FIFO high watermark threshold reached.,5
INFO,CLOCK_MANAGER,PLL bandwidth configured for optimal performance,CLOCK_MANAGER PLL bandwidth configured for optimal performance,0
WARNING,DMA_ENGINE,DMA queue nearing saturation on channel 1,DMA_ENGINE DMA queue nearing saturation on channel 1,3
WARNING,CACHE_CTRL,Cache directory lookup timeout,CACHE_CTRL Cache directory lookup timeout,1
INFO,AXI_CTRL,AXI interconnect reset sequence completed,AXI_CTRL AXI interconnect reset sequence completed,2
INFO,MEM_CTRL,Memory page opened for access.,MEM_CTRL Memory page opened for access.,1
INFO,DMA_ENGINE,DMA transfer aborted by software request,DMA_ENGINE DMA transfer aborted by software request,3
ERROR,MEM_CTRL,Memory controller received a write request to a read-only region,MEM_CTRL Memory controller received a write request to a read-only region,1
WARNING,AXI_CTRL,AXI slave S1 returned unexpected AXI_RRESP,AXI_CTRL AXI slave S1 returned unexpected AXI_RRESP,2
CRITICAL,AXI_CTRL,AXI_CTRL: System-level deadlock detected. Unrecoverable hardware state. (inter-module deadlock),AXI_CTRL AXI_CTRL: System-level deadlock detected. Unrecoverable hardware state. (inter-module deadlock),2
WARNING,DDR_CTRL,DDR ZQ calibration period approaching,DDR_CTRL DDR ZQ calibration period approaching,1
WARNING,AXI_CTRL,AXI slave response delay exceeding expected threshold.,AXI_CTRL AXI slave response delay exceeding expected threshold.,2
ERROR,CACHE_CTRL,L1 cache entry invalidation command timed out,CACHE_CTRL L1 cache entry invalidation command timed out,1
INFO,INTERRUPT_CTRL,Interrupt dispatch completed for IRQ 1,INTERRUPT_CTRL Interrupt dispatch completed for IRQ 1,1
WARNING,AXI_CTRL,AXI slave response delay observed,AXI_CTRL AXI slave response delay observed,2
WARNING,CLOCK_MANAGER,CLOCK_MANAGER logic showing high activity leading to potential thermal increase.,CLOCK_MANAGER CLOCK_MANAGER logic showing high activity leading to potential thermal increase.,-1
ERROR,FIFO_BUF,FIFO synchronization error on write operation,FIFO_BUF FIFO synchronization error on write operation,5
ERROR,CLOCK_MANAGER,Reset de-assertion skew across clock domains,CLOCK_MANAGER Reset de-assertion skew across clock domains,0
ERROR,INTERRUPT_CTRL,Interrupt routing table entry corrupted,INTERRUPT_CTRL Interrupt routing table entry corrupted,1
WARNING,DDR_CTRL,DDR temperature approaching max junction temperature,DDR_CTRL DDR temperature approaching max junction temperature,1
WARNING,INTERRUPT_CTRL,Interrupt enable register read as unexpected value for IRQ 0x6,INTERRUPT_CTRL Interrupt enable register read as unexpected value for IRQ 0x6,1
WARNING,PCIE_CTRL,PCIe upstream write posted buffer utilization high,PCIE_CTRL PCIe upstream write posted buffer utilization high,6
CRITICAL,POWER_CTRL,Power brownout leading to unrecoverable system state,POWER_CTRL Power brownout leading to unrecoverable system state,4
CRITICAL,PCIE_CTRL,PCIe electrical layer integrity compromised,PCIE_CTRL PCIe electrical layer integrity compromised,6
WARNING,DMA_ENGINE,DMA channel 0 descriptor queue nearly empty,DMA_ENGINE DMA channel 0 descriptor queue nearly empty,3
WARNING,DMA_ENGINE,Buffer chain nearly exhausted,DMA_ENGINE Buffer chain nearly exhausted,3
INFO,MEM_CTRL,Data written to memory successfully at address 0x1000,MEM_CTRL Data written to memory successfully at address 0x1000,1
ERROR,PCIE_CTRL,PCIe link re-training initiated due to errors,PCIE_CTRL PCIe link re-training initiated due to errors,6
CRITICAL,AXI_CTRL,AXI transaction ID collision with active transactions,AXI_CTRL AXI transaction ID collision with active transactions,2
INFO,PCIE_CTRL,PCIe configuration read access to Vendor ID,PCIE_CTRL PCIe configuration read access to Vendor ID,6
INFO,INTERRUPT_CTRL,Interrupt vector 0x1A dispatched to handler,INTERRUPT_CTRL Interrupt vector 0x1A dispatched to handler,1
WARNING,AXI_CTRL,AXI outstanding transactions (15) exceeding soft threshold (10),AXI_CTRL AXI outstanding transactions (15) exceeding soft threshold (10),2
ERROR,CLOCK_MANAGER,Clock frequency instability detected,CLOCK_MANAGER Clock frequency instability detected,0
WARNING,DDR_CTRL,DDR memory controller reports performance degradation,DDR_CTRL DDR memory controller reports performance degradation,1
INFO,CLOCK_MANAGER,Clock domain crossing bridge enabled,CLOCK_MANAGER Clock domain crossing bridge enabled,0
CRITICAL,DDR_CTRL,DDR self-refresh entry failed,DDR_CTRL DDR self-refresh entry failed,1
ERROR,PCIE_CTRL,PCIe transaction layer packet malformed,PCIE_CTRL PCIe transaction layer packet malformed,6
CRITICAL,DMA_ENGINE,DMA engine unable to service critical request,DMA_ENGINE DMA engine unable to service critical request,3
INFO,INTERRUPT_CTRL,Interrupt vector 0x0C serviced,INTERRUPT_CTRL Interrupt vector 0x0C serviced,1
INFO,DMA_ENGINE,DMA descriptor processed successfully.,DMA_ENGINE DMA descriptor processed successfully.,3
CRITICAL,CLOCK_MANAGER,Clock source failure impacting CLOCK_MANAGER. All time-sensitive operations stopped.,CLOCK_MANAGER Clock source failure impacting CLOCK_MANAGER. All time-sensitive operations stopped.,0
WARNING,POWER_CTRL,Power domain isolation logic taking longer to settle,POWER_CTRL Power domain isolation logic taking longer to settle,4
INFO,CLOCK_MANAGER,PLL locked successfully (4814MHz).,CLOCK_MANAGER PLL locked successfully (4814MHz).,0
WARNING,PCIE_CTRL,PCIe completion timeout counter incremented,PCIE_CTRL PCIe completion timeout counter incremented,6
INFO,CACHE_CTRL,Cache line successfully snooped,CACHE_CTRL Cache line successfully snooped,1
ERROR,AXI_CTRL,AXI security violation detected,AXI_CTRL AXI security violation detected,2
WARNING,AXI_CTRL,AXI master arbitration conflict detected,AXI_CTRL AXI master arbitration conflict detected,2
INFO,MEM_CTRL,Cache flush operation initiated for entire memory region,MEM_CTRL Cache flush operation initiated for entire memory region,1
CRITICAL,POWER_CTRL,Core voltage rail experienced momentary collapse,POWER_CTRL Core voltage rail experienced momentary collapse,4
INFO,CLOCK_MANAGER,Clock frequency configuration applied (1560MHz).,CLOCK_MANAGER Clock frequency configuration applied (1560MHz).,0
WARNING,FIFO_BUF,"FIFO depth nearing 95%, potential overflow imminent","FIFO_BUF FIFO depth nearing 95%, potential overflow imminent",5
WARNING,DDR_CTRL,DDR memory channel B experiencing increased latency,DDR_CTRL DDR memory channel B experiencing increased latency,1
CRITICAL,CLOCK_MANAGER,Clock domain crossing failure leading to metastability.,CLOCK_MANAGER Clock domain crossing failure leading to metastability.,0
ERROR,CLOCK_MANAGER,Clock enable signal stuck active/inactive,CLOCK_MANAGER Clock enable signal stuck active/inactive,0
CRITICAL,POWER_CTRL,Core voltage rail VDD_CORE below minimum operating threshold,POWER_CTRL Core voltage rail VDD_CORE below minimum operating threshold,4
WARNING,PCIE_CTRL,PCIe link speed negotiation took multiple attempts,PCIE_CTRL PCIe link speed negotiation took multiple attempts,6
ERROR,AXI_CTRL,AXI burst read terminated prematurely by slave,AXI_CTRL AXI burst read terminated prematurely by slave,2
INFO,CLOCK_MANAGER,System clock frequency successfully reconfigured to 500MHz,CLOCK_MANAGER System clock frequency successfully reconfigured to 500MHz,0
WARNING,DMA_ENGINE,DMA channel priority inversion observed,DMA_ENGINE DMA channel priority inversion observed,3
WARNING,CACHE_CTRL,CACHE_CTRL performance counter indicating suboptimal behavior.,CACHE_CTRL CACHE_CTRL performance counter indicating suboptimal behavior.,-1
WARNING,FIFO_BUF,FIFO 'data_in_queue' approaching 90% capacity,FIFO_BUF FIFO 'data_in_queue' approaching 90% capacity,5
WARNING,POWER_CTRL,Power consumption exceeding estimated budget by 60%.,POWER_CTRL Power consumption exceeding estimated budget by 60%.,4
ERROR,INTERRUPT_CTRL,Interrupt request input stuck high,INTERRUPT_CTRL Interrupt request input stuck high,1
CRITICAL,DDR_CTRL,Uncorrectable ECC error detected during DDR initialization,DDR_CTRL Uncorrectable ECC error detected during DDR initialization,1
INFO,PCIE_CTRL,PCIe link error detection enabled,PCIE_CTRL PCIe link error detection enabled,6
WARNING,PCIE_CTRL,PCIe upstream link bandwidth nearing capacity,PCIE_CTRL PCIe upstream link bandwidth nearing capacity,6
INFO,CACHE_CTRL,Cache enabled,CACHE_CTRL Cache enabled,1
WARNING,PCIE_CTRL,PCIe link re-negotiation due to CRC errors,PCIE_CTRL PCIe link re-negotiation due to CRC errors,6
CRITICAL,DDR_CTRL,DDR memory access stall due to controller deadlock,DDR_CTRL DDR memory access stall due to controller deadlock,1
ERROR,AXI_CTRL,AXI protocol mismatch on write channel,AXI_CTRL AXI protocol mismatch on write channel,2
WARNING,DMA_ENGINE,DMA channel 2 read transaction issued to unmapped address,DMA_ENGINE DMA channel 2 read transaction issued to unmapped address,3
ERROR,AXI_CTRL,AXI transaction '0xABCDEF' response mismatch between expected and actual,AXI_CTRL AXI transaction '0xABCDEF' response mismatch between expected and actual,2
CRITICAL,CLOCK_MANAGER,Primary clock source failed to oscillate,CLOCK_MANAGER Primary clock source failed to oscillate,0
ERROR,POWER_CTRL,Power management unit state corruption,POWER_CTRL Power management unit state corruption,4
INFO,INTERRUPT_CTRL,Interrupt controller enabled all sources,INTERRUPT_CTRL Interrupt controller enabled all sources,1
WARNING,AXI_CTRL,AXI handshake delay approaching threshold for master CPU.,AXI_CTRL AXI handshake delay approaching threshold for master CPU.,2
WARNING,DDR_CTRL,DDR command queue stall detected,DDR_CTRL DDR command queue stall detected,1
WARNING,POWER_CTRL,Power good signal unstable,POWER_CTRL Power good signal unstable,4
ERROR,FIFO_BUF,FIFO clear operation failed to reset pointers correctly,FIFO_BUF FIFO clear operation failed to reset pointers correctly,5
INFO,CACHE_CTRL,Cache hit on instruction fetch.,CACHE_CTRL Cache hit on instruction fetch.,1
ERROR,POWER_CTRL,Voltage drop detected on core rail,POWER_CTRL Voltage drop detected on core rail,4
CRITICAL,CACHE_CTRL,Cache directory coherence failure,CACHE_CTRL Cache directory coherence failure,1
INFO,FIFO_BUF,FIFO data available for read,FIFO_BUF FIFO data available for read,5
ERROR,DDR_CTRL,DDR MR register access error (reg=23).,DDR_CTRL DDR MR register access error (reg=23).,1
ERROR,DMA_ENGINE,DMA address translation fault,DMA_ENGINE DMA address translation fault,3
INFO,DDR_CTRL,DDR training eye diagram analysis initiated,DDR_CTRL DDR training eye diagram analysis initiated,-1
WARNING,CLOCK_MANAGER,Clock domain X frequency deviation,CLOCK_MANAGER Clock domain X frequency deviation,0
CRITICAL,FIFO_BUF,Multi-clock FIFO data corruption observed due to clock domain crossing failure.,FIFO_BUF Multi-clock FIFO data corruption observed due to clock domain crossing failure.,5
WARNING,AXI_CTRL,AXI master asserting read address without corresponding write address,AXI_CTRL AXI master asserting read address without corresponding write address,2
INFO,INTERRUPT_CTRL,Interrupt mask updated for CPU core 0,INTERRUPT_CTRL Interrupt mask updated for CPU core 0,1
WARNING,FIFO_BUF,"FIFO almost empty, low watermark reached","FIFO_BUF FIFO almost empty, low watermark reached",5
CRITICAL,CLOCK_MANAGER,"Clock generation PLL lock lost, system clock source unstable and out of spec.","CLOCK_MANAGER Clock generation PLL lock lost, system clock source unstable and out of spec.",0
WARNING,DMA_ENGINE,DMA channel X transfer rate below target,DMA_ENGINE DMA channel X transfer rate below target,3
CRITICAL,DMA_ENGINE,"DMA descriptor queue exhausted, no more transfers possible.","DMA_ENGINE DMA descriptor queue exhausted, no more transfers possible.",3
INFO,DMA_ENGINE,DMA channel 0 paused by software,DMA_ENGINE DMA channel 0 paused by software,3
ERROR,CACHE_CTRL,Cache line not found in directory for dirty writeback.,CACHE_CTRL Cache line not found in directory for dirty writeback.,1
INFO,CACHE_CTRL,Cache prefetch depth configured,CACHE_CTRL Cache prefetch depth configured,1
INFO,DDR_CTRL,Refresh rate configured,DDR_CTRL Refresh rate configured,1
INFO,CLOCK_MANAGER,Clock monitor self-test passed.,CLOCK_MANAGER Clock monitor self-test passed.,-1
ERROR,FIFO_BUF,FIFO almost-full flag stuck active,FIFO_BUF FIFO almost-full flag stuck active,5
INFO,CACHE_CTRL,Cache 'L2' hit rate 92%,CACHE_CTRL Cache 'L2' hit rate 92%,1
WARNING,PCIE_CTRL,TLP processing backlog,PCIE_CTRL TLP processing backlog,6
ERROR,AXI_CTRL,AXI response channel detected unexpected value for BVALID.,AXI_CTRL AXI response channel detected unexpected value for BVALID.,2
INFO,INTERRUPT_CTRL,Interrupt controller internal counters reset,INTERRUPT_CTRL Interrupt controller internal counters reset,1
CRITICAL,MEM_CTRL,Memory mapping unit configuration invalid,MEM_CTRL Memory mapping unit configuration invalid,1
INFO,DDR_CTRL,DDR4 calibration passed successfully,DDR_CTRL DDR4 calibration passed successfully,1
ERROR,INTERRUPT_CTRL,Invalid interrupt vector received: 0xFF,INTERRUPT_CTRL Invalid interrupt vector received: 0xFF,1
WARNING,CACHE_CTRL,Cache line dirty bit unexpectedly set,CACHE_CTRL Cache line dirty bit unexpectedly set,1
INFO,DMA_ENGINE,DMA transfer resume command issued,DMA_ENGINE DMA transfer resume command issued,3
CRITICAL,MEM_CTRL,Data bus stuck-at-fault detected on memory interface,MEM_CTRL Data bus stuck-at-fault detected on memory interface,1
WARNING,CLOCK_MANAGER,Clock output frequency deviation,CLOCK_MANAGER Clock output frequency deviation,0
INFO,INTERRUPT_CTRL,Interrupt priority level 3 serviced,INTERRUPT_CTRL Interrupt priority level 3 serviced,1
INFO,DDR_CTRL,DDR MRS commands issued successfully,DDR_CTRL DDR MRS commands issued successfully,1
WARNING,CLOCK_MANAGER,Clock gating logic detected potential race condition,CLOCK_MANAGER Clock gating logic detected potential race condition,0
WARNING,DMA_ENGINE,DMA queue for channel 2 nearing saturation,DMA_ENGINE DMA queue for channel 2 nearing saturation,3
INFO,AXI_CTRL,AXI write request successfully queued,AXI_CTRL AXI write request successfully queued,2
WARNING,CACHE_CTRL,Cache line writeback stalled due to bus congestion,CACHE_CTRL Cache line writeback stalled due to bus congestion,1
WARNING,CLOCK_MANAGER,Clock tree synthesis report indicates high fanout path,CLOCK_MANAGER Clock tree synthesis report indicates high fanout path,0
ERROR,INTERRUPT_CTRL,Interrupt handler address fetch failed,INTERRUPT_CTRL Interrupt handler address fetch failed,1
INFO,POWER_CTRL,Debug registers read for POWER_CTRL.,POWER_CTRL Debug registers read for POWER_CTRL.,-1
ERROR,POWER_CTRL,Voltage regulator for VDD_PERIPH entered a fault state.,POWER_CTRL Voltage regulator for VDD_PERIPH entered a fault state.,-1
CRITICAL,CACHE_CTRL,"Fatal cache coherence violation, system requires reset.","CACHE_CTRL Fatal cache coherence violation, system requires reset.",1
ERROR,CACHE_CTRL,Cache tag update operation failed due to hardware error.,CACHE_CTRL Cache tag update operation failed due to hardware error.,1
ERROR,DDR_CTRL,DDR write latency violation detected,DDR_CTRL DDR write latency violation detected,1
ERROR,MEM_CTRL,Memory controller address bus tristate control error,MEM_CTRL Memory controller address bus tristate control error,1
ERROR,AXI_CTRL,AXI master issued illegal address.,AXI_CTRL AXI master issued illegal address.,2
INFO,AXI_CTRL,AXI slave 0x5 configured for non-cached access,AXI_CTRL AXI slave 0x5 configured for non-cached access,2
WARNING,MEM_CTRL,Memory write access latency increased,MEM_CTRL Memory write access latency increased,1
WARNING,DDR_CTRL,DDR bank access patterns show high contention,DDR_CTRL DDR bank access patterns show high contention,1
WARNING,INTERRUPT_CTRL,Interrupt source 0xAA unacknowledged for too long.,INTERRUPT_CTRL Interrupt source 0xAA unacknowledged for too long.,1
CRITICAL,CACHE_CTRL,Unrecoverable cache memory error: parity check failed on multiple lines,CACHE_CTRL Unrecoverable cache memory error: parity check failed on multiple lines,1
INFO,MEM_CTRL,Memory initialization sequence completed.,MEM_CTRL Memory initialization sequence completed.,1
INFO,DDR_CTRL,DDR mode registers updated successfully,DDR_CTRL DDR mode registers updated successfully,1
ERROR,CACHE_CTRL,Cache line replacement policy fault,CACHE_CTRL Cache line replacement policy fault,1
WARNING,PCIE_CTRL,PCIe receiver FIFO approaching full,PCIE_CTRL PCIe receiver FIFO approaching full,6
WARNING,PCIE_CTRL,PCIe TLP latency exceeding threshold for endpoint,PCIE_CTRL PCIe TLP latency exceeding threshold for endpoint,6
WARNING,INTERRUPT_CTRL,Interrupt queue not draining fast enough,INTERRUPT_CTRL Interrupt queue not draining fast enough,1
CRITICAL,PCIE_CTRL,PCIe fundamental reset (FLR) failed to assert,PCIE_CTRL PCIe fundamental reset (FLR) failed to assert,6
WARNING,AXI_CTRL,AXI bus utilization exceeding 90%.,AXI_CTRL AXI bus utilization exceeding 90%.,2
ERROR,CACHE_CTRL,Cache coherency protocol deadlock detected between two cores,CACHE_CTRL Cache coherency protocol deadlock detected between two cores,1
ERROR,AXI_CTRL,AXI write response (BVALID) asserted without BREADY for too long,AXI_CTRL AXI write response (BVALID) asserted without BREADY for too long,2
WARNING,CACHE_CTRL,Cache line eviction rate unusually high,CACHE_CTRL Cache line eviction rate unusually high,1
WARNING,CACHE_CTRL,Cache miss rate exceeding expected threshold of 60%,CACHE_CTRL Cache miss rate exceeding expected threshold of 60%,1
INFO,DMA_ENGINE,DMA transfer channel enabled,DMA_ENGINE DMA transfer channel enabled,3
INFO,DDR_CTRL,DDR memory operating in burst mode.,DDR_CTRL DDR memory operating in burst mode.,1
WARNING,FIFO_BUF,FIFO almost full condition for extended duration,FIFO_BUF FIFO almost full condition for extended duration,5
WARNING,AXI_CTRL,AXI outstanding transaction limit nearing capacity (13 of 31).,AXI_CTRL AXI outstanding transaction limit nearing capacity (13 of 31).,2
WARNING,CLOCK_MANAGER,Clock domain crossing synchronizer path Y showing high latency.,CLOCK_MANAGER Clock domain crossing synchronizer path Y showing high latency.,0
ERROR,CLOCK_MANAGER,Primary PLL lost lock frequency,CLOCK_MANAGER Primary PLL lost lock frequency,0
INFO,AXI_CTRL,AXI slave B responded to write request.,AXI_CTRL AXI slave B responded to write request.,2
CRITICAL,DMA_ENGINE,DMA controller issued command to an illegal memory region,DMA_ENGINE DMA controller issued command to an illegal memory region,3
CRITICAL,POWER_CTRL,Voltage monitoring unit detected critical power rail shutdown,POWER_CTRL Voltage monitoring unit detected critical power rail shutdown,4
WARNING,AXI_CTRL,AXI read address channel receiving excessive retries,AXI_CTRL AXI read address channel receiving excessive retries,2
ERROR,DDR_CTRL,Memory controller unable to complete calibration due to unstable clock.,DDR_CTRL Memory controller unable to complete calibration due to unstable clock.,1
ERROR,CACHE_CTRL,Cache data corruption detected on read,CACHE_CTRL Cache data corruption detected on read,1
ERROR,MEM_CTRL,Memory command decode unit detected invalid opcode,MEM_CTRL Memory command decode unit detected invalid opcode,1
WARNING,CLOCK_MANAGER,Clock buffer drive strength marginal,CLOCK_MANAGER Clock buffer drive strength marginal,0
CRITICAL,MEM_CTRL,Read modify write operation stalled indefinitely,MEM_CTRL Read modify write operation stalled indefinitely,1
WARNING,INTERRUPT_CTRL,Interrupt latency exceeding threshold (865 cycles).,INTERRUPT_CTRL Interrupt latency exceeding threshold (865 cycles).,1
ERROR,MEM_CTRL,Memory controller command queue deadlock detected,MEM_CTRL Memory controller command queue deadlock detected,1
ERROR,PCIE_CTRL,PCIe Data Link Layer protocol violation,PCIE_CTRL PCIe Data Link Layer protocol violation,6
ERROR,PCIE_CTRL,PCIe TLP header parity error detected,PCIE_CTRL PCIe TLP header parity error detected,6
WARNING,FIFO_BUF,"FIFO read pointer approaching write pointer, potential for underflow.","FIFO_BUF FIFO read pointer approaching write pointer, potential for underflow.",5
WARNING,DDR_CTRL,DDR write recovery time parameter violation,DDR_CTRL DDR write recovery time parameter violation,1
INFO,AXI_CTRL,AXI read burst length set to 4,AXI_CTRL AXI read burst length set to 4,2
INFO,DMA_ENGINE,DMA transfer pre-fetch enabled,DMA_ENGINE DMA transfer pre-fetch enabled,3
ERROR,PCIE_CTRL,PCIe Completion Timeout (CTO) received for outstanding request,PCIE_CTRL PCIe Completion Timeout (CTO) received for outstanding request,6
ERROR,MEM_CTRL,Memory controller state machine entered an unrecoverable state,MEM_CTRL Memory controller state machine entered an unrecoverable state,1
ERROR,AXI_CTRL,AXI write data (WDATA) parity error detected,AXI_CTRL AXI write data (WDATA) parity error detected,2
CRITICAL,POWER_CTRL,System power rail experienced a hard fault,POWER_CTRL System power rail experienced a hard fault,4
INFO,PCIE_CTRL,PCIe endpoint device reset complete,PCIE_CTRL PCIe endpoint device reset complete,6
WARNING,PCIE_CTRL,Retransmission rate increasing,PCIE_CTRL Retransmission rate increasing,6
INFO,DMA_ENGINE,DMA channel 1 transfer resumed,DMA_ENGINE DMA channel 1 transfer resumed,3
INFO,INTERRUPT_CTRL,Software interrupt trigger acknowledged,INTERRUPT_CTRL Software interrupt trigger acknowledged,1
ERROR,CLOCK_MANAGER,Clock output buffer degradation detected,CLOCK_MANAGER Clock output buffer degradation detected,0
CRITICAL,CLOCK_MANAGER,Global clock network skew exceeding design limits,CLOCK_MANAGER Global clock network skew exceeding design limits,-1
INFO,FIFO_BUF,FIFO bypass path activated,FIFO_BUF FIFO bypass path activated,5
INFO,PCIE_CTRL,PCIe endpoint device detected,PCIE_CTRL PCIe endpoint device detected,6
INFO,DDR_CTRL,DDR memory controller in IDLE state,DDR_CTRL DDR memory controller in IDLE state,1
INFO,INTERRUPT_CTRL,Interrupt vector 5 successfully registered,INTERRUPT_CTRL Interrupt vector 5 successfully registered,1
WARNING,INTERRUPT_CTRL,Interrupt controller processing backlog increasing.,INTERRUPT_CTRL Interrupt controller processing backlog increasing.,1
CRITICAL,POWER_CTRL,Critical voltage regulator failure,POWER_CTRL Critical voltage regulator failure,4
INFO,MEM_CTRL,Memory controller is in idle state,MEM_CTRL Memory controller is in idle state,1
INFO,DMA_ENGINE,DMA engine reset completed,DMA_ENGINE DMA engine reset completed,3
ERROR,CLOCK_MANAGER,External clock input signal vanished,CLOCK_MANAGER External clock input signal vanished,0
ERROR,INTERRUPT_CTRL,Interrupt dispatch logic failure,INTERRUPT_CTRL Interrupt dispatch logic failure,1
INFO,FIFO_BUF,FIFO synchronization error resolved,FIFO_BUF FIFO synchronization error resolved,5
CRITICAL,POWER_CTRL,Critical voltage rail shut down unexpectedly,POWER_CTRL Critical voltage rail shut down unexpectedly,4
INFO,CLOCK_MANAGER,Clock source switched from external to internal PLL,CLOCK_MANAGER Clock source switched from external to internal PLL,0
INFO,AXI_CTRL,AXI low-power state entered,AXI_CTRL AXI low-power state entered,-1
WARNING,INTERRUPT_CTRL,Interrupt masking applied asynchronously,INTERRUPT_CTRL Interrupt masking applied asynchronously,1
ERROR,INTERRUPT_CTRL,Interrupt source masked erroneously,INTERRUPT_CTRL Interrupt source masked erroneously,1
INFO,CLOCK_MANAGER,All clocks re-synchronized after reset,CLOCK_MANAGER All clocks re-synchronized after reset,0
INFO,AXI_CTRL,AXI write request issued with ID 0x07.,AXI_CTRL AXI write request issued with ID 0x07.,2
WARNING,POWER_CTRL,Power domain transition delay detected for VDDPST,POWER_CTRL Power domain transition delay detected for VDDPST,4