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- <!doctype html>
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- <html>
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- <head>
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- <meta charset="utf-8" />
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- <meta name="viewport" content="width=device-width" />
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- <title>My static Space</title>
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- <link rel="stylesheet" href="style.css" />
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- </head>
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- <body>
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- <div class="card">
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- <h1>Welcome to your static Space!</h1>
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- <p>You can modify this app directly by editing <i>index.html</i> in the Files and versions tab.</p>
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- <p>
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- Also don't forget to check the
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- <a href="https://huggingface.co/docs/hub/spaces" target="_blank">Spaces documentation</a>.
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- </p>
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- </div>
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- </body>
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- </html>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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+ <!DOCTYPE html>
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+ <html lang="en">
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+ <head>
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+ <meta charset="UTF-8">
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+ <meta name="viewport" content="width=device-width, initial-scale=1.0">
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+ <title>HSPA Core Explorer</title>
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+ <link rel="icon" type="image/x-icon" href="/static/favicon.ico">
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+ <link rel="stylesheet" href="style.css">
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+ <script src="https://cdn.tailwindcss.com"></script>
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+ <script src="https://cdn.jsdelivr.net/npm/feather-icons/dist/feather.min.js"></script>
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+ <script src="https://unpkg.com/feather-icons"></script>
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+ <script src="https://cdn.jsdelivr.net/npm/vanta@latest/dist/vanta.globe.min.js"></script>
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+ </head>
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+ <body class="bg-gray-900 text-white min-h-screen flex flex-col">
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+ <custom-navbar></custom-navbar>
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+
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+ <div id="vanta-bg" class="absolute inset-0 z-0"></div>
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+
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+ <main class="relative z-10 flex-grow container mx-auto px-4 py-8">
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+ <section class="text-center py-16">
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+ <h1 class="text-5xl font-bold mb-6">HSPA Core Explorer</h1>
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+ <p class="text-xl max-w-2xl mx-auto mb-10">Dive into the next-generation Probabilistic Semantic Processing Architecture</p>
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+ <div class="flex justify-center gap-4">
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+ <a href="#architecture" class="bg-blue-600 hover:bg-blue-700 text-white font-bold py-3 px-6 rounded-lg transition duration-300">Explore Architecture</a>
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+ <a href="#prototype" class="bg-purple-600 hover:bg-purple-700 text-white font-bold py-3 px-6 rounded-lg transition duration-300">View Prototype</a>
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+ </div>
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+ </section>
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+
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+ <section id="architecture" class="py-16">
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+ <h2 class="text-3xl font-bold mb-8 text-center">System Architecture</h2>
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+ <div class="grid grid-cols-1 md:grid-cols-2 lg:grid-cols-3 gap-8">
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+ <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">
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+ <i data-feather="cpu" class="w-12 h-12 mb-4 text-blue-400"></i>
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+ <h3 class="text-xl font-bold mb-2">PMCU</h3>
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+ <p>Probabilistic Microcontroller Unit with Bayesian scheduling</p>
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+ </div>
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+ <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">
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+ <i data-feather="grid" class="w-12 h-12 mb-4 text-green-400"></i>
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+ <h3 class="text-xl font-bold mb-2">RLC Fabric</h3>
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+ <p>Reconfigurable Logic Cell array for parallel execution</p>
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+ </div>
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+ <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">
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+ <i data-feather="database" class="w-12 h-12 mb-4 text-yellow-400"></i>
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+ <h3 class="text-xl font-bold mb-2">SEG Memory</h3>
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+ <p>Semantic Execution Graph storage and management</p>
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+ </div>
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+ <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">
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+ <i data-feather="layers" class="w-12 h-12 mb-4 text-red-400"></i>
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+ <h3 class="text-xl font-bold mb-2">UML</h3>
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+ <p>Unified Memory Lattice with semantic tagging</p>
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+ </div>
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+ <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">
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+ <i data-feather="trending-up" class="w-12 h-12 mb-4 text-purple-400"></i>
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+ <h3 class="text-xl font-bold mb-2">SOML</h3>
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+ <p>Self-Optimizing Microcode Layer for adaptive performance</p>
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+ </div>
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+ <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">
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+ <i data-feather="refresh-cw" class="w-12 h-12 mb-4 text-indigo-400"></i>
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+ <h3 class="text-xl font-bold mb-2">MIT</h3>
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+ <p>Meta-ISA Translator for legacy compatibility</p>
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+ </div>
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+ </div>
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+ </section>
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+
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+ <section id="prototype" class="py-16">
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+ <h2 class="text-3xl font-bold mb-8 text-center">Verilog Prototype</h2>
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+ <div class="bg-gray-800 bg-opacity-70 rounded-xl p-8 backdrop-blur-sm">
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+ <div class="flex flex-wrap gap-4 mb-6">
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+ <button class="prototype-tab active" data-file="seg_memory.v">seg_memory.v</button>
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+ <button class="prototype-tab" data-file="pmcu.v">pmcu.v</button>
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+ <button class="prototype-tab" data-file="rlc.v">rlc.v</button>
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+ <button class="prototype-tab" data-file="uml.v">uml.v</button>
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+ <button class="prototype-tab" data-file="soml.v">soml.v</button>
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+ <button class="prototype-tab" data-file="mit_translator.v">mit_translator.v</button>
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+ <button class="prototype-tab" data-file="top.v">top.v</button>
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+ </div>
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+ <pre id="prototype-code" class="bg-gray-900 p-4 rounded-lg overflow-x-auto text-sm max-h-96"><code>// Loading prototype code...</code></pre>
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+ </div>
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+ </section>
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+
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+ <section class="py-16">
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+ <h2 class="text-3xl font-bold mb-8 text-center">FPGA Carrier Board</h2>
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+ <div class="bg-gray-800 bg-opacity-70 rounded-xl p-8 backdrop-blur-sm">
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+ <div class="grid grid-cols-1 md:grid-cols-2 gap-8">
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+ <div>
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+ <h3 class="text-xl font-bold mb-4">Key Specifications</h3>
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+ <ul class="space-y-2">
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>
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+ Xilinx Zynq UltraScale+ MPSoC ZU9EG
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>
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+ 2x 72-bit DDR4 ECC banks (up to 4GB)
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>
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+ PCIe Gen3 x8 edge connector
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>
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+ 2x SFP+ cages (10GbE)
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>
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+ FMC HPC connector for expansion
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+ </li>
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+ </ul>
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+ </div>
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+ <div>
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+ <h3 class="text-xl font-bold mb-4">Features</h3>
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+ <ul class="space-y-2">
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>
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+ Partial reconfiguration support
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>
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+ PMBus power management
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>
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+ Si5345 clock generation
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>
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+ Thermal management with fan control
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+ </li>
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+ <li class="flex items-center">
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+ <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>
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+ JTAG/UART debugging interface
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+ </li>
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+ </ul>
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+ </div>
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+ </div>
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+ </div>
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+ </section>
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+ </main>
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+
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+ <custom-footer></custom-footer>
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+ <script src="components/navbar.js"></script>
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+ <script src="components/footer.js"></script>
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+ <script src="script.js"></script>
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+ <script>feather.replace();</script>
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+ </body>
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+ </html>