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| """ | |
| Physics-inspired digital core model for virtual GPU v2. | |
| Contains AdvancedCore class and example usage. | |
| """ | |
| from logic_gates import ControlUnit, ALU2Bit, RegisterFile2x2, SimpleMMU | |
| class AdvancedCore: | |
| """ | |
| Simulates a physics-inspired digital core with: | |
| - Control unit | |
| - ALU | |
| - Register file | |
| - MMU | |
| - Clocking and timing at the voltage/physics level | |
| """ | |
| def __init__(self, bits=2, num_registers=2): | |
| self.control = ControlUnit() | |
| self.alu = ALU2Bit() | |
| self.regfile = RegisterFile2x2() | |
| self.mmu = SimpleMMU(num_registers=num_registers, bits=bits) | |
| self.clk = 0.7 # High voltage for clock | |
| self.bits = bits | |
| def step(self, a, b, cin, opcode, reg_sel): | |
| # Set control signals | |
| self.control.set_opcode(opcode) | |
| ctrl = self.control.get_control_signals() | |
| # ALU operation | |
| (r0, r1), cout = self.alu.operate(a[0], a[1], b[0], b[1], cin, ctrl['alu_op']) | |
| # Write to register file | |
| self.regfile.write(r0, r1, self.clk, reg_sel) | |
| # MMU write (simulate memory-mapped register) | |
| self.mmu.write(reg_sel, [r0, r1], self.clk) | |
| # Read back | |
| reg_out = self.regfile.read(reg_sel) | |
| mmu_out = self.mmu.read(reg_sel) | |
| return { | |
| 'alu_result': (r0, r1), | |
| 'carry_out': cout, | |
| 'regfile_out': reg_out, | |
| 'mmu_out': mmu_out, | |
| 'control': ctrl | |
| } | |
| if __name__ == "__main__": | |
| print("\n--- Advanced Core Simulation ---") | |
| core = AdvancedCore(bits=2, num_registers=2) | |
| # Simulate an ADD operation between (1,0) and (1,1), store in reg0 | |
| result = core.step([0.7, 0.0], [0.7, 0.7], 0.0, 0b10, 0) | |
| print("Core step (ADD):", result) | |
| # Simulate an OR operation between (1,0) and (1,1), store in reg1 | |
| result = core.step([0.7, 0.0], [0.7, 0.7], 0.0, 0b01, 1) | |
| print("Core step (OR):", result) | |