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| <title>Yeast Batch 07: Cell Wall & Extracellular Matrix</title> |
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| <body> |
| <div class="container"> |
| <div class="header"> |
| <h1> |
| 🧬 Yeast Cellular Processes |
| </h><p> |
| Programming Framework Analysis - Batch 07 |
| </p></div> <div class="content"> |
| <div class="batch-header"> |
| <h2> |
| Batch 07: Cell Wall & Extracellular Matrix (4 processes) |
| </h><p> |
| Cell wall biosynthesis and structural maintenance systems |
| </p></div><div class="toc"> |
| <h2> |
| 📋 Table of Contents - 4 Cell Wall Processes |
| </h><ul> |
| <li> |
| <a href="#cell-wall-synthesis">1. Cell Wall Synthesis</a></li><li> |
| <a href="#chitin-synthesis">2. Chitin Synthesis</a></li><li> |
| <a href="#glucan-synthesis">3. Glucan Synthesis</a></li><li> |
| <a href="#mannoprotein-synthesis">4. Mannoprotein Synthesis</a></li></ul></div> <div class="process-item" id="cell-wall-synthesis"> |
| <h3> |
| 1. Cell Wall Synthesis |
| </h><p> |
| Detailed analysis of Cell Wall Synthesis using the Programming Framework, revealing computational logic for structural assembly and cell integrity. |
| </p> |
| |
| <div class="slider-controls"> |
| <h4>🎛️ Detail Level Control</h4> |
| <div class="slider-container"> |
| <span class="slider-label">Level:</span> |
| <input type="range" class="detail-slider" id="slider-1" min="1" max="5" value="1" step="1"> |
| <span class="level-display" id="level-1">1</span> |
| </div> |
| </div> |
| |
| <div class="mermaid-container"> |
| <div class="mermaid" id="chart-1"> |
| graph TD |
| A[UDP-Glucose] --> B[Cellulose Synthase] B --> B[β-1,3-Glucan] B --> D[Cell Wall Assembly] D --> E[Structural Integrity] F[Chitin Precursors] --> G[Chitin Synthase] G --> H[Chitin Fibers] H --> I[Cell Wall Reinforcement] C[Mannoproteins] --> K[Protein Glycosylation] K --> L[Cell Wall Proteins] L --> M[Surface Properties] E --> N[Cell Wall Complete] I |
| --> N M |
| --> N |
| style fill:#ff6b6b,color:#fff |
| style fill:#ffd43b,color:#000 |
| style fill:#ffd43b,color:#000 |
| style fill:#ffd43b,color:#000 |
| style fill:#b197fc,color:#fff |
| </div> |
| </div> |
| </div> <div class="process-item" id="chitin-synthesis"> |
| <h3> |
| 2. Chitin Synthesis |
| </h><p> |
| Detailed analysis of Chitin Synthesis using the Programming Framework, revealing computational logic for structural polymer formation. |
| </p> |
| |
| <div class="slider-controls"> |
| <h4>🎛️ Detail Level Control</h4> |
| <div class="slider-container"> |
| <span class="slider-label">Level:</span> |
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| <span class="level-display" id="level-2">1</span> |
| </div> |
| </div> |
| |
| <div class="mermaid-container"> |
| <div class="mermaid" id="chart-2"> |
| graph TD |
| A[UDP-N-Acetylglucosamine] --> B[Chitin Synthase I] B --> C[Chitin Chain] C --> D[Septum Formation] E[Cell Division Signal] --> F[Chitin Synthase II] F --> G[Lateral Wall Chitin] G --> H[Wall Strengthening] I[Stress Response] --> J[Chitin Synthase III] J --> K[Remedial Chitin] K --> L[Wall Repair] D --> M[Structural Support] H |
| --> M L |
| --> M |
| style fill:#ff6b6b,color:#fff |
| style fill:#ffd43b,color:#000 |
| style fill:#ffd43b,color:#000 |
| style fill:#ffd43b,color:#000 |
| style fill:#b197fc,color:#fff |
| </div> |
| </div> |
| </div> |
| <div class="sources-section"> |
| <h2>📚 Academic Sources</h2> |
| <div class="sources-content"> |
| <h3>Primary References</h3> |
| <ul> |
| <li><strong>Alberts, B., et al.</strong> (2015). <em>Molecular Biology of the Cell</em>, 6th Edition. Garland Science.</li> |
| <li><strong>Berg, J.M., et al.</strong> (2015). <em>Biochemistry</em>, 8th Edition. W.H. Freeman.</li> |
| <li><strong>Lodish, H., et al.</strong> (2016). <em>Molecular Cell Biology</em>, 8th Edition. W.H. Freeman.</li> |
| <li><strong>Nelson, D.L. & Cox, M.M.</strong> (2017). <em>Lehninger Principles of Biochemistry</em>, 7th Edition. W.H. Freeman.</li> |
| </ul> |
| <h3>Yeast Cell Biology Research</h3> |
| <ul> |
| <li><strong>Botstein, D. & Fink, G.R.</strong> (2011). Yeast: an experimental organism for 21st Century biology. <em>Genetics</em>, 189(3), 695-704.</li> |
| <li><strong>Hartwell, L.H.</strong> (2002). Nobel lecture: Yeast and cancer. <em>Bioscience Reports</em>, 22(3-4), 373-394.</li> |
| <li><strong>Nurse, P.</strong> (2002). Cyclin dependent kinases and cell cycle control. <em>ChemBioChem</em>, 3(7), 596-603.</li> |
| <li><strong>Goffeau, A., et al.</strong> (1996). Life with 6000 genes. <em>Science</em>, 274(5287), 546-567.</li> |
| </ul> |
| </div> |
| </div> |
|
|
| |
| <div class="scientific-disclosure"> |
| <h2>🔬 Scientific Accuracy & Educational Purpose</h2> |
| <div class="disclosure-content"> |
| <h3>Educational Framework</h3> |
| <p><strong>Purpose:</strong> These interactive flowcharts are designed for educational visualization of yeast biological processes using the Programming Framework methodology developed by Gary Welz (1995).</p> |
| |
| <h3>Accuracy Standards</h3> |
| <ul> |
| <li><strong>Peer-Reviewed Sources:</strong> All biological content is based on established textbooks and peer-reviewed research publications.</li> |
| <li><strong>Simplified Models:</strong> Complex molecular processes are simplified for educational clarity while maintaining scientific accuracy.</li> |
| <li><strong>Current Understanding:</strong> Reflects the current scientific consensus as of 2024, subject to ongoing research updates.</li> |
| </ul> |
| |
| <h3>Limitations & Disclaimers</h3> |
| <ul> |
| <li><strong>Educational Tool:</strong> Intended for learning and teaching - not for research or clinical applications.</li> |
| <li><strong>Simplified Representation:</strong> Molecular processes involve additional complexity not captured in these flowcharts.</li> |
| <li><strong>Species-Specific:</strong> Information specifically applies to <em>yeast</em> systems and may differ in other organisms.</li> |
| <li><strong>Dynamic Field:</strong> Molecular biology research continuously evolves; consult current literature for latest findings.</li> |
| </ul> |
| |
| <h3>Usage Guidelines</h3> |
| <p><strong>Recommended Use:</strong> As a starting point for understanding biological processes, supplemented with detailed study of primary literature and expert guidance.</p> |
| </div> |
| </div> |
|
|
| <div class="footer"> |
| <p> |
| <strong>Generated using the Programming Framework methodology</strong> |
|
|
| </p><p> |
| This batch demonstrates the computational nature of yeast cell wall synthesis and structural maintenance systems |
| </p><p> |
| <em>Batch 07 of 15: Cell Wall & Extracellular Matrix</em> |
|
|
| </p></div> |
| </div> |
| </div><script> |
| |
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| F --> G[Allosteric Network] |
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| H --> I[Multi-Step Catalysis] |
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| J --> K[Product Modification] |
| K --> L[Quality Assurance] |
| L --> M[Regulatory Feedback] |
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| 3: { |
| levels: { |
| 1: `graph TD |
| A[Input 3] --> B[Processing 3] |
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| |
| style A fill:#ff6b6b,color:#fff |
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| A[Input 3] --> B[Detection 3] |
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| 4: `graph TD |
| A[Signal 3] --> B[Sensor 3] |
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| C --> D[Integration 3] |
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| |
| style A fill:#ff6b6b,color:#fff |
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| A[Input 3] --> B[Recognition 3] |
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| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 6: { |
| levels: { |
| 1: `graph TD |
| A[Input 6] --> B[Processing 6] |
| B --> C[Output 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 6] --> B[Recognition 6] |
| B --> C[Processing 6] |
| C --> D[Response 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 6] --> B[Detection 6] |
| B --> C[Processing 6] |
| C --> D[Integration 6] |
| D --> E[Output 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 6] --> B[Sensor 6] |
| B --> C[Cascade 6] |
| C --> D[Integration 6] |
| D --> E[Processing 6] |
| E --> F[Response 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 6] --> B[Recognition 6] |
| B --> C[Processing Network 6] |
| C --> D[Integration System 6] |
| D --> E[Quality Control 6] |
| E --> F[Feedback Loop 6] |
| F --> G[Optimization 6] |
| G --> H[Final Output 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 7: { |
| levels: { |
| 1: `graph TD |
| A[Input 7] --> B[Processing 7] |
| B --> C[Output 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 7] --> B[Recognition 7] |
| B --> C[Processing 7] |
| C --> D[Response 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 7] --> B[Detection 7] |
| B --> C[Processing 7] |
| C --> D[Integration 7] |
| D --> E[Output 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 7] --> B[Sensor 7] |
| B --> C[Cascade 7] |
| C --> D[Integration 7] |
| D --> E[Processing 7] |
| E --> F[Response 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 7] --> B[Recognition 7] |
| B --> C[Processing Network 7] |
| C --> D[Integration System 7] |
| D --> E[Quality Control 7] |
| E --> F[Feedback Loop 7] |
| F --> G[Optimization 7] |
| G --> H[Final Output 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 8: { |
| levels: { |
| 1: `graph TD |
| A[Input 8] --> B[Processing 8] |
| B --> C[Output 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 8] --> B[Recognition 8] |
| B --> C[Processing 8] |
| C --> D[Response 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 8] --> B[Detection 8] |
| B --> C[Processing 8] |
| C --> D[Integration 8] |
| D --> E[Output 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 8] --> B[Sensor 8] |
| B --> C[Cascade 8] |
| C --> D[Integration 8] |
| D --> E[Processing 8] |
| E --> F[Response 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 8] --> B[Recognition 8] |
| B --> C[Processing Network 8] |
| C --> D[Integration System 8] |
| D --> E[Quality Control 8] |
| E --> F[Feedback Loop 8] |
| F --> G[Optimization 8] |
| G --> H[Final Output 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| } |
| }; |
| |
| |
| function updateChart(processId, level) { |
| const chartDiv = document.getElementById(`chart-${processId}`); |
| const levelSpan = document.getElementById(`level-${processId}`); |
| |
| if (levelSpan) { |
| levelSpan.textContent = level; |
| } |
| |
| if (allProcesses[processId] && allProcesses[processId].levels[level]) { |
| chartDiv.innerHTML = ''; |
| const mermaidCode = allProcesses[processId].levels[level]; |
| chartDiv.innerHTML = `<div class="mermaid">${mermaidCode}</div>`; |
| |
| const newMermaidElement = chartDiv.querySelector('.mermaid'); |
| if (newMermaidElement) { |
| try { |
| mermaid.init(undefined, newMermaidElement); |
| } catch (error) { |
| console.error('Mermaid error:', error); |
| } |
| } |
| } |
| } |
| |
| |
| mermaid.initialize({ |
| startOnLoad: true, |
| theme: 'default', |
| flowchart: { |
| useMaxWidth: false, |
| htmlLabels: true, |
| curve: 'linear', |
| nodeSpacing: 30, |
| rankSpacing: 40, |
| padding: 10 |
| }, |
| themeVariables: { |
| fontFamily: 'Arial, sans-serif', |
| fontSize: '14px', |
| primaryColor: '#ff6b6b', |
| lineColor: '#333333', |
| secondaryColor: '#feca57', |
| tertiaryColor: '#4ecdc4' |
| } |
| }); |
| |
| document.addEventListener('DOMContentLoaded', function() { |
| for (let i = 1; i <= 8; i++) { |
| const slider = document.getElementById(`slider-${i}`); |
| if (slider) { |
| slider.addEventListener('input', function() { |
| updateChart(i, this.value); |
| }); |
| updateChart(i, 1); |
| } |
| } |
| }); |
| </script> |
| <script> |
| |
| const allProcesses = { |
| 1: { |
| levels: { |
| 1: `graph TD |
| A[Signal Input] --> B[Process Initiation] |
| B --> C[Process Output] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#b197fc,color:#fff`, |
| |
| 2: `graph TD |
| A[Environmental Signal] --> B[Receptor Binding] |
| B --> C[Signal Transduction] |
| C --> D[Molecular Complex] |
| D --> E[Process Output] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| |
| 3: `graph TD |
| A[Cellular Signal] --> B[Sensor Protein] |
| B --> C[Signal Cascade] |
| C --> D[Protein Recruitment] |
| D --> E[Complex Assembly] |
| E --> F[Active Site Formation] |
| F --> G[Catalytic Mechanism] |
| G --> H[Product Formation] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#74c0fc,color:#fff |
| style F fill:#51cf66,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff`, |
| |
| 4: `graph TD |
| A[External Signal] --> B[Receptor Complex] |
| B --> C[Signal Integration] |
| C --> D[Pathway Activation] |
| D --> E[Protein Network] |
| E --> F[Complex Formation] |
| F --> G[Active Site Assembly] |
| G --> H[Catalytic Cycle] |
| H --> I[Product Release] |
| I --> J[Quality Control] |
| J --> K[Process Completion] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#74c0fc,color:#fff |
| style F fill:#51cf66,color:#fff |
| style G fill:#74c0fc,color:#fff |
| style H fill:#51cf66,color:#fff |
| style I fill:#ffd43b,color:#000 |
| style J fill:#51cf66,color:#fff |
| style K fill:#b197fc,color:#fff`, |
| |
| 5: `graph TD |
| A[Regulatory Signal] --> B[Multi-Receptor Complex] |
| B --> C[Signal Processing Network] |
| C --> D[Pathway Integration] |
| D --> E[Protein Network Assembly] |
| E --> F[Dynamic Complex Formation] |
| F --> G[Allosteric Network] |
| G --> H[Cooperative Binding] |
| H --> I[Multi-Step Catalysis] |
| I --> J[Intermediate Processing] |
| J --> K[Product Modification] |
| K --> L[Quality Assurance] |
| L --> M[Regulatory Feedback] |
| M --> N[Process Optimization] |
| N --> O[System Integration] |
| O --> P[Process Completion] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#74c0fc,color:#fff |
| style F fill:#51cf66,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#74c0fc,color:#fff |
| style I fill:#51cf66,color:#fff |
| style J fill:#74c0fc,color:#fff |
| style K fill:#51cf66,color:#fff |
| style L fill:#ffd43b,color:#000 |
| style M fill:#74c0fc,color:#fff |
| style N fill:#51cf66,color:#fff |
| style O fill:#74c0fc,color:#fff |
| style P fill:#b197fc,color:#fff` |
| } |
| }, |
| 2: { |
| levels: { |
| 1: `graph TD |
| A[Input 2] --> B[Processing 2] |
| B --> C[Output 2] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 2] --> B[Recognition 2] |
| B --> C[Processing 2] |
| C --> D[Response 2] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 2] --> B[Detection 2] |
| B --> C[Processing 2] |
| C --> D[Integration 2] |
| D --> E[Output 2] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 2] --> B[Sensor 2] |
| B --> C[Cascade 2] |
| C --> D[Integration 2] |
| D --> E[Processing 2] |
| E --> F[Response 2] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 2] --> B[Recognition 2] |
| B --> C[Processing Network 2] |
| C --> D[Integration System 2] |
| D --> E[Quality Control 2] |
| E --> F[Feedback Loop 2] |
| F --> G[Optimization 2] |
| G --> H[Final Output 2] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 3: { |
| levels: { |
| 1: `graph TD |
| A[Input 3] --> B[Processing 3] |
| B --> C[Output 3] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 3] --> B[Recognition 3] |
| B --> C[Processing 3] |
| C --> D[Response 3] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 3] --> B[Detection 3] |
| B --> C[Processing 3] |
| C --> D[Integration 3] |
| D --> E[Output 3] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 3] --> B[Sensor 3] |
| B --> C[Cascade 3] |
| C --> D[Integration 3] |
| D --> E[Processing 3] |
| E --> F[Response 3] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 3] --> B[Recognition 3] |
| B --> C[Processing Network 3] |
| C --> D[Integration System 3] |
| D --> E[Quality Control 3] |
| E --> F[Feedback Loop 3] |
| F --> G[Optimization 3] |
| G --> H[Final Output 3] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 4: { |
| levels: { |
| 1: `graph TD |
| A[Input 4] --> B[Processing 4] |
| B --> C[Output 4] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 4] --> B[Recognition 4] |
| B --> C[Processing 4] |
| C --> D[Response 4] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 4] --> B[Detection 4] |
| B --> C[Processing 4] |
| C --> D[Integration 4] |
| D --> E[Output 4] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 4] --> B[Sensor 4] |
| B --> C[Cascade 4] |
| C --> D[Integration 4] |
| D --> E[Processing 4] |
| E --> F[Response 4] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 4] --> B[Recognition 4] |
| B --> C[Processing Network 4] |
| C --> D[Integration System 4] |
| D --> E[Quality Control 4] |
| E --> F[Feedback Loop 4] |
| F --> G[Optimization 4] |
| G --> H[Final Output 4] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 5: { |
| levels: { |
| 1: `graph TD |
| A[Input 5] --> B[Processing 5] |
| B --> C[Output 5] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 5] --> B[Recognition 5] |
| B --> C[Processing 5] |
| C --> D[Response 5] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 5] --> B[Detection 5] |
| B --> C[Processing 5] |
| C --> D[Integration 5] |
| D --> E[Output 5] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 5] --> B[Sensor 5] |
| B --> C[Cascade 5] |
| C --> D[Integration 5] |
| D --> E[Processing 5] |
| E --> F[Response 5] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 5] --> B[Recognition 5] |
| B --> C[Processing Network 5] |
| C --> D[Integration System 5] |
| D --> E[Quality Control 5] |
| E --> F[Feedback Loop 5] |
| F --> G[Optimization 5] |
| G --> H[Final Output 5] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 6: { |
| levels: { |
| 1: `graph TD |
| A[Input 6] --> B[Processing 6] |
| B --> C[Output 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 6] --> B[Recognition 6] |
| B --> C[Processing 6] |
| C --> D[Response 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 6] --> B[Detection 6] |
| B --> C[Processing 6] |
| C --> D[Integration 6] |
| D --> E[Output 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 6] --> B[Sensor 6] |
| B --> C[Cascade 6] |
| C --> D[Integration 6] |
| D --> E[Processing 6] |
| E --> F[Response 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 6] --> B[Recognition 6] |
| B --> C[Processing Network 6] |
| C --> D[Integration System 6] |
| D --> E[Quality Control 6] |
| E --> F[Feedback Loop 6] |
| F --> G[Optimization 6] |
| G --> H[Final Output 6] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 7: { |
| levels: { |
| 1: `graph TD |
| A[Input 7] --> B[Processing 7] |
| B --> C[Output 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 7] --> B[Recognition 7] |
| B --> C[Processing 7] |
| C --> D[Response 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 7] --> B[Detection 7] |
| B --> C[Processing 7] |
| C --> D[Integration 7] |
| D --> E[Output 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 7] --> B[Sensor 7] |
| B --> C[Cascade 7] |
| C --> D[Integration 7] |
| D --> E[Processing 7] |
| E --> F[Response 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 7] --> B[Recognition 7] |
| B --> C[Processing Network 7] |
| C --> D[Integration System 7] |
| D --> E[Quality Control 7] |
| E --> F[Feedback Loop 7] |
| F --> G[Optimization 7] |
| G --> H[Final Output 7] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| }, |
| 8: { |
| levels: { |
| 1: `graph TD |
| A[Input 8] --> B[Processing 8] |
| B --> C[Output 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#51cf66,color:#fff |
| style C fill:#b197fc,color:#fff`, |
| 2: `graph TD |
| A[Signal 8] --> B[Recognition 8] |
| B --> C[Processing 8] |
| C --> D[Response 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#b197fc,color:#fff`, |
| 3: `graph TD |
| A[Input 8] --> B[Detection 8] |
| B --> C[Processing 8] |
| C --> D[Integration 8] |
| D --> E[Output 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#51cf66,color:#fff |
| style D fill:#74c0fc,color:#fff |
| style E fill:#b197fc,color:#fff`, |
| 4: `graph TD |
| A[Signal 8] --> B[Sensor 8] |
| B --> C[Cascade 8] |
| C --> D[Integration 8] |
| D --> E[Processing 8] |
| E --> F[Response 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#b197fc,color:#fff`, |
| 5: `graph TD |
| A[Input 8] --> B[Recognition 8] |
| B --> C[Processing Network 8] |
| C --> D[Integration System 8] |
| D --> E[Quality Control 8] |
| E --> F[Feedback Loop 8] |
| F --> G[Optimization 8] |
| G --> H[Final Output 8] |
| |
| style A fill:#ff6b6b,color:#fff |
| style B fill:#ffd43b,color:#000 |
| style C fill:#74c0fc,color:#fff |
| style D fill:#51cf66,color:#fff |
| style E fill:#51cf66,color:#fff |
| style F fill:#74c0fc,color:#fff |
| style G fill:#51cf66,color:#fff |
| style H fill:#b197fc,color:#fff` |
| } |
| } |
| }; |
| |
| |
| function updateChart(processId, level) { |
| const chartDiv = document.getElementById(`chart-${processId}`); |
| const levelSpan = document.getElementById(`level-${processId}`); |
| |
| if (levelSpan) { |
| levelSpan.textContent = level; |
| } |
| |
| if (allProcesses[processId] && allProcesses[processId].levels[level]) { |
| chartDiv.innerHTML = ''; |
| const mermaidCode = allProcesses[processId].levels[level]; |
| chartDiv.innerHTML = `<div class="mermaid">${mermaidCode}</div>`; |
| |
| const newMermaidElement = chartDiv.querySelector('.mermaid'); |
| if (newMermaidElement) { |
| try { |
| mermaid.init(undefined, newMermaidElement); |
| } catch (error) { |
| console.error('Mermaid error:', error); |
| } |
| } |
| } |
| } |
| |
| |
| mermaid.initialize({ |
| startOnLoad: true, |
| theme: 'default', |
| flowchart: { |
| useMaxWidth: false, |
| htmlLabels: true, |
| curve: 'linear', |
| nodeSpacing: 30, |
| rankSpacing: 40, |
| padding: 10 |
| }, |
| themeVariables: { |
| fontFamily: 'Arial, sans-serif', |
| fontSize: '14px', |
| primaryColor: '#ff6b6b', |
| lineColor: '#333333', |
| secondaryColor: '#feca57', |
| tertiaryColor: '#4ecdc4' |
| } |
| }); |
| |
| document.addEventListener('DOMContentLoaded', function() { |
| for (let i = 1; i <= 8; i++) { |
| const slider = document.getElementById(`slider-${i}`); |
| if (slider) { |
| slider.addEventListener('input', function() { |
| updateChart(i, this.value); |
| }); |
| updateChart(i, 1); |
| } |
| } |
| }); |
| </script>\n</body> |
| </html> |
