Update verilog.txt

verilog.txt

@@ -535,4 +535,181 @@ Line 61: end - Ends the write operation block.
 Line 62: end - Ends the else block (normal operation).
 Line 63: end - Ends the synchronous always block.
 Line 64: - Blank line for visual separation.
-Line 65: endmodule - Ends the Register File module definition.
+Line 65: endmodule - Ends the Register File module definition.
+
+[Processor Top Module]
+Line 1: `timescale 1ns / 1ps - Sets simulation time unit to 1 nanosecond and precision to 1 picosecond.
+Line 2: - Blank line for visual separation.
+Line 3: module Processor( - Defines the start of the main Processor module.
+Line 4: input clk, - Declares the global clock input for synchronous operations.
+Line 5: input rst - Declares the global reset input to initialize the processor.
+Line 6: ); - Closes the module port declaration list.
+Line 7: reg [7:0] pc; - Declares an 8-bit register for the Program Counter.
+Line 8: // The program counter register - Comment explaining the PC register.
+Line 9: reg [3:0] status_reg; - Declares a 4-bit register to hold processor status flags.
+Line 10: // Register holding all the flags - Comment explaining status register purpose.
+Line 11: reg [7:0] next_pc; - Declares an 8-bit register for the next PC value.
+Line 12: // Value of next address to go to - Comment explaining next PC calculation.
+Line 13: reg [63:0] hi_reg , lo_reg; - Declares two 64-bit registers for multiplication results.
+Line 14: // Our special purpose registers - Comment explaining HI/LO registers.
+Line 15: wire [19:0] instruction_wire; - Declares a 20-bit wire for instruction transmission.
+Line 16: //Wire carrying the actual 20 bit instruction - Comment explaining instruction wire.
+Line 17: reg signed [63:0] alu_input_b; - Declares a signed 64-bit register for ALU's second input.
+Line 18: reg [63:0] write_back_data; - Declares a 64-bit register for register write-back data.
+Line 19: // Data going to be saved in register coming from either alu or memory ( selected through mux) - Comment explaining write-back data source.
+Line 20: // Data path wires - Comment section header for data path wires.
+Line 21: wire [63:0] read_data1_reg; - Declares a 64-bit wire for first register read data.
+Line 22: // Holds input 'a' going to alu - Comment explaining ALU input A.
+Line 23: wire [63:0] read_data2_reg; - Declares a 64-bit wire for second register read data.
+Line 24: // Holds input 'b' goes to mux - Comment explaining ALU input B source.
+Line 25: wire [63:0] alu_result; - Declares a 64-bit wire for ALU computation result.
+Line 26: // Holds the result of the alu after calculation - Comment explaining ALU result.
+Line 27: wire [63:0] mem_read_data; - Declares a 64-bit wire for memory read data.
+Line 28: // Data from memory going to register or alu through mux ( load word or load immediate ) - Comment explaining memory data path.
+Line 29: wire [63:0] alu_hi_out , alu_lo_out; - Declares two 64-bit wires for ALU's HI/LO outputs.
+Line 30: // wires holding hi and lo - Comment explaining HI/LO wires.
+Line 31: - Blank line for visual separation.
+Line 32: // Control signal wires - Comment section header for control signals.
+Line 33: wire partial_write_signal; - Declares wire for partial write control signal.
+Line 34: // control signal for mlw - Comment explaining modified load word signal.
+Line 35: wire jump , branch , zero_flag , neg_flag , carry_flag , overflow_flag; - Declares multiple control and flag wires.
+Line 36: wire reg_write_en , mem_write_en; - Declares wires for register and memory write enables.
+Line 37: // enabelers to write to memory(store word) and registers - Comment explaining write enables (typo: "enablers").
+Line 38: wire vector_mode; - Declares wire for vector mode control signal.
+Line 39: // control signal for our custom vector load instruction - Comment explaining vector mode.
+Line 40: wire alu_mux; - Declares wire for ALU input multiplexer select.
+Line 41: // select line for mux before alu - Comment explaining ALU mux purpose.
+Line 42: wire mem_to_reg; - Declares wire for memory-to-register multiplexer select.
+Line 43: // select line choosing btw alu result or memory data to be stored in register file - Comment explaining write-back mux.
+Line 44: // Splitter splitiing the instruction bits into respective wires according to the instruction type - Comment about instruction decoding (typo: "splitting").
+Line 45: wire [4:0] opcode = instruction_wire[4:0]; - Extracts 5-bit opcode from instruction.
+Line 46: wire [2:0] rd = instruction_wire[7:5]; - Extracts 3-bit destination register field.
+Line 47: wire [2:0] rs = instruction_wire[10:8]; - Extracts 3-bit source register 1 field.
+Line 48: wire [2:0] rt = instruction_wire[13:11]; - Extracts 3-bit source register 2 field.
+Line 49: wire [8:0] branch_offset = instruction_wire[19:11]; - Extracts 9-bit branch offset field.
+Line 50: wire [13:0] jump_const = instruction_wire[17:5]; - Extracts 14-bit jump constant field.
+Line 51: wire [1:0] i_mod_lane = instruction_wire[19:18]; - Extracts 2-bit lane selector field.
+Line 52: //lane selector - Comment explaining lane selection field.
+Line 53: wire [5:0] shift_amount = instruction_wire[19:14]; - Extracts 6-bit shift amount field.
+Line 54: // sign extension - Comment section header for sign extension.
+Line 55: wire signed [8:0] signed_const = instruction_wire[19:11]; - Sign-extends I-type constant to 9 bits.
+Line 56: // signed constant for simple i type - Comment explaining I-type constant.
+Line 57: wire signed [6:0] i_mod_const = instruction_wire[17:11]; - Sign-extends modified I-type constant to 7 bits.
+Line 58: // signed constant for mod i type - Comment explaining modified I-type constant.
+Line 59: reg [2:0]reg2_address_in; - Declares 3-bit register for second register address input.
+Line 60: // sequential logic to control clock - Comment explaining clocked sequential logic.
+Line 61: always @ (posedge clk) - Begins synchronous always block on positive clock edge.
+Line 62: begin - Starts the synchronous always block.
+Line 63: if (rst == 1) begin - Conditional check for reset signal.
+Line 64: pc <= 8'd0; - Resets Program Counter to zero.
+Line 65: status_reg <= 4'd0; - Resets status register flags to zero.
+Line 66: end - Ends the reset block.
+Line 67: else - Else clause for normal operation.
+Line 68: begin - Starts normal operation block.
+Line 69: pc <= next_pc; - Updates PC with next PC value.
+Line 70: status_reg <= {carry_flag , overflow_flag , zero_flag , neg_flag}; - Updates status register with ALU flags.
+Line 71: if (opcode == 5'b01101 || opcode == 5'b10000) begin - Conditional check for multiplication instructions.
+Line 72: hi_reg <= alu_hi_out; - Updates HI register with ALU HI output.
+Line 73: lo_reg <= alu_lo_out; - Updates LO register with ALU LO output.
+Line 74: end - Ends multiplication update block.
+Line 75: end - Ends normal operation block.
+Line 76: end - Ends the synchronous always block.
+Line 77: // PC logic - Comment section header for PC calculation.
+Line 78: always @ (*) - Begins combinatorial always block for PC logic.
+Line 79: begin - Starts the PC logic block.
+Line 80: if (jump == 1) - Conditional check for jump instruction.
+Line 81: next_pc = pc + jump_const; - Calculates next PC for jump (PC + jump constant).
+Line 82: else if ((branch == 1) && (zero_flag == 1)) - Conditional check for taken branch.
+Line 83: next_pc = pc + branch_offset; - Calculates next PC for branch (PC + branch offset).
+Line 84: else - Else clause for normal sequential execution.
+Line 85: next_pc = pc + 1; - Calculates next PC for normal flow (PC + 1).
+Line 86: end - Ends the PC logic block.
+Line 87: // Mux before alu to select btw data from reg or mem - Comment explaining ALU input multiplexer.
+Line 88: always @ (*) - Begins combinatorial always block for ALU input selection.
+Line 89: if (alu_mux == 0) - Conditional check for register source.
+Line 90: if (opcode==5'b01010) - Nested conditional for BEQZ instruction.
+Line 91: begin - Starts BEQZ handling block.
+Line 92: alu_input_b = 64'd0; - Sets ALU input B to zero for BEQZ comparison.
+Line 93: end - Ends BEQZ handling block.
+Line 94: else - Else clause for other register-source instructions.
+Line 95: begin - Starts normal register source block.
+Line 96: alu_input_b = read_data2_reg ; - Sets ALU input B to register read data 2.
+Line 97: end - Ends normal register source block.
+Line 98: else - Else clause for immediate/constant source.
+Line 99: begin - Starts immediate source block.
+Line 100: // when i mod instruction or mlw - Comment about modified instructions.
+Line 101: if (opcode == 5'b10011) - Conditional check for modified load word.
+Line 102: alu_input_b = i_mod_const; - Sets ALU input B to modified I-type constant.
+Line 103: // if normal i type instruction - Comment about normal I-type.
+Line 104: else - Else clause for normal I-type.
+Line 105: alu_input_b = signed_const; - Sets ALU input B to sign-extended I-type constant.
+Line 106: end - Ends immediate source block.
+Line 107: // Mux to decide where is data coming from to be stored in reg - Comment explaining write-back multiplexer.
+Line 108: always @ (*) - Begins combinatorial always block for write-back selection.
+Line 109: // coming from alu - Comment for ALU source.
+Line 110: if (mem_to_reg == 0) - Conditional check for ALU source.
+Line 111: begin - Starts ALU source block.
+Line 112: write_back_data = alu_result ; - Selects ALU result for write-back.
+Line 113: end - Ends ALU source block.
+Line 114: // coming from memory ( zero extended because data coming from mem is 16 bit and reg file is 64 bit ) - Comment for memory source.
+Line 115: else - Else clause for memory source.
+Line 116: begin - Starts memory source block.
+Line 117: write_back_data = mem_read_data ; - Selects memory read data for write-back.
+Line 118: end - Ends memory source block.
+Line 119: always @(*) begin - Begins combinatorial always block for register address handling.
+Line 120: // If the instruction is store word (sw), use 'rd' - Comment explaining SW register addressing.
+Line 121: if (opcode == 5'b01000) begin - Conditional check for Store Word instruction.
+Line 122: reg2_address_in = rd; - Uses destination register as source for SW.
+Line 123: end - Ends SW handling block.
+Line 124: // Otherwise, use the standard 'rt' - Comment for standard register addressing.
+Line 125: else begin - Else clause for other instructions.
+Line 126: reg2_address_in = rt; - Uses standard RT field for register addressing.
+Line 127: end - Ends standard addressing block.
+Line 128: end - Ends the register address handling block.
+Line 129: - Blank line for visual separation.
+Line 130: instruction_memory inst_mem ( .PC(pc) , .instruction(instruction_wire) ); - Instantiates Instruction Memory module.
+Line 131: control_unit cntrl_un ( .opcode_instruction(opcode) - Instantiates Control Unit module with opcode.
+Line 132: , .mem_write_sel(mem_write_en) - Connects memory write select signal.
+Line 133: , .reg_write_en(reg_write_en) - Connects register write enable signal.
+Line 134: , .alu_mux(alu_mux) - Connects ALU multiplexer select signal.
+Line 135: , .mem_to_reg(mem_to_reg) - Connects memory-to-register select signal.
+Line 136: , .branch(branch) - Connects branch control signal.
+Line 137: , .jump(jump) - Connects jump control signal.
+Line 138: ,.vector_mode(vector_mode) - Connects vector mode signal.
+Line 139: ,.partial_write(partial_write_signal) - Connects partial write signal.
+Line 140: ); - Ends Control Unit instantiation.
+Line 141: - Blank line for visual separation.
+Line 142: register_file reg_file ( .clk(clk), - Instantiates Register File module with clock.
+Line 143: .rst(rst), - Connects reset signal.
+Line 144: .write_en(reg_write_en), - Connects register write enable.
+Line 145: .write_data(write_back_data), - Connects write-back data.
+Line 146: .read_reg1(rs), - Connects first read register address.
+Line 147: .read_reg2(reg2_address_in), - Connects second read register address.
+Line 148: .write_reg(rd), - Connects write register address.
+Line 149: .read_data1(read_data1_reg), - Connects first read data output.
+Line 150: .read_data2(read_data2_reg) - Connects second read data output.
+Line 151: ,.lane_select(i_mod_lane) - Connects lane selection input.
+Line 152: ,.partial_write_en(partial_write_signal) - Connects partial write enable.
+Line 153: ); - Ends Register File instantiation.
+Line 154: alu alu_uut ( .a(read_data1_reg), - Instantiates ALU module with input A.
+Line 155: .b(alu_input_b), - Connects ALU input B.
+Line 156: .alu_control(opcode), - Connects ALU control (opcode).
+Line 157: .hi_in(hi_reg), - Connects HI register input.
+Line 158: .lo_in(lo_reg), - Connects LO register input.
+Line 159: .shamt(shift_amount[4:0]), - Connects shift amount.
+Line 160: .result(alu_result), - Connects ALU result output.
+Line 161: .hi_out(alu_hi_out), - Connects ALU HI output.
+Line 162: .lo_out(alu_lo_out), - Connects ALU LO output.
+Line 163: .zero(zero_flag), - Connects zero flag output.
+Line 164: .neg(neg_flag), - Connects negative flag output.
+Line 165: .carry(carry_flag), - Connects carry flag output.
+Line 166: .overflow(overflow_flag) - Connects overflow flag output.
+Line 167: ); - Ends ALU instantiation.
+Line 168: data_memory data_mem ( .clk(clk), - Instantiates Data Memory module with clock.
+Line 169: .mem_write_en(mem_write_en), - Connects memory write enable.
+Line 170: .mem_address(alu_result[15:0]), - Connects memory address from ALU result.
+Line 171: .write_data(read_data2_reg[15:0]), - Connects write data from register.
+Line 172: .read_data(mem_read_data), - Connects memory read data output.
+Line 173: .vector_mode(vector_mode) - Connects vector mode signal.
+Line 174: ); - Ends Data Memory instantiation.
+Line 175: endmodule - Ends the Processor module definition.