Update verilog.txt

verilog.txt

@@ -1,8 +1,8 @@
 [Author info]
-- Hashir Ehtisham: NUST student, made this chatbot for ICT project.
-
-This is an ALU module of the code for processor.
+- Hashir Ehtisham: Computer Engineering student at National University of Science & Technology and contributed to developing the chatbot and handling all AI operations of app.
+- Abdullah Ikram: Computer Engineering student at National University of Science & Technology and contributed to writing the ALU code for processor.
 [ALU Module]
+This is an ALU module of the code for processor written in verilog.
 Line 1: `timescale 1ns / 1ps - Sets simulation time unit to 1ns and precision to 1ps.
 Line 2: module alu( - Defines the start of the Arithmetic Logic Unit (ALU) hardware module.
 Line 3: // Data inputs - Comment indicating the start of input port definitions.