instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
import os
os.environ['CUDA_VISIBLE_DEVICES'] = '0,1'
device = torch.device('cuda:0')
model = model.cuda()
print(torch.version.cuda)

output:
import torch
import os
os.environ['HIP_VISIBLE_DEVICES'] = '0,1'
device = torch.device('cuda:0')  # PyTorch ROCm uses 'cuda' alias for HIP
model = model.cuda()  # Works natively on ROCm via HIP backend
print(torch.version.hip)  # ROCm reports HIP version


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
torch.backends.cudnn.benchmark = True
torch.backends.cudnn.deterministic = False
model = torch.nn.DataParallel(model)

output:
import torch
torch.backends.cudnn.benchmark = True  # Maps to MIOpen on ROCm
torch.backends.cudnn.deterministic = False  # MIOpen equivalent
model = torch.nn.DataParallel(model)  # Works on ROCm natively


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
from vllm import LLM, SamplingParams
import os
os.environ['CUDA_HOME'] = '/usr/local/cuda-12.1'
llm = LLM(model='meta-llama/Llama-2-7b', tensor_parallel_size=2, enforce_eager=False)

output:
from vllm import LLM, SamplingParams
import os
os.environ['ROCM_HOME'] = '/opt/rocm'
llm = LLM(model='meta-llama/Llama-2-7b', tensor_parallel_size=2, enforce_eager=True)  # enforce_eager=True recommended for ROCm stability


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
from torch.cuda.amp import autocast, GradScaler
scaler = GradScaler()
with autocast():
    output = model(input)
    loss = criterion(output, target)
scaler.scale(loss).backward()
scaler.step(optimizer)
scaler.update()

output:
import torch
from torch.cuda.amp import autocast, GradScaler  # Works on ROCm via HIP
scaler = GradScaler()
with autocast():  # AMP supported on ROCm
    output = model(input)
    loss = criterion(output, target)
scaler.scale(loss).backward()
scaler.step(optimizer)
scaler.update()


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
if torch.cuda.is_available():
    print(f'GPU: {torch.cuda.get_device_name(0)}')
    print(f'Memory: {torch.cuda.get_device_properties(0).total_mem / 1e9:.1f} GB')
    torch.cuda.empty_cache()
    torch.cuda.synchronize()

output:
import torch
if torch.cuda.is_available():  # Returns True on ROCm (HIP backend)
    print(f'GPU: {torch.cuda.get_device_name(0)}')  # Reports AMD GPU name
    print(f'Memory: {torch.cuda.get_device_properties(0).total_mem / 1e9:.1f} GB')
    torch.cuda.empty_cache()  # Works on ROCm
    torch.cuda.synchronize()  # HIP synchronization


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
os.environ['CUDA_LAUNCH_BLOCKING'] = '1'
os.environ['NCCL_DEBUG'] = 'INFO'
os.environ['NCCL_SOCKET_IFNAME'] = 'eth0'
torch.distributed.init_process_group(backend='nccl')

output:
os.environ['HIP_LAUNCH_BLOCKING'] = '1'
os.environ['NCCL_DEBUG'] = 'INFO'  # RCCL uses same env vars
os.environ['NCCL_SOCKET_IFNAME'] = 'eth0'
torch.distributed.init_process_group(backend='nccl')  # RCCL is drop-in replacement for NCCL


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
from torch.utils.cpp_extension import load_inline
cuda_src = '''
#include <cuda_runtime.h>
#include <cuda.h>
__global__ void add_kernel(float* a, float* b, float* c, int n) {
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    if (i < n) c[i] = a[i] + b[i];
}
'''
module = load_inline(name='ops', cuda_sources=[cuda_src])

output:
from torch.utils.cpp_extension import load_inline
hip_src = '''
#include <hip/hip_runtime.h>
__global__ void add_kernel(float* a, float* b, float* c, int n) {
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    if (i < n) c[i] = a[i] + b[i];
}
'''
module = load_inline(name='ops', cuda_sources=[hip_src])  # PyTorch compiles HIP via hipcc


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
# Dockerfile
FROM nvidia/cuda:12.1.0-devel-ubuntu22.04
RUN pip install torch torchvision --index-url https://download.pytorch.org/whl/cu121
ENV CUDA_HOME=/usr/local/cuda
ENV LD_LIBRARY_PATH=/usr/local/cuda/lib64:$LD_LIBRARY_PATH

output:
# Dockerfile
FROM rocm/pytorch:latest
RUN pip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/rocm6.2
ENV ROCM_HOME=/opt/rocm
ENV LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
import deepspeed
model_engine, optimizer, _, _ = deepspeed.initialize(
    model=model, config='ds_config.json')
for batch in dataloader:
    loss = model_engine(batch)
    model_engine.backward(loss)
    model_engine.step()

output:
import torch
import deepspeed  # DeepSpeed has native ROCm support
model_engine, optimizer, _, _ = deepspeed.initialize(
    model=model, config='ds_config.json')  # Ensure ds_config uses fp16 or bf16
for batch in dataloader:
    loss = model_engine(batch)
    model_engine.backward(loss)
    model_engine.step()  # DeepSpeed handles HIP dispatch automatically


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
from transformers import AutoModelForCausalLM, AutoTokenizer, BitsAndBytesConfig
quant_config = BitsAndBytesConfig(load_in_4bit=True, bnb_4bit_compute_dtype=torch.float16)
model = AutoModelForCausalLM.from_pretrained('meta-llama/Llama-2-7b', quantization_config=quant_config, device_map='auto')

output:
import torch
from transformers import AutoModelForCausalLM, AutoTokenizer, BitsAndBytesConfig
# NOTE: bitsandbytes ROCm support requires bitsandbytes-rocm fork
# pip install bitsandbytes --prefer-binary (ROCm wheels available)
quant_config = BitsAndBytesConfig(load_in_4bit=True, bnb_4bit_compute_dtype=torch.float16)
model = AutoModelForCausalLM.from_pretrained('meta-llama/Llama-2-7b', quantization_config=quant_config, device_map='auto')


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
pip install torch==2.1.0+cu121 torchvision==0.16.0+cu121 torchaudio==2.1.0+cu121 --index-url https://download.pytorch.org/whl/cu121
pip install nvidia-cublas-cu12 nvidia-cudnn-cu12 nvidia-nccl-cu12

output:
pip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/rocm6.2
# No separate library installs needed — ROCm bundles rocBLAS, MIOpen, RCCL
# Verify: python -c "import torch; print(torch.cuda.is_available())"


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
# Multi-GPU training with FSDP
from torch.distributed.fsdp import FullyShardedDataParallel as FSDP
model = FSDP(model, device_id=torch.cuda.current_device())
torch.cuda.set_device(local_rank)
dist.init_process_group('nccl')

output:
import torch
# Multi-GPU training with FSDP — works natively on ROCm
from torch.distributed.fsdp import FullyShardedDataParallel as FSDP
model = FSDP(model, device_id=torch.cuda.current_device())  # HIP backend
torch.cuda.set_device(local_rank)  # Maps to HIP device
dist.init_process_group('nccl')  # Uses RCCL on AMD GPUs


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import triton
import triton.language as tl
@triton.jit
def matmul_kernel(a_ptr, b_ptr, c_ptr, M, N, K, BLOCK_M: tl.constexpr, BLOCK_N: tl.constexpr):
    pid = tl.program_id(0)
    # ... kernel body

output:
import triton
import triton.language as tl
# Triton has native AMD GPU support via ROCm backend
@triton.jit
def matmul_kernel(a_ptr, b_ptr, c_ptr, M, N, K, BLOCK_M: tl.constexpr, BLOCK_N: tl.constexpr):
    pid = tl.program_id(0)
    # NOTE: AMD wavefront=64 vs NVIDIA warp=32; tune BLOCK sizes to multiples of 64
    # ... kernel body


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
# nvidia-smi monitoring
import subprocess
result = subprocess.run(['nvidia-smi', '--query-gpu=memory.used,utilization.gpu', '--format=csv'], capture_output=True, text=True)
print(result.stdout)

output:
# rocm-smi monitoring
import subprocess
result = subprocess.run(['rocm-smi', '--showmeminfo', 'vram', '--showuse'], capture_output=True, text=True)
print(result.stdout)
# Alternative: rocm-smi --json for structured output


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
from peft import LoraConfig, get_peft_model, prepare_model_for_kbit_training
model = prepare_model_for_kbit_training(model)
lora_config = LoraConfig(r=16, lora_alpha=32, target_modules=['q_proj', 'v_proj'], lora_dropout=0.05)
model = get_peft_model(model, lora_config)
model.print_trainable_parameters()

output:
import torch
from peft import LoraConfig, get_peft_model, prepare_model_for_kbit_training
# PEFT/LoRA works on ROCm — ensure torch is installed with ROCm wheels
model = prepare_model_for_kbit_training(model)
lora_config = LoraConfig(r=16, lora_alpha=32, target_modules=['q_proj', 'v_proj'], lora_dropout=0.05)
model = get_peft_model(model, lora_config)
model.print_trainable_parameters()  # Runs identically on AMD GPUs


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
# TensorRT optimization
import tensorrt as trt
logger = trt.Logger(trt.Logger.WARNING)
builder = trt.Builder(logger)
network = builder.create_network(1 << int(trt.NetworkDefinitionCreationFlag.EXPLICIT_BATCH))

output:
# MIGraphX optimization (AMD equivalent of TensorRT)
import migraphx
model = migraphx.parse_onnx('model.onnx')
model.compile(migraphx.get_target('gpu'))
# MIGraphX provides graph-level optimization for AMD GPUs
# Export model to ONNX first, then optimize with MIGraphX


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
# Profiling with NVIDIA tools
with torch.cuda.nvtx.range('forward_pass'):
    output = model(input)
with torch.profiler.profile(activities=[torch.profiler.ProfilerActivity.CUDA]) as prof:
    model(input)
print(prof.key_averages().table())

output:
import torch
# Profiling with ROCm tools
# Use rocprof for GPU profiling: rocprof --hip-trace python train.py
with torch.profiler.profile(activities=[torch.profiler.ProfilerActivity.CUDA]) as prof:  # HIP activity
    model(input)
print(prof.key_averages().table())
# Additional: rocprof --stats python script.py for kernel-level stats


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
# Flash Attention (NVIDIA)
from flash_attn import flash_attn_func
output = flash_attn_func(q, k, v, dropout_p=0.1, causal=True)

output:
import torch
# Flash Attention on AMD uses CK (Composable Kernel) backend
# pip install flash-attn --no-build-isolation (ROCm build)
from flash_attn import flash_attn_func
output = flash_attn_func(q, k, v, dropout_p=0.1, causal=True)
# Alternative: Use PyTorch 2.0+ scaled_dot_product_attention which auto-selects CK on AMD


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
export CUDA_VISIBLE_DEVICES=0,1,2,3
export CUDA_HOME=/usr/local/cuda-12.1
export LD_LIBRARY_PATH=$CUDA_HOME/lib64:$LD_LIBRARY_PATH
export NCCL_P2P_DISABLE=0
export NCCL_IB_DISABLE=0

output:
export HIP_VISIBLE_DEVICES=0,1,2,3
export ROCM_HOME=/opt/rocm
export LD_LIBRARY_PATH=$ROCM_HOME/lib:$LD_LIBRARY_PATH
export NCCL_P2P_DISABLE=0  # RCCL uses same env vars
export NCCL_IB_DISABLE=0
export PYTORCH_ROCM_ARCH="gfx90a;gfx942"  # MI250/MI300X targets
export HSA_OVERRIDE_GFX_VERSION=11.0.0


instruction: Migrate the following NVIDIA CUDA Python code to AMD ROCm.

input:
import torch
# Custom CUDA memory management
torch.cuda.set_per_process_memory_fraction(0.8, device=0)
pool = torch.cuda.graph_pool_handle()
with torch.cuda.graph(pool=pool) as g:
    output = model(static_input)

output:
import torch
# ROCm memory management
torch.cuda.set_per_process_memory_fraction(0.8, device=0)  # Works on ROCm
# CUDA Graphs have experimental ROCm support
# Set: export PYTORCH_HIP_ALLOC_CONF=expandable_segments:True
pool = torch.cuda.graph_pool_handle()
with torch.cuda.graph(pool=pool) as g:  # Experimental on ROCm
    output = model(static_input)