import React, { useState, useCallback } from "react"; import Header from "./components/Header"; import Footer from "./components/Footer"; import YAMLForm from "./components/YAMLForm"; import PreviewPanel from "./components/PreviewPanel"; import PipelineRunner from "./components/PipelineRunner"; import ErrorBoundary from "./components/ErrorBoundary"; import { Cpu, FileCode, ShieldCheck, Zap } from "lucide-react"; const FEATURES = [ { icon: Cpu, title: "Full UVM Generation", description: "Complete testbenches with agents, drivers, monitors, scoreboards, and sequences.", }, { icon: FileCode, title: "RAL Model Support", description: "Automatic UVM Register Abstraction Layer generation from YAML register specs.", }, { icon: ShieldCheck, title: "Built-in Verification", description: "Multi-stage verification validates syntax, signals, registers, and coverage.", }, { icon: Zap, title: "Coverage-Driven", description: "Auto-training mode iterates to maximize coverage with targeted sequences.", }, ]; export default function App() { const [spec, setSpec] = useState(null); const handleSpecChange = useCallback((parsed) => { setSpec(parsed); }, []); return (
{/* Hero Section */}
Production Ready v0.3.0

Professional UVM Testbench
Generator

Generate complete, production-grade UVM verification environments from simple YAML specifications. Supports UART, SPI, I2C, AXI4-Lite, APB, and Wishbone protocols out of the box.

{/* Feature badges */}
{["UVM RAL", "Serial Monitors", "Scoreboarding", "Coverage", "Auto-Train"].map((f) => ( {f} ))}
{/* Feature Cards */}
{FEATURES.map((feature, i) => { const Icon = feature.icon; return (

{feature.title}

{feature.description}

); })}
{/* Main Workspace */}
{/* Section header */}

Design Workspace

Configure your spec, preview, and generate

{spec && (
Spec Loaded: {spec.design_name || "unnamed"}
)}
{/* Form + Preview */}
{/* Pipeline */}
); } function CheckCircledDot({ size }) { return ( ); }