vxkyyy commited on
Commit
1878e10
·
1 Parent(s): bf2e089

fix: ensure litellm is installed for LLM backend, .env never overrides HuggingFace secrets, add /ping endpoint

Browse files
benchmark/README.md ADDED
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+ # AgentIC Benchmark Suite
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+
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+ Drop this entire `benchmark/` folder into your AgentIC root directory and run.
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+
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+ ## Quick Start
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+
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+ ```bash
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+ # From AgentIC root directory:
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+
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+ # Run all 10 designs (full pipeline including OpenLane)
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+ python3 benchmark/run_benchmark.py
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+
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+ # Run RTL-only (faster, skips physical flow — good for first pass)
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+ python3 benchmark/run_benchmark.py --skip-openlane
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+
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+ # Run a single design to test
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+ python3 benchmark/run_benchmark.py --design uart_tx
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+
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+ # Use GF180 instead of Sky130
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+ python3 benchmark/run_benchmark.py --pdk gf180
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+
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+ # Run each design 3 times (for statistical reliability)
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+ python3 benchmark/run_benchmark.py --attempts 3
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+ ```
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+
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+ ## What It Produces
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+
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+ After running you get two files in `benchmark/results/`:
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+
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+ - `benchmark_YYYY-MM-DD.md` — human readable report with tables, analysis, bottleneck identification
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+ - `benchmark_YYYY-MM-DD.json` — raw data for programmatic use
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+
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+ Results are also saved after every single build as `interim_YYYY-MM-DD.json`
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+ so you never lose data if a build crashes halfway through.
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+
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+ ## The 10 Test Designs
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+
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+ | # | Design | Complexity | Tests |
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+ |---|--------|-----------|-------|
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+ | 1 | counter_8bit | Simple | Basic sequential logic |
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+ | 2 | uart_tx | Simple | Serial communication |
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+ | 3 | pwm_generator | Simple | Configurable output + registers |
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+ | 4 | spi_master | Simple | SPI protocol state machine |
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+ | 5 | fifo_sync | Simple | Memory + pointer logic |
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+ | 6 | alu_8bit | Medium | Combinational logic, flags |
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+ | 7 | i2c_master | Medium | Complex protocol, open-drain |
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+ | 8 | apb_timer | Medium | APB bus interface + interrupt |
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+ | 9 | vga_controller | Medium | Timing generation, counters |
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+ | 10 | wishbone_uart | Complex | Full bus interface + FIFOs |
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+
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+ ## Which Steps Matter in Industry
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+
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+ | Stage | Matters For | Skip OK? |
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+ |-------|------------|----------|
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+ | RTL_GEN + RTL_FIX | Everything — this is the chip | Never |
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+ | VERIFICATION | Proving functionality | Never |
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+ | HARDENING | Physical layout | Never |
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+ | SIGNOFF | Fab acceptance | Never |
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+ | FORMAL_VERIFY | Safety-critical designs | Simple designs: yes |
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+ | COVERAGE_CHECK | Test completeness | If sim passes: yes |
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+ | REGRESSION | Robustness | Yes |
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+ | ECO_PATCH | Post-signoff fixes | First attempt: yes |
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+ | CONVERGENCE | Timing closure | Simple designs: yes |
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+
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+ **The 4 things a fab actually cares about:**
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+ RTL correctness → Functional simulation → Place & Route → DRC/LVS/STA Signoff
benchmark/results/benchmark_2026-03-06.json ADDED
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benchmark/results/benchmark_2026-03-06.md ADDED
@@ -0,0 +1,53 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # AgentIC Benchmark Report
2
+ **Date:** March 06, 2026
3
+ **PDK:** sky130
4
+ **Model:** NVIDIA NIM — Llama 3.3 70B
5
+ **Mode:** RTL only
6
+
7
+ ## Summary
8
+ | Metric | Value |
9
+ |--------|-------|
10
+ | Total Designs | 10 |
11
+ | **First-Attempt Pass Rate** | **20% (2/10)** |
12
+ | Average Build Time | 5.0 min |
13
+ | RTL Generated (incl. failures) | 10/10 |
14
+ | GDS Generated | 0/10 |
15
+
16
+ ## Results
17
+ | Design | Complexity | Pass? | Failed At | Time | RTL | GDS |
18
+ |--------|-----------|-------|-----------|------|-----|-----|
19
+ | counter8 | Simple | ✓ | — | 5.0 min | ✓ | ✗ |
20
+ | uart_tx | Simple | ✗ | RTL Lint & Syntax Fix | 7.9 min | ✓ | ✗ |
21
+ | pwm_gen | Simple | ✗ | Functional Simulation | 0.5 min | ✓ | ✗ |
22
+ | spi_master | Simple | ✗ | Formal Verification | 1.3 min | ✓ | ✗ |
23
+ | sync_fifo | Simple | ✗ | RTL Lint & Syntax Fix | 2.4 min | ✓ | ✗ |
24
+ | alu8 | Medium | ✗ | Formal Verification | 5.2 min | ✓ | ✗ |
25
+ | i2c_master | Medium | ✗ | — | 9.8 min | ✓ | ✗ |
26
+ | apb_timer | Medium | ✓ | — | 4.2 min | ✓ | ✗ |
27
+ | vga_ctrl | Medium | ✗ | RTL Lint & Syntax Fix | 6.7 min | ✓ | ✗ |
28
+ | wb_uart | Complex | ✗ | RTL Lint & Syntax Fix | 7.0 min | ✓ | ✗ |
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+
30
+ ## Stage Failure Analysis
31
+ | Stage | Industry Name | Failures | Critical? |
32
+ |-------|--------------|----------|-----------|
33
+ | RTL_FIX | RTL Lint & Syntax Fix | 4 | 🔴 Yes |
34
+ | FORMAL_VERIFY | Formal Verification | 2 | 🟡 Optional |
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+ | VERIFICATION | Functional Simulation | 1 | 🔴 Yes |
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+
37
+ **Fix `RTL_FIX` first.**
38
+
39
+ ## Which Stages Matter in Industry
40
+ | Stage | Skip OK? | Why |
41
+ |-------|----------|-----|
42
+ | RTL_GEN + RTL_FIX | ❌ Never | This is the chip |
43
+ | VERIFICATION | ❌ Never | Proves it works |
44
+ | HARDENING | ❌ Never | Physical layout |
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+ | SIGNOFF | ❌ Never | Fab requirement |
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+ | FORMAL_VERIFY | ✅ Simple designs | Optional for non-safety-critical |
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+ | COVERAGE_CHECK | ✅ If sim passes | Nice to have |
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+ | REGRESSION | ✅ Yes | Corner cases only |
49
+ | ECO_PATCH | ✅ First attempt | Only if signoff fails |
50
+ | CONVERGENCE | ✅ Simple designs | Embedded in hardening |
51
+
52
+ ---
53
+ *Generated by AgentIC Benchmark Runner — March 06, 2026*
benchmark/results/interim_2026-03-06.json ADDED
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+ }
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+ }
benchmark/run_benchmark.py ADDED
@@ -0,0 +1,549 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ #!/usr/bin/env python3
2
+ #!/usr/bin/env python3
3
+ """
4
+ AgentIC Benchmark Runner v2
5
+ ============================
6
+ Runs 10 chip designs through the AgentIC pipeline and produces
7
+ a detailed report of real pass/fail rates, stage failures, timing,
8
+ and artifact recovery.
9
+
10
+ Usage (from AgentIC root directory):
11
+ python3 benchmark/run_benchmark.py
12
+ python3 benchmark/run_benchmark.py --skip-openlane
13
+ python3 benchmark/run_benchmark.py --full-signoff
14
+ python3 benchmark/run_benchmark.py --design uart_tx
15
+ python3 benchmark/run_benchmark.py --pdk gf180
16
+ """
17
+
18
+ import os
19
+ import re
20
+ import sys
21
+ import json
22
+ import time
23
+ import argparse
24
+ import datetime
25
+ import subprocess
26
+ from pathlib import Path
27
+
28
+ # ─────────────────────────────────────────────────────────────
29
+ # 10 TEST DESIGNS — simple to complex
30
+ # ─────────────────────────────────────────────────────────────
31
+ TEST_DESIGNS = [
32
+ {
33
+ "id": "counter8",
34
+ "complexity": "Simple",
35
+ "desc": (
36
+ "8-bit synchronous up-counter with active-high synchronous reset and "
37
+ "active-high enable. On every rising clock edge, if reset is high the "
38
+ "counter clears to zero. If enable is high and reset is low, the counter "
39
+ "increments by one. When it reaches 255 it wraps to zero. Output the 8-bit count."
40
+ ),
41
+ },
42
+ {
43
+ "id": "uart_tx",
44
+ "complexity": "Simple",
45
+ "desc": (
46
+ "UART transmitter at 115200 baud, 8N1 format. Accepts parallel 8-bit data "
47
+ "and a start signal. Outputs a serial TX line. 50 MHz system clock. "
48
+ "Signals transmission complete via a done flag. Idle state is logic high."
49
+ ),
50
+ },
51
+ {
52
+ "id": "pwm_gen",
53
+ "complexity": "Simple",
54
+ "desc": (
55
+ "PWM generator with a 16-bit period register and 16-bit duty cycle register, "
56
+ "both writable via a simple register interface with address and write-enable. "
57
+ "Outputs a single PWM signal. 50 MHz clock. Edge-aligned mode."
58
+ ),
59
+ },
60
+ {
61
+ "id": "spi_master",
62
+ "complexity": "Simple",
63
+ "desc": (
64
+ "SPI master controller, mode 0 only (CPOL=0 CPHA=0). 8-bit transfers. "
65
+ "Generates SCLK, MOSI, CS. Accepts MISO. Clock divider to set SPI speed "
66
+ "from 50 MHz system clock. Busy and done status signals."
67
+ ),
68
+ },
69
+ {
70
+ "id": "sync_fifo",
71
+ "complexity": "Simple",
72
+ "desc": (
73
+ "Synchronous FIFO, 8-bit data width, 16-entry depth, single clock domain. "
74
+ "Push and pop with full and empty flags. Almost-full flag when 2 or fewer "
75
+ "slots remain. Almost-empty flag when 2 or fewer entries stored."
76
+ ),
77
+ },
78
+ {
79
+ "id": "alu8",
80
+ "complexity": "Medium",
81
+ "desc": (
82
+ "8-bit ALU with 4-bit opcode selecting: ADD, SUB, AND, OR, XOR, NOT, "
83
+ "left shift by 1, right shift by 1, increment, decrement. Outputs 8-bit "
84
+ "result and 4-bit flags: zero, carry, overflow, negative. Fully combinational."
85
+ ),
86
+ },
87
+ {
88
+ "id": "i2c_master",
89
+ "complexity": "Medium",
90
+ "desc": (
91
+ "I2C master controller, standard mode 100 kHz. Generates SCL and SDA with "
92
+ "open-drain outputs. 7-bit addressing. Handles START, STOP conditions. "
93
+ "ACK/NACK detection. Register interface for address, data, read/write, "
94
+ "start trigger. Busy, done, error status. 50 MHz system clock."
95
+ ),
96
+ },
97
+ {
98
+ "id": "apb_timer",
99
+ "complexity": "Medium",
100
+ "desc": (
101
+ "32-bit APB timer peripheral with interrupt. APB3 slave interface with "
102
+ "PCLK, PRESETn, PSEL, PENABLE, PWRITE, PADDR, PWDATA, PRDATA, PREADY. "
103
+ "Registers: control, prescaler, reload value, current count, interrupt status. "
104
+ "Supports one-shot and continuous modes. Interrupt when counter reaches zero. "
105
+ "Prescaler divides clock 1 to 65536."
106
+ ),
107
+ },
108
+ {
109
+ "id": "vga_ctrl",
110
+ "complexity": "Medium",
111
+ "desc": (
112
+ "VGA timing controller for 640x480 at 60 Hz. Generates HSYNC and VSYNC "
113
+ "with correct timing. Outputs current pixel X and Y coordinates and "
114
+ "active video enable signal. Pixel clock input at 25 MHz."
115
+ ),
116
+ },
117
+ {
118
+ "id": "wb_uart",
119
+ "complexity": "Complex",
120
+ "desc": (
121
+ "UART transceiver with Wishbone B4 slave interface. 8N1 format. "
122
+ "Configurable baud rate via baud divisor register. 16-byte TX FIFO and "
123
+ "16-byte RX FIFO. Wishbone registers: TX data, RX data, status "
124
+ "(TX full, TX empty, RX full, RX empty, overrun), control (baud divisor, "
125
+ "loopback enable), interrupt enable. Interrupt on RX available and TX empty. "
126
+ "50 MHz clock. Wishbone signals: CLK_I RST_I ADR_I DAT_I DAT_O WE_I STB_I ACK_O CYC_I."
127
+ ),
128
+ },
129
+ ]
130
+
131
+ # ─────────────────────────────────────────────────────────────
132
+ # STAGE METADATA
133
+ # ─────────────────────────────────────────────────────────────
134
+ STAGE_INFO = {
135
+ "INIT": {"name": "Environment Setup", "critical": True},
136
+ "SPEC": {"name": "Architectural Planning", "critical": True},
137
+ "RTL_GEN": {"name": "RTL Generation", "critical": True},
138
+ "RTL_FIX": {"name": "RTL Lint & Syntax Fix", "critical": True},
139
+ "VERIFICATION": {"name": "Functional Simulation", "critical": True},
140
+ "FORMAL_VERIFY": {"name": "Formal Verification", "critical": False},
141
+ "COVERAGE_CHECK": {"name": "Coverage Closure", "critical": False},
142
+ "REGRESSION": {"name": "Regression Testing", "critical": False},
143
+ "SDC_GEN": {"name": "Timing Constraints", "critical": True},
144
+ "FLOORPLAN": {"name": "Physical Floorplanning", "critical": True},
145
+ "HARDENING": {"name": "Place & Route", "critical": True},
146
+ "CONVERGENCE": {"name": "Timing Convergence", "critical": True},
147
+ "ECO_PATCH": {"name": "Engineering Change Order", "critical": False},
148
+ "SIGNOFF": {"name": "DRC/LVS/STA Signoff", "critical": True},
149
+ }
150
+
151
+ SUCCESS_MARKERS = [
152
+ "PIPELINE COMPLETE", "BUILD COMPLETE", "ALL STAGES PASSED",
153
+ "SIGNOFF PASSED", "BUILD SUCCEEDED", "SUCCESS",
154
+ ]
155
+ FAILURE_MARKERS = [
156
+ "PIPELINE FAILED", "BUILD FAILED", "FATAL ERROR",
157
+ "STAGE FAILED", "ABORTING", "FAIL-CLOSED",
158
+ ]
159
+
160
+ STAGE_PATTERN = re.compile(
161
+ r"\b(INIT|SPEC|RTL_GEN|RTL_FIX|VERIFICATION|FORMAL_VERIFY|"
162
+ r"COVERAGE_CHECK|REGRESSION|SDC_GEN|FLOORPLAN|HARDENING|"
163
+ r"CONVERGENCE|ECO_PATCH|SIGNOFF)\b",
164
+ re.IGNORECASE,
165
+ )
166
+
167
+
168
+ def parse_args():
169
+ p = argparse.ArgumentParser(description="AgentIC Benchmark Runner v2")
170
+ p.add_argument("--pdk", default="sky130", choices=["sky130", "gf180"])
171
+ p.add_argument("--skip-openlane", action="store_true")
172
+ p.add_argument("--skip-coverage", action="store_true")
173
+ p.add_argument("--full-signoff", action="store_true")
174
+ p.add_argument("--design", default=None)
175
+ p.add_argument("--max-retries", default=3, type=int)
176
+ p.add_argument("--output-dir", default="benchmark/results")
177
+ p.add_argument("--attempts", default=1, type=int)
178
+ p.add_argument("--timeout", default=3600, type=int)
179
+ return p.parse_args()
180
+
181
+
182
+ def build_command(design, args):
183
+ cmd = [
184
+ "python3", "main.py", "build",
185
+ "--name", design["id"],
186
+ "--desc", design["desc"],
187
+ "--pdk-profile", args.pdk,
188
+ "--max-retries", str(args.max_retries),
189
+ "--strict-gates",
190
+ ]
191
+ if args.skip_openlane:
192
+ cmd.append("--skip-openlane")
193
+ if args.skip_coverage:
194
+ cmd.append("--skip-coverage")
195
+ if args.full_signoff:
196
+ cmd.append("--full-signoff")
197
+ return cmd
198
+
199
+
200
+ def detect_pass_fail(stdout, stderr, returncode):
201
+ combined = (stdout + stderr).upper()
202
+ for marker in FAILURE_MARKERS:
203
+ if marker in combined:
204
+ return False
205
+ for marker in SUCCESS_MARKERS:
206
+ if marker in combined:
207
+ return True
208
+ return returncode == 0
209
+
210
+
211
+ def extract_failed_stage(stdout, stderr):
212
+ combined = stdout + stderr
213
+ last_stage = None
214
+ for line in combined.split("\n"):
215
+ m = STAGE_PATTERN.search(line)
216
+ if m:
217
+ last_stage = m.group(1).upper()
218
+ if any(kw in line.upper() for kw in ["FAILED", "ERROR", "FATAL", "ABORT", "FAIL-CLOSED"]):
219
+ return last_stage, line.strip()[:250]
220
+ return None, None
221
+
222
+
223
+ def extract_completed_stages(stdout):
224
+ completed = []
225
+ for line in stdout.split("\n"):
226
+ m = STAGE_PATTERN.search(line)
227
+ if m:
228
+ stage = m.group(1).upper()
229
+ if any(kw in line.upper() for kw in [
230
+ "COMPLETE", "PASSED", "SUCCESS", "DONE", "TRANSITION", "FINISHED"
231
+ ]):
232
+ if stage not in completed:
233
+ completed.append(stage)
234
+ return completed
235
+
236
+
237
+ def find_openlane_root():
238
+ env = os.environ.get("OPENLANE_ROOT")
239
+ if env and Path(env).exists():
240
+ return env
241
+ for c in [Path.home() / "OpenLane", Path("/opt/OpenLane")]:
242
+ if c.exists():
243
+ return str(c)
244
+ return str(Path.home() / "OpenLane")
245
+
246
+
247
+ def find_artifacts(design_id, openlane_root):
248
+ """Only find files actually belonging to THIS design — no false positives."""
249
+ found = {}
250
+ type_map = {
251
+ ".v": "RTL", ".sv": "RTL", ".sva": "FORMAL", ".sby": "FORMAL",
252
+ ".sdc": "TIMING", ".tcl": "PHYSICAL", ".lef": "PHYSICAL",
253
+ ".def": "PHYSICAL", ".gds": "PHYSICAL", ".json": "CONFIG",
254
+ ".log": "LOG", ".rpt": "SIGNOFF",
255
+ }
256
+ scan_dirs = [
257
+ Path(f"outputs/{design_id}"),
258
+ Path(f"results/{design_id}"),
259
+ Path(f"designs/{design_id}"),
260
+ Path(openlane_root) / "designs" / design_id,
261
+ ]
262
+ for d in scan_dirs:
263
+ if not d.exists():
264
+ continue
265
+ for f in d.rglob("*"):
266
+ if not f.is_file():
267
+ continue
268
+ # STRICT: only files where design_id is in filename OR direct parent folder
269
+ in_name = design_id.lower() in f.name.lower()
270
+ in_parent = design_id.lower() in f.parent.name.lower()
271
+ if not (in_name or in_parent):
272
+ continue
273
+ atype = type_map.get(f.suffix.lower())
274
+ if not atype:
275
+ continue
276
+ if atype == "RTL" and "_tb" in f.name.lower():
277
+ atype = "TESTBENCH"
278
+ if atype not in found:
279
+ found[atype] = []
280
+ sz = f.stat().st_size
281
+ found[atype].append({
282
+ "file": f.name,
283
+ "path": str(f),
284
+ "size_bytes": sz,
285
+ "size_human": fmt_size(sz),
286
+ })
287
+ return found
288
+
289
+
290
+ def fmt_size(b):
291
+ if b < 1024: return f"{b} B"
292
+ elif b < 1048576: return f"{b/1024:.1f} KB"
293
+ else: return f"{b/1048576:.1f} MB"
294
+
295
+
296
+ def run_build(design, args, attempt):
297
+ openlane_root = find_openlane_root()
298
+ cmd = build_command(design, args)
299
+ timestamp = datetime.datetime.now().isoformat()
300
+
301
+ print(f"\n{'─'*60}")
302
+ print(f" Design : {design['id']} ({design['complexity']})")
303
+ print(f" Attempt : {attempt}")
304
+ print(f" PDK : {args.pdk}")
305
+ print(f" Command : {' '.join(cmd[:6])} ...")
306
+ print(f"{'─'*60}")
307
+
308
+ start = time.time()
309
+ try:
310
+ proc = subprocess.run(cmd, capture_output=True, text=True, timeout=args.timeout)
311
+ stdout, stderr, retcode = proc.stdout, proc.stderr, proc.returncode
312
+ except subprocess.TimeoutExpired:
313
+ dur = round((time.time() - start) / 60, 1)
314
+ print(f" Result : ✗ TIMEOUT ({dur} min)")
315
+ return make_result(design, attempt, args, False, "TIMEOUT",
316
+ f"Exceeded {args.timeout}s timeout", [], {}, dur, timestamp, True)
317
+ except FileNotFoundError:
318
+ print("ERROR: main.py not found. Run from AgentIC root.")
319
+ sys.exit(1)
320
+
321
+ dur = round((time.time() - start) / 60, 1)
322
+ passed = detect_pass_fail(stdout, stderr, retcode)
323
+
324
+ # Sanity check — real builds never finish in under 2 minutes
325
+ # BUT only apply this if no real stages completed (otherwise it was a real fast failure)
326
+ completed = extract_completed_stages(stdout)
327
+ if dur < 2.0 and len(completed) <= 1:
328
+ print(f" ⚠ WARNING: Finished in {dur} min with no meaningful progress.")
329
+ print(f" ⚠ Check that your CLI args match and the orchestrator actually ran.")
330
+ passed = False
331
+ failed_stage = "INIT"
332
+ failed_reason = f"Build exited in {dur} min with ≤1 stage — CLI args may be wrong."
333
+ elif dur < 2.0:
334
+ # Build ran real stages but failed fast — use real failure data
335
+ print(f" ⚠ NOTE: Build completed in {dur} min (fast failure after {len(completed)} stages).")
336
+ failed_stage, failed_reason = (None, None) if passed else extract_failed_stage(stdout, stderr)
337
+ else:
338
+ failed_stage, failed_reason = (None, None) if passed else extract_failed_stage(stdout, stderr)
339
+
340
+
341
+ artifacts = find_artifacts(design["id"], openlane_root)
342
+
343
+ status = "✓ PASS" if passed else "✗ FAIL"
344
+ fail_info = ""
345
+ if failed_stage:
346
+ name = STAGE_INFO.get(failed_stage, {}).get("name", failed_stage)
347
+ fail_info = f" — failed at {failed_stage} ({name})"
348
+
349
+ print(f" Result : {status}{fail_info}")
350
+ print(f" Time : {dur} min")
351
+ print(f" Stages : {len(completed)} completed")
352
+ print(f" Artifacts: {', '.join(artifacts.keys()) if artifacts else 'none found for this design'}")
353
+
354
+ return make_result(design, attempt, args, passed, failed_stage,
355
+ failed_reason, completed, artifacts, dur, timestamp)
356
+
357
+
358
+ def make_result(design, attempt, args, passed, failed_stage, failed_reason,
359
+ completed, artifacts, duration, timestamp, timed_out=False):
360
+ info = STAGE_INFO.get(failed_stage, {}) if failed_stage else {}
361
+ return {
362
+ "design_id": design["id"],
363
+ "complexity": design["complexity"],
364
+ "attempt": attempt,
365
+ "passed": passed,
366
+ "timed_out": timed_out,
367
+ "failed_stage": failed_stage,
368
+ "failed_stage_name": info.get("name"),
369
+ "failed_stage_critical": info.get("critical"),
370
+ "failed_reason": failed_reason,
371
+ "completed_stages": completed,
372
+ "completed_stages_count": len(completed),
373
+ "artifacts": artifacts,
374
+ "artifact_types": list(artifacts.keys()),
375
+ "rtl_generated": "RTL" in artifacts,
376
+ "testbench_generated": "TESTBENCH" in artifacts,
377
+ "gds_generated": "PHYSICAL" in artifacts,
378
+ "duration_minutes": duration,
379
+ "timestamp": timestamp,
380
+ "pdk": args.pdk,
381
+ }
382
+
383
+
384
+ def print_summary(results):
385
+ passed = [r for r in results if r["passed"]]
386
+ failed = [r for r in results if not r["passed"]]
387
+ rate = len(passed) / len(results) * 100 if results else 0
388
+ avg = sum(r["duration_minutes"] for r in results) / len(results)
389
+ fails = {}
390
+ for r in failed:
391
+ s = r.get("failed_stage")
392
+ if s: fails[s] = fails.get(s, 0) + 1
393
+
394
+ print(f"\n{'═'*60}")
395
+ print(f" BENCHMARK COMPLETE")
396
+ print(f"{'═'*60}")
397
+ print(f" Pass Rate : {rate:.0f}% ({len(passed)}/{len(results)})")
398
+ print(f" Avg Time : {avg:.1f} min")
399
+ print(f"{'─'*60}")
400
+ for r in passed:
401
+ print(f" ✓ {r['design_id']:<22} {r['duration_minutes']} min")
402
+ for r in failed:
403
+ at = r.get("failed_stage_name") or r.get("failed_stage") or "unknown"
404
+ print(f" ✗ {r['design_id']:<22} failed at {at}")
405
+ if fails:
406
+ worst = max(fails, key=fails.get)
407
+ name = STAGE_INFO.get(worst, {}).get("name", worst)
408
+ print(f"\n ⚠ Bottleneck: {worst} ({name}) — fix this first")
409
+ print(f"{'═'*60}\n")
410
+
411
+
412
+ def generate_markdown(results, args):
413
+ today = datetime.date.today().strftime("%B %d, %Y")
414
+ passed = [r for r in results if r["passed"]]
415
+ failed = [r for r in results if not r["passed"]]
416
+ rate = len(passed) / len(results) * 100 if results else 0
417
+ avg = sum(r["duration_minutes"] for r in results) / len(results)
418
+ fails = {}
419
+ for r in failed:
420
+ s = r.get("failed_stage")
421
+ if s: fails[s] = fails.get(s, 0) + 1
422
+
423
+ L = [
424
+ f"# AgentIC Benchmark Report",
425
+ f"**Date:** {today} ",
426
+ f"**PDK:** {args.pdk} ",
427
+ f"**Model:** NVIDIA NIM — Llama 3.3 70B ",
428
+ f"**Mode:** {'RTL only' if args.skip_openlane else 'Full pipeline'}",
429
+ "",
430
+ "## Summary",
431
+ "| Metric | Value |",
432
+ "|--------|-------|",
433
+ f"| Total Designs | {len(results)} |",
434
+ f"| **First-Attempt Pass Rate** | **{rate:.0f}% ({len(passed)}/{len(results)})** |",
435
+ f"| Average Build Time | {avg:.1f} min |",
436
+ f"| RTL Generated (incl. failures) | {sum(1 for r in results if r.get('rtl_generated'))}/{len(results)} |",
437
+ f"| GDS Generated | {sum(1 for r in results if r.get('gds_generated'))}/{len(results)} |",
438
+ "",
439
+ "## Results",
440
+ "| Design | Complexity | Pass? | Failed At | Time | RTL | GDS |",
441
+ "|--------|-----------|-------|-----------|------|-----|-----|",
442
+ ]
443
+ for r in results:
444
+ s = "✓" if r["passed"] else "✗"
445
+ f = r.get("failed_stage_name") or r.get("failed_stage") or "—"
446
+ L.append(f"| {r['design_id']} | {r['complexity']} | {s} | {f} | {r['duration_minutes']} min | {'✓' if r.get('rtl_generated') else '✗'} | {'✓' if r.get('gds_generated') else '✗'} |")
447
+
448
+ if fails:
449
+ L += ["", "## Stage Failure Analysis",
450
+ "| Stage | Industry Name | Failures | Critical? |",
451
+ "|-------|--------------|----------|-----------|"]
452
+ for stage, count in sorted(fails.items(), key=lambda x: -x[1]):
453
+ info = STAGE_INFO.get(stage, {})
454
+ L.append(f"| {stage} | {info.get('name', stage)} | {count} | {'🔴 Yes' if info.get('critical') else '🟡 Optional'} |")
455
+ worst = max(fails, key=fails.get)
456
+ L += ["", f"**Fix `{worst}` first.**"]
457
+
458
+ L += [
459
+ "", "## Which Stages Matter in Industry",
460
+ "| Stage | Skip OK? | Why |",
461
+ "|-------|----------|-----|",
462
+ "| RTL_GEN + RTL_FIX | ❌ Never | This is the chip |",
463
+ "| VERIFICATION | ❌ Never | Proves it works |",
464
+ "| HARDENING | ❌ Never | Physical layout |",
465
+ "| SIGNOFF | ❌ Never | Fab requirement |",
466
+ "| FORMAL_VERIFY | ✅ Simple designs | Optional for non-safety-critical |",
467
+ "| COVERAGE_CHECK | ✅ If sim passes | Nice to have |",
468
+ "| REGRESSION | ✅ Yes | Corner cases only |",
469
+ "| ECO_PATCH | ✅ First attempt | Only if signoff fails |",
470
+ "| CONVERGENCE | ✅ Simple designs | Embedded in hardening |",
471
+ "", "---",
472
+ f"*Generated by AgentIC Benchmark Runner — {today}*",
473
+ ]
474
+ return "\n".join(L)
475
+
476
+
477
+ def main():
478
+ args = parse_args()
479
+
480
+ if not Path("main.py").exists():
481
+ print("ERROR: Run from AgentIC root directory (where main.py is).")
482
+ sys.exit(1)
483
+
484
+ output_dir = Path(args.output_dir)
485
+ output_dir.mkdir(parents=True, exist_ok=True)
486
+
487
+ designs = TEST_DESIGNS
488
+ if args.design:
489
+ designs = [d for d in TEST_DESIGNS if d["id"] == args.design]
490
+ if not designs:
491
+ print(f"ERROR: '{args.design}' not found.")
492
+ print(f"Available IDs: {[d['id'] for d in TEST_DESIGNS]}")
493
+ sys.exit(1)
494
+
495
+ total = len(designs) * args.attempts
496
+ est_mins = total * 25
497
+
498
+ print(f"\n{'═'*60}")
499
+ print(f" AgentIC Benchmark Runner v2")
500
+ print(f"{'═'*60}")
501
+ print(f" Designs : {len(designs)}")
502
+ print(f" Total runs: {total}")
503
+ print(f" PDK : {args.pdk}")
504
+ mode_parts = []
505
+ if args.skip_openlane:
506
+ mode_parts.append("RTL only (--skip-openlane)")
507
+ else:
508
+ mode_parts.append("Full pipeline")
509
+ if args.skip_coverage:
510
+ mode_parts.append("skip coverage (--skip-coverage)")
511
+ print(f" Mode : {', '.join(mode_parts)}")
512
+ print(f" Est. time : ~{est_mins} min")
513
+ print(f" Output : {output_dir}/")
514
+ print(f"{'═'*60}\n")
515
+
516
+ all_results = []
517
+ date_str = datetime.date.today().strftime("%Y-%m-%d")
518
+
519
+ for design in designs:
520
+ for attempt in range(1, args.attempts + 1):
521
+ result = run_build(design, args, attempt)
522
+ all_results.append(result)
523
+ # Save after every build
524
+ with open(output_dir / f"interim_{date_str}.json", "w") as f:
525
+ json.dump({"results": all_results}, f, indent=2)
526
+
527
+ # Final saves
528
+ with open(output_dir / f"benchmark_{date_str}.json", "w") as f:
529
+ json.dump({
530
+ "meta": {
531
+ "date": date_str, "pdk": args.pdk,
532
+ "pass_rate_pct": round(
533
+ len([r for r in all_results if r["passed"]]) / len(all_results) * 100, 1
534
+ )
535
+ },
536
+ "results": all_results
537
+ }, f, indent=2)
538
+
539
+ md_path = output_dir / f"benchmark_{date_str}.md"
540
+ with open(md_path, "w") as f:
541
+ f.write(generate_markdown(all_results, args))
542
+
543
+ print_summary(all_results)
544
+ print(f" Saved: {md_path}")
545
+ print(f" Saved: {output_dir}/benchmark_{date_str}.json\n")
546
+
547
+
548
+ if __name__ == "__main__":
549
+ main()
docs/IP_SAFETY_AND_EXPANSION.md ADDED
@@ -0,0 +1,146 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # AgentIC — IP Safety, Data Privacy & Expansion Plan
2
+
3
+ ## 1. Is Your IP Secure?
4
+
5
+ **Short answer: Yes, by design — with caveats to understand.**
6
+
7
+ Your chip designs (RTL, specs, build prompts) pass through external LLM APIs during the build. Here is precisely what leaves the system and what never does.
8
+
9
+ ---
10
+
11
+ ## 2. What Data Leaves AgentIC
12
+
13
+ | Data | Where it goes | Can you control it? |
14
+ |---|---|---|
15
+ | Design description + RTL prompts | NVIDIA NIM API (`integrate.api.nvidia.com`) | Yes — route to local Ollama instead |
16
+ | Spec + RTL during agent reasoning | Same NVIDIA endpoint | Yes — BYOK plan lets you use your own hosted API |
17
+ | Build logs | Stays on server only | N/A — never sent externally |
18
+ | VCD waveforms | Stays on server only | N/A |
19
+ | GDS layout files | Stays on server only | N/A |
20
+ | Training JSONL export | Stays on local disk (`training/agentic_sft_data.jsonl`) | N/A — never uploaded |
21
+ | API keys | HuggingFace Space Secrets (encrypted at rest by HF) | Yes — rotate at any time |
22
+ | User profiles + build counts | Supabase (only when auth is enabled) | Yes — opt-in, use your own Supabase project |
23
+
24
+ **Nothing is ever sold, shared, or used to train third-party models.** The training JSONL is written locally on your machine or HF Space persistent storage — it stays yours.
25
+
26
+ ---
27
+
28
+ ## 3. The LLM API Risk — And How to Eliminate It
29
+
30
+ When a user submits `"Design a 32-bit RISC-V processor with branch prediction"`, that prompt goes to NVIDIA's inference endpoint. NVIDIA's [API Terms of Service](https://www.nvidia.com/en-us/agreements/enterprise-software/nvidia-api-trial-terms-of-service/) state they do not use API inputs to train their models.
31
+
32
+ **If your design is confidential, use the BYOK plan:**
33
+ - Set `plan = byok` for your account in Supabase
34
+ - Store your own API key (pointing to a **self-hosted** vLLM/Ollama endpoint)
35
+ - The build runs entirely on-premises — nothing leaves your network
36
+
37
+ **Self-hosted LLM options (zero data egress):**
38
+ ```
39
+ # Ollama — local GPU inference
40
+ LLM_BASE_URL=http://localhost:11434
41
+ LLM_MODEL=ollama/llama3.3:70b
42
+
43
+ # vLLM on your own server
44
+ LLM_BASE_URL=http://YOUR_SERVER:8000/v1
45
+ LLM_MODEL=meta-llama/Llama-3.3-70B-Instruct
46
+ ```
47
+
48
+ ---
49
+
50
+ ## 4. What Stays Completely Private
51
+
52
+ These never leave the system under any configuration:
53
+
54
+ - **EDA tool execution** — `iverilog`, `verilator`, `yosys`, `sby` run 100% locally
55
+ - **VCD simulation waveforms** — generated and stored locally
56
+ - **GDS chip layouts** — OpenLane output, stays on disk
57
+ - **Training JSONL** — local fine-tuning data, never uploaded
58
+ - **Build logs** — streamed to your browser via SSE, never stored externally
59
+ - **Supabase data** — your own Supabase project, your data
60
+
61
+ ---
62
+
63
+ ## 5. Expansion Plan
64
+
65
+ ### Phase 1 — Platform Foundation (Current)
66
+ - [x] Multi-agent RTL build pipeline (RTL → Verification → Formal → Coverage → GDSII)
67
+ - [x] Human-in-the-loop approval at each stage
68
+ - [x] Supabase auth + plan tiers (Free / Starter / Pro / BYOK)
69
+ - [x] Razorpay billing with webhook verification
70
+ - [x] HuggingFace Spaces deployment (Docker)
71
+ - [x] Training data export pipeline (local JSONL)
72
+
73
+ ### Phase 2 — Scale & Monetize (Q1 2026)
74
+ - [ ] **Frontend auth UI** — login/signup pages using Supabase Auth JS SDK
75
+ - [ ] **Pricing page** — Razorpay checkout integration in React
76
+ - [ ] **User dashboard** — build history, plan status, upgrade prompts
77
+ - [ ] **BYOK key management UI** — set/update encrypted API key from browser
78
+ - [ ] **Team accounts** — shared plan, shared build quota
79
+
80
+ ### Phase 3 — IP Hardening (Q2 2026)
81
+ - [ ] **On-premise mode** — single Docker Compose stack with bundled local LLM (Ollama)
82
+ - [ ] **Air-gapped deployment guide** — no internet required, all EDA tools + LLM in one stack
83
+ - [ ] **Design vault** — encrypted storage for completed RTL/GDS with per-user S3-compatible bucket
84
+ - [ ] **Differential privacy** on training export — strip user identifiers from JSONL before fine-tuning
85
+ - [ ] **Audit log** — every API call that contains design data is logged with timestamp + user
86
+
87
+ ### Phase 4 — Enterprise (Q3 2026)
88
+ - [ ] **SSO** — SAML/OIDC via Supabase (works with Google Workspace, Okta)
89
+ - [ ] **NDA-grade deployment** — dedicated HF Space per enterprise tenant with isolated secrets
90
+ - [ ] **Custom PDK support** — bring your own standard cell library without submitting it to any cloud
91
+ - [ ] **Multi-project wafer slot reservation** — integration with Efabless / Skywater shuttle APIs
92
+ - [ ] **SLA agreement** — 99.9% uptime on HF Pro+ hardware (A10G GPU)
93
+
94
+ ---
95
+
96
+ ## 6. Security Architecture Summary
97
+
98
+ ```
99
+ User Browser
100
+
101
+ │ HTTPS (TLS 1.3)
102
+
103
+ HuggingFace Space (Docker container)
104
+
105
+ ├── FastAPI (server/api.py)
106
+ │ ├── Supabase JWT verification ← user never sees DB directly
107
+ │ ├── Plan guard (402 on limit)
108
+ │ └── BYOK key decrypt ← key never logged
109
+
110
+ ├── LLM call ─��────────────────────► NVIDIA NIM API (or your private endpoint)
111
+ │ └── Design prompt goes here ← only this crosses the boundary
112
+
113
+ ├── EDA tools (iverilog, yosys, sby) ← 100% local, no network calls
114
+
115
+ └── Build artifacts → local disk
116
+ training/agentic_sft_data.jsonl ← yours only
117
+
118
+ Supabase (your project)
119
+ ├── profiles (plan, build count, encrypted BYOK key)
120
+ ├── builds (job history)
121
+ └── payments (Razorpay records)
122
+ ```
123
+
124
+ ---
125
+
126
+ ## 7. Secrets You Control
127
+
128
+ | Secret | Stored where | How to rotate |
129
+ |---|---|---|
130
+ | `NVIDIA_API_KEY` | HF Space Secrets + local `.env` | NVIDIA dashboard → regenerate |
131
+ | `SUPABASE_SERVICE_KEY` | HF Space Secrets only | Supabase → Settings → API |
132
+ | `ENCRYPTION_KEY` | HF Space Secrets only | Change + re-encrypt stored BYOK keys |
133
+ | `RAZORPAY_KEY_SECRET` | HF Space Secrets only | Razorpay dashboard |
134
+ | `HF_TOKEN` | GitHub Actions Secrets | HuggingFace → Settings → Tokens |
135
+
136
+ **Rotate all keys immediately if:**
137
+ - A key appears in any public log, PR, or error message
138
+ - You suspect unauthorized use
139
+ - Any team member with access leaves
140
+
141
+ To update HF Space secrets programmatically:
142
+ ```python
143
+ from huggingface_hub import HfApi
144
+ api = HfApi(token="your_new_hf_token")
145
+ api.add_space_secret("vxkyyy/AgentIC", "NVIDIA_API_KEY", "new_value")
146
+ ```
metircs/apb_timer/apb_timer_industry_benchmark_20260306_020245.json ADDED
@@ -0,0 +1,80 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ {
2
+ "design_name": "apb_timer",
3
+ "generated_at_epoch": 1772742765,
4
+ "build_status": "SUCCESS",
5
+ "signoff_result": "UNKNOWN",
6
+ "pdk_profile": "sky130",
7
+ "pdk": "sky130A",
8
+ "std_cell_library": "sky130_fd_sc_hd",
9
+ "verification_metadata": {
10
+ "tb_gate_mode": "strict",
11
+ "tb_max_retries": 3,
12
+ "tb_fallback_template": "uvm_lite",
13
+ "tb_static_fail_count": 0,
14
+ "tb_compile_fail_count": 0,
15
+ "tb_repair_fail_count": 0,
16
+ "tb_gate_history_count": 1,
17
+ "tb_gate_history": [
18
+ {
19
+ "timestamp": 1772742645,
20
+ "gate": "compile",
21
+ "ok": true,
22
+ "action": "gate_pass",
23
+ "issue_categories": [
24
+ "compile_ok"
25
+ ],
26
+ "fingerprint": "f0eae3025ab704df"
27
+ }
28
+ ],
29
+ "coverage_backend": "auto",
30
+ "coverage_fallback_policy": "fallback_oss",
31
+ "coverage_profile": "balanced",
32
+ "coverage_thresholds": {
33
+ "line": 85.0,
34
+ "branch": 80.0,
35
+ "toggle": 75.0,
36
+ "functional": 80.0
37
+ },
38
+ "coverage_mode": "unknown",
39
+ "coverage_error_kind": "",
40
+ "coverage_diag_path": "",
41
+ "coverage_threshold_pass": {
42
+ "line": false,
43
+ "branch": false,
44
+ "toggle": false,
45
+ "functional": false
46
+ }
47
+ },
48
+ "industry_benchmark": {
49
+ "area_um2": 0.0,
50
+ "cell_count": 0.0,
51
+ "utilization_pct": 0.0,
52
+ "timing_wns_ns": 0.0,
53
+ "timing_tns_ns": 0.0,
54
+ "hold_slack_ns": 0.0,
55
+ "drc_violations": -1,
56
+ "lvs_errors": -1,
57
+ "antenna_violations": -1,
58
+ "total_power_mw": 0.0,
59
+ "internal_power_mw": 0.0,
60
+ "switching_power_mw": 0.0,
61
+ "leakage_power_uw": 0.0,
62
+ "irdrop_vpwr_mv": 0.0,
63
+ "irdrop_vgnd_mv": 0.0,
64
+ "congestion_usage_pct": 0.0,
65
+ "congestion_overflow": 0,
66
+ "coverage_line_pct": 0.0,
67
+ "coverage_branch_pct": 0.0,
68
+ "coverage_toggle_pct": 0.0,
69
+ "coverage_functional_pct": 0.0,
70
+ "coverage_backend": "auto",
71
+ "coverage_mode": "unknown",
72
+ "formal_result": "PASS",
73
+ "lec_result": "UNKNOWN",
74
+ "regression_passed": 0,
75
+ "regression_total": 0,
76
+ "clock_period_ns": "10.0",
77
+ "pivots_used": 0,
78
+ "global_steps": 7
79
+ }
80
+ }
metircs/apb_timer/apb_timer_industry_benchmark_20260306_020245.md ADDED
@@ -0,0 +1,39 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # apb_timer Industry Benchmark Metrics
2
+
3
+ - Generated At (epoch): `1772742765`
4
+ - Build Status: `SUCCESS`
5
+ - Signoff Result: `UNKNOWN`
6
+ - PDK Profile: `sky130`
7
+
8
+ | Metric | Value |
9
+ |---|---|
10
+ | `area_um2` | `0.0` |
11
+ | `cell_count` | `0.0` |
12
+ | `utilization_pct` | `0.0` |
13
+ | `timing_wns_ns` | `0.0` |
14
+ | `timing_tns_ns` | `0.0` |
15
+ | `hold_slack_ns` | `0.0` |
16
+ | `drc_violations` | `-1` |
17
+ | `lvs_errors` | `-1` |
18
+ | `antenna_violations` | `-1` |
19
+ | `total_power_mw` | `0.0` |
20
+ | `internal_power_mw` | `0.0` |
21
+ | `switching_power_mw` | `0.0` |
22
+ | `leakage_power_uw` | `0.0` |
23
+ | `irdrop_vpwr_mv` | `0.0` |
24
+ | `irdrop_vgnd_mv` | `0.0` |
25
+ | `congestion_usage_pct` | `0.0` |
26
+ | `congestion_overflow` | `0` |
27
+ | `coverage_line_pct` | `0.0` |
28
+ | `coverage_branch_pct` | `0.0` |
29
+ | `coverage_toggle_pct` | `0.0` |
30
+ | `coverage_functional_pct` | `0.0` |
31
+ | `coverage_backend` | `auto` |
32
+ | `coverage_mode` | `unknown` |
33
+ | `formal_result` | `PASS` |
34
+ | `lec_result` | `UNKNOWN` |
35
+ | `regression_passed` | `0` |
36
+ | `regression_total` | `0` |
37
+ | `clock_period_ns` | `10.0` |
38
+ | `pivots_used` | `0` |
39
+ | `global_steps` | `7` |
metircs/apb_timer/latest.json ADDED
@@ -0,0 +1,80 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ {
2
+ "design_name": "apb_timer",
3
+ "generated_at_epoch": 1772742765,
4
+ "build_status": "SUCCESS",
5
+ "signoff_result": "UNKNOWN",
6
+ "pdk_profile": "sky130",
7
+ "pdk": "sky130A",
8
+ "std_cell_library": "sky130_fd_sc_hd",
9
+ "verification_metadata": {
10
+ "tb_gate_mode": "strict",
11
+ "tb_max_retries": 3,
12
+ "tb_fallback_template": "uvm_lite",
13
+ "tb_static_fail_count": 0,
14
+ "tb_compile_fail_count": 0,
15
+ "tb_repair_fail_count": 0,
16
+ "tb_gate_history_count": 1,
17
+ "tb_gate_history": [
18
+ {
19
+ "timestamp": 1772742645,
20
+ "gate": "compile",
21
+ "ok": true,
22
+ "action": "gate_pass",
23
+ "issue_categories": [
24
+ "compile_ok"
25
+ ],
26
+ "fingerprint": "f0eae3025ab704df"
27
+ }
28
+ ],
29
+ "coverage_backend": "auto",
30
+ "coverage_fallback_policy": "fallback_oss",
31
+ "coverage_profile": "balanced",
32
+ "coverage_thresholds": {
33
+ "line": 85.0,
34
+ "branch": 80.0,
35
+ "toggle": 75.0,
36
+ "functional": 80.0
37
+ },
38
+ "coverage_mode": "unknown",
39
+ "coverage_error_kind": "",
40
+ "coverage_diag_path": "",
41
+ "coverage_threshold_pass": {
42
+ "line": false,
43
+ "branch": false,
44
+ "toggle": false,
45
+ "functional": false
46
+ }
47
+ },
48
+ "industry_benchmark": {
49
+ "area_um2": 0.0,
50
+ "cell_count": 0.0,
51
+ "utilization_pct": 0.0,
52
+ "timing_wns_ns": 0.0,
53
+ "timing_tns_ns": 0.0,
54
+ "hold_slack_ns": 0.0,
55
+ "drc_violations": -1,
56
+ "lvs_errors": -1,
57
+ "antenna_violations": -1,
58
+ "total_power_mw": 0.0,
59
+ "internal_power_mw": 0.0,
60
+ "switching_power_mw": 0.0,
61
+ "leakage_power_uw": 0.0,
62
+ "irdrop_vpwr_mv": 0.0,
63
+ "irdrop_vgnd_mv": 0.0,
64
+ "congestion_usage_pct": 0.0,
65
+ "congestion_overflow": 0,
66
+ "coverage_line_pct": 0.0,
67
+ "coverage_branch_pct": 0.0,
68
+ "coverage_toggle_pct": 0.0,
69
+ "coverage_functional_pct": 0.0,
70
+ "coverage_backend": "auto",
71
+ "coverage_mode": "unknown",
72
+ "formal_result": "PASS",
73
+ "lec_result": "UNKNOWN",
74
+ "regression_passed": 0,
75
+ "regression_total": 0,
76
+ "clock_period_ns": "10.0",
77
+ "pivots_used": 0,
78
+ "global_steps": 7
79
+ }
80
+ }
metircs/apb_timer/latest.md ADDED
@@ -0,0 +1,39 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # apb_timer Industry Benchmark Metrics
2
+
3
+ - Generated At (epoch): `1772742765`
4
+ - Build Status: `SUCCESS`
5
+ - Signoff Result: `UNKNOWN`
6
+ - PDK Profile: `sky130`
7
+
8
+ | Metric | Value |
9
+ |---|---|
10
+ | `area_um2` | `0.0` |
11
+ | `cell_count` | `0.0` |
12
+ | `utilization_pct` | `0.0` |
13
+ | `timing_wns_ns` | `0.0` |
14
+ | `timing_tns_ns` | `0.0` |
15
+ | `hold_slack_ns` | `0.0` |
16
+ | `drc_violations` | `-1` |
17
+ | `lvs_errors` | `-1` |
18
+ | `antenna_violations` | `-1` |
19
+ | `total_power_mw` | `0.0` |
20
+ | `internal_power_mw` | `0.0` |
21
+ | `switching_power_mw` | `0.0` |
22
+ | `leakage_power_uw` | `0.0` |
23
+ | `irdrop_vpwr_mv` | `0.0` |
24
+ | `irdrop_vgnd_mv` | `0.0` |
25
+ | `congestion_usage_pct` | `0.0` |
26
+ | `congestion_overflow` | `0` |
27
+ | `coverage_line_pct` | `0.0` |
28
+ | `coverage_branch_pct` | `0.0` |
29
+ | `coverage_toggle_pct` | `0.0` |
30
+ | `coverage_functional_pct` | `0.0` |
31
+ | `coverage_backend` | `auto` |
32
+ | `coverage_mode` | `unknown` |
33
+ | `formal_result` | `PASS` |
34
+ | `lec_result` | `UNKNOWN` |
35
+ | `regression_passed` | `0` |
36
+ | `regression_total` | `0` |
37
+ | `clock_period_ns` | `10.0` |
38
+ | `pivots_used` | `0` |
39
+ | `global_steps` | `7` |
metircs/counter8/counter8_industry_benchmark_20260306_013138.json ADDED
@@ -0,0 +1,100 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ {
2
+ "design_name": "counter8",
3
+ "generated_at_epoch": 1772740898,
4
+ "build_status": "SUCCESS",
5
+ "signoff_result": "UNKNOWN",
6
+ "pdk_profile": "sky130",
7
+ "pdk": "sky130A",
8
+ "std_cell_library": "sky130_fd_sc_hd",
9
+ "verification_metadata": {
10
+ "tb_gate_mode": "strict",
11
+ "tb_max_retries": 3,
12
+ "tb_fallback_template": "uvm_lite",
13
+ "tb_static_fail_count": 0,
14
+ "tb_compile_fail_count": 1,
15
+ "tb_repair_fail_count": 0,
16
+ "tb_gate_history_count": 3,
17
+ "tb_gate_history": [
18
+ {
19
+ "timestamp": 1772740616,
20
+ "gate": "compile",
21
+ "ok": false,
22
+ "action": "gate_fail",
23
+ "issue_categories": [
24
+ "compile_error"
25
+ ],
26
+ "fingerprint": "ae3cc7ecd62b2214"
27
+ },
28
+ {
29
+ "timestamp": 1772740616,
30
+ "gate": "compile",
31
+ "ok": false,
32
+ "action": "auto_repair",
33
+ "issue_categories": [
34
+ "compile_error"
35
+ ],
36
+ "fingerprint": "ae3cc7ecd62b2214"
37
+ },
38
+ {
39
+ "timestamp": 1772740616,
40
+ "gate": "compile",
41
+ "ok": true,
42
+ "action": "gate_pass",
43
+ "issue_categories": [
44
+ "compile_ok"
45
+ ],
46
+ "fingerprint": "db727dd2dc2e58b0"
47
+ }
48
+ ],
49
+ "coverage_backend": "auto",
50
+ "coverage_fallback_policy": "fallback_oss",
51
+ "coverage_profile": "balanced",
52
+ "coverage_thresholds": {
53
+ "line": 85.0,
54
+ "branch": 80.0,
55
+ "toggle": 75.0,
56
+ "functional": 80.0
57
+ },
58
+ "coverage_mode": "unknown",
59
+ "coverage_error_kind": "",
60
+ "coverage_diag_path": "",
61
+ "coverage_threshold_pass": {
62
+ "line": false,
63
+ "branch": false,
64
+ "toggle": false,
65
+ "functional": false
66
+ }
67
+ },
68
+ "industry_benchmark": {
69
+ "area_um2": 0.0,
70
+ "cell_count": 0.0,
71
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+ }
metircs/counter8/counter8_industry_benchmark_20260306_013138.md ADDED
@@ -0,0 +1,39 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # counter8 Industry Benchmark Metrics
2
+
3
+ - Generated At (epoch): `1772740898`
4
+ - Build Status: `SUCCESS`
5
+ - Signoff Result: `UNKNOWN`
6
+ - PDK Profile: `sky130`
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+
8
+ | Metric | Value |
9
+ |---|---|
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+ | `area_um2` | `0.0` |
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+ | `cell_count` | `0.0` |
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+ | `utilization_pct` | `0.0` |
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+ | `hold_slack_ns` | `0.0` |
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+ | `drc_violations` | `-1` |
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+ | `lvs_errors` | `-1` |
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+ | `antenna_violations` | `-1` |
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+ | `total_power_mw` | `0.0` |
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+ | `internal_power_mw` | `0.0` |
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+ | `switching_power_mw` | `0.0` |
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+ | `leakage_power_uw` | `0.0` |
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+ | `irdrop_vpwr_mv` | `0.0` |
24
+ | `irdrop_vgnd_mv` | `0.0` |
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+ | `congestion_usage_pct` | `0.0` |
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+ | `coverage_line_pct` | `0.0` |
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+ | `coverage_branch_pct` | `0.0` |
29
+ | `coverage_toggle_pct` | `0.0` |
30
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31
+ | `coverage_backend` | `auto` |
32
+ | `coverage_mode` | `unknown` |
33
+ | `formal_result` | `PASS` |
34
+ | `lec_result` | `UNKNOWN` |
35
+ | `regression_passed` | `0` |
36
+ | `regression_total` | `0` |
37
+ | `clock_period_ns` | `10.0` |
38
+ | `pivots_used` | `0` |
39
+ | `global_steps` | `13` |
metircs/counter8/latest.json ADDED
@@ -0,0 +1,100 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ {
2
+ "design_name": "counter8",
3
+ "generated_at_epoch": 1772740898,
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+ "build_status": "SUCCESS",
5
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+ "pdk": "sky130A",
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+ "std_cell_library": "sky130_fd_sc_hd",
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+ "verification_metadata": {
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+ {
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+ "fingerprint": "ae3cc7ecd62b2214"
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+ },
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+ {
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+ "timestamp": 1772740616,
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+ }
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+ ],
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98
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+ }
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+ }
metircs/counter8/latest.md ADDED
@@ -0,0 +1,39 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # counter8 Industry Benchmark Metrics
2
+
3
+ - Generated At (epoch): `1772740898`
4
+ - Build Status: `SUCCESS`
5
+ - Signoff Result: `UNKNOWN`
6
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+
8
+ | Metric | Value |
9
+ |---|---|
10
+ | `area_um2` | `0.0` |
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+ | `cell_count` | `0.0` |
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+ | `utilization_pct` | `0.0` |
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+ | `total_power_mw` | `0.0` |
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+ | `switching_power_mw` | `0.0` |
22
+ | `leakage_power_uw` | `0.0` |
23
+ | `irdrop_vpwr_mv` | `0.0` |
24
+ | `irdrop_vgnd_mv` | `0.0` |
25
+ | `congestion_usage_pct` | `0.0` |
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+ | `congestion_overflow` | `0` |
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+ | `coverage_line_pct` | `0.0` |
28
+ | `coverage_branch_pct` | `0.0` |
29
+ | `coverage_toggle_pct` | `0.0` |
30
+ | `coverage_functional_pct` | `0.0` |
31
+ | `coverage_backend` | `auto` |
32
+ | `coverage_mode` | `unknown` |
33
+ | `formal_result` | `PASS` |
34
+ | `lec_result` | `UNKNOWN` |
35
+ | `regression_passed` | `0` |
36
+ | `regression_total` | `0` |
37
+ | `clock_period_ns` | `10.0` |
38
+ | `pivots_used` | `0` |
39
+ | `global_steps` | `13` |
metircs/the_dhruva_chip_is/latest.json ADDED
@@ -0,0 +1,90 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ {
2
+ "design_name": "the_dhruva_chip_is",
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+ "generated_at_epoch": 1773041127,
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+ "build_status": "SUCCESS",
5
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+ "pdk": "sky130A",
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+ "std_cell_library": "sky130_fd_sc_hd",
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81
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82
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83
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84
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+ }
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+ }
metircs/the_dhruva_chip_is/latest.md ADDED
@@ -0,0 +1,39 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # the_dhruva_chip_is Industry Benchmark Metrics
2
+
3
+ - Generated At (epoch): `1773041127`
4
+ - Build Status: `SUCCESS`
5
+ - Signoff Result: `UNKNOWN`
6
+ - PDK Profile: `sky130`
7
+
8
+ | Metric | Value |
9
+ |---|---|
10
+ | `area_um2` | `0.0` |
11
+ | `cell_count` | `0.0` |
12
+ | `utilization_pct` | `0.0` |
13
+ | `timing_wns_ns` | `0.0` |
14
+ | `timing_tns_ns` | `0.0` |
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+ | `hold_slack_ns` | `0.0` |
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+ | `drc_violations` | `-1` |
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+ | `lvs_errors` | `-1` |
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+ | `antenna_violations` | `-1` |
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+ | `total_power_mw` | `0.0` |
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+ | `internal_power_mw` | `0.0` |
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+ | `switching_power_mw` | `0.0` |
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+ | `leakage_power_uw` | `0.0` |
23
+ | `irdrop_vpwr_mv` | `0.0` |
24
+ | `irdrop_vgnd_mv` | `0.0` |
25
+ | `congestion_usage_pct` | `0.0` |
26
+ | `congestion_overflow` | `0` |
27
+ | `coverage_line_pct` | `0.0` |
28
+ | `coverage_branch_pct` | `0.0` |
29
+ | `coverage_toggle_pct` | `0.0` |
30
+ | `coverage_functional_pct` | `0.0` |
31
+ | `coverage_backend` | `auto` |
32
+ | `coverage_mode` | `unknown` |
33
+ | `formal_result` | `UNKNOWN` |
34
+ | `lec_result` | `UNKNOWN` |
35
+ | `regression_passed` | `0` |
36
+ | `regression_total` | `0` |
37
+ | `clock_period_ns` | `10.0` |
38
+ | `pivots_used` | `0` |
39
+ | `global_steps` | `15` |
metircs/the_dhruva_chip_is/the_dhruva_chip_is_industry_benchmark_20260309_125527.json ADDED
@@ -0,0 +1,90 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ {
2
+ "design_name": "the_dhruva_chip_is",
3
+ "generated_at_epoch": 1773041127,
4
+ "build_status": "SUCCESS",
5
+ "signoff_result": "UNKNOWN",
6
+ "pdk_profile": "sky130",
7
+ "pdk": "sky130A",
8
+ "std_cell_library": "sky130_fd_sc_hd",
9
+ "verification_metadata": {
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11
+ "tb_max_retries": 3,
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+ "action": "gate_pass",
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+ "issue_categories": [
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25
+ ],
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+ "fingerprint": "fe89b3612bbd8d10"
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+ },
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+ {
29
+ "timestamp": 1773041078,
30
+ "gate": "compile",
31
+ "ok": true,
32
+ "action": "gate_pass",
33
+ "issue_categories": [
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+ "compile_ok"
35
+ ],
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+ "fingerprint": "719d55d7cf9f66b7"
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+ }
38
+ ],
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+ "coverage_backend": "auto",
40
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41
+ "coverage_profile": "balanced",
42
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44
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45
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48
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49
+ "coverage_error_kind": "",
50
+ "coverage_diag_path": "",
51
+ "coverage_threshold_pass": {
52
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53
+ "branch": false,
54
+ "toggle": false,
55
+ "functional": false
56
+ }
57
+ },
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+ "utilization_pct": 0.0,
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79
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80
+ "coverage_backend": "auto",
81
+ "coverage_mode": "unknown",
82
+ "formal_result": "UNKNOWN",
83
+ "lec_result": "UNKNOWN",
84
+ "regression_passed": 0,
85
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86
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87
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88
+ "global_steps": 15
89
+ }
90
+ }
metircs/the_dhruva_chip_is/the_dhruva_chip_is_industry_benchmark_20260309_125527.md ADDED
@@ -0,0 +1,39 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # the_dhruva_chip_is Industry Benchmark Metrics
2
+
3
+ - Generated At (epoch): `1773041127`
4
+ - Build Status: `SUCCESS`
5
+ - Signoff Result: `UNKNOWN`
6
+ - PDK Profile: `sky130`
7
+
8
+ | Metric | Value |
9
+ |---|---|
10
+ | `area_um2` | `0.0` |
11
+ | `cell_count` | `0.0` |
12
+ | `utilization_pct` | `0.0` |
13
+ | `timing_wns_ns` | `0.0` |
14
+ | `timing_tns_ns` | `0.0` |
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+ | `hold_slack_ns` | `0.0` |
16
+ | `drc_violations` | `-1` |
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+ | `lvs_errors` | `-1` |
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+ | `antenna_violations` | `-1` |
19
+ | `total_power_mw` | `0.0` |
20
+ | `internal_power_mw` | `0.0` |
21
+ | `switching_power_mw` | `0.0` |
22
+ | `leakage_power_uw` | `0.0` |
23
+ | `irdrop_vpwr_mv` | `0.0` |
24
+ | `irdrop_vgnd_mv` | `0.0` |
25
+ | `congestion_usage_pct` | `0.0` |
26
+ | `congestion_overflow` | `0` |
27
+ | `coverage_line_pct` | `0.0` |
28
+ | `coverage_branch_pct` | `0.0` |
29
+ | `coverage_toggle_pct` | `0.0` |
30
+ | `coverage_functional_pct` | `0.0` |
31
+ | `coverage_backend` | `auto` |
32
+ | `coverage_mode` | `unknown` |
33
+ | `formal_result` | `UNKNOWN` |
34
+ | `lec_result` | `UNKNOWN` |
35
+ | `regression_passed` | `0` |
36
+ | `regression_total` | `0` |
37
+ | `clock_period_ns` | `10.0` |
38
+ | `pivots_used` | `0` |
39
+ | `global_steps` | `15` |
requirements.txt CHANGED
@@ -2,6 +2,8 @@
2
  crewai==1.9.3
3
  crewai-tools
4
  langchain_openai
 
 
5
 
6
  # ── CLI & Logging ─────────────────────────────────────────────────────
7
  typer
 
2
  crewai==1.9.3
3
  crewai-tools
4
  langchain_openai
5
+ litellm>=1.0.0
6
+ openai>=1.0.0
7
 
8
  # ── CLI & Logging ─────────────────────────────────────────────────────
9
  typer
server/api.py CHANGED
@@ -829,6 +829,12 @@ def read_root():
829
  return {"message": "AgentIC API is online", "version": "3.0.0"}
830
 
831
 
 
 
 
 
 
 
832
  @app.get("/health")
833
  def health_check():
834
  """Health probe — verifies the LLM backend is reachable."""
 
829
  return {"message": "AgentIC API is online", "version": "3.0.0"}
830
 
831
 
832
+ @app.get("/ping")
833
+ def ping():
834
+ """Zero-processing liveness probe for uptime monitors."""
835
+ return {"status": "ok"}
836
+
837
+
838
  @app.get("/health")
839
  def health_check():
840
  """Health probe — verifies the LLM backend is reachable."""
src/__init__.py ADDED
File without changes
src/agentic/config.py CHANGED
@@ -4,8 +4,12 @@ from dotenv import load_dotenv
4
 
5
  # Project Paths
6
  WORKSPACE_ROOT = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
7
- load_dotenv(os.path.join(WORKSPACE_ROOT, ".env"))
8
- load_dotenv()
 
 
 
 
9
 
10
  OPENLANE_ROOT = os.environ.get("OPENLANE_ROOT", os.path.expanduser("~/OpenLane"))
11
  DESIGNS_DIR = os.path.join(OPENLANE_ROOT, "designs")
 
4
 
5
  # Project Paths
6
  WORKSPACE_ROOT = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
7
+
8
+ # Load .env file ONLY if it exists, and NEVER override environment variables
9
+ # already set by the platform (e.g. HuggingFace Spaces secrets).
10
+ _dotenv_path = os.path.join(WORKSPACE_ROOT, ".env")
11
+ if os.path.isfile(_dotenv_path):
12
+ load_dotenv(_dotenv_path, override=False)
13
 
14
  OPENLANE_ROOT = os.environ.get("OPENLANE_ROOT", os.path.expanduser("~/OpenLane"))
15
  DESIGNS_DIR = os.path.join(OPENLANE_ROOT, "designs")
tests/test_reliability_contracts.py ADDED
@@ -0,0 +1,123 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ import sys
2
+ import contextlib
3
+ import unittest
4
+ from unittest import mock
5
+ from pathlib import Path
6
+
7
+ REPO_ROOT = Path(__file__).resolve().parents[1]
8
+ SRC_ROOT = REPO_ROOT / "src"
9
+ if str(SRC_ROOT) not in sys.path:
10
+ sys.path.insert(0, str(SRC_ROOT))
11
+
12
+ from agentic.contracts import FailureClass, extract_json_object, infer_failure_class, validate_agent_payload
13
+ from agentic.orchestrator import BuildOrchestrator, BuildState
14
+
15
+
16
+ class ReliabilityContractsTest(unittest.TestCase):
17
+ def _make_orchestrator(self) -> BuildOrchestrator:
18
+ orch = BuildOrchestrator(
19
+ name="demo",
20
+ desc="demo design",
21
+ llm=object(),
22
+ verbose=False,
23
+ )
24
+ orch.logger = mock.Mock()
25
+ orch.state = BuildState.VERIFICATION
26
+ orch.artifacts["rtl_code"] = (
27
+ "module demo(input logic clk, input logic rst_n, output logic y);\n"
28
+ "assign y = clk;\n"
29
+ "endmodule\n"
30
+ )
31
+ orch.artifacts["rtl_path"] = "/tmp/demo.v"
32
+ return orch
33
+
34
+ def test_extract_json_object_from_fenced_text(self):
35
+ raw = 'noise\n```json\n{"class":"B","root_cause":"bad"}\n```\n'
36
+ parsed = extract_json_object(raw)
37
+ self.assertEqual(parsed, {"class": "B", "root_cause": "bad"})
38
+
39
+ def test_validate_agent_payload_missing_keys(self):
40
+ errors = validate_agent_payload({"class": "A"}, ["class", "root_cause"])
41
+ self.assertEqual(errors, ["Missing required key 'root_cause'."])
42
+
43
+ def test_infer_failure_class(self):
44
+ cls = infer_failure_class(
45
+ producer="llm_fixer",
46
+ raw_output="This is not valid json",
47
+ diagnostics=["Missing required key 'root_cause'."],
48
+ )
49
+ self.assertEqual(cls, FailureClass.LLM_FORMAT_ERROR)
50
+
51
+ def test_transition_resets_retry_count(self):
52
+ orch = self._make_orchestrator()
53
+ orch.retry_count = 3
54
+ orch.transition(BuildState.FORMAL_VERIFY)
55
+ self.assertEqual(orch.retry_count, 0)
56
+
57
+ def test_required_artifact_handoff_raises(self):
58
+ orch = self._make_orchestrator()
59
+ with self.assertRaises(RuntimeError):
60
+ orch._consume_handoff("tb_regen_context", consumer="VERIFICATION", required=True)
61
+
62
+ def test_parse_structured_agent_json_rejects_prose(self):
63
+ orch = self._make_orchestrator()
64
+ result = orch._parse_structured_agent_json(
65
+ agent_name="VerificationAnalyst",
66
+ raw_output="The issue is likely in the RTL.",
67
+ required_keys=["class", "root_cause"],
68
+ )
69
+ self.assertFalse(result.ok)
70
+ self.assertEqual(result.failure_class, FailureClass.LLM_FORMAT_ERROR)
71
+
72
+ def test_validate_rtl_candidate_rejects_hierarchy_rewrite(self):
73
+ orch = self._make_orchestrator()
74
+ previous = (
75
+ "module demo(input logic clk, output logic y); assign y = clk; endmodule\n"
76
+ "module demo_helper(input logic a, output logic b); assign b = a; endmodule\n"
77
+ )
78
+ candidate = "module demo(input logic clk, output logic y); assign y = clk; endmodule\n"
79
+ issues = orch._validate_rtl_candidate(candidate, previous)
80
+ self.assertTrue(any("module inventory" in issue for issue in issues))
81
+
82
+ def test_validate_tb_candidate_requires_waveform_and_name(self):
83
+ orch = self._make_orchestrator()
84
+ issues = orch._validate_tb_candidate("module wrong_tb; initial begin $finish; end endmodule")
85
+ self.assertTrue(any("TB module name" in issue for issue in issues))
86
+ self.assertTrue(any("dumpfile" in issue for issue in issues))
87
+
88
+ def test_tb_regen_context_bypasses_golden_tb(self):
89
+ orch = self._make_orchestrator()
90
+ orch.artifacts["golden_tb"] = "module counter_tb; endmodule"
91
+ orch.artifacts["golden_template"] = "counter"
92
+ orch._set_artifact(
93
+ "tb_regen_context",
94
+ '{"issue":"pin mismatch"}',
95
+ producer="test",
96
+ consumer="VERIFICATION",
97
+ required=True,
98
+ blocking=True,
99
+ )
100
+ generated_tb = """module demo_tb;
101
+ initial begin
102
+ $dumpfile("demo_wave.vcd");
103
+ $dumpvars(0, demo_tb);
104
+ $display("TEST FAILED");
105
+ $display("TEST PASSED");
106
+ $finish;
107
+ end
108
+ endmodule
109
+ """
110
+
111
+ with mock.patch("agentic.orchestrator.get_testbench_agent", return_value=object()), \
112
+ mock.patch("agentic.orchestrator.Task", side_effect=lambda **kwargs: kwargs), \
113
+ mock.patch.object(orch, "_kickoff_with_timeout", return_value=generated_tb) as kickoff, \
114
+ mock.patch("agentic.orchestrator.console.status", return_value=contextlib.nullcontext()), \
115
+ mock.patch("agentic.orchestrator.write_verilog", return_value="/tmp/demo_tb.v"), \
116
+ mock.patch("agentic.orchestrator.run_tb_static_contract_check", side_effect=RuntimeError("stop_after_generation")):
117
+ with self.assertRaisesRegex(RuntimeError, "stop_after_generation"):
118
+ orch.do_verification()
119
+ self.assertTrue(kickoff.called)
120
+
121
+
122
+ if __name__ == "__main__":
123
+ unittest.main()
tests/test_vlsi_tools_temp_paths.py ADDED
@@ -0,0 +1,83 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ import os
2
+ import subprocess
3
+ import sys
4
+ import tempfile
5
+ import unittest
6
+ from pathlib import Path
7
+ from unittest import mock
8
+
9
+
10
+ REPO_ROOT = Path(__file__).resolve().parents[1]
11
+ SRC_ROOT = REPO_ROOT / "src"
12
+ if str(SRC_ROOT) not in sys.path:
13
+ sys.path.insert(0, str(SRC_ROOT))
14
+
15
+ from agentic.tools import vlsi_tools
16
+
17
+
18
+ class TempPathRewriteTests(unittest.TestCase):
19
+ def test_rewrite_temp_paths_replaces_absolute_and_basename_forms(self):
20
+ original = "/workspace/designs/counter8/src/counter8.v"
21
+ staged = "/tmp/tmpabc/counter8.v"
22
+ staged_map = {original: staged}
23
+
24
+ rewritten_abs = vlsi_tools._rewrite_temp_paths(
25
+ f"%Error: {staged}:12:3: syntax error",
26
+ staged_map,
27
+ )
28
+ rewritten_base = vlsi_tools._rewrite_temp_paths(
29
+ "%Error: counter8.v:12:3: syntax error",
30
+ staged_map,
31
+ )
32
+
33
+ self.assertIn(original, rewritten_abs)
34
+ self.assertIn(original, rewritten_base)
35
+ self.assertNotIn("/tmp/tmpabc", rewritten_abs)
36
+ self.assertNotIn("/tmp/tmpabc", rewritten_base)
37
+
38
+ def test_rewrite_result_paths_sanitizes_all_text_fields(self):
39
+ original = "/workspace/designs/counter8/src/counter8.v"
40
+ staged = "/tmp/tmpxyz/counter8.v"
41
+ staged_map = {original: staged}
42
+ payload = {
43
+ "stdout": f"warning in {staged}:4:1",
44
+ "stderr": "counter8.v:7:2: syntax error",
45
+ "diagnostics": [
46
+ f"%Error: {staged}:9:9: bad token",
47
+ "counter8.v:10:11: width warning",
48
+ ],
49
+ }
50
+
51
+ sanitized = vlsi_tools._rewrite_result_paths(payload, staged_map)
52
+
53
+ for text in [sanitized["stdout"], sanitized["stderr"], *sanitized["diagnostics"]]:
54
+ self.assertIn(original, text)
55
+ self.assertNotIn("/tmp/tmpxyz", text)
56
+
57
+ def test_run_syntax_check_returns_original_path_in_legacy_message(self):
58
+ with tempfile.TemporaryDirectory() as src_dir:
59
+ rtl_path = os.path.join(src_dir, "counter8.v")
60
+ with open(rtl_path, "w", encoding="utf-8") as f:
61
+ f.write("module counter8; endmodule\n")
62
+
63
+ seen = {}
64
+
65
+ def fake_run(cmd, capture_output, text, timeout, cwd=None):
66
+ seen["cwd"] = cwd
67
+ return subprocess.CompletedProcess(
68
+ cmd,
69
+ 1,
70
+ stdout="",
71
+ stderr=f"%Error: {cwd}/counter8.v:12:3: syntax error\n",
72
+ )
73
+
74
+ with mock.patch("agentic.tools.vlsi_tools.subprocess.run", side_effect=fake_run):
75
+ ok, message = vlsi_tools.run_syntax_check(rtl_path)
76
+
77
+ self.assertFalse(ok)
78
+ self.assertIn(rtl_path, message)
79
+ self.assertNotIn(seen["cwd"], message)
80
+
81
+
82
+ if __name__ == "__main__":
83
+ unittest.main()