Tier-1 upgrade: fail-closed orchestration, CI, and benchmark export

.github/workflows/ci.yml

@@ -0,0 +1,57 @@
+name: AgentIC CI
+
+on:
+  pull_request:
+  push:
+    branches: [ "main", "master" ]
+  schedule:
+    - cron: "0 3 * * *"
+  workflow_dispatch:
+
+jobs:
+  pr-smoke:
+    name: PR Smoke
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+
+      - name: Setup Python
+        uses: actions/setup-python@v5
+        with:
+          python-version: "3.11"
+
+      - name: Install deps
+        run: |
+          python -m pip install --upgrade pip
+          pip install -r requirements.txt
+
+      - name: Smoke checks
+        run: |
+          bash scripts/ci/smoke.sh
+
+  nightly-full:
+    name: Nightly Full Flow
+    if: github.event_name == 'schedule' || github.event_name == 'workflow_dispatch'
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+
+      - name: Setup Python
+        uses: actions/setup-python@v5
+        with:
+          python-version: "3.11"
+
+      - name: Install deps
+        run: |
+          python -m pip install --upgrade pip
+          pip install -r requirements.txt
+
+      - name: Nightly full workflow
+        env:
+          NVIDIA_API_KEY: ${{ secrets.NVIDIA_API_KEY }}
+          LLM_BASE_URL: ${{ secrets.LLM_BASE_URL }}
+          OPENLANE_ROOT: ${{ vars.OPENLANE_ROOT }}
+        run: |
+          bash scripts/ci/nightly_full.sh

README.md

@@ -1,406 +1,294 @@
-# AgentIC: AI-Powered Text-to-Silicon Compiler
-
-![Python](https://img.shields.io/badge/Python-3.10%2B-blue) ![License](https://img.shields.io/badge/License-Proprietary-red) ![OpenLane](https://img.shields.io/badge/OpenLane-Integrated-purple) ![Verification](https://img.shields.io/badge/Formal_Verification-SVA-red)
-
-**AgentIC** transforms natural language descriptions into verified, manufacturable chip layouts (GDSII). It orchestrates a crew of specialized AI agents through a self-correcting pipeline — from RTL generation through formal verification to physical design — producing industry-standard silicon with minimal human intervention.
-
-> **"Build a radiation-hardened SPI master with TMR"** → Verified RTL → GDSII layout
-
----
-
-## Architecture
+# AgentIC: Tier-1 Autonomous Text-to-Silicon
+
+![Python](https://img.shields.io/badge/Python-3.10%2B-blue)
+![Flow](https://img.shields.io/badge/Flow-Fail--Closed-critical)
+![Signoff](https://img.shields.io/badge/Signoff-Multi--Corner_STA%20%2B%20LEC-success)
+![PDK](https://img.shields.io/badge/PDK-Sky130%20%7C%20GF180-informational)
+
+AgentIC converts natural-language hardware intent into RTL, verification artifacts, and OpenLane physical implementation with autonomous repair loops.
+
+This README reflects the **Tier-1 upgrade**: strict fail-closed gates, bounded loop control, semantic rigor checks, multi-corner timing parsing, LEC integration, floorplan/convergence/ECO stages, and adapter-based OSS-PDK portability.
+
+## Why this version is different
+
+AgentIC is now built to avoid two expensive failure modes:
+
+1. **Silent quality regression**: weak checks passing bad designs.
+2. **Infinite churn**: retrying the same failing strategy forever.
+
+Tier-1 addresses both.
+
+## Tier-1 upgrade highlights
+
+- **Fail-closed mode is first-class** (`--strict-gates` default).
+- **Startup toolchain self-check** before build starts.
+- **Deterministic semantic preflight** for:
+  - width mismatch diagnostics,
+  - port shadowing rejection.
+- **Loop safety controls**:
+  - failure fingerprint detection,
+  - per-state retries,
+  - global step budget,
+  - capped strategy pivots.
+- **EDA intelligence layer** to summarize large logs into structured top issues.
+- **Physical feedback loop** with:
+  - floorplan stage,
+  - congestion assessment,
+  - convergence assessor,
+  - ECO stage.
+- **Signoff upgrades**:
+  - multi-corner STA parsing (setup + hold),
+  - numeric power + IR-drop parsing,
+  - EQY-based LEC check.
+- **Hierarchy/IP scaling scaffold**:
+  - auto hierarchy planner,
+  - per-block artifact emission,
+  - reusable `ip_manifest.json`.
+- **CI split**:
+  - PR smoke checks,
+  - nightly full-flow path.
+
+## Architecture (easy view)
 
 ```mermaid
-graph TD
-    A["User: build --name chip --desc 'description'"] --> B[Architect Agent]
-    
-    subgraph "Phase 1: Design"
-        B -->|Spec| C{Golden Template Match?}
-        C -->|Yes: Simple Design| D[Use Pre-Verified Template]
-        C -->|No: Complex Design| E[LLM RTL Generation]
-        D --> F[Syntax Check — Icarus Verilog]
-        E --> F
-        F -->|Fail| G["Autonomous Fix (regex)"]
-        G -->|SV Compat Fixed| F
-        G -->|Unknown Error| G2[LLM Fix Agent]
-        G2 --> F
-        F -->|Pass| H[Lint Check — Verilator]
-        H -->|Fail| G
-        H -->|Pass| H2[Pre-Synthesis Validation]
-        H2 -->|Undriven Signals| H3[Auto-Fix: Tie to 0 / Remove]
-        H3 --> F
-    end
-
-    subgraph "Phase 2: Verification"
-        H2 -->|Clean| I[Testbench Generation]
-        I --> J[Simulation — iverilog + vvp]
-        J -->|Compile Fail| G
-        J -->|Logic Fail| K[Error Analyst]
-        K -->|TB Error| I
-        K -->|RTL Error| E
-        J -->|Pass| L[Formal Verification — SymbiYosys]
-        L --> M[Coverage Analysis]
-    end
-
-    subgraph "Phase 3: Physical Design"
-        M --> N["Auto-Config Generation"]
-        N --> O[OpenLane — Synthesis to GDSII]
-        O --> P[PPA Analysis]
-        P -->|Violations| Q[Backend Optimizer]
-        Q --> E
-        P -->|Pass| R["GDSII Tapeout File"]
-    end
-```
-
----
-
-## Key Features
-
-### Industry Standards Compliance
-AgentIC is fully compliant with industry standards for chip production, ensuring synthesizable and verifiable designs without human intervention:
-- **Strict Linting:** Verilator (`-Wall`) catches implicit truncations, width mismatches, and combinational loops early.
-- **Simulation Signoff:** Icarus Verilog (`iverilog`) for behavioral bounding and gate-level simulation (GLS) validation.
-- **Formal Verification:** SymbiYosys (SBY) integration natively proves SVA properties for corner-case bug elimination.
-- **Physical Tapeout (RTL-to-GDSII):** Fully automated OpenLane workflow (SkyWater 130nm default) generating GDSII files with built-in DRC (Design Rule Check), LVS (Layout vs Schematic), and STA (Static Timing Analysis) signoff.
-
-### Autonomous Self-Healing Pipeline
-AgentIC doesn't just generate code — it detects and fixes errors **without LLM calls** whenever possible:
-
-| Error Type | Detection | Fix | LLM Needed? |
-|-----------|-----------|-----|-------------|
-| `always_comb` in iverilog | Error log pattern match | `always_comb` → `always @(*)` | ❌ No |
-| Explicit type casts | `This assignment requires an explicit cast` | `type'(val)` → `(val)` | ❌ No |
-| `unique case` / `priority case` | Error log match | Strip qualifier | ❌ No |
-| Undriven signals | Pre-synthesis scan | Tie to 0 or remove | ❌ No |
-| TB compilation error | `Compilation failed` in output | SV→Verilog regex fix | ❌ No |
-| Logic bugs | `TEST FAILED` in simulation | Error Analyst + Fixer | ✅ Yes |
-| Unknown syntax errors | Unmatched error patterns | LLM Syntax Rectifier | ✅ Yes |
-
-### Multi-Agent Crew
-
-| Agent | Role | Tools |
-|-------|------|-------|
-| **Architect** | Defines micro-architecture, interfaces, and FSM states | Specification generation |
-| **Designer** | Writes synthesizable Verilog/SystemVerilog RTL | `write_verilog`, `syntax_check` |
-| **Verification Engineer** | Generates SVA assertions (industry + Yosys-compatible) | `convert_sva_to_yosys`, SymbiYosys |
-| **Testbench Agent** | Creates self-checking testbenches with port-accurate DUT instantiation | `run_simulation` |
-| **Error Analyst** | Classifies failures as RTL vs testbench bugs, directs fixes | Log analysis |
-| **Backend Engineer** | Configures OpenLane, optimizes PPA (Power, Performance, Area) | `run_openlane` |
-
-### Golden Reference Library
-Pre-verified RTL + testbench pairs for common IP blocks — **95% first-attempt success**:
-
-| Template | Description | Complexity |
-|----------|-------------|------------|
-| `counter` | N-bit up/down counter with enable and load | Simple |
-| `fifo` | Synchronous FIFO with parameterizable width/depth | Medium |
-| `uart_tx` | UART Transmitter with configurable baud rate | Medium |
-| `spi_master` | SPI Master with configurable CPOL/CPHA | Medium |
-| `fsm` | Generic FSM with configurable states | Simple |
-| `pwm` | PWM generator with configurable resolution | Simple |
-| `timer` | General-purpose timer with prescaler | Medium |
-| `shift_register` | Shift register with serial/parallel IO | Simple |
-
-> **Smart Matching**: Complex designs (TMR, AES, DMA, pipelined, radiation-hardened, etc.) automatically bypass templates and use full LLM generation from scratch.
-
-### Auto-Generated OpenLane Config
-No manual `config.tcl` needed — the system reads the RTL file, estimates complexity, and generates appropriate die area, clock period, and synthesis settings:
-
-| RTL Size | Die Area | Utilization | Clock Period |
-|----------|----------|-------------|-------------|
-| < 100 lines (counter, PWM) | 300×300µm | 50% | 10ns |
-| 100-300 lines (FIFO, UART, SPI) | 500×500µm | 40% | 15ns |
-| 300+ lines (TMR, AES, CPU) | 800×800µm | 35% | 20ns |
-
-### Dual-Mode Formal Verification
-- **Industry SVA**: Generates `property`/`assert property` assertions for commercial EDA tools
-- **Yosys SVA**: Auto-converts to SymbiYosys format for open-source k-induction proofs
-
-### Strict Two-Model Policy
-```
-NVIDIA Cloud (Qwen3-Coder-480B) → Local VeriReason (Privacy/Offline)
-```
-AgentIC enforces a strict policy: High-performance cloud inference via NVIDIA, or fully offline privacy-preserving inference via VeriReason.
-See [User Guide](docs/USER_GUIDE.md) for switching instructions.
+flowchart TD
+    U[User Prompt] --> CLI[CLI Build Command]
+    CLI --> SC[Startup Self-Check]
+    SC -->|pass| INIT[INIT]
+    SC -->|fail + strict| FAIL[FAIL]
 
-### Anti-Hallucination Engine
-- Strips `<think>` blocks, `Thought:`/`Action:` lines, markdown fences
-- Auto-converts `always_comb` → `always @(*)`, `always_ff @(...)` → `always @(...)`
-- Auto-fixes `signed'()` → `$signed()`, type casts, `unique case` → `case`
-- Validates every output contains a valid `module` definition before writing
-- Security scan blocks `$system`, shell commands, and path traversal attacks
+    INIT --> SPEC[SPEC]
+    SPEC --> RTLGEN[RTL_GEN]
+    RTLGEN --> RIGOR[RTL_FIX + Semantic Rigor Gate]
 
-### Web Interface
-AgentIC features a production-grade Web Application designed to make autonomous chip building interactive and visually stunning.
-- **Frontend Stack**: React, TypeScript, Vite
-- **Backend Bridge**: FastAPI integrating directly with the AgentIC Python orchestrator
-- **Key Views**:
-  - **Landing Page**: Immersive 3D silicon chip rendering (`@react-three/fiber`).
-  - **Dashboard**: "Mission Control" providing real-time metrics (WNS, Area, Power) parsed directly from OpenLane `metrics.csv`, complete with AgentIC's intelligent LLM Signoff reporting.
-  - **Design Studio**: Send prompts, view Verilog code (`react-simple-code-editor`), and read live AI agent logs.
-  - **Fabrication**: Provides 2D/3D visualizations of hardened layouts and enables one-click GDSII tapeout downloads.
+    RIGOR -->|syntax/lint/semantic fail| FIXLOOP[Autonomous Fix Loop]
+    FIXLOOP --> RIGOR
 
----
+    RIGOR --> VERIF[VERIFICATION + TB Strict Gate]
+    VERIF -->|sim fail| ANALYZE[Error Analyst + Focused Fix]
+    ANALYZE --> VERIF
 
-## VeriReason: Functioning & Industry Comparison
+    VERIF --> FORMAL[FORMAL_VERIFY]
+    FORMAL --> COV[COVERAGE_CHECK]
+    COV --> REG[REGRESSION]
 
-AgentIC natively supports **VeriReason** (e.g., `VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb`), a highly specialized local LLM finetuned explicitly for RTL coding and formal verification. 
+    REG --> FLOOR[FLOORPLAN]
+    FLOOR --> HARDEN[HARDENING OpenLane]
+    HARDEN --> CONV[CONVERGENCE_REVIEW]
 
-### Core Functioning & Capabilities
-VeriReason drives the AgentIC autonomous loop with hardware-specific reasoning:
-- **Zero-Shot RTL Generation:** Translates natural language architectural specs directly into synthesizable Verilog.
-- **Interactive Terminal Chat:** Powers the CLI `chat` module for interactive, conversational debugging and instant structural queries.
-- **Testbench Crafting:** Authors edge-case aware, self-checking testbenches with precise port mapping and cycle-accurate stimulus.
-- **Autonomous Error Recovery:** Parses `iverilog` errors and Verilator warnings, instantly zeroing in on logic mapping issues instead of generic software fixes.
-- **Hardware Anti-Hallucination:** inherently avoids generalized LLM pitfalls like non-synthesizable `#10` delays, un-driven wires, and mixed blocking/non-blocking assignments.
+    CONV -->|congestion/stagnation| PIVOT[Strategy Pivot]
+    PIVOT --> FLOOR
 
-### Testbench Generation & Error Handling: VeriReason vs. Industry Giants
+    CONV --> SIGN[SIGNOFF DRC/LVS/STA/Power/IR/LEC]
+    SIGN -->|fail| ECO[ECO_PATCH]
+    ECO --> HARDEN
 
-Generating robust, simulation-ready testbenches is typically the highest failure point for general-purpose LLMs. Below is a comparison detailing testbench reliability and error resolution between VeriReason (a specialized 3B model) and Industry Giants (e.g., GPT-4o, Claude 3.5 Sonnet):
+    SIGN -->|pass| OK[SUCCESS]
 
-| Metric | VeriReason (3B Specialized) | Industry Giants (General Massive LLMs)| AgentIC Advantage |
-|--------|-----------------------------|---------------------------------------|-------------------|
-| **Testbench Syntax Errors** | **~8%** | ~20% | Domain-specific training prevents SV/Verilog-2005 syntax mixups. |
-| **Simulation Logic Bug Rate**| **~12%** | ~30% | Natively understands cycle boundaries and reset logic states. |
-| **Auto-Fix Iterations** | **1-2 Attempts** | 3-5 Attempts | Directly maps simulator error logs to exact RTL flaws. |
-| **Un-driven Nets in TB** | **< 1%** | ~15% | Properly initializes test vectors and stimulus variables. |
-| **Cost & Latency** | **$0.00 / Local Native** | High API Costs / Cloud Latency | Infinite free iterative validation on consumer hardware. |
+    FIXLOOP -->|fingerprint repeats / budgets exceeded| FAIL
+    PIVOT -->|pivot cap exceeded| FAIL
+```
 
-VeriReason's GRPO reasoning engine ensures that testbench generation and error resolution hit industry-standard verification constraints significantly faster—and cheaper—than generalized models.
+## Autonomous repair model
 
----
+AgentIC is not just an error printer. It has repair loops with decision logic.
 
-## Performance
+### Loop behavior
 
-| Metric | Golden Templates | LLM-Generated |
-|--------|-----------------|---------------|
-| First-attempt RTL success | ~95% | ~80% |
-| Lint pass rate | ~95% | ~90% (with auto-fix) |
-| Simulation pass (with retries) | ~95% | ~85% |
-| Formal verification | ~70% | ~30% |
-| Build completion | ~95% | ~85% |
+- For compile/sim failures, it classifies cause (**TB vs RTL**) and applies targeted fixes.
+- For large logs, it passes a **structured summary** instead of dumping raw text into prompts.
+- If the same `(state + error + artifact fingerprint)` repeats, it fails closed instead of spinning.
 
-*Benchmarked on simple-to-medium complexity designs (counters, FIFOs, SPI, UART, FSMs, timers).*
+### Convergence behavior
 
----
+- Tracks timing/congestion snapshots per iteration.
+- If WNS stagnates (< 0.01ns improvement for 2 consecutive iterations), triggers strategy pivot:
+  1. timing constraint tune,
+  2. area expansion,
+  3. logic decoupling hint (register slicing),
+  4. fail closed if capped pivots are exhausted.
 
-## AgentIC vs. Traditional EDA (Cadence/Synopsys)
+## Quality gates (strict mode)
 
-AgentIC is designed to dramatically contrast with the legacy segmentation of traditional EDA platforms.
+| Stage | Gate |
+|---|---|
+| Startup | required tools + environment must resolve |
+| RTL Fix | syntax + lint + semantic rigor must pass |
+| Verification | TB contract + simulation must pass |
+| Formal | formal result is blocking in strict mode |
+| Coverage | minimum coverage threshold is blocking |
+| Regression | regression failures are blocking |
+| Signoff | DRC/LVS/STA/power/IR/LEC all contribute to final pass/fail |
 
-| Feature | Legacy Big-Firm Workflow (Cadence / Synopsys) | AgentIC Autonomous Pipeline |
-|---------|----------------------------------------------|-----------------------------|
-| **Error Spotting** | Manual log analysis across fragmented tools (e.g. Verdi, Design Compiler). | Automated log-parsing and intelligent LLM-driven feedback loop catching RTL logic bugs on the fly. |
-| **Workflow** | Segmented, requiring expert TCL scripts for each physical design node. | End-to-end Python Orchestration: Natural Language → GDSII with zero manual intervention. |
-| **Time-to-Market** | Weeks to months for RTL iteration and physical verification. | Minutes to hours. Case study below achieved full tapeout in ~15 minutes. |
-| **Verification** | Lengthy UVM testbench writing and manual SVA creations. | Auto-generated testbenches targeting behavioral bounding, plus native SymbiYosys Formal Assertions. |
-| **Cost** | Multi-million dollar per-seat licensing over expensive cloud/on-prem clusters. | Open-Source EDA toolchain (Icarus, OpenLane) + Model API cost (or fully free via Local LLM). |
+## PDK portability model
 
-### Case Study: APB PWM Controller
-To demonstrate production readiness, an `apb_pwm_controller` (an APB interface bridging a PWM generator) was submitted to AgentIC strictly via a natural language prompt.
-* **RTL Generation:** Valid, synthesizable SystemVerilog generated and auto-fixed in 2 attempts.
-* **Verification:** Auto-generated testbench passed the simulated waveform.
-* **Tapeout (GDSII):** The `harden` workflow yielded a **~5.9 MB GDSII file** in approximately 15 minutes. The OpenLane LVS and DRC logs reported **0 violations**. Static Timing Analysis (STA) on the standard Sky130 nom process corner reported **0 setup violations and 0 hold violations**.
+AgentIC uses an adapter-style OSS-PDK profile model.
 
-### Quantitative Benchmarks: AgentIC vs Manual Legacy Flows
-AgentIC intrinsically reduces logic errors by removing the human-in-the-loop variable during redundant syntax drafting and verification bounding:
+Supported profiles now:
 
-| Metric | Manual Legacy Approach | AgentIC (Autonomous) | Improvement Factor |
-|--------|-----------------------|----------------------|--------------------|
-| **Syntax Error Rate (Pre-Lint)** | ~15-20% | **< 5%** (LLM Pre-Trained) | 4x Reduction |
-| **Linting & DRC Compliance** | Manual Fixes iteratively | **100%** Auto-Resolved | Full Automation |
-| **Logic Bug Escape Rate** | ~5-10% (Relying on human UVM tests) | **< 1%** (Formal Verification) | 10x Accuracy Increase |
-| **Verification Coverage** | Dependent on Engineer Skill | Auto-generated SymbiYosys bounds | Exhaustive State Checks |
-| **Time to Zero-DRC GDSII** | 2-4 Weeks | **< 1 Hour** | > 100x Speedup |
+- `sky130`
+- `gf180`
 
----
+This is **portability support**, not foundry certification.
 
-## Contributor / New Feature Guide
+## CLI quick start
 
-Before adding new intelligent agents or workflows to AgentIC, contributors MUST:
-1. **Read the Full Architecture:** Thoroughly read the *Architecture* and *Key Features* sections in this README. Ensure you understand the state machine (INIT → SPEC → RTL_GEN ... → SUCCESS).
-2. **Strict LLM Isolation:** If your feature requires LLM intervention, remember AgentIC's anti-hallucination paradigm. Wrap the feature so that tools handle syntax first, and LLMs are called *only* on logical boundaries (like the Error Analyst mapping log traces).
-3. **No Hardcoded Paths:** Ensure no physical tool paths (like OpenLane or OpenROAD) are hardcoded in the templates. Rely on config definitions like `os.path.expanduser`.
-4. **Log Observability:** Produce detailed module logs for the new agent matching the pipeline's logging format (`[YOUR_AGENT] Transitioning...`).
+### 1) Standard strict build
 
----
+```bash
+python3 main.py build \
+  --name my_chip \
+  --desc "32-bit APB timer with interrupt" \
+  --full-signoff
+```
 
-## Installation
+### 2) Portable profile selection
 
-### Prerequisites
-- **Linux/WSL2** (Ubuntu 20.04+)
-- **Python 3.10+**
-- **Icarus Verilog**: `sudo apt install iverilog`
-- **Verilator**: `sudo apt install verilator` (for lint checks)
-- **Docker** (for OpenLane physical design)
-- **SymbiYosys** (optional, for formal verification — via [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build))
+```bash
+python3 main.py build \
+  --name my_fifo \
+  --desc "Dual-clock FIFO with status flags" \
+  --pdk-profile sky130 \
+  --strict-gates
+```
 
-### Setup
+### 3) Tune convergence controls
 
 ```bash
-git clone https://github.com/Vickyrrrrrr/AgentIC.git
-cd AgentIC
-python -m venv .venv && source .venv/bin/activate
-pip install -r requirements.txt
+python3 main.py build \
+  --name deep_pipeline \
+  --desc "Pipelined datapath with valid/ready" \
+  --max-pivots 2 \
+  --congestion-threshold 10 \
+  --hierarchical auto
 ```
 
-Create `.env` in the project root:
-```bash
-# At least one LLM API key required
-NVIDIA_API_KEY="nvapi-..."       # Primary (recommended)
-GROQ_API_KEY="gsk_..."           # Fallback
-# OPENAI_API_KEY="sk-..."        # Optional
-
-# Tool paths (defaults usually work)
-# OPENLANE_ROOT="/home/user/OpenLane"
-# PDK_ROOT="/home/user/pdk"
+## Build command options (Tier-1)
+
+```text
+--strict-gates / --no-strict-gates   (default: strict)
+--pdk-profile {sky130,gf180}         (default: sky130)
+--max-pivots N                        (default: 2)
+--congestion-threshold FLOAT          (default: 10.0)
+--hierarchical {auto,off,on}          (default: auto)
 ```
 
----
+Existing options remain (`--skip-openlane`, `--full-signoff`, `--min-coverage`, `--max-retries`, etc.).
 
-## Usage
+## Human-readable architecture internals
 
-## Usage
+### Orchestrator states
 
-> **Full Documentation**: See [User Guide](docs/USER_GUIDE.md) for advanced usage and LLM switching.
+`INIT -> SPEC -> RTL_GEN -> RTL_FIX -> VERIFICATION -> FORMAL_VERIFY -> COVERAGE_CHECK -> REGRESSION -> FLOORPLAN -> HARDENING -> CONVERGENCE_REVIEW -> SIGNOFF -> SUCCESS/FAIL`
 
-### Build a Chip (Full Pipeline)
-```bash
-python main.py build \
-    --name my_spi_controller \
-    --desc "SPI master with configurable clock polarity and 8-bit data width"
-```
+With optional recovery path:
 
-### Quick RTL Iteration (Skip Physical Design)
-```bash
-python main.py build \
-    --name fast_counter \
-    --desc "32-bit counter with overflow detection" \
-    --skip-openlane
-```
+`SIGNOFF fail -> ECO_PATCH -> HARDENING -> CONVERGENCE_REVIEW`
 
-### Complex Design (Full LLM Generation)
-```bash
-python main.py build \
-    --name tmr_processor \
-    --desc "Radiation-hardened ALU with Triple Modular Redundancy and majority voting" \
-    --skip-openlane --max-retries 5
-```
+### Key generated artifacts
 
-### Other Commands
-```bash
-# Simulate existing design
-python main.py simulate --name my_design --max-retries 10
+- `config.tcl` (OpenLane config)
+- `macro_placement.tcl` (floorplan macro scaffold)
+- `<design>.eqy` (LEC config)
+- `<design>_eco_patch.tcl` (ECO patch artifact)
+- `ip_manifest.json` (reusable block metadata)
+- `src/blocks/*.v` (hierarchy-enabled block artifacts)
+- `metircs/<design>/latest.json` (industry benchmark snapshot)
+- `metircs/<design>/latest.md` (human-readable benchmark table)
 
-# Run OpenLane hardening only (auto-generates config.tcl)
-python main.py harden --name my_design
+## CI model
 
+### PR smoke checks
 
-```
+- Python compile check for `src/agentic`
+- Tier-1 unit tests (`tests/test_tier1_upgrade.py`)
 
-### CLI Options
-| Option | Description | Default |
-|--------|-------------|---------|
-| `--name` | Design/module name | Required |
-| `--desc` | Natural language description | Required |
-| `--skip-openlane` | Stop after verification (skip GDSII) | `False` |
-| `--show-thinking` | Display LLM reasoning (CoT) | `False` |
-| `--max-retries` | Max auto-fix attempts per stage | `5` |
+### Nightly full checks
 
----
+- Runs smoke first
+- Attempts full build+signoff path when environment is available
 
-## Project Structure
+Files:
 
-```
-AgentIC/
-├── main.py                          # Entry point
-├── requirements.txt
-├── .env                             # API keys (not committed)
-└── src/agentic/
-    ├── cli.py                       # CLI commands (build, simulate, harden, chat)
-    ├── config.py                    # LLM & path configuration
-    ├── orchestrator.py              # Build state machine & pipeline orchestration
-    ├── agents/
-    │   ├── designer.py              # RTL generation & fixing agent
-    │   ├── testbench_designer.py    # Testbench generation agent
-    │   └── verifier.py              # SVA & error analysis agents
-    ├── golden_lib/
-    │   ├── template_matcher.py      # Keyword + complexity-aware template matching
-    │   └── templates/               # 8 pre-verified RTL + testbench pairs
-    └── tools/
-        └── vlsi_tools.py            # write_verilog, syntax/lint/sim/formal/coverage
-```
+- `.github/workflows/ci.yml`
+- `scripts/ci/smoke.sh`
+- `scripts/ci/nightly_full.sh`
 
----
+## Tests included for Tier-1
 
-## Build Pipeline
+- conflict marker integrity checks
+- semantic gate checks (port shadowing)
+- log parser behavior on large synthetic logs
+- multi-corner STA parser correctness
+- congestion parser correctness
+- loop fingerprint guard behavior
+- hierarchy threshold activation
 
-```
-INIT → SPEC → RTL_GEN → RTL_FIX → VERIFICATION → FORMAL_VERIFY → COVERAGE → HARDENING → SUCCESS
-                  ↑          |           |
-                  └──────────┘           │  (on failure)
-                  ↑                      │
-                  └──────────────────────┘
-```
+Run locally:
 
-### RTL_FIX Stage (Autonomous)
-```
-Syntax Error? → Check if known SV↔Verilog pattern
-    ├── YES → Regex fix instantly (0 LLM calls)
-    └── NO  → LLM Fix Agent (with iverilog hints in prompt)
-
-Lint Passed? → Pre-Synthesis Validation
-    ├── Undriven signal used? → Tie to 0
-    ├── Undriven signal unused? → Remove declaration
-    └── All clean → Proceed to Verification
+```bash
+bash scripts/ci/smoke.sh
 ```
 
-### Verification Stage (Autonomous)
-```
-Simulation failed with "Compilation failed"?
-    ├── TB file in error → Auto-fix SV issues in TB
-    ├── RTL file in error → Auto-fix SV issues in RTL
-    └── Unknown error → LLM Error Analyst → LLM Fixer
-```
+## Installation
 
-If SystemVerilog fails after max retries, the system automatically pivots to Verilog-2005 style and restarts.
+### Prerequisites
 
----
+- Linux / WSL2
+- Python 3.10+
+- Docker
+- Verilator
+- Icarus Verilog (`iverilog`, `vvp`)
+- OpenLane installation
+- OSS CAD tools for formal/LEC (`sby`, `yosys`, `eqy`)
 
-## Troubleshooting
+### Setup
 
-| Problem | Cause | Solution |
-|---------|-------|----------|
-| Lint fails on unused signals | Verilator `-Wall` too strict | Fixed: uses `-Wno-UNUSED` now |
-| `always_comb` errors in iverilog | SV construct not fully supported | Fixed: auto-converted to `always @(*)` |
-| Template used for complex design | Keyword matcher too aggressive | Fixed: complexity indicators block simple templates |
-| Undriven signal in synthesis | LLM declared but forgot to assign | Fixed: pre-synthesis validation auto-fixes |
-| OpenLane deprecated variable error | Old config.tcl format | Fixed: auto-generates modern config |
-| "Docker Error" during hardening | Docker not running or PDK mismatch | Run `docker ps`, check `PDK_ROOT` |
-| "LLM API Failed" | Invalid key or service down | Auto-fallback: NVIDIA → Groq → Local |
-| Simulation timeout | Infinite loop in generated RTL | Increase timeout or simplify description |
+```bash
+git clone https://github.com/Vickyrrrrrr/AgentIC.git
+cd AgentIC
+python3 -m venv .venv
+source .venv/bin/activate
+pip install -r requirements.txt
+```
 
----
+Configure `.env` (minimum):
 
-## Security
+```bash
+# LLM backend
+NVIDIA_API_KEY="..."          # cloud path
+# or
+LLM_BASE_URL="http://localhost:11434"  # local path
+
+# Physical flow roots
+OPENLANE_ROOT="/home/user/OpenLane"
+PDK_ROOT="/home/user/.ciel"
+```
 
-- **Input Sanitization**: Blocks `$system`, shell injection, and path traversal
-- **Air-Gapped Deployment**: Supports fully local LLM inference via Ollama
-- **Auditable Output**: All generated code is human-readable Verilog/SystemVerilog
-- **No Binary Blobs**: Every artifact is inspectable plain text
+## Practical boundaries (current implementation)
 
----
+- ECO and hierarchy are production-oriented scaffolds in this phase, with concrete artifacts and control flow, but not yet a full foundry-tuned incremental optimization stack.
+- Portability means adapter-based OSS-PDK support, not tapeout certification claims.
 
-## License
+## Project layout
+
+```text
+AgentIC/
+├── main.py
+├── src/agentic/
+│   ├── cli.py
+│   ├── config.py
+│   ├── orchestrator.py
+│   ├── agents/
+│   └── tools/vlsi_tools.py
+├── tests/test_tier1_upgrade.py
+├── scripts/ci/
+└── .github/workflows/ci.yml
+```
 
-**Proprietary and Confidential.**
-Copyright (c) 2026 Vicky Nishad. All Rights Reserved.
+## License
 
-You may NOT use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of this software in any form. Any unauthorized use of this software, in whole or in part, without express written permission is strictly prohibited.
+Proprietary and Confidential.
 
-## References
-- [OpenLane Documentation](https://openlane.readthedocs.io/)
-- [SkyWater 130nm PDK](https://skywater-pdk.readthedocs.io/)
-- [SymbiYosys Documentation](https://symbiyosys.readthedocs.io/)
-- [Icarus Verilog](http://iverilog.icarus.com/)
-- [Verilator](https://www.veripool.org/verilator/)
+Copyright (c) 2026 Vicky Nishad.
+All rights reserved.

scripts/ci/nightly_full.sh

@@ -0,0 +1,36 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+REPO_ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)"
+cd "$REPO_ROOT"
+
+# Always run smoke first.
+"$REPO_ROOT/scripts/ci/smoke.sh"
+
+# Full flow requires local EDA/runtime environment and an available LLM backend.
+for bin in docker verilator iverilog vvp; do
+  if ! command -v "$bin" >/dev/null 2>&1; then
+    echo "[nightly] missing required binary: $bin (skipping full flow)"
+    exit 0
+  fi
+done
+
+if [[ ! -d "${OPENLANE_ROOT:-$HOME/OpenLane}" ]]; then
+  echo "[nightly] OPENLANE_ROOT not present (skipping full flow)"
+  exit 0
+fi
+
+if [[ -z "${NVIDIA_API_KEY:-}" && -z "${LLM_BASE_URL:-}" ]]; then
+  echo "[nightly] no LLM backend configured (skipping full flow)"
+  exit 0
+fi
+
+# End-to-end strict run on reference design.
+python3 main.py build \
+  --name ci_nightly_counter \
+  --desc "8-bit counter with enable and async reset" \
+  --full-signoff \
+  --strict-gates \
+  --pdk-profile sky130 \
+  --max-retries 2 \
+  --min-coverage 80

scripts/ci/smoke.sh

@@ -0,0 +1,8 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+REPO_ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)"
+cd "$REPO_ROOT"
+
+python3 -m compileall -q src/agentic
+python3 -m unittest discover -s tests -p 'test_tier1_upgrade.py'

src/agentic/agents/designer.py

@@ -15,19 +15,24 @@ def get_designer_agent(llm, goal, verbose=False, strategy="SV_MODULAR"):
         You write rock-solid Verilog-2005 code that works on any simulator (Icarus, Verilator, commercial).
         You avoid 'logic', 'always_ff', and 'enum'. You use 'reg', 'wire', 'eval', and 'localparam'.
         Your code is simple, flat, and robust."""
-    else:
-        role = "SystemVerilog Architect"
-        backstory = """You are a Principal ASIC Architect at a top-tier semiconductor company (NVIDIA/Intel).
-        You DO NOT write "toy" code or "student" projects. You write PRODUCTION-READY RTL.
-        
+    else:
+        role = "SystemVerilog Architect"
+        backstory = """You are a Principal ASIC Architect at a top-tier semiconductor company (NVIDIA/Intel).
+        You DO NOT write "toy" code or "student" projects. You write PRODUCTION-READY RTL.
+        
         Your Principles:
         1. **Completeness**: You NEVER use "placeholders", "simplified logic", or "magic numbers".
            - If a NPU has 4x4 cells, you implement ALL 16 cells and the data paths to feed them.
            - If a FIFO needs memory, you implement the full pointer logic and mem array.
-        2. **Scalability**: You ALWAYS use `parameter` for dimensions (e.g., `DATA_WIDTH`, `FIFO_DEPTH`).
-        3. **Standard Interfaces**: You use AXI-Stream (`tvalid`, `tready`, `tdata`) or APB/AHB for control.
-        4. **Modern SystemVerilog**: You use `logic`, `always_ff`, `always_comb`, `enum`, and `struct`.
-        """
+        2. **Scalability**: You ALWAYS use `parameter` for dimensions (e.g., `DATA_WIDTH`, `FIFO_DEPTH`).
+        3. **Standard Interfaces**: You use AXI-Stream (`tvalid`, `tready`, `tdata`) or APB/AHB for control.
+        4. **Modern SystemVerilog**: You use `logic`, `always_ff`, `always_comb`, `enum`, and `struct`.
+        5. **Hardware Rigor (Mandatory)**:
+           - **Port Inventory First**: Before internal declarations, list all module ports and avoid any duplicate declaration.
+           - **Port Shadowing Forbidden**: Never redeclare a name that already exists in module ports.
+           - **Bit-Width Safety**: Ensure LHS and RHS bit widths are compatible for every assignment.
+           - **Reset Intent**: Every state-holding register must be explicitly initialized in reset logic.
+        """
 
     return Agent(
         role=role,
@@ -36,4 +41,4 @@ def get_designer_agent(llm, goal, verbose=False, strategy="SV_MODULAR"):
         llm=llm, 
         verbose=verbose,
         allow_delegation=False
-    )
+    )

src/agentic/agents/testbench_designer.py

@@ -30,9 +30,13 @@ def get_testbench_agent(llm, goal, verbose=False, strategy="SV_MODULAR"):
              d. `class Environment` (Depends on Driver, Monitor, Scoreboard)
              e. `module tb` (The top level)
              
-        3. **Self-Checking**: You NEVER rely on waveform inspection. The testbench MUST print "TEST PASSED" only if all checks pass.
-        4. **Coverage**: You use `covergroup` and `bins` to ensure all states and transitions are hit.
-        """
+        3. **Self-Checking**: You NEVER rely on waveform inspection. The testbench MUST print "TEST PASSED" only if all checks pass.
+        4. **Coverage**: You use `covergroup` and `bins` to ensure all states and transitions are hit.
+        5. **Strict Gate Contract**:
+           - Include `class Transaction` and at least one of `class Driver`/`class Monitor`/`class Scoreboard`.
+           - Emit explicit PASS/FAIL markers (`TEST PASSED` and `TEST FAILED` paths).
+           - Return complete compilable testbench code only.
+        """
 
     return Agent(
         role=role,

src/agentic/cli.py

@@ -18,13 +18,18 @@ from rich.panel import Panel
 from rich.progress import Progress, SpinnerColumn, TextColumn
 from crewai import Agent, Task, Crew, LLM
 
-# Local imports
-# Local imports
-<<<<<<< HEAD
-from .config import OPENLANE_ROOT, LLM_MODEL, LLM_BASE_URL, LLM_API_KEY, NVIDIA_CONFIG, LOCAL_CONFIG, GLM5_CONFIG, PDK
-=======
-from .config import OPENLANE_ROOT, LLM_MODEL, LLM_BASE_URL, LLM_API_KEY, NVIDIA_CONFIG, LOCAL_CONFIG, NEMOTRON_CONFIG, PDK
->>>>>>> 1e4247e (Update README with VeriReason benchmarks and functioning details)
+# Local imports
+from .config import (
+    OPENLANE_ROOT,
+    LLM_MODEL,
+    LLM_BASE_URL,
+    LLM_API_KEY,
+    NVIDIA_CONFIG,
+    LOCAL_CONFIG,
+    NEMOTRON_CONFIG,
+    GLM5_CONFIG,
+    PDK,
+)
 from .agents.designer import get_designer_agent
 from .agents.testbench_designer import get_testbench_agent
 from .agents.verifier import get_verification_agent, get_error_analyst_agent
@@ -42,34 +47,29 @@ from .tools.vlsi_tools import (
     write_sby_config,
     run_formal_verification,
     check_physical_metrics,
-    run_lint_check,
-    run_gls_simulation,
-    signoff_check_tool
-)
+    run_lint_check,
+    run_gls_simulation,
+    signoff_check_tool,
+    startup_self_check,
+)
 
 # --- INITIALIZE ---
 app = typer.Typer()
 console = Console()
 
 # Setup Brain
-def get_llm():
+def get_llm():
     """Returns the LLM instance. Strict 3-Model Policy:
        1. NVIDIA Nemotron Cloud (Primary)
        2. NVIDIA Qwen Cloud (High Perf)
        3. VeriReason Local (Fallback)
     """
     
-    configs = [
-<<<<<<< HEAD
-        ("NVIDIA Nemotron Cloud",  NVIDIA_CONFIG),
-        ("Backup GLM5 Cloud",  GLM5_CONFIG),
-        ("VeriReason Local",   LOCAL_CONFIG),
-=======
-        ("NVIDIA Nemotron Cloud", NEMOTRON_CONFIG),   # Primary (Mapped via NEMOTRON_CONFIG in config.py)
-        ("Backup GLM5 Cloud",      NVIDIA_CONFIG), # Backup (Mapped via NVIDIA_CONFIG in config.py)
-        ("VeriReason Local",       LOCAL_CONFIG),
->>>>>>> 1e4247e (Update README with VeriReason benchmarks and functioning details)
-    ]
+    configs = [
+        ("NVIDIA Nemotron Cloud", NEMOTRON_CONFIG),
+        ("Backup GLM5 Cloud", GLM5_CONFIG),
+        ("VeriReason Local", LOCAL_CONFIG),
+    ]
     
     for name, cfg in configs:
         key = cfg.get("api_key", "")
@@ -107,9 +107,22 @@ def get_llm():
             console.print(f"[yellow]⚠ {name} init failed: {e}[/yellow]")
     
     # Critical Failure if both fail
-    console.print(f"[bold red]CRITICAL: No valid LLM backend found.[/bold red]")
-    console.print(f"Please set [bold]NVIDIA_API_KEY[/bold] for Cloud or configure [bold]LLM_BASE_URL[/bold] for Local.")
-    raise typer.Exit(1)
+    console.print(f"[bold red]CRITICAL: No valid LLM backend found.[/bold red]")
+    console.print(f"Please set [bold]NVIDIA_API_KEY[/bold] for Cloud or configure [bold]LLM_BASE_URL[/bold] for Local.")
+    raise typer.Exit(1)
+
+
+def run_startup_diagnostics(strict: bool = True):
+    diag = startup_self_check()
+    ok = bool(diag.get("ok", False))
+    status = "[green]PASS[/green]" if ok else "[red]FAIL[/red]"
+    console.print(Panel(f"Startup Toolchain Check: {status}", title="🔧 Environment"))
+    if not ok:
+        for check in diag.get("checks", []):
+            if not check.get("ok"):
+                console.print(f"  [red]✗ {check.get('tool')}[/red] -> {check.get('resolved')}")
+        if strict:
+            raise typer.Exit(1)
 
 
 @app.command()
@@ -420,15 +433,20 @@ def harden(
 
 # --- THE BUILD COMMAND ---
 @app.command()
-def build(
-    name: str = typer.Option(..., "--name", "-n", help="Design name (e.g., counter)"),
-    desc: str = typer.Option(..., "--desc", "-d", help="Natural language description"),
-    max_retries: int = typer.Option(5, "--max-retries", "-r", min=0, help="Max auto-fix retries for RTL/TB/sim failures"),
+def build(
+    name: str = typer.Option(..., "--name", "-n", help="Design name (e.g., counter)"),
+    desc: str = typer.Option(..., "--desc", "-d", help="Natural language description"),
+    max_retries: int = typer.Option(5, "--max-retries", "-r", min=0, help="Max auto-fix retries for RTL/TB/sim failures"),
     skip_openlane: bool = typer.Option(False, "--skip-openlane", help="Stop after simulation (no RTL→GDSII hardening)"),
-    show_thinking: bool = typer.Option(False, "--show-thinking", help="Print DeepSeek <think> reasoning for each generation/fix step"),
-    full_signoff: bool = typer.Option(False, "--full-signoff", help="Run full industry signoff (formal + coverage + regression + DRC/LVS)"),
-    min_coverage: float = typer.Option(80.0, "--min-coverage", help="Minimum line coverage percentage to pass verification")
-):
+    show_thinking: bool = typer.Option(False, "--show-thinking", help="Print DeepSeek <think> reasoning for each generation/fix step"),
+    full_signoff: bool = typer.Option(False, "--full-signoff", help="Run full industry signoff (formal + coverage + regression + DRC/LVS)"),
+    min_coverage: float = typer.Option(80.0, "--min-coverage", help="Minimum line coverage percentage to pass verification"),
+    strict_gates: bool = typer.Option(True, "--strict-gates/--no-strict-gates", help="Enable strict fail-closed gating"),
+    pdk_profile: str = typer.Option("sky130", "--pdk-profile", help="PDK adapter profile: sky130 or gf180"),
+    max_pivots: int = typer.Option(2, "--max-pivots", min=0, help="Maximum strategy pivots before fail-closed"),
+    congestion_threshold: float = typer.Option(10.0, "--congestion-threshold", help="Routing congestion threshold (%)"),
+    hierarchical: str = typer.Option("auto", "--hierarchical", help="Hierarchical mode: auto, off, on"),
+):
     """Build a chip from natural language description (Autonomous Orchestrator 2.0)."""
     
     from .orchestrator import BuildOrchestrator
@@ -441,18 +459,24 @@ def build(
         title="🚀 Starting Autonomous Orchestrator"
     ))
 
-    llm = get_llm()
+    run_startup_diagnostics(strict=strict_gates)
+    llm = get_llm()
     
     orchestrator = BuildOrchestrator(
         name=name,
         desc=desc,
         llm=llm,
         max_retries=max_retries,
-        verbose=show_thinking,
-        skip_openlane=skip_openlane,
-        full_signoff=full_signoff,
-        min_coverage=min_coverage
-    )
+        verbose=show_thinking,
+        skip_openlane=skip_openlane,
+        full_signoff=full_signoff,
+        min_coverage=min_coverage,
+        strict_gates=strict_gates,
+        pdk_profile=pdk_profile,
+        max_pivots=max_pivots,
+        congestion_threshold=congestion_threshold,
+        hierarchical_mode=hierarchical,
+    )
     
     orchestrator.run()
 
@@ -466,4 +490,4 @@ def verify(name: str = typer.Argument(..., help="Design name to verify")):
 
 
 if __name__ == "__main__":
-    app()
+    app()

src/agentic/config.py

@@ -1,4 +1,5 @@
 import os
+from typing import Dict, Any, Optional
 from dotenv import load_dotenv
 
 # Project Paths
@@ -10,54 +11,119 @@ OPENLANE_ROOT = os.environ.get("OPENLANE_ROOT", os.path.expanduser("~/OpenLane")
 DESIGNS_DIR = os.path.join(OPENLANE_ROOT, "designs")
 SCRIPTS_DIR = os.path.join(WORKSPACE_ROOT, "scripts")
 
-# Strict Three-Model Policy:
-<<<<<<< HEAD
-# 1. Backup GLM5 Cloud
-GLM5_CONFIG = {
-    "model": os.environ.get("BACKUP_MODEL", "openai/z-ai/glm5"),
-    "base_url": os.environ.get("BACKUP_BASE_URL", "https://integrate.api.nvidia.com/v1"),
-    "api_key": os.environ.get("NVIDIA_API_KEY", "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")
-}
-
-# 2. NVIDIA Qwen Cloud (High Performance) -> Now nemotron-3-nano
-NVIDIA_CONFIG = {
-    "model": os.environ.get("NVIDIA_MODEL", "nvidia/nemotron-3-nano-30b-a3b"),
-    "base_url": os.environ.get("NVIDIA_BASE_URL", "https://integrate.api.nvidia.com/v1"),
-    "api_key": os.environ.get("NVIDIA_API_KEY", "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")
-=======
-# 1. NVIDIA Nemotron Cloud (Primary) - Integrated into AgentIC ReAct Loop
+# LLM backends (env-only secrets)
 NEMOTRON_CONFIG = {
     "model": os.environ.get("NVIDIA_MODEL", "nvidia/nemotron-3-nano-30b-a3b"),
     "base_url": os.environ.get("NVIDIA_BASE_URL", "https://integrate.api.nvidia.com/v1"),
-    "api_key": os.environ.get("NVIDIA_API_KEY") # API Key hidden for security
+    "api_key": os.environ.get("NVIDIA_API_KEY", ""),
 }
 
-# 2. Backup GLM5 Cloud
-NVIDIA_CONFIG = {
+GLM5_CONFIG = {
     "model": os.environ.get("BACKUP_MODEL", "openai/z-ai/glm5"),
     "base_url": os.environ.get("BACKUP_BASE_URL", "https://integrate.api.nvidia.com/v1"),
-    "api_key": os.environ.get("NVIDIA_API_KEY") # API Key hidden for security
->>>>>>> 1e4247e (Update README with VeriReason benchmarks and functioning details)
+    "api_key": os.environ.get("BACKUP_API_KEY", os.environ.get("NVIDIA_API_KEY", "")),
 }
 
-# 3. VeriReason Local (Fallback)
-# Explicitly uses the VeriReason model defined in .env
 LOCAL_CONFIG = {
-    "model": os.environ.get("LLM_MODEL", "ollama/hf.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF:Q4_K_M"),
+    "model": os.environ.get(
+        "LLM_MODEL",
+        "ollama/hf.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF:Q4_K_M",
+    ),
     "base_url": os.environ.get("LLM_BASE_URL", "http://localhost:11434"),
-    "api_key": os.environ.get("LLM_API_KEY", "NA")
+    "api_key": os.environ.get("LLM_API_KEY", "NA"),
 }
 
-# Expose 'active' config variables (Defaults to Local if NVIDIA missing, but CLI handles logic)
+# Backward-compat alias used by parts of the codebase/docs
+NVIDIA_CONFIG = GLM5_CONFIG
+
+# Expose active defaults (CLI chooses concrete backend)
 LLM_MODEL = LOCAL_CONFIG["model"]
 LLM_BASE_URL = LOCAL_CONFIG["base_url"]
 LLM_API_KEY = LOCAL_CONFIG["api_key"]
 
+# Portable OSS-PDK profiles (adapter-style)
+PDK_PROFILES: Dict[str, Dict[str, Any]] = {
+    "sky130": {
+        "pdk": "sky130A",
+        "std_cell_library": "sky130_fd_sc_hd",
+        "default_clock_period": "10.0",
+    },
+    "gf180": {
+        "pdk": "gf180mcuC",
+        "std_cell_library": "gf180mcu_fd_sc_mcu7t5v0",
+        "default_clock_period": "15.0",
+    },
+}
+
+DEFAULT_PDK_PROFILE = os.environ.get("PDK_PROFILE", "sky130").strip().lower()
+if DEFAULT_PDK_PROFILE not in PDK_PROFILES:
+    DEFAULT_PDK_PROFILE = "sky130"
+
 # Tool Settings
-PDK_ROOT = os.environ.get('PDK_ROOT', os.path.expanduser('~/.ciel'))
-PDK = os.environ.get('PDK', 'sky130A') # Default to SkyWater 130nm
+PDK_ROOT = os.environ.get("PDK_ROOT", os.path.expanduser("~/.ciel"))
+PDK = os.environ.get("PDK", PDK_PROFILES[DEFAULT_PDK_PROFILE]["pdk"])
 OPENLANE_IMAGE = "ghcr.io/the-openroad-project/openlane:ff5509f65b17bfa4068d5336495ab1718987ff69-amd64"
 
-# OSS CAD Suite (SymbiYosys, Yosys) - Self-contained within AgentIC
-OSS_CAD_SUITE_ROOT = os.environ.get('OSS_CAD_SUITE_HOME', os.path.join(WORKSPACE_ROOT, 'oss-cad-suite'))
-SBY_BIN = os.path.join(OSS_CAD_SUITE_ROOT, 'bin', 'sby')
+
+def _resolve_tool_binary(bin_name: str, env_var: Optional[str] = None) -> str:
+    """Resolve tool binary using configured roots before PATH.
+
+    Fallback order:
+    1) Explicit env var for that tool (if provided)
+    2) OSS_CAD_SUITE_HOME/bin
+    3) WORKSPACE_ROOT/oss-cad-suite/bin
+    4) /home/vickynishad/oss-cad-suite/bin
+    5) bin_name from PATH
+    """
+    explicit = os.environ.get(env_var, "").strip() if env_var else ""
+    if explicit and os.path.exists(explicit):
+        return explicit
+
+    roots = []
+    oss_home = os.environ.get("OSS_CAD_SUITE_HOME", "").strip()
+    if oss_home:
+        roots.append(oss_home)
+    roots.append(os.path.join(WORKSPACE_ROOT, "oss-cad-suite"))
+    roots.append("/home/vickynishad/oss-cad-suite")
+
+    for root in roots:
+        candidate = os.path.join(root, "bin", bin_name)
+        if os.path.exists(candidate):
+            return candidate
+
+    return bin_name
+
+
+OSS_CAD_SUITE_ROOT = os.environ.get("OSS_CAD_SUITE_HOME", os.path.join(WORKSPACE_ROOT, "oss-cad-suite"))
+SBY_BIN = _resolve_tool_binary("sby", env_var="SBY_BIN")
+YOSYS_BIN = _resolve_tool_binary("yosys", env_var="YOSYS_BIN")
+EQY_BIN = _resolve_tool_binary("eqy", env_var="EQY_BIN")
+
+
+def get_pdk_profile(profile: str) -> Dict[str, Any]:
+    key = (profile or DEFAULT_PDK_PROFILE).strip().lower()
+    if key not in PDK_PROFILES:
+        key = "sky130"
+    data = dict(PDK_PROFILES[key])
+    data["profile"] = key
+    return data
+
+
+def get_toolchain_diagnostics() -> Dict[str, Any]:
+    """Return resolved toolchain paths and existence info for startup checks."""
+    bins = {
+        "sby": SBY_BIN,
+        "yosys": YOSYS_BIN,
+        "eqy": EQY_BIN,
+    }
+    return {
+        "workspace_root": WORKSPACE_ROOT,
+        "openlane_root": OPENLANE_ROOT,
+        "pdk_root": PDK_ROOT,
+        "pdk": PDK,
+        "oss_cad_suite_home": os.environ.get("OSS_CAD_SUITE_HOME", ""),
+        "bins": {
+            name: {"path": path, "exists": os.path.exists(path) if os.path.isabs(path) else False}
+            for name, path in bins.items()
+        },
+    }

src/agentic/orchestrator.py

@@ -3,13 +3,16 @@ import time
 import logging
 import os
 import re
+import hashlib
+import json
+from dataclasses import dataclass, asdict
 from typing import Optional, Dict, Any, List
 from rich.console import Console
 from rich.panel import Panel
 from crewai import Agent, Task, Crew, LLM
 
 # Local imports
-from .config import OPENLANE_ROOT, LLM_MODEL, LLM_BASE_URL, LLM_API_KEY, PDK
+from .config import OPENLANE_ROOT, LLM_MODEL, LLM_BASE_URL, LLM_API_KEY, PDK, WORKSPACE_ROOT, get_pdk_profile
 from .agents.designer import get_designer_agent
 from .agents.testbench_designer import get_testbench_agent
 from .agents.verifier import get_verification_agent, get_error_analyst_agent, get_regression_agent
@@ -34,7 +37,13 @@ from .tools.vlsi_tools import (
     check_physical_metrics,
     run_cdc_check,
     generate_design_doc,
-    convert_sva_to_yosys
+    convert_sva_to_yosys,
+    startup_self_check,
+    run_semantic_rigor_check,
+    parse_eda_log_summary,
+    parse_congestion_metrics,
+    run_eqy_lec,
+    apply_eco_patch,
 )
 
 console = Console()
@@ -52,13 +61,49 @@ class BuildState(enum.Enum):
     FORMAL_VERIFY = "Formal Property Verification"
     COVERAGE_CHECK = "Coverage Analysis"
     REGRESSION = "Regression Testing"
+    FLOORPLAN = "Floorplanning"
     HARDENING = "GDSII Hardening"
+    CONVERGENCE_REVIEW = "Convergence Review"
+    ECO_PATCH = "ECO Patch"
     SIGNOFF = "DRC/LVS Signoff"
     SUCCESS = "Build Complete"
     FAIL = "Build Failed"
 
+
+@dataclass
+class ConvergenceSnapshot:
+    iteration: int
+    wns: float
+    tns: float
+    congestion: float
+    area_um2: float
+    power_w: float
+
+
+@dataclass
+class BuildHistory:
+    state: str
+    message: str
+    timestamp: float
+
 class BuildOrchestrator:
-    def __init__(self, name: str, desc: str, llm: LLM, max_retries: int = 5, verbose: bool = True, skip_openlane: bool = False, full_signoff: bool = False, min_coverage: float = 80.0):
+    def __init__(
+        self,
+        name: str,
+        desc: str,
+        llm: LLM,
+        max_retries: int = 5,
+        verbose: bool = True,
+        skip_openlane: bool = False,
+        full_signoff: bool = False,
+        min_coverage: float = 80.0,
+        strict_gates: bool = True,
+        pdk_profile: str = "sky130",
+        max_pivots: int = 2,
+        congestion_threshold: float = 10.0,
+        hierarchical_mode: str = "auto",
+        global_step_budget: int = 120,
+    ):
         self.name = name
         self.desc = desc
         self.llm = llm
@@ -67,10 +112,25 @@ class BuildOrchestrator:
         self.skip_openlane = skip_openlane
         self.full_signoff = full_signoff
         self.min_coverage = min_coverage
+        self.strict_gates = strict_gates
+        self.pdk_profile = get_pdk_profile(pdk_profile)
+        self.max_pivots = max_pivots
+        self.congestion_threshold = congestion_threshold
+        self.hierarchical_mode = hierarchical_mode
+        self.global_step_budget = global_step_budget
         
         self.state = BuildState.INIT
         self.strategy = BuildStrategy.SV_MODULAR
         self.retry_count = 0
+        self.state_retry_counts: Dict[str, int] = {}
+        self.failure_fingerprint_history: Dict[str, int] = {}
+        self.global_step_count = 0
+        self.pivot_count = 0
+        self.strategy_pivot_stage = 0
+        self.convergence_history: List[ConvergenceSnapshot] = []
+        self.build_history: List[BuildHistory] = []
+        self.floorplan_attempts = 0
+        self.eco_attempts = 0
         self.artifacts = {}  # Store paths to gathered files
         self.history = []    # Log of state transitions and errors
         self.errors = []     # List of error messages
@@ -94,7 +154,9 @@ class BuildOrchestrator:
 
     def log(self, message: str, refined: bool = False):
         """Logs a message to the console (if refined) and file (always)."""
-        self.history.append({"state": self.state.name, "msg": message, "time": time.time()})
+        now = time.time()
+        self.history.append({"state": self.state.name, "msg": message, "time": now})
+        self.build_history.append(BuildHistory(state=self.state.name, message=message, timestamp=now))
         
         # File Log
         if hasattr(self, 'logger'):
@@ -113,6 +175,32 @@ class BuildOrchestrator:
         self.state = new_state
         if not preserve_retries:
             self.retry_count = 0  # Reset retries on state change
+            self.state_retry_counts[new_state.name] = 0
+
+    def _bump_state_retry(self) -> int:
+        count = self.state_retry_counts.get(self.state.name, 0) + 1
+        self.state_retry_counts[self.state.name] = count
+        return count
+
+    def _artifact_fingerprint(self) -> str:
+        rtl = self.artifacts.get("rtl_code", "")
+        tb = ""
+        tb_path = self.artifacts.get("tb_path", "")
+        if tb_path and os.path.exists(tb_path):
+            try:
+                with open(tb_path, "r") as f:
+                    tb = f.read()
+            except OSError:
+                tb = ""
+        digest = hashlib.sha256((rtl + "\n" + tb).encode("utf-8", errors="ignore")).hexdigest()
+        return digest[:16]
+
+    def _record_failure_fingerprint(self, error_text: str) -> bool:
+        base = f"{self.state.name}|{error_text[:500]}|{self._artifact_fingerprint()}"
+        fp = hashlib.sha256(base.encode("utf-8", errors="ignore")).hexdigest()
+        count = self.failure_fingerprint_history.get(fp, 0) + 1
+        self.failure_fingerprint_history[fp] = count
+        return count >= 2
 
     def run(self):
         """Main execution loop."""
@@ -120,6 +208,11 @@ class BuildOrchestrator:
         
         try:
             while self.state != BuildState.SUCCESS and self.state != BuildState.FAIL:
+                self.global_step_count += 1
+                if self.global_step_count > self.global_step_budget:
+                    self.log(f"Global step budget exceeded ({self.global_step_budget}). Failing closed.", refined=True)
+                    self.state = BuildState.FAIL
+                    break
                 if self.state == BuildState.INIT:
                     self.do_init()
                 elif self.state == BuildState.SPEC:
@@ -136,8 +229,14 @@ class BuildOrchestrator:
                     self.do_coverage_check()
                 elif self.state == BuildState.REGRESSION:
                     self.do_regression()
+                elif self.state == BuildState.FLOORPLAN:
+                    self.do_floorplan()
                 elif self.state == BuildState.HARDENING:
                     self.do_hardening()
+                elif self.state == BuildState.CONVERGENCE_REVIEW:
+                    self.do_convergence_review()
+                elif self.state == BuildState.ECO_PATCH:
+                    self.do_eco_patch()
                 elif self.state == BuildState.SIGNOFF:
                     self.do_signoff()
                 else:
@@ -151,7 +250,10 @@ class BuildOrchestrator:
             self.state = BuildState.FAIL
 
         if self.state == BuildState.SUCCESS:
-            import json
+            try:
+                self._save_industry_benchmark_metrics()
+            except Exception as e:
+                self.log(f"Benchmark metrics export warning: {e}", refined=True)
             # Create a clean summary of just the paths
             summary = {k: v for k, v in self.artifacts.items() if 'code' not in k and 'spec' not in k}
             
@@ -170,6 +272,19 @@ class BuildOrchestrator:
             # Setup directories, check tools
             self.artifacts['root'] = f"{OPENLANE_ROOT}/designs/{self.name}"
             self.setup_logger() # Setup logging to file
+            self.artifacts["pdk_profile"] = self.pdk_profile
+            self.log(
+                f"PDK profile: {self.pdk_profile.get('profile')} "
+                f"(PDK={self.pdk_profile.get('pdk')}, LIB={self.pdk_profile.get('std_cell_library')})",
+                refined=True,
+            )
+            diag = startup_self_check()
+            self.artifacts["startup_check"] = diag
+            self.logger.info(f"STARTUP SELF CHECK: {diag}")
+            if self.strict_gates and not diag.get("ok", False):
+                self.log("Startup self-check failed in strict mode.", refined=True)
+                self.state = BuildState.FAIL
+                return
             time.sleep(1) # Visual pause
             self.transition(BuildState.SPEC)
 
@@ -216,6 +331,7 @@ Outputs:
             - **NO PLACEHOLDERS**: Do not write `// Simplified check` or `assign data = 0;`. Implement the ACTUAL LOGIC.
             - **NO PARTIAL IMPLEMENTATIONS**: If it's a 4x4 array, enable ALL cells.
             - **NO HARDCODING**: Use `parameter` for widths and depths.
+            - **HARDWARE RIGOR**: Validate bit-width compatibility on every assignment and never shadow module ports with internal signals.
             """
         else:
             return """
@@ -291,6 +407,204 @@ Outputs:
         header_match = re.search(r'(module\s+\w+[\s\S]*?;)', rtl_code)
         return header_match.group(1) if header_match else "Could not extract ports — see full RTL below."
 
+    @staticmethod
+    def _tb_meets_strict_contract(tb_code: str, strategy: BuildStrategy) -> tuple:
+        missing = []
+        text = tb_code or ""
+        if "TEST PASSED" not in text:
+            missing.append("Missing TEST PASSED marker")
+        if "TEST FAILED" not in text:
+            missing.append("Missing TEST FAILED marker")
+        if strategy == BuildStrategy.SV_MODULAR:
+            if "class Transaction" not in text:
+                missing.append("Missing class Transaction")
+            if all(token not in text for token in ["class Driver", "class Monitor", "class Scoreboard"]):
+                missing.append("Missing transaction flow classes")
+        return len(missing) == 0, missing
+
+    def _condense_failure_log(self, raw_text: str, kind: str) -> str:
+        if not raw_text:
+            return raw_text
+        if len(raw_text) < 12000:
+            return raw_text
+        src_dir = f"{OPENLANE_ROOT}/designs/{self.name}/src"
+        os.makedirs(src_dir, exist_ok=True)
+        log_path = os.path.join(src_dir, f"{self.name}_{kind}_failure.log")
+        try:
+            with open(log_path, "w") as f:
+                f.write(raw_text)
+            summary = parse_eda_log_summary(log_path, kind=kind, top_n=10)
+            return f"LOG_SUMMARY: {summary}"
+        except OSError:
+            return raw_text[-12000:]
+
+    def _evaluate_hierarchy(self, rtl_code: str):
+        module_count = len(re.findall(r"\bmodule\b", rtl_code))
+        rtl_lines = len([l for l in rtl_code.splitlines() if l.strip()])
+        if self.hierarchical_mode == "on":
+            enabled = True
+        elif self.hierarchical_mode == "off":
+            enabled = False
+        else:
+            enabled = module_count >= 3 and rtl_lines >= 600
+        self.artifacts["hierarchy_plan"] = {
+            "mode": self.hierarchical_mode,
+            "enabled": enabled,
+            "module_count": module_count,
+            "rtl_lines": rtl_lines,
+            "thresholds": {"module_count": 3, "rtl_lines": 600},
+        }
+        if enabled:
+            self.log("Hierarchical synthesis planner: enabled.", refined=True)
+        else:
+            self.log("Hierarchical synthesis planner: disabled.", refined=True)
+
+    def _write_ip_manifest(self):
+        rtl_path = self.artifacts.get("rtl_path", "")
+        if not rtl_path or not os.path.exists(rtl_path):
+            return
+        with open(rtl_path, "r") as f:
+            rtl_code = f.read()
+        modules = re.findall(r"module\s+([A-Za-z_]\w*)", rtl_code)
+        params = re.findall(r"parameter\s+([A-Za-z_]\w*)\s*=\s*([^,;\)]+)", rtl_code)
+        ports = re.findall(
+            r"\b(input|output|inout)\s+(?:reg|wire|logic)?\s*(?:\[[^\]]+\])?\s*([A-Za-z_]\w*)",
+            rtl_code,
+        )
+        manifest = {
+            "ip_name": self.name,
+            "version": "1.0.0",
+            "clock_reset": {"clock": "clk", "reset": "rst_n", "reset_active_low": True},
+            "modules": modules,
+            "dependencies": [m for m in modules if m != self.name],
+            "parameters": [{"name": n, "default": v.strip()} for n, v in params],
+            "ports": [{"direction": d, "name": n} for d, n in ports],
+            "verification_status": {
+                "simulation": "PASS" if self.state == BuildState.SUCCESS else "UNKNOWN",
+                "formal": self.artifacts.get("formal_result", "UNKNOWN"),
+                "signoff": self.artifacts.get("signoff_result", "UNKNOWN"),
+            },
+            "ipxact_bridge_ready": True,
+        }
+        out = os.path.join(OPENLANE_ROOT, "designs", self.name, "ip_manifest.json")
+        with open(out, "w") as f:
+            json.dump(manifest, f, indent=2)
+        self.artifacts["ip_manifest"] = out
+
+    def _build_industry_benchmark_snapshot(self) -> Dict[str, Any]:
+        metrics = self.artifacts.get("metrics", {}) or {}
+        sta = self.artifacts.get("sta_signoff", {}) or {}
+        power = self.artifacts.get("power_signoff", {}) or {}
+        signoff = self.artifacts.get("signoff", {}) or {}
+        congestion = self.artifacts.get("congestion", {}) or {}
+        coverage = self.artifacts.get("coverage", {}) or {}
+        regression_results = self.artifacts.get("regression_results", []) or []
+
+        regression_pass = sum(1 for x in regression_results if x.get("status") == "PASS")
+        regression_total = len(regression_results)
+
+        snapshot = {
+            "design_name": self.name,
+            "generated_at_epoch": int(time.time()),
+            "build_status": self.state.name,
+            "signoff_result": self.artifacts.get("signoff_result", "UNKNOWN"),
+            "pdk_profile": self.pdk_profile.get("profile"),
+            "pdk": self.pdk_profile.get("pdk"),
+            "std_cell_library": self.pdk_profile.get("std_cell_library"),
+            "industry_benchmark": {
+                "area_um2": metrics.get("chip_area_um2", 0.0),
+                "cell_count": metrics.get("area", 0.0),
+                "utilization_pct": metrics.get("utilization", 0.0),
+                "timing_wns_ns": sta.get("worst_setup", metrics.get("timing_wns", 0.0)),
+                "timing_tns_ns": metrics.get("timing_tns", 0.0),
+                "hold_slack_ns": sta.get("worst_hold", 0.0),
+                "drc_violations": signoff.get("drc_violations", -1),
+                "lvs_errors": signoff.get("lvs_errors", -1),
+                "antenna_violations": signoff.get("antenna_violations", -1),
+                "total_power_mw": float(power.get("total_power_w", 0.0)) * 1000.0,
+                "internal_power_mw": float(power.get("internal_power_w", 0.0)) * 1000.0,
+                "switching_power_mw": float(power.get("switching_power_w", 0.0)) * 1000.0,
+                "leakage_power_uw": float(power.get("leakage_power_w", 0.0)) * 1e6,
+                "irdrop_vpwr_mv": float(power.get("irdrop_max_vpwr", 0.0)) * 1000.0,
+                "irdrop_vgnd_mv": float(power.get("irdrop_max_vgnd", 0.0)) * 1000.0,
+                "congestion_usage_pct": congestion.get("total_usage_pct", 0.0),
+                "congestion_overflow": congestion.get("total_overflow", 0),
+                "coverage_line_pct": coverage.get("line_pct", 0.0),
+                "formal_result": self.artifacts.get("formal_result", "UNKNOWN"),
+                "lec_result": self.artifacts.get("lec_result", "UNKNOWN"),
+                "regression_passed": regression_pass,
+                "regression_total": regression_total,
+                "clock_period_ns": self.artifacts.get("clock_period_override", self.pdk_profile.get("default_clock_period")),
+                "pivots_used": self.pivot_count,
+                "global_steps": self.global_step_count,
+            },
+        }
+        return snapshot
+
+    def _save_industry_benchmark_metrics(self):
+        """Write benchmark metrics after successful chip creation to metircs/."""
+        snapshot = self._build_industry_benchmark_snapshot()
+        metrics_root = os.path.join(WORKSPACE_ROOT, "metircs")
+        design_dir = os.path.join(metrics_root, self.name)
+        os.makedirs(design_dir, exist_ok=True)
+
+        stamp = time.strftime("%Y%m%d_%H%M%S")
+        json_path = os.path.join(design_dir, f"{self.name}_industry_benchmark_{stamp}.json")
+        md_path = os.path.join(design_dir, f"{self.name}_industry_benchmark_{stamp}.md")
+        latest_json = os.path.join(design_dir, "latest.json")
+        latest_md = os.path.join(design_dir, "latest.md")
+
+        with open(json_path, "w") as f:
+            json.dump(snapshot, f, indent=2)
+
+        ib = snapshot["industry_benchmark"]
+        lines = [
+            f"# {self.name} Industry Benchmark Metrics",
+            "",
+            f"- Generated At (epoch): `{snapshot['generated_at_epoch']}`",
+            f"- Build Status: `{snapshot['build_status']}`",
+            f"- Signoff Result: `{snapshot['signoff_result']}`",
+            f"- PDK Profile: `{snapshot['pdk_profile']}`",
+            "",
+            "| Metric | Value |",
+            "|---|---|",
+        ]
+        for k, v in ib.items():
+            lines.append(f"| `{k}` | `{v}` |")
+        with open(md_path, "w") as f:
+            f.write("\n".join(lines) + "\n")
+
+        # Keep a latest pointer as plain copied files for easy consumption.
+        with open(latest_json, "w") as f:
+            json.dump(snapshot, f, indent=2)
+        with open(latest_md, "w") as f:
+            f.write("\n".join(lines) + "\n")
+
+        self.artifacts["benchmark_metrics_json"] = json_path
+        self.artifacts["benchmark_metrics_md"] = md_path
+        self.artifacts["benchmark_metrics_dir"] = design_dir
+        self.log(f"Saved industry benchmark metrics to {design_dir}", refined=True)
+
+    def _emit_hierarchical_block_artifacts(self):
+        plan = self.artifacts.get("hierarchy_plan", {})
+        if not plan.get("enabled"):
+            return
+        rtl_code = self.artifacts.get("rtl_code", "")
+        block_dir = os.path.join(OPENLANE_ROOT, "designs", self.name, "src", "blocks")
+        os.makedirs(block_dir, exist_ok=True)
+        modules = re.findall(r"(module\s+[A-Za-z_]\w*[\s\S]*?endmodule)", rtl_code)
+        block_files = []
+        for mod in modules:
+            m = re.search(r"module\s+([A-Za-z_]\w*)", mod)
+            if not m:
+                continue
+            mod_name = m.group(1)
+            path = os.path.join(block_dir, f"{mod_name}.v")
+            with open(path, "w") as f:
+                f.write(mod.strip() + "\n")
+            block_files.append(path)
+        self.artifacts["hierarchy_blocks"] = block_files
+
     def do_rtl_gen(self):
         # Check Golden Reference Library for a matching template
         from .golden_lib import get_best_template
@@ -333,6 +647,9 @@ SPECIFICATION:
 STRATEGY GUIDELINES:
 {strategy_prompt}
 
+LOGIC DECOUPLING HINT:
+{self.artifacts.get('logic_decoupling_hint', 'N/A')}
+
 CRITICAL RULES:
 1. Module name must be "{self.name}"
 2. Async active-low reset `rst_n`
@@ -362,6 +679,8 @@ CRITICAL RULES:
         # Store the CLEANED code (read back from file), not raw LLM output
         with open(path, 'r') as f:
             self.artifacts['rtl_code'] = f.read()
+        self._evaluate_hierarchy(self.artifacts['rtl_code'])
+        self._emit_hierarchical_block_artifacts()
         self.transition(BuildState.RTL_FIX)
 
     def do_rtl_fix(self):
@@ -393,9 +712,23 @@ CRITICAL RULES:
                         self.artifacts['rtl_code'] = f.read()
                     # Re-check syntax after fix (stay in RTL_FIX)
                     return
-                
-                self.transition(BuildState.VERIFICATION)
-                return
+
+                sem_ok, sem_report = run_semantic_rigor_check(path)
+                self.logger.info(f"SEMANTIC RIGOR: {sem_report}")
+                if not sem_ok:
+                    if self.strict_gates:
+                        self.log("Semantic rigor gate failed. Routing back to RTL fix.", refined=True)
+                        errors = f"SEMANTIC_RIGOR_FAILURE: {sem_report}"
+                    else:
+                        self.log("Semantic rigor warnings detected (non-blocking).", refined=True)
+                        self.artifacts["semantic_report"] = sem_report
+                        self.transition(BuildState.VERIFICATION)
+                        return
+                else:
+                    self.artifacts["semantic_report"] = sem_report
+                    self.transition(BuildState.VERIFICATION)
+                    return
+
             else:
                 self.log(f"Lint Failed. Check log for details.", refined=True)
                 errors = f"SYNTAX OK, BUT LINT FAILED:\n{lint_report}"
@@ -406,6 +739,10 @@ CRITICAL RULES:
 
         # Handle Syntax/Lint Errors that need LLM
         self.logger.info(f"SYNTAX/LINT ERRORS:\n{errors}")
+        if self._record_failure_fingerprint(str(errors)):
+            self.log("Detected repeated syntax/lint failure fingerprint. Failing closed.", refined=True)
+            self.state = BuildState.FAIL
+            return
         self.retry_count += 1
         if self.retry_count > self.max_retries:
             self.log("Max Retries Exceeded for Syntax/Lint Fix.", refined=True)
@@ -422,12 +759,13 @@ CRITICAL RULES:
                 return
 
         self.log(f"Fixing Code (Attempt {self.retry_count}/{self.max_retries})", refined=True)
+        errors_for_llm = self._condense_failure_log(str(errors), kind="timing")
         
         # Agents fix syntax
         fix_prompt = f"""Fix Syntax/Lint Errors in "{self.name}".
         
         Error Log:
-        {errors}
+        {errors_for_llm}
         
         Strategy: {self.strategy.name} (Keep consistency!)
         
@@ -566,6 +904,29 @@ RULES:
              # It should be there from generation or reading above
              with open(self.artifacts['tb_path'], 'r') as f:
                 tb_code = f.read()
+
+        if self.strict_gates:
+            tb_ok, tb_issues = self._tb_meets_strict_contract(tb_code, self.strategy)
+            if self.artifacts.get("golden_template"):
+                # Golden library TBs are pre-verified and may be procedural.
+                tb_issues = [i for i in tb_issues if "class" not in i.lower()]
+                tb_ok = len(tb_issues) == 0
+            if not tb_ok:
+                self.log(f"Testbench strict gate failed: {tb_issues}", refined=True)
+                self.logger.info(f"TB STRICT GATE FAILURE: {tb_issues}")
+                self.retry_count += 1
+                if self.retry_count > self.max_retries:
+                    self.log("Max TB generation retries exceeded.", refined=True)
+                    self.state = BuildState.FAIL
+                    return
+                # Force regeneration path on next loop
+                if 'tb_path' in self.artifacts:
+                    try:
+                        os.remove(self.artifacts['tb_path'])
+                    except OSError:
+                        pass
+                    self.artifacts.pop('tb_path', None)
+                return
         
         # Run Sim
         with console.status("[bold magenta]Running Simulation...[/bold magenta]"):
@@ -579,15 +940,25 @@ RULES:
                  self.log("Skipping Hardening (--skip-openlane).", refined=True)
                  self.transition(BuildState.FORMAL_VERIFY)
             else:
-                 # Interactive Prompt for Hardening
+                # Interactive Prompt for Hardening
                  import typer
-                 console.print()
-                 if typer.confirm("Simulation Passed. Proceed to OpenLane Hardening (takes 10-30 mins)?", default=True):
+                 import sys
+                 if not sys.stdin.isatty():
+                     self.log("Non-interactive session: auto-proceeding after simulation pass.", refined=True)
                      self.transition(BuildState.FORMAL_VERIFY)
                  else:
-                     self.log("Skipping Hardening (User Cancelled).", refined=True)
-                     self.transition(BuildState.FORMAL_VERIFY)
+                     console.print()
+                     if typer.confirm("Simulation Passed. Proceed to OpenLane Hardening (takes 10-30 mins)?", default=True):
+                         self.transition(BuildState.FORMAL_VERIFY)
+                     else:
+                         self.log("Skipping Hardening (User Cancelled).", refined=True)
+                         self.transition(BuildState.FORMAL_VERIFY)
         else:
+            output_for_llm = self._condense_failure_log(output, kind="timing")
+            if self._record_failure_fingerprint(output_for_llm):
+                self.log("Detected repeated simulation failure fingerprint. Failing closed.", refined=True)
+                self.state = BuildState.FAIL
+                return
             self.retry_count += 1
             if self.retry_count > self.max_retries:
                  self.log(f"Max Sim Retries ({self.max_retries}) Exceeded. Simulation Failed.", refined=True)
@@ -604,7 +975,7 @@ RULES:
             analysis_task = Task(
                 description=f'''Analyze this Verification Failure.
 Error Log:
-{output}
+{output_for_llm}
 Is this a:
 A) TESTBENCH_ERROR (Syntax, $monitor usage, race condition, compilation fail)
 B) RTL_LOGIC_ERROR (Mismatch, Wrong State, Functional Failure)
@@ -626,7 +997,7 @@ Reply with ONLY "A" or "B".''',
                 fix_prompt = f"""Fix the Testbench logic/syntax.
 
 ERROR LOG:
-{output}
+{output_for_llm}
 
 MODULE INTERFACE (use EXACT port names):
 {port_info}
@@ -660,7 +1031,7 @@ CRITICAL:
                 {error_summary}
                 
                 Full Log:
-                {output}
+                {output_for_llm}
                 
                 Current RTL:
                 ```verilog
@@ -813,12 +1184,17 @@ CRITICAL:
                 self.artifacts['formal_result'] = 'PASS'
             else:
                 self.log(f"Formal Verification: {result[:200]}", refined=True)
-                self.artifacts['formal_result'] = 'FAIL (non-blocking)'
-                # Formal failure is non-blocking — we log it but continue
-                # Industry note: In production, this would be blocking
+                self.artifacts['formal_result'] = 'FAIL'
+                if self.strict_gates:
+                    self.log("Formal verification failed under strict mode.", refined=True)
+                    self.state = BuildState.FAIL
+                    return
         except Exception as e:
-            self.log(f"Formal verification error: {str(e)}. Continuing.", refined=True)
+            self.log(f"Formal verification error: {str(e)}.", refined=True)
             self.artifacts['formal_result'] = f'ERROR: {str(e)}'
+            if self.strict_gates:
+                self.state = BuildState.FAIL
+                return
         
         # 4. Run CDC check
         with console.status("[bold cyan]Running CDC Analysis...[/bold cyan]"):
@@ -830,7 +1206,11 @@ CRITICAL:
         if cdc_clean:
             self.log("CDC Analysis: CLEAN", refined=True)
         else:
-            self.log(f"CDC Analysis: warnings found (non-blocking)", refined=True)
+            self.log(f"CDC Analysis: warnings found", refined=True)
+            if self.strict_gates:
+                self.log("CDC issues are blocking under strict mode.", refined=True)
+                self.state = BuildState.FAIL
+                return
         
         self.transition(BuildState.COVERAGE_CHECK)
 
@@ -871,7 +1251,7 @@ CRITICAL:
             elif self.skip_openlane:
                 self.transition(BuildState.SUCCESS)
             else:
-                self.transition(BuildState.HARDENING)
+                self.transition(BuildState.FLOORPLAN)
         else:
             self.retry_count += 1
             # Cap coverage retries at 2 — the metric is heuristic-based (iverilog
@@ -883,14 +1263,17 @@ CRITICAL:
                      self.log(f"Restoring Best Testbench ({self.best_coverage:.1f}%) before proceeding.", refined=True)
                      import shutil
                      shutil.copy(self.best_tb_backup, self.artifacts['tb_path'])
-
+                if self.strict_gates:
+                    self.log(f"Coverage below threshold after {coverage_max_retries} attempts. Failing strict gate.", refined=True)
+                    self.state = BuildState.FAIL
+                    return
                 self.log(f"Coverage below threshold after {coverage_max_retries} attempts. Proceeding anyway.", refined=True)
                 if self.full_signoff:
                     self.transition(BuildState.REGRESSION)
                 elif self.skip_openlane:
                     self.transition(BuildState.SUCCESS)
                 else:
-                    self.transition(BuildState.HARDENING)
+                    self.transition(BuildState.FLOORPLAN)
                 return
             
             # Ask LLM to generate additional tests to improve coverage
@@ -1075,13 +1458,187 @@ CRITICAL:
             self.log(f"All {len(test_results)} regression tests PASSED!", refined=True)
         else:
             passed_count = sum(1 for tr in test_results if tr['status'] == 'PASS')
-            self.log(f"Regression: {passed_count}/{len(test_results)} passed (non-blocking)", refined=True)
+            self.log(f"Regression: {passed_count}/{len(test_results)} passed", refined=True)
+            if self.strict_gates:
+                self.log("Regression failures are blocking under strict mode.", refined=True)
+                self.state = BuildState.FAIL
+                return
         
         # Regression failures are non-blocking (logged but proceed)
         if self.skip_openlane:
             self.transition(BuildState.SUCCESS)
         else:
-            self.transition(BuildState.HARDENING)
+            self.transition(BuildState.FLOORPLAN)
+
+    def do_floorplan(self):
+        """Generate floorplan artifacts and feed hardening with spatial intent."""
+        self.floorplan_attempts += 1
+        self.log(f"Preparing floorplan attempt {self.floorplan_attempts}...", refined=True)
+        src_dir = f"{OPENLANE_ROOT}/designs/{self.name}/src"
+        os.makedirs(src_dir, exist_ok=True)
+
+        rtl_code = self.artifacts.get("rtl_code", "")
+        line_count = max(1, len([l for l in rtl_code.splitlines() if l.strip()]))
+        cell_count_est = max(100, line_count * 4)
+
+        base_die = 300 if line_count < 100 else 500 if line_count < 300 else 800
+        area_scale = self.artifacts.get("area_scale", 1.0)
+        die = int(base_die * area_scale)
+        util = 40 if line_count >= 200 else 50
+        clock_period = self.artifacts.get("clock_period_override", self.pdk_profile.get("default_clock_period", "10.0"))
+
+        macro_placement_tcl = os.path.join(src_dir, "macro_placement.tcl")
+        with open(macro_placement_tcl, "w") as f:
+            f.write(
+                "# Auto-generated macro placement skeleton\n"
+                f"# die_area={die}x{die} cell_count_est={cell_count_est}\n"
+                "set macros {}\n"
+                "foreach m $macros {\n"
+                "  # placeholder for macro coordinates\n"
+                "}\n"
+            )
+
+        floorplan_tcl = os.path.join(src_dir, f"{self.name}_floorplan.tcl")
+        with open(floorplan_tcl, "w") as f:
+            f.write(
+                f"set ::env(DESIGN_NAME) \"{self.name}\"\n"
+                f"set ::env(PDK) \"{self.pdk_profile.get('pdk', PDK)}\"\n"
+                f"set ::env(STD_CELL_LIBRARY) \"{self.pdk_profile.get('std_cell_library', 'sky130_fd_sc_hd')}\"\n"
+                f"set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/{self.name}.v]\n"
+                "set ::env(FP_SIZING) \"absolute\"\n"
+                f"set ::env(DIE_AREA) \"0 0 {die} {die}\"\n"
+                f"set ::env(FP_CORE_UTIL) {util}\n"
+                f"set ::env(PL_TARGET_DENSITY) {util / 100 + 0.05:.2f}\n"
+                f"set ::env(CLOCK_PERIOD) \"{clock_period}\"\n"
+                f"set ::env(CLOCK_PORT) \"clk\"\n"
+                "set ::env(GRT_ADJUSTMENT) 0.15\n"
+            )
+
+        self.artifacts["macro_placement_tcl"] = macro_placement_tcl
+        self.artifacts["floorplan_tcl"] = floorplan_tcl
+        self.artifacts["floorplan_meta"] = {
+            "die_area": die,
+            "cell_count_est": cell_count_est,
+            "clock_period": clock_period,
+            "attempt": self.floorplan_attempts,
+        }
+        self.transition(BuildState.HARDENING)
+
+    def _pivot_strategy(self, reason: str):
+        self.pivot_count += 1
+        self.log(f"Strategy pivot triggered ({self.pivot_count}/{self.max_pivots}): {reason}", refined=True)
+        if self.pivot_count > self.max_pivots:
+            self.log("Pivot budget exceeded. Failing closed.", refined=True)
+            self.state = BuildState.FAIL
+            return
+
+        stage = self.strategy_pivot_stage % 3
+        self.strategy_pivot_stage += 1
+
+        if stage == 0:
+            old = float(self.artifacts.get("clock_period_override", self.pdk_profile.get("default_clock_period", "10.0")))
+            new = round(old * 1.10, 2)
+            self.artifacts["clock_period_override"] = str(new)
+            self.log(f"Pivot step: timing constraint tune ({old}ns -> {new}ns).", refined=True)
+            self.transition(BuildState.FLOORPLAN, preserve_retries=True)
+            return
+
+        if stage == 1:
+            old_scale = float(self.artifacts.get("area_scale", 1.0))
+            new_scale = round(old_scale * 1.15, 3)
+            self.artifacts["area_scale"] = new_scale
+            self.log(f"Pivot step: area expansion ({old_scale}x -> {new_scale}x).", refined=True)
+            self.transition(BuildState.FLOORPLAN, preserve_retries=True)
+            return
+
+        # stage 2: logic decoupling prompt
+        self.artifacts["logic_decoupling_hint"] = (
+            "Apply register slicing / pipeline decoupling on critical path; "
+            "reduce combinational depth while preserving behavior."
+        )
+        self.log("Pivot step: requesting logic decoupling (register slicing) in RTL regen.", refined=True)
+        self.transition(BuildState.RTL_GEN, preserve_retries=True)
+
+    def do_convergence_review(self):
+        """Assess congestion/timing convergence and prevent futile loops."""
+        self.log("Assessing convergence (timing + congestion + PPA)...", refined=True)
+
+        congestion = parse_congestion_metrics(self.name, run_tag=self.artifacts.get("run_tag", "agentrun"))
+        sta = parse_sta_signoff(self.name)
+        power = parse_power_signoff(self.name)
+        metrics, _ = check_physical_metrics(self.name)
+
+        self.artifacts["congestion"] = congestion
+        self.artifacts["sta_signoff"] = sta
+        self.artifacts["power_signoff"] = power
+        if metrics:
+            self.artifacts["metrics"] = metrics
+
+        wns = float(sta.get("worst_setup", 0.0)) if not sta.get("error") else -999.0
+        tns = 0.0
+        area_um2 = float(metrics.get("chip_area_um2", 0.0)) if metrics else 0.0
+        power_w = float(power.get("total_power_w", 0.0))
+        cong_pct = float(congestion.get("total_usage_pct", 0.0))
+        snap = ConvergenceSnapshot(
+            iteration=len(self.convergence_history) + 1,
+            wns=wns,
+            tns=tns,
+            congestion=cong_pct,
+            area_um2=area_um2,
+            power_w=power_w,
+        )
+        self.convergence_history.append(snap)
+        self.artifacts["convergence_history"] = [asdict(x) for x in self.convergence_history]
+
+        self.log(
+            f"Convergence snapshot: WNS={wns:.3f}ns, congestion={cong_pct:.2f}%, area={area_um2:.1f}um^2, power={power_w:.6f}W",
+            refined=True,
+        )
+
+        # Congestion-driven loop
+        if cong_pct > self.congestion_threshold:
+            self.log(
+                f"Congestion {cong_pct:.2f}% exceeds threshold {self.congestion_threshold:.2f}%.",
+                refined=True,
+            )
+            # area expansion up to 2 times, then pivot logic
+            area_expansions = int(self.artifacts.get("area_expansions", 0))
+            if area_expansions < 2:
+                self.artifacts["area_expansions"] = area_expansions + 1
+                self.artifacts["area_scale"] = round(float(self.artifacts.get("area_scale", 1.0)) * 1.15, 3)
+                self.log("Applying +15% area expansion due to congestion.", refined=True)
+                self.transition(BuildState.FLOORPLAN, preserve_retries=True)
+                return
+            self._pivot_strategy("congestion persisted after area expansions")
+            return
+
+        # WNS stagnation logic
+        if len(self.convergence_history) >= 3:
+            w_prev = self.convergence_history[-2].wns
+            w_curr = self.convergence_history[-1].wns
+            w_prev2 = self.convergence_history[-3].wns
+            improve1 = w_curr - w_prev
+            improve2 = w_prev - w_prev2
+            if improve1 < 0.01 and improve2 < 0.01:
+                self._pivot_strategy("WNS stagnated for 2 iterations (<0.01ns)")
+                return
+
+        self.transition(BuildState.SIGNOFF)
+
+    def do_eco_patch(self):
+        """Dual-mode ECO: attempt gate patch first, fallback to RTL micro-patch."""
+        self.eco_attempts += 1
+        self.log(f"Running ECO attempt {self.eco_attempts}...", refined=True)
+        strategy = "gate" if self.eco_attempts == 1 else "rtl"
+        ok, patch_result = apply_eco_patch(self.name, strategy=strategy)
+        self.artifacts["eco_patch"] = patch_result
+        if not ok:
+            self.log(f"ECO patch failed: {patch_result}", refined=True)
+            self.state = BuildState.FAIL
+            return
+        # For now, ECO patch is represented as artifact + rerun hardening/signoff.
+        self.log(f"ECO artifact generated: {patch_result}", refined=True)
+        self.transition(BuildState.HARDENING, preserve_retries=True)
 
     def do_hardening(self):
         # 1. Generate config.tcl (CRITICAL: Required for OpenLane)
@@ -1101,18 +1658,19 @@ CRITICAL:
 # Modern OpenLane Config Template
         # Note: We use GRT_ADJUSTMENT instead of deprecated GLB_RT_ADJUSTMENT
         
-        # Determine STD_CELL_LIBRARY based on PDK (or default to sky130_fd_sc_hd)
-        # This should ideally come from global config
-        std_cell_lib = "sky130_fd_sc_hd"
-        if "gf180" in PDK:
-            std_cell_lib = "gf180mcu_fd_sc_mcu7t5v0"
+        std_cell_lib = self.pdk_profile.get("std_cell_library", "sky130_fd_sc_hd")
+        pdk_name = self.pdk_profile.get("pdk", PDK)
+        clock_period = str(self.artifacts.get("clock_period_override", self.pdk_profile.get("default_clock_period", "10.0")))
+        floor_meta = self.artifacts.get("floorplan_meta", {})
+        die = int(floor_meta.get("die_area", 500))
+        util = 40 if die >= 500 else 50
             
         config_tcl = f"""
 # User config
 set ::env(DESIGN_NAME) "{self.name}"
 
 # PDK Setup
-set ::env(PDK) "{PDK}"
+set ::env(PDK) "{pdk_name}"
 set ::env(STD_CELL_LIBRARY) "{std_cell_lib}"
 
 # Verilog Files
@@ -1121,16 +1679,17 @@ set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/{self.name}.v]
 # Clock Configuration
 set ::env(CLOCK_PORT) "{clock_port}"
 set ::env(CLOCK_NET) "{clock_port}"
-set ::env(CLOCK_PERIOD) "10.0"
+set ::env(CLOCK_PERIOD) "{clock_period}"
 
 # Synthesis
 set ::env(SYNTH_STRATEGY) "AREA 0"
 set ::env(SYNTH_SIZING) 1
 
 # Floorplanning
-set ::env(FP_SIZING) "relative"
-set ::env(FP_CORE_UTIL) 40
-set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) "0 0 {die} {die}"
+set ::env(FP_CORE_UTIL) {util}
+set ::env(PL_TARGET_DENSITY) {util / 100 + 0.05:.2f}
 
 # Routing
 set ::env(GRT_ADJUSTMENT) 0.15
@@ -1148,14 +1707,22 @@ set ::env(MAGIC_DRC_USE_GDS) 1
              return
 
         # 2. Run OpenLane
+        run_tag = f"agentrun_{self.global_step_count}"
+        floorplan_tcl = self.artifacts.get("floorplan_tcl", "")
         with console.status("[bold blue]Hardening Layout (OpenLane)...[/bold blue]"):
-            success, result = run_openlane(self.name, background=False)
+            success, result = run_openlane(
+                self.name,
+                background=False,
+                run_tag=run_tag,
+                floorplan_tcl=floorplan_tcl,
+                pdk_name=pdk_name,
+            )
             
         if success:
             self.artifacts['gds'] = result
+            self.artifacts['run_tag'] = run_tag
             self.log(f"GDSII generated: {result}", refined=True)
-            # Always proceed to Signoff for final checks
-            self.transition(BuildState.SIGNOFF)
+            self.transition(BuildState.CONVERGENCE_REVIEW)
         else:
             self.log(f"Hardening Failed: {result}")
             self.state = BuildState.FAIL
@@ -1164,6 +1731,21 @@ set ::env(MAGIC_DRC_USE_GDS) 1
         """Performs full fabrication-readiness signoff: DRC/LVS, timing closure, power analysis."""
         self.log("Running Fabrication Readiness Signoff...", refined=True)
         fab_ready = True
+        run_tag = self.artifacts.get("run_tag", "agentrun")
+        gate_netlist = f"{OPENLANE_ROOT}/designs/{self.name}/runs/{run_tag}/results/final/verilog/gl/{self.name}.v"
+        rtl_path = self.artifacts.get("rtl_path", f"{OPENLANE_ROOT}/designs/{self.name}/src/{self.name}.v")
+        if os.path.exists(rtl_path) and os.path.exists(gate_netlist):
+            lec_ok, lec_log = run_eqy_lec(self.name, rtl_path, gate_netlist)
+            self.artifacts["lec_result"] = "PASS" if lec_ok else "FAIL"
+            self.logger.info(f"LEC RESULT:\n{lec_log}")
+            if lec_ok:
+                self.log("LEC: PASS", refined=True)
+            else:
+                self.log("LEC: FAIL", refined=True)
+                fab_ready = False
+        else:
+            self.artifacts["lec_result"] = "SKIP"
+            self.log("LEC: skipped (missing RTL or gate netlist)", refined=True)
         
         # ── 1. DRC / LVS ──
         with console.status("[bold blue]Checking DRC/LVS Reports...[/bold blue]"):
@@ -1191,6 +1773,7 @@ set ::env(MAGIC_DRC_USE_GDS) 1
         
         if sta.get('error'):
             self.log(f"STA: {sta['error']}", refined=True)
+            fab_ready = False
         else:
             for c in sta['corners']:
                 status = "✓" if (c['setup_slack'] >= 0 and c['hold_slack'] >= 0) else "✗"
@@ -1278,6 +1861,18 @@ set ::env(MAGIC_DRC_USE_GDS) 1
             self.log(f"Datasheet generated: {doc_path}", refined=True)
         except Exception as e:
             self.log(f"Error writing datasheet: {e}", refined=True)
+
+        try:
+            self._write_ip_manifest()
+        except Exception as e:
+            self.log(f"IP manifest generation warning: {e}", refined=True)
+
+        if self.strict_gates:
+            if self.artifacts.get("formal_result", "").startswith("FAIL") or str(self.artifacts.get("formal_result", "")).startswith("ERROR"):
+                fab_ready = False
+            cov = self.artifacts.get("coverage", {})
+            if cov and float(cov.get("line_pct", 0.0)) < float(self.min_coverage):
+                fab_ready = False
         
         # FINAL VERDICT
         timing_status = "MET" if sta.get('timing_met') else "FAILED" if not sta.get('error') else "N/A"
@@ -1292,6 +1887,7 @@ set ::env(MAGIC_DRC_USE_GDS) 1
             f"Timing:     {timing_status} (WNS={sta.get('worst_setup', 0):.2f}ns)\n"
             f"Power:      {power_status}\n"
             f"IR-Drop:    {irdrop_status}\n"
+            f"LEC:        {self.artifacts.get('lec_result', 'N/A')}\n"
             f"Coverage:   {self.artifacts.get('coverage', {}).get('line_pct', 'N/A')}%\n"
             f"Formal:     {self.artifacts.get('formal_result', 'SKIPPED')}\n\n"
             f"{'[bold green]FABRICATION READY ✓[/]' if fab_ready else '[bold red]NOT FABRICATION READY ✗[/]'}",
@@ -1303,6 +1899,11 @@ set ::env(MAGIC_DRC_USE_GDS) 1
             self.artifacts['signoff_result'] = 'PASS'
             self.transition(BuildState.SUCCESS)
         else:
+            # Trigger ECO path before final fail when strict gates are enabled.
+            if self.strict_gates and self.eco_attempts < 2:
+                self.log("Signoff failed. Triggering ECO patch stage.", refined=True)
+                self.transition(BuildState.ECO_PATCH, preserve_retries=True)
+                return
             self.log("❌ SIGNOFF FAILED (Violations Found)", refined=True)
             self.artifacts['signoff_result'] = 'FAIL'
             self.errors.append("Signoff failed (see report).")

src/agentic/tools/vlsi_tools.py

@@ -1,11 +1,26 @@
 # tools/vlsi_tools.py
-import os
-import re
-import subprocess
-from crewai.tools import tool
-from ..config import OPENLANE_ROOT, SCRIPTS_DIR, PDK_ROOT, PDK, OPENLANE_IMAGE, SBY_BIN
+import os
+import re
+import json
+import hashlib
+import subprocess
+from collections import Counter, defaultdict, deque
+from typing import Dict, Any, List, Tuple
+import shutil
+from crewai.tools import tool
+from ..config import (
+    OPENLANE_ROOT,
+    SCRIPTS_DIR,
+    PDK_ROOT,
+    PDK,
+    OPENLANE_IMAGE,
+    SBY_BIN,
+    YOSYS_BIN,
+    EQY_BIN,
+    get_pdk_profile,
+)
 
-def SecurityCheck(rtl_code: str) -> tuple:
+def SecurityCheck(rtl_code: str) -> tuple:
     """
     Performs a static security analysis on the generated RTL.
     Returns (True, "Safe") if safe, or (False, "reason") if malicious patterns detected.
@@ -21,7 +36,68 @@ def SecurityCheck(rtl_code: str) -> tuple:
         if re.search(pattern, rtl_code, re.IGNORECASE):
             return False, f"Detected potentially malicious pattern: {pattern}"
             
-    return True, "Safe"
+    return True, "Safe"
+
+
+def _resolve_binary(bin_hint: str) -> str:
+    """Resolve a tool path from hint/path/PATH."""
+    if not bin_hint:
+        return ""
+    if os.path.isabs(bin_hint) and os.path.exists(bin_hint):
+        return bin_hint
+    found = shutil.which(bin_hint)
+    if found:
+        return found
+    return bin_hint
+
+
+def startup_self_check() -> Dict[str, Any]:
+    """Validate required tooling and environment before running the flow."""
+    checks: List[Dict[str, Any]] = []
+    required_bins = {
+        "verilator": "verilator",
+        "iverilog": "iverilog",
+        "vvp": "vvp",
+        "docker": "docker",
+        "yosys": YOSYS_BIN,
+        "sby": SBY_BIN,
+        "eqy": EQY_BIN,
+    }
+    all_pass = True
+
+    for name, hint in required_bins.items():
+        resolved = _resolve_binary(hint)
+        exists = bool(resolved and (os.path.isabs(resolved) and os.path.exists(resolved) or shutil.which(resolved)))
+        checks.append(
+            {
+                "tool": name,
+                "hint": hint,
+                "resolved": resolved,
+                "ok": exists,
+            }
+        )
+        if not exists:
+            all_pass = False
+
+    env_checks = {
+        "OPENLANE_ROOT": OPENLANE_ROOT,
+        "PDK_ROOT": PDK_ROOT,
+        "PDK": PDK,
+    }
+    env_status = {
+        key: {"value": value, "exists": os.path.exists(value) if key.endswith("_ROOT") else True}
+        for key, value in env_checks.items()
+    }
+    for key, info in env_status.items():
+        if not info["exists"]:
+            all_pass = False
+            checks.append({"tool": key, "hint": info["value"], "resolved": info["value"], "ok": False})
+
+    return {
+        "ok": all_pass,
+        "checks": checks,
+        "env": env_status,
+    }
 
 def write_config(design_name: str, code: str) -> str:
     """Writes config.tcl to the OpenLane design directory."""
@@ -187,7 +263,7 @@ def run_syntax_check(file_path: str) -> tuple:
     except FileNotFoundError:
         return False, "Verilator not found. Please install Verilator 5.0+."
 
-def run_lint_check(file_path: str) -> tuple:
+def run_lint_check(file_path: str) -> tuple:
     """
     Runs Verilator --lint-only for stricter static analysis.
     Returns: (True, "OK") or (False, ErrorLog)
@@ -217,8 +293,73 @@ def run_lint_check(file_path: str) -> tuple:
         
     except FileNotFoundError:
          return True, "Verilator not found (Skipping Lint)"
-    except subprocess.TimeoutExpired:
-         return False, "Lint check timed out."
+    except subprocess.TimeoutExpired:
+         return False, "Lint check timed out."
+
+
+def run_semantic_rigor_check(file_path: str) -> Tuple[bool, Dict[str, Any]]:
+    """Deterministic semantic preflight for width-safety and port-shadowing."""
+    report: Dict[str, Any] = {
+        "ok": True,
+        "width_issues": [],
+        "port_shadowing": [],
+        "details": "",
+    }
+
+    if not os.path.exists(file_path):
+        report["ok"] = False
+        report["details"] = f"File not found: {file_path}"
+        return False, report
+
+    with open(file_path, "r") as f:
+        code = f.read()
+
+    # --- Port shadowing detection ---
+    port_names = set()
+    module_match = re.search(r"module\s+\w+\s*(?:#\s*\(.*?\))?\s*\((.*?)\)\s*;", code, re.DOTALL)
+    if module_match:
+        port_block = module_match.group(1)
+        for m in re.finditer(r"\b(?:input|output|inout)\b[^;,\)]*\b([A-Za-z_]\w*)\b", port_block):
+            port_names.add(m.group(1))
+
+    shadowing = []
+    for m in re.finditer(
+        r"^\s*(?:reg|wire|logic)\s+(?:signed\s+)?(?:\[[^]]+\]\s+)?([A-Za-z_]\w*)\b",
+        code,
+        re.MULTILINE,
+    ):
+        sig = m.group(1)
+        if sig in port_names:
+            shadowing.append(sig)
+    if shadowing:
+        report["port_shadowing"] = sorted(set(shadowing))
+
+    # --- Width mismatch detection via Verilator diagnostics ---
+    width_patterns = (
+        "WIDTHTRUNC",
+        "WIDTHEXPAND",
+        "WIDTH",
+        "UNSIGNED",
+        "signed",
+        "truncat",
+    )
+    cmd = ["verilator", "--lint-only", "--sv", "--timing", "-Wall", file_path]
+    try:
+        result = subprocess.run(cmd, capture_output=True, text=True, timeout=60)
+        stderr = result.stderr or ""
+        width_lines = []
+        for line in stderr.splitlines():
+            upper = line.upper()
+            if any(p.upper() in upper for p in width_patterns):
+                width_lines.append(line.strip())
+        if width_lines:
+            report["width_issues"] = width_lines[:20]
+            report["details"] = "\n".join(width_lines[:20])
+    except Exception as exc:
+        report["details"] = f"Semantic width scan fallback triggered: {exc}"
+
+    report["ok"] = not report["port_shadowing"] and not report["width_issues"]
+    return report["ok"], report
 
 
 def validate_rtl_for_synthesis(file_path: str) -> tuple:
@@ -522,7 +663,7 @@ def run_formal_verification(design_name):
         return False, "SBY configuration file not found."
 
     # Run SBY (using bundled binary)
-    sby_cmd = SBY_BIN if os.path.exists(SBY_BIN) else "sby"
+    sby_cmd = _resolve_binary(SBY_BIN)
     try:
         result = subprocess.run(
             [sby_cmd, "-f", f"{design_name}.sby"],
@@ -579,10 +720,10 @@ def check_physical_metrics(design_name):
     if not os.path.exists(metrics_path):
         return None, "Metrics file not found. OpenLane might have failed."
 
-    try:
-        with open(metrics_path, 'r') as f:
-            reader = csv.DictReader(f)
-            data = next(reader) # Only one row usually
+    try:
+        with open(metrics_path, 'r') as f:
+            reader = csv.DictReader(f)
+            data = next(reader) # Only one row usually
             
             # Extract key metrics safely handling both OpenLane 1 and 2 keys
             area = float(data.get("Total_Physical_Cells", data.get("synth_cell_count", 0)))
@@ -605,19 +746,17 @@ def check_physical_metrics(design_name):
             if utilization < 1.0: # OL1 might report as 0.45 instead of 45%
                 utilization *= 100
 
-            metrics = {
-                "area": area,
-                "chip_area_um2": chip_area_um2,
-                "timing_tns": tns, # Total Negative Slack
-                "timing_wns": wns, # Worst Negative Slack
-                "power_total": power_total,
-                "utilization": utilization
-            }
-            return metrics, "OK"
-    except Exception as e:
-            return metrics, "OK"
-    except Exception as e:
-        return None, f"Error parsing metrics: {str(e)}"
+            metrics = {
+                "area": area,
+                "chip_area_um2": chip_area_um2,
+                "timing_tns": tns, # Total Negative Slack
+                "timing_wns": wns, # Worst Negative Slack
+                "power_total": power_total,
+                "utilization": utilization
+            }
+            return metrics, "OK"
+    except Exception as e:
+        return None, f"Error parsing metrics: {str(e)}"
 
 @tool("Signoff Checker")
 def signoff_check_tool(design_name: str):
@@ -728,12 +867,19 @@ def run_simulation(design_name: str) -> tuple:
         
     return False, sim_text
 
-def run_openlane(design_name: str, background: bool = False):
-    """Triggers the OpenLane flow via Docker."""
+def run_openlane(
+    design_name: str,
+    background: bool = False,
+    run_tag: str = "agentrun",
+    floorplan_tcl: str = "",
+    pdk_name: str = "",
+):
+    """Triggers the OpenLane flow via Docker."""
     
     # --- Autonomous Environment Fix ---
     # If PDK_ROOT is not set, try to find it in common locations
-    effective_pdk_root = PDK_ROOT
+    effective_pdk_root = PDK_ROOT
+    selected_pdk = pdk_name or PDK
     if not effective_pdk_root or not os.path.exists(effective_pdk_root):
         common_paths = [
             os.path.expanduser("~/.ciel"),
@@ -745,10 +891,10 @@ def run_openlane(design_name: str, background: bool = False):
         found = False
         for path in common_paths:
             # Check for generic PDK structure, not just sky130A
-            if os.path.exists(path) and (os.path.exists(os.path.join(path, PDK)) or os.path.exists(os.path.join(path, "sky130A"))):
-                effective_pdk_root = path
-                found = True
-                break
+            if os.path.exists(path) and (os.path.exists(os.path.join(path, selected_pdk)) or os.path.exists(os.path.join(path, "sky130A"))):
+                effective_pdk_root = path
+                found = True
+                break
         
         if not found:
             return False, f"PDK_ROOT not found in environment or common paths ({common_paths}). Please set PDK_ROOT."
@@ -760,16 +906,18 @@ def run_openlane(design_name: str, background: bool = False):
 
     # Direct Docker command (non-interactive)
     # Using the configured PDK variable
-    cmd = [
-        "docker", "run", "--rm",
-        "-v", f"{OPENLANE_ROOT}:/openlane",
-        "-v", f"{effective_pdk_root}:{effective_pdk_root}",
-        "-e", f"PDK_ROOT={effective_pdk_root}",
-        "-e", f"PDK={PDK}",
-        "-e", "PWD=/openlane",
-        OPENLANE_IMAGE,
-        "./flow.tcl", "-design", design_name, "-tag", "agentrun", "-overwrite", "-ignore_mismatches"
-    ]
+    cmd = [
+        "docker", "run", "--rm",
+        "-v", f"{OPENLANE_ROOT}:/openlane",
+        "-v", f"{effective_pdk_root}:{effective_pdk_root}",
+        "-e", f"PDK_ROOT={effective_pdk_root}",
+        "-e", f"PDK={selected_pdk}",
+        "-e", "PWD=/openlane",
+        OPENLANE_IMAGE,
+        "./flow.tcl", "-design", design_name, "-tag", run_tag, "-overwrite", "-ignore_mismatches"
+    ]
+    if floorplan_tcl:
+        cmd.extend(["-config_file", floorplan_tcl])
     
     if background:
         log_file_path = os.path.join(design_dir, "harden.log")
@@ -797,7 +945,7 @@ def run_openlane(design_name: str, background: bool = False):
         return False, "OpenLane Hardening Timed Out (Exceeded 60 mins)."
     
     # Check if GDS was created
-    gds_path = f"{OPENLANE_ROOT}/designs/{design_name}/runs/agentrun/results/final/gds/{design_name}.gds"
+    gds_path = f"{OPENLANE_ROOT}/designs/{design_name}/runs/{run_tag}/results/final/gds/{design_name}.gds"
     success = os.path.exists(gds_path)
 
     if success:
@@ -839,7 +987,7 @@ def run_verification(design_name: str) -> str:
     except Exception as e:
         return f"Error running verification: {str(e)}"
 
-def run_gls_simulation(design_name: str) -> tuple:
+def run_gls_simulation(design_name: str) -> tuple:
     """Compiles and runs the Gate-Level Simulation (GLS) for the design."""
     src_dir = f"{OPENLANE_ROOT}/designs/{design_name}/src"
     tb_file = f"{src_dir}/{design_name}_tb.v"
@@ -914,8 +1062,240 @@ def run_gls_simulation(design_name: str) -> tuple:
         if "TEST PASSED" in sim_text:
             return True, f"GLS Simulation PASSED.\n{sim_text}"
         return False, f"GLS Simulation FAILED or missing PASS marker.\n{sim_text}"
-    except subprocess.TimeoutExpired:
-        return False, "GLS Simulation Timed Out."
+    except subprocess.TimeoutExpired:
+        return False, "GLS Simulation Timed Out."
+
+
+def parse_eda_log_summary(log_path: str, kind: str, top_n: int = 10) -> Dict[str, Any]:
+    """Stream parse EDA logs and return normalized top issues for LLM-safe context."""
+    summary: Dict[str, Any] = {
+        "kind": kind,
+        "path": log_path,
+        "top_issues": [],
+        "counts": {},
+        "total_lines": 0,
+        "error": "",
+    }
+    if not os.path.exists(log_path):
+        summary["error"] = f"log not found: {log_path}"
+        return summary
+
+    patterns = {
+        "timing": [
+            (r"\bwns\b|\btns\b|slack|setup|hold", "timing_violation", "high", "timing_tune"),
+            (r"unconstrained|no clock", "constraint_issue", "medium", "constraints"),
+        ],
+        "routing": [
+            (r"overflow|congestion|gcell|resource|usage", "routing_congestion", "high", "area_or_floorplan"),
+            (r"antenna", "antenna_issue", "medium", "routing_rule_fix"),
+        ],
+        "drc": [
+            (r"violation|error|drc", "drc_violation", "high", "layout_fix"),
+        ],
+        "lvs": [
+            (r"mismatch|lvs|error", "lvs_mismatch", "high", "netlist_match_fix"),
+        ],
+        "cdc": [
+            (r"cdc|clock domain|metastab|sync", "cdc_warning", "medium", "synchronizer_fix"),
+        ],
+        "formal": [
+            (r"assert|prove|fail|counterexample", "formal_failure", "high", "property_or_logic_fix"),
+        ],
+    }
+    selected = patterns.get(kind.lower(), patterns["timing"])
+    counters: Counter = Counter()
+    examples: Dict[str, deque] = defaultdict(lambda: deque(maxlen=3))
+    fixes: Dict[str, str] = {}
+    severities: Dict[str, str] = {}
+
+    with open(log_path, "r", errors="ignore") as f:
+        for line in f:
+            summary["total_lines"] += 1
+            text = line.strip()
+            if not text:
+                continue
+            for pattern, issue_type, severity, fix_cat in selected:
+                if re.search(pattern, text, re.IGNORECASE):
+                    counters[issue_type] += 1
+                    examples[issue_type].append(text[:240])
+                    fixes[issue_type] = fix_cat
+                    severities[issue_type] = severity
+                    break
+
+    summary["counts"] = dict(counters)
+    for issue_type, count in counters.most_common(top_n):
+        ex = next(iter(examples[issue_type]), "")
+        summary["top_issues"].append(
+            {
+                "issue_type": issue_type,
+                "severity": severities.get(issue_type, "medium"),
+                "count": count,
+                "representative_snippet": ex,
+                "probable_fix_category": fixes.get(issue_type, "general_fix"),
+            }
+        )
+    return summary
+
+
+def extract_top_sta_paths(sta_report_path: str, top_n: int = 10) -> List[Dict[str, Any]]:
+    """Extract top failing paths/endpoints from STA report text."""
+    results: List[Dict[str, Any]] = []
+    if not os.path.exists(sta_report_path):
+        return results
+
+    slack_re = re.compile(r"slack\s*\(?VIOLATED\)?\s*([-\d.]+)", re.IGNORECASE)
+    end_re = re.compile(r"endpoint:\s*(\S+)", re.IGNORECASE)
+    start_re = re.compile(r"startpoint:\s*(\S+)", re.IGNORECASE)
+    current: Dict[str, Any] = {}
+
+    with open(sta_report_path, "r", errors="ignore") as f:
+        for line in f:
+            text = line.strip()
+            m = start_re.search(text)
+            if m:
+                current["startpoint"] = m.group(1)
+            m = end_re.search(text)
+            if m:
+                current["endpoint"] = m.group(1)
+            m = slack_re.search(text)
+            if m:
+                try:
+                    current["slack"] = float(m.group(1))
+                except ValueError:
+                    current["slack"] = 0.0
+                if current:
+                    results.append(dict(current))
+                current = {}
+
+    results.sort(key=lambda x: x.get("slack", 0.0))
+    return results[:top_n]
+
+
+def parse_congestion_metrics(design_name: str, run_tag: str = "agentrun") -> Dict[str, Any]:
+    """Parse global routing congestion from OpenLane routing logs."""
+    log_path = os.path.join(
+        OPENLANE_ROOT,
+        "designs",
+        design_name,
+        "runs",
+        run_tag,
+        "logs",
+        "routing",
+        "19-global.log",
+    )
+    result = {
+        "log_path": log_path,
+        "total_usage_pct": 0.0,
+        "total_overflow": 0,
+        "layers": [],
+        "error": "",
+    }
+    if not os.path.exists(log_path):
+        result["error"] = "global routing log missing"
+        return result
+
+    line_re = re.compile(
+        r"^(?P<layer>[A-Za-z0-9_]+)\s+(?P<resource>\d+)\s+(?P<demand>\d+)\s+(?P<usage>[\d.]+)%\s+(?P<overflow>\d+\s*/\s*\d+\s*/\s*\d+)$"
+    )
+    total_re = re.compile(
+        r"^Total\s+(?P<resource>\d+)\s+(?P<demand>\d+)\s+(?P<usage>[\d.]+)%\s+(?P<overflow>\d+\s*/\s*\d+\s*/\s*\d+)$"
+    )
+    with open(log_path, "r", errors="ignore") as f:
+        for raw in f:
+            text = raw.strip()
+            m = total_re.match(text)
+            if m:
+                overflow_triplet = m.group("overflow").split("/")
+                result["total_usage_pct"] = float(m.group("usage"))
+                result["total_overflow"] = int(overflow_triplet[-1].strip())
+                continue
+            m = line_re.match(text)
+            if m:
+                if m.group("layer").lower() == "total":
+                    continue
+                overflow_triplet = m.group("overflow").split("/")
+                total_over = int(overflow_triplet[-1].strip())
+                result["layers"].append(
+                    {
+                        "layer": m.group("layer"),
+                        "usage_pct": float(m.group("usage")),
+                        "overflow_total": total_over,
+                    }
+                )
+                continue
+    return result
+
+
+def run_eqy_lec(design_name: str, gold_rtl: str, gate_netlist: str) -> Tuple[bool, str]:
+    """Run EQY logical equivalence between reference RTL and gate netlist."""
+    if not os.path.exists(gold_rtl):
+        return False, f"gold rtl missing: {gold_rtl}"
+    if not os.path.exists(gate_netlist):
+        return False, f"gate netlist missing: {gate_netlist}"
+
+    eqy_bin = _resolve_binary(EQY_BIN)
+    yosys_bin = _resolve_binary(YOSYS_BIN)
+    if not shutil.which(eqy_bin) and not os.path.exists(eqy_bin):
+        return False, f"eqy not found ({EQY_BIN})"
+    if not shutil.which(yosys_bin) and not os.path.exists(yosys_bin):
+        return False, f"yosys not found ({YOSYS_BIN})"
+
+    src_dir = os.path.join(OPENLANE_ROOT, "designs", design_name, "src")
+    os.makedirs(src_dir, exist_ok=True)
+    eqy_cfg = os.path.join(src_dir, f"{design_name}.eqy")
+    top = design_name
+    cfg = f"""[options]
+multiclock on
+
+[gold]
+read_verilog {gold_rtl}
+prep -top {top}
+
+[gate]
+read_verilog {gate_netlist}
+prep -top {top}
+
+[strategy simple]
+"""
+    with open(eqy_cfg, "w") as f:
+        f.write(cfg)
+
+    try:
+        result = subprocess.run(
+            [eqy_bin, eqy_cfg],
+            cwd=src_dir,
+            capture_output=True,
+            text=True,
+            timeout=900,
+        )
+    except subprocess.TimeoutExpired:
+        return False, "EQY timed out (>900s)"
+    except FileNotFoundError:
+        return False, "EQY binary not executable"
+
+    text = (result.stdout or "") + ("\n" + result.stderr if result.stderr else "")
+    if result.returncode == 0 and re.search(r"PASS|equivalent|success", text, re.IGNORECASE):
+        return True, text[-2000:]
+    return False, text[-4000:]
+
+
+def apply_eco_patch(design_name: str, target_net: str = "", strategy: str = "gate") -> Tuple[bool, str]:
+    """Apply a localized ECO patch placeholder; returns patch artifact path."""
+    src_dir = os.path.join(OPENLANE_ROOT, "designs", design_name, "src")
+    os.makedirs(src_dir, exist_ok=True)
+    patch_path = os.path.join(src_dir, f"{design_name}_eco_patch.tcl")
+    patch_note = (
+        f"# ECO patch strategy={strategy}\\n"
+        f"# target_net={target_net or 'AUTO_SELECT'}\\n"
+        "# This patch is generated by AgentIC and intended for incremental routing/repair.\\n"
+        "puts \"Applying localized ECO patch\"\\n"
+    )
+    try:
+        with open(patch_path, "w") as f:
+            f.write(patch_note)
+        return True, patch_path
+    except OSError as exc:
+        return False, f"ECO patch write failed: {exc}"
 
 # ============================================================
 # INDUSTRY-STANDARD TOOLS (Coverage, CDC, DRC/LVS, Documentation)
@@ -1453,73 +1833,83 @@ def generate_design_doc(design_name: str, spec: str = "", metrics: dict = None)
     except Exception as e:
         return f"Error writing documentation: {e}"
 
-def parse_sta_signoff(design_name: str) -> dict:
-    """Parses OpenLane STA (Static Timing Analysis) reports for signoff.
-    
-    Args:
-        design_name (str): Name of the design.
-        
-    Returns:
-        dict: A dictionary containing timing metrics and violation status.
-    """
-    try:
-        # Locate the latest run directory
-        runs_dir = os.path.join(OPENLANE_ROOT, "designs", design_name, "runs")
-        if not os.path.exists(runs_dir):
-            return {"error": "No runs directory found", "timing_met": False}
-            
-        # Get the latest run
-        latest_run = sorted([d for d in os.listdir(runs_dir) if os.path.isdir(os.path.join(runs_dir, d))])[-1]
-        report_dir = os.path.join(runs_dir, latest_run, "reports", "signoff")
-        
-        # Check for STA report
-        sta_report = None
-        if os.path.exists(report_dir):
-            for f in os.listdir(report_dir):
-                if f.endswith(".sta.rpt") or "sta" in f:
-                    sta_report = os.path.join(report_dir, f)
-                    break
-        
-        if not sta_report:
-             return {"error": "STA report not found", "timing_met": False}
-             
-        with open(sta_report, 'r') as f:
-            content = f.read()
-            
-        # Parse slack (WNS = Worst Negative Slack -> Setup)
-        wns_match = re.search(r'wns\s+([-\d.]+)', content, re.IGNORECASE)
-        tns_match = re.search(r'tns\s+([-\d.]+)', content, re.IGNORECASE)
-        
-        wns = float(wns_match.group(1)) if wns_match else 0.0
-        tns = float(tns_match.group(1)) if tns_match else 0.0
-        
-        # In a real flow, we'd parse hold slack too. For now assume hold is OK if wns is OK, or parse if available.
-        # OpenLane often puts hold analysis in a separate Min/Fast corner file. 
-        # For simplicity/robustness, we'll map WNS to setup slack.
-        
-        setup_slack = wns
-        hold_slack = 0.0 # Placeholder if not parsed
-        
-        timing_met = (setup_slack >= 0.0)
-        
-        return {
-            "timing_met": timing_met,
-            "worst_setup": setup_slack,
-            "worst_hold": hold_slack,
-            "corners": [
-                {
-                    "name": "Typical",
-                    "setup_slack": setup_slack,
-                    "hold_slack": hold_slack
-                }
-            ],
-            "report_path": sta_report
-        }
+def parse_sta_signoff(design_name: str) -> dict:
+    """Parse multi-corner STA summary reports and aggregate worst setup/hold."""
+    try:
+        runs_dir = os.path.join(OPENLANE_ROOT, "designs", design_name, "runs")
+        if not os.path.exists(runs_dir):
+            return {"error": "No runs directory found", "timing_met": False}
+
+        latest_run = sorted([d for d in os.listdir(runs_dir) if os.path.isdir(os.path.join(runs_dir, d))])[-1]
+        signoff_dir = os.path.join(runs_dir, latest_run, "reports", "signoff")
+        if not os.path.exists(signoff_dir):
+            return {"error": "Signoff report directory not found", "timing_met": False}
+
+        summary_reports: List[str] = []
+        for root, _, files in os.walk(signoff_dir):
+            for fname in files:
+                if fname.endswith(".summary.rpt") and "sta" in fname.lower():
+                    summary_reports.append(os.path.join(root, fname))
+                elif fname.endswith(".sta.rpt"):
+                    summary_reports.append(os.path.join(root, fname))
+        summary_reports = sorted(set(summary_reports))
+        if not summary_reports:
+            return {"error": "STA report not found", "timing_met": False}
+
+        corners = []
+        worst_setup = float("inf")
+        worst_hold = float("inf")
+        top_paths: List[Dict[str, Any]] = []
+
+        for sta_report in summary_reports:
+            corner_name = os.path.basename(os.path.dirname(sta_report))
+            if corner_name == "signoff":
+                corner_name = os.path.basename(sta_report).replace(".summary.rpt", "")
+
+            with open(sta_report, "r", errors="ignore") as f:
+                content = f.read()
+
+            setup_match = re.search(r"report_worst_slack -max.*?worst slack\s+([-\d.]+)", content, re.IGNORECASE | re.DOTALL)
+            hold_match = re.search(r"report_worst_slack -min.*?worst slack\s+([-\d.]+)", content, re.IGNORECASE | re.DOTALL)
+            wns_match = re.search(r"\bwns\s+([-\d.]+)", content, re.IGNORECASE)
+            all_worst = re.findall(r"worst slack\s+([-\d.]+)", content, re.IGNORECASE)
+
+            setup_slack = float(setup_match.group(1)) if setup_match else (float(wns_match.group(1)) if wns_match else (float(all_worst[0]) if all_worst else 0.0))
+            hold_slack = float(hold_match.group(1)) if hold_match else (float(all_worst[1]) if len(all_worst) > 1 else 0.0)
+
+            worst_setup = min(worst_setup, setup_slack)
+            worst_hold = min(worst_hold, hold_slack)
+
+            corners.append(
+                {
+                    "name": corner_name,
+                    "setup_slack": setup_slack,
+                    "hold_slack": hold_slack,
+                    "report_path": sta_report,
+                }
+            )
+            top_paths.extend(extract_top_sta_paths(sta_report, top_n=3))
+
+        if worst_setup == float("inf"):
+            worst_setup = 0.0
+        if worst_hold == float("inf"):
+            worst_hold = 0.0
+
+        timing_met = all((c["setup_slack"] >= 0.0 and c["hold_slack"] >= 0.0) for c in corners)
+        top_paths = sorted(top_paths, key=lambda x: x.get("slack", 0.0))[:10]
+
+        return {
+            "timing_met": timing_met,
+            "worst_setup": worst_setup,
+            "worst_hold": worst_hold,
+            "corners": corners,
+            "top_paths": top_paths,
+            "report_dir": signoff_dir,
+        }
+    except Exception as e:
+        return {"error": str(e), "timing_met": False}
 
-    except Exception as e:
-        return {"error": str(e), "timing_met": False}
-
-def parse_power_signoff(design_name: str) -> dict:
+def parse_power_signoff(design_name: str) -> dict:
     """Parses OpenLane Power Signoff reports.
     
     Args:
@@ -1528,58 +1918,92 @@ def parse_power_signoff(design_name: str) -> dict:
     Returns:
         dict: A dictionary containing power metrics.
     """
-    try:
-        # Default empty result
-        result = {
-            "total_power_w": 0.0,
-            "internal_power_w": 0.0,
-            "switching_power_w": 0.0,
-            "leakage_power_w": 0.0,
-            "sequential_pct": 0.0,
-            "combinational_pct": 0.0,
-            "irdrop_max_vpwr": 0.0,
-            "irdrop_max_vgnd": 0.0,
-            "power_ok": True
-        }
-        
-        runs_dir = os.path.join(OPENLANE_ROOT, "designs", design_name, "runs")
-        if not os.path.exists(runs_dir):
-            return result
-            
-        latest_run = sorted([d for d in os.listdir(runs_dir) if os.path.isdir(os.path.join(runs_dir, d))])[-1]
-        report_dir = os.path.join(runs_dir, latest_run, "reports", "signoff")
-        
-        # 1. Parse Power Report (e.g., .power.rpt)
-        power_report = None
-        if os.path.exists(report_dir):
-            for f in os.listdir(report_dir):
-                if "power" in f and f.endswith(".rpt"):
-                    power_report = os.path.join(report_dir, f)
-                    break
-                    
-        if power_report:
-            with open(power_report, 'r') as f:
-                content = f.read()
-                # Simple regex parsing for Total Power
-                # Format often: "Total Power: 1.23e-03"
-                total_match = re.search(r'Total Power.*?([\d.e+-]+)', content, re.IGNORECASE)
-                if total_match:
-                    result["total_power_w"] = float(total_match.group(1))
-                    
-                # Breakdowns (simplified)
-                internal_match = re.search(r'Internal Power.*?([\d.e+-]+)', content, re.IGNORECASE)
-                if internal_match: result["internal_power_w"] = float(internal_match.group(1))
-                
-                switching_match = re.search(r'Switching Power.*?([\d.e+-]+)', content, re.IGNORECASE)
-                if switching_match: result["switching_power_w"] = float(switching_match.group(1))
-                
-                leakage_match = re.search(r'Leakage Power.*?([\d.e+-]+)', content, re.IGNORECASE)
-                if leakage_match: result["leakage_power_w"] = float(leakage_match.group(1))
-
-        # 2. Parse IR Drop (Simplified placeholder)
-        # Real flow would parse openroad reports. for now assume safe.
-        return result
-
-    except Exception as e:
-        return result
+    # Default empty result
+    result = {
+        "total_power_w": 0.0,
+        "internal_power_w": 0.0,
+        "switching_power_w": 0.0,
+        "leakage_power_w": 0.0,
+        "sequential_pct": 0.0,
+        "combinational_pct": 0.0,
+        "irdrop_max_vpwr": 0.0,
+        "irdrop_max_vgnd": 0.0,
+        "power_ok": True,
+        "power_report": "",
+    }
+    try:
+        runs_dir = os.path.join(OPENLANE_ROOT, "designs", design_name, "runs")
+        if not os.path.exists(runs_dir):
+            return result
+
+        latest_run = sorted([d for d in os.listdir(runs_dir) if os.path.isdir(os.path.join(runs_dir, d))])[-1]
+        report_dir = os.path.join(runs_dir, latest_run, "reports", "signoff")
+        if not os.path.exists(report_dir):
+            return result
+
+        # Parse *.power.rpt
+        power_report = None
+        for root, _, files in os.walk(report_dir):
+            for f in files:
+                if "power" in f.lower() and f.endswith(".rpt"):
+                    power_report = os.path.join(root, f)
+                    break
+            if power_report:
+                break
+
+        if power_report and os.path.exists(power_report):
+            result["power_report"] = power_report
+            with open(power_report, "r", errors="ignore") as f:
+                content = f.read()
+            total_match = re.search(r"Total\\s+([\\d.eE+\\-]+)\\s+([\\d.eE+\\-]+)\\s+([\\d.eE+\\-]+)\\s+([\\d.eE+\\-]+)", content)
+            if total_match:
+                result["internal_power_w"] = float(total_match.group(1))
+                result["switching_power_w"] = float(total_match.group(2))
+                result["leakage_power_w"] = float(total_match.group(3))
+                result["total_power_w"] = float(total_match.group(4))
+            else:
+                total_match = re.search(r"Total\\s+Power.*?([\\d.eE+\\-]+)", content, re.IGNORECASE)
+                if total_match:
+                    result["total_power_w"] = float(total_match.group(1))
+
+            seq_match = re.search(r"Sequential.*?\\s([\\d.]+)%", content)
+            comb_match = re.search(r"Combinational.*?\\s([\\d.]+)%", content)
+            if seq_match:
+                result["sequential_pct"] = float(seq_match.group(1))
+            if comb_match:
+                result["combinational_pct"] = float(comb_match.group(1))
+
+        # Parse IR-drop reports
+        def _parse_irdrop(path: str) -> float:
+            max_drop = 0.0
+            if not os.path.exists(path):
+                return max_drop
+            with open(path, "r", errors="ignore") as f:
+                header = f.readline()
+                for line in f:
+                    parts = [p.strip() for p in line.split(",")]
+                    if len(parts) < 4:
+                        continue
+                    try:
+                        v = float(parts[3])
+                    except ValueError:
+                        continue
+                    if "VPWR" in os.path.basename(path):
+                        drop = max(0.0, 1.8 - v) if v > 0.1 else 0.0
+                    else:
+                        drop = abs(v)
+                    if drop > max_drop:
+                        max_drop = drop
+            return max_drop
+
+        vpwr_path = os.path.join(report_dir, "32-irdrop-VPWR.rpt")
+        vgnd_path = os.path.join(report_dir, "32-irdrop-VGND.rpt")
+        result["irdrop_max_vpwr"] = _parse_irdrop(vpwr_path)
+        result["irdrop_max_vgnd"] = _parse_irdrop(vgnd_path)
+
+        # 5% of 1.8V ~= 90mV
+        result["power_ok"] = result["irdrop_max_vpwr"] <= 0.09 and result["irdrop_max_vgnd"] <= 0.09
+        return result
+    except Exception:
+        return result
 

tests/test_tier1_upgrade.py

@@ -0,0 +1,203 @@
+import os
+import re
+import sys
+import shutil
+import tempfile
+import textwrap
+import unittest
+
+REPO_ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
+SRC_ROOT = os.path.join(REPO_ROOT, "src")
+if SRC_ROOT not in sys.path:
+    sys.path.insert(0, SRC_ROOT)
+
+from agentic.tools import vlsi_tools  # noqa: E402
+from agentic.orchestrator import BuildOrchestrator  # noqa: E402
+
+
+class SyntaxIntegrityTests(unittest.TestCase):
+    def test_no_merge_conflict_markers(self):
+        base = os.path.join(REPO_ROOT, "src", "agentic")
+        bad = []
+        for root, _, files in os.walk(base):
+            for fname in files:
+                if not fname.endswith(".py"):
+                    continue
+                path = os.path.join(root, fname)
+                with open(path, "r", errors="ignore") as f:
+                    for idx, line in enumerate(f, start=1):
+                        if line.startswith("<<<<<<<") or line.startswith(">>>>>>>"):
+                            bad.append(f"{path}:{idx}")
+        self.assertEqual([], bad, msg=f"Found conflict markers: {bad}")
+
+
+class SemanticGateTests(unittest.TestCase):
+    def _write_tmp(self, code: str) -> str:
+        tmpdir = tempfile.mkdtemp(prefix="tier1_sem_")
+        path = os.path.join(tmpdir, "dut.sv")
+        with open(path, "w") as f:
+            f.write(code)
+        self.addCleanup(lambda: shutil.rmtree(tmpdir, ignore_errors=True))
+        return path
+
+    def test_port_shadowing_rejected(self):
+        code = textwrap.dedent(
+            """
+            module dut(
+                input logic clk,
+                input logic a,
+                output logic y
+            );
+                logic a;
+                always_comb y = a;
+            endmodule
+            """
+        )
+        path = self._write_tmp(code)
+        ok, report = vlsi_tools.run_semantic_rigor_check(path)
+        self.assertFalse(ok)
+        self.assertIn("a", report.get("port_shadowing", []))
+
+    def test_clean_semantics_pass(self):
+        code = textwrap.dedent(
+            """
+            module dut(
+                input logic clk,
+                input logic [3:0] a,
+                output logic [3:0] y
+            );
+                always_comb y = a;
+            endmodule
+            """
+        )
+        path = self._write_tmp(code)
+        ok, report = vlsi_tools.run_semantic_rigor_check(path)
+        self.assertTrue(ok, msg=str(report))
+
+
+class ParserTests(unittest.TestCase):
+    def test_log_summary_stream_parser(self):
+        tmpdir = tempfile.mkdtemp(prefix="tier1_log_")
+        self.addCleanup(lambda: shutil.rmtree(tmpdir, ignore_errors=True))
+        log = os.path.join(tmpdir, "routing.log")
+        with open(log, "w") as f:
+            for _ in range(5000):
+                f.write("[INFO GRT] overflow on met2 congestion\n")
+            for _ in range(200):
+                f.write("[WARN] antenna violation\n")
+        summary = vlsi_tools.parse_eda_log_summary(log, kind="routing", top_n=10)
+        self.assertEqual(summary.get("total_lines"), 5200)
+        self.assertTrue(summary.get("top_issues"))
+        self.assertIn("routing_congestion", summary.get("counts", {}))
+
+    def test_multi_corner_sta_parse(self):
+        tmp = tempfile.mkdtemp(prefix="tier1_sta_")
+        self.addCleanup(lambda: shutil.rmtree(tmp, ignore_errors=True))
+        original = vlsi_tools.OPENLANE_ROOT
+        vlsi_tools.OPENLANE_ROOT = tmp
+        self.addCleanup(lambda: setattr(vlsi_tools, "OPENLANE_ROOT", original))
+
+        base = os.path.join(tmp, "designs", "chip", "runs", "run1", "reports", "signoff")
+        for corner, setup, hold in [
+            ("26-mca", "5.20", "0.11"),
+            ("28-mca", "5.00", "0.09"),
+            ("30-mca", "4.90", "0.08"),
+        ]:
+            os.makedirs(os.path.join(base, corner), exist_ok=True)
+            path = os.path.join(base, corner, f"{corner}_sta.summary.rpt")
+            with open(path, "w") as f:
+                f.write(
+                    textwrap.dedent(
+                        f"""
+                        report_wns
+                        wns {setup}
+                        report_worst_slack -max (Setup)
+                        worst slack {setup}
+                        report_worst_slack -min (Hold)
+                        worst slack {hold}
+                        """
+                    )
+                )
+        sta = vlsi_tools.parse_sta_signoff("chip")
+        self.assertFalse(sta.get("error"))
+        self.assertEqual(3, len(sta.get("corners", [])))
+        self.assertAlmostEqual(4.90, sta.get("worst_setup"), places=2)
+        self.assertAlmostEqual(0.08, sta.get("worst_hold"), places=2)
+
+    def test_congestion_parser(self):
+        tmp = tempfile.mkdtemp(prefix="tier1_cong_")
+        self.addCleanup(lambda: shutil.rmtree(tmp, ignore_errors=True))
+        original = vlsi_tools.OPENLANE_ROOT
+        vlsi_tools.OPENLANE_ROOT = tmp
+        self.addCleanup(lambda: setattr(vlsi_tools, "OPENLANE_ROOT", original))
+
+        log_dir = os.path.join(tmp, "designs", "chip", "runs", "agentrun", "logs", "routing")
+        os.makedirs(log_dir, exist_ok=True)
+        log_path = os.path.join(log_dir, "19-global.log")
+        with open(log_path, "w") as f:
+            f.write("met1 8342 44 0.53% 0 / 0 / 0\n")
+            f.write("met2 8036 1580 19.66% 5 / 2 / 7\n")
+            f.write("Total 16378 1624 9.91% 5 / 2 / 7\n")
+        data = vlsi_tools.parse_congestion_metrics("chip")
+        self.assertAlmostEqual(9.91, data.get("total_usage_pct"), places=2)
+        self.assertEqual(7, data.get("total_overflow"))
+
+
+class OrchestratorSafetyTests(unittest.TestCase):
+    def test_failure_fingerprint_repetition(self):
+        orch = BuildOrchestrator(
+            name="fingerprint_demo",
+            desc="demo",
+            llm=None,
+            strict_gates=True,
+        )
+        first = orch._record_failure_fingerprint("same failure")
+        second = orch._record_failure_fingerprint("same failure")
+        self.assertFalse(first)
+        self.assertTrue(second)
+
+    def test_hierarchy_auto_threshold(self):
+        orch = BuildOrchestrator(
+            name="hier_demo",
+            desc="demo",
+            llm=None,
+            hierarchical_mode="auto",
+        )
+        rtl = "\n".join([
+            "module top(input logic clk, output logic y); assign y = 1'b0; endmodule",
+            "module blk_a(input logic i, output logic o); assign o = i; endmodule",
+            "module blk_b(input logic i, output logic o); assign o = i; endmodule",
+        ] + ["// filler"] * 650)
+        orch._evaluate_hierarchy(rtl)
+        plan = orch.artifacts.get("hierarchy_plan", {})
+        self.assertTrue(plan.get("enabled"), msg=str(plan))
+
+    def test_benchmark_metrics_written_to_metircs(self):
+        import agentic.orchestrator as orch_mod
+
+        tmp = tempfile.mkdtemp(prefix="tier1_metircs_")
+        self.addCleanup(lambda: shutil.rmtree(tmp, ignore_errors=True))
+        old_workspace = orch_mod.WORKSPACE_ROOT
+        orch_mod.WORKSPACE_ROOT = tmp
+        self.addCleanup(lambda: setattr(orch_mod, "WORKSPACE_ROOT", old_workspace))
+
+        orch = BuildOrchestrator(name="metric_chip", desc="demo", llm=None)
+        orch.state = orch.state.SUCCESS
+        orch.artifacts["signoff_result"] = "PASS"
+        orch.artifacts["metrics"] = {"chip_area_um2": 1234.5, "area": 321, "utilization": 42.0, "timing_tns": 0.0, "timing_wns": 0.1}
+        orch.artifacts["sta_signoff"] = {"worst_setup": 0.1, "worst_hold": 0.05}
+        orch.artifacts["power_signoff"] = {"total_power_w": 1e-3, "internal_power_w": 5e-4, "switching_power_w": 4e-4, "leakage_power_w": 1e-5, "irdrop_max_vpwr": 0.01, "irdrop_max_vgnd": 0.02}
+        orch.artifacts["signoff"] = {"drc_violations": 0, "lvs_errors": 0, "antenna_violations": 0}
+        orch.artifacts["coverage"] = {"line_pct": 90.0}
+        orch.artifacts["formal_result"] = "PASS"
+        orch.artifacts["lec_result"] = "PASS"
+        orch._save_industry_benchmark_metrics()
+
+        metircs_dir = os.path.join(tmp, "metircs", "metric_chip")
+        self.assertTrue(os.path.isdir(metircs_dir))
+        self.assertTrue(os.path.isfile(os.path.join(metircs_dir, "latest.json")))
+        self.assertTrue(os.path.isfile(os.path.join(metircs_dir, "latest.md")))
+
+
+if __name__ == "__main__":
+    unittest.main()