Initial commit of AgentIC

.gitignore

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+# Python
+__pycache__/
+*.pyc
+*.pyo
+*.pyd
+.Python
+env/
+venv/
+.env
+.venv
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+
+# AgentIC Specific
+# Ignore massive run logs or temporary build artifacts if they end up here
+runs/
+*.log
+*.vcd
+work/
+transcript
+
+# System
+.DS_Store
+Thumbs.db
+
+# OpenLane outputs (if copied here)
+# Uncomment the line below if you don't want to version control large GDS files
+# *.gds

AZURE_STUDENT_GUIDE.md

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+# ☁️ Azure Student Developer Pack Guide for AgentIC
+
+Since your local PC is overheating, moving to Azure is the perfect solution. With the **Microsoft Azure Student Pack**, you get **$100 credit** and free access to specific services.
+
+This guide will help you create a **Virtual Machine (VM)** to run OpenLane and AgentIC without burning your laptop.
+
+## 1. Create the Virtual Machine (VM)
+The "hectic" part is the OpenLane build process (compiling 30,000 transistors!).
+
+1.  Log in to the [Azure Portal](https://portal.azure.com).
+2.  Click **"Create a resource"** > **"Virtual Machine"**.
+3.  **Basics Tab**:
+    *   **Subscription**: Azure for Students.
+    *   **Resource Group**: Create new (e.g., `rg-agentic`).
+    *   **Virtual Machine Name**: `vm-agentic`.
+    *   **Region**: Pick one close to you (e.g., East US).
+    *   **Image**: **Ubuntu Server 22.04 LTS - x64 Gen2**.
+    *   **Size**: **Standard D4s v3** (4 vCPUs, 16 GiB memory).
+        *   *Note:* This costs about ~$0.18/hour. Since you have $100 credits, you can run this for ~500 hours.
+        *   *Important:* Remember to **STOP** the VM when you aren't using it to save credits!
+4.  **Administrator Account**:
+    *   **Authentication type**: SSH public key.
+    *   **Username**: `azureuser`.
+    *   **Key source**: Generate new key pair.
+5.  **Review + create** > **Create**.
+    *   Download the private key (`.pem` file) when prompted. Keep it safe!
+
+## 2. Connect to the Cloud
+1.  Open your local terminal (Git Bash or WSL).
+2.  Move the key to a safe place and secure it:
+    ```bash
+    mv ~/Downloads/vm-agentic_key.pem ~/.ssh/
+    chmod 400 ~/.ssh/vm-agentic_key.pem
+    ```
+3.  Connect (replace `YOUR_VM_IP` with the Public IP from Azure Portal):
+    ```bash
+    ssh -i ~/.ssh/vm-agentic_key.pem azureuser@YOUR_VM_IP
+    ```
+
+## 3. Install the Environment (One-Time Setup)
+Copy and paste this block into your Azure SSH terminal to install everything:
+
+```bash
+# Update and Install Docker
+sudo apt-get update
+sudo apt-get install -y docker.io python3-pip python3-venv git make
+sudo usermod -aG docker $USER
+newgrp docker
+
+# Setup OpenLane
+git clone https://github.com/The-OpenROAD-Project/OpenLane.git ~/OpenLane
+cd ~/OpenLane
+# This download is heavy (~2GB), but it runs on Azure's fast internet!
+make pull-openlane 
+
+# Get your AgentIC code
+# (You can clone your repo, or we create a fresh one)
+mkdir -p ~/AgentIC
+```
+
+## 4. Solving the "Thinking" Heat (The LLM)
+Running Ollama (DeepSeek) locally is what heats up your GPU. On an Azure CPU VM, it will be slow.
+**Recommendation:** Use the **DeepSeek API** instead. It costs pennies and offloads the "brain" work to DeepSeek's servers.
+
+1.  Get an API Key from [platform.deepseek.com](https://platform.deepseek.com).
+2.  On the Azure VM, export it:
+    ```bash
+    export OPENAI_API_KEY="sk-..."  # Your DeepSeek Key
+    export OPENAI_API_BASE="https://api.deepseek.com"
+    export LLM_MODEL="deepseek-chat"
+    ```
+
+## 5. Running the Flow
+Now, your laptop stays cool while Azure does the work.
+
+```bash
+# On Azure VM
+cd ~/AgentIC
+python3 main.py build --name cloud_chip --desc "An 8-bit counter"
+```
+
+## 6. Retrieving the Result
+When finished, download the GDS file to your laptop to view it:
+
+```bash
+# On Local Laptop
+scp -i ~/.ssh/vm-agentic_key.pem azureuser@YOUR_VM_IP:~/AgentIC/cloud_chip.gds ./
+```

CLOUD_DEPLOY.md

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+# Cloud Migration Guide for AgentIC + OpenLane
+
+This guide explains how to move your local AI-to-GDSII flow to a cloud provider (AWS, GCP, Azure, Lambda Labs, or RunPod).
+
+## 1. Hardware Requirements
+OpenLane and Local LLMs are resource-intensive. Do not use a "Free Tier" (t2.micro) instance.
+
+*   **CPU**: 4 vCPUs minimum (8 recommended for Place & Route).
+*   **RAM**: 16 GB minimum (32 GB recommended).
+*   **Storage**: 50 GB SSD minimum (Docker images + PDKs take ~30GB).
+*   **GPU**: NVIDIA T4 (16GB VRAM) or better recommended if running Ollama locally.
+
+## 2. Setup Script (Ubuntu 22.04 / 24.04)
+Run these commands on your new cloud instance to replicate your environment.
+
+### A. Install System Dependencies
+```bash
+sudo apt-get update && sudo apt-get install -y \
+    docker.io \
+    python3-pip \
+    python3-venv \
+    git \
+    make \
+    curl \
+    iverilog
+    
+# Add user to docker group (avoids sudo for docker)
+sudo usermod -aG docker $USER
+newgrp docker
+```
+
+### B. Install Ollama (for DeepSeek)
+If you have a GPU, install the Nvidia Container Toolkit first. If CPU-only, just run:
+```bash
+curl -fsSL https://ollama.com/install.sh | sh
+
+# Pull the model
+ollama pull deepseek-r1
+```
+
+### C. Clone & Setup Your Workspace
+```bash
+# Clone OpenLane (Infrastructure)
+git clone https://github.com/The-OpenROAD-Project/OpenLane.git ~/OpenLane
+cd ~/OpenLane
+make pull-openlane  # Downloads the heavy Docker images
+
+# Clone AgentIC (Your Logic)
+# (Assuming you push your local code to a git repo first)
+git clone <YOUR_GITHUB_REPO_URL> ~/AgentIC
+
+# Setup Python Env
+cd ~/AgentIC
+python3 -m venv agentic_env
+source agentic_env/bin/activate
+pip install -r requirements.txt
+```
+
+## 3. Remote Access
+To view your designs (GDSII files) or access the terminal easily, use VS Code Remote - SSH.
+
+1.  In local VS Code: Install "Remote - SSH" extension.
+2.  Connect to `ssh user@your-cloud-ip`.
+3.  Open the folder `/home/user/AgentIC`.
+
+## 4. Modified Flow for Cloud (Headless)
+Since you won't have a GUI window for `klayout` or unnecessary graphics:
+
+1.  Run the build command normally:
+    ```bash
+    python main.py build --name cloud_adder --desc "8-bit adder"
+    ```
+2.  **Viewing Results**: Do not try to open KLayout on the server. Instead, use the `scp` command to copy the final GDS file to your local machine:
+    ```bash
+    # Run this on your LOCAL machine
+    scp user@your-cloud-ip:~/OpenLane/designs/cloud_adder/runs/agentrun/results/final/gds/cloud_adder.gds ./
+    ```

COOL_MODE.md

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+# 🔥 Cooling Down: How to Run Locally Safely
+
+**No, your computer will not "blast".**
+Modern CPUs and GPUs have safety sensors. If they get too hot (usually 100°C+), they will automatically slow down ("thermal throttle") or shut off the computer to prevent damage.
+
+However, running a 5GB model like `deepseek-r1` pins your processor to 100% usage, which generates max heat.
+
+## Solution: Use a "Lighter" Brain
+Since you need to run strictly locally ($0 cost), the best way to reduce heat is to use a **smaller model**.
+
+A 1.5B or 3B model requires **much less math** per second than a 7B/8B model. It will run faster and generate less heat.
+
+### Recommended Models for Coding (Low Heat)
+1.  **DeepSeek Coder 1.3B** (Tiny, very fast, decent at Verilog)
+2.  **Qwen 2.5 Coder 3B** (Excellent balance of smarts and speed)
+
+### How to Switch
+1.  **Open Terminal and Pull a Tiny Model:**
+    ```bash
+    # Try the 1.3 Billion parameter version (approx 700MB - 1GB)
+    ollama pull deepseek-coder:1.3b
+    
+    # OR try Qwen 3B (approx 2GB) - Better quality
+    ollama pull qwen2.5-coder:3b
+    ```
+
+2.  **Update AgentIC to use it:**
+    Open `src/agentic/config.py` and change `LLM_MODEL`:
+    ```python
+    # LLM_MODEL = "ollama/deepseek-r1"  <-- Comment this out (Heat: High)
+    LLM_MODEL = "ollama/deepseek-coder:1.3b"  # <-- Use this (Heat: Low)
+    ```
+
+3.  **Physical Tips:**
+    *   Prop up the back of your laptop for airflow.
+    *   Use a cooling pad if you have one.

README.md

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+# AgentIC Workflow Guide
+
+This document outlines the automated chip design workflow using **AgentIC** and **OpenLane**.
+
+## Logic Flow
+
+The system transforms natural language descriptions into physical GDSII manufacturing files through a multi-step agentic pipeline.
+
+```mermaid
+graph TD
+    User[User Command] -->|main.py build| A[AgentIC]
+    A -->|Step 1: Generated RTL| B(VLSI Design Agent)
+    B -->|vicky_adder.v| C{Syntax Check}
+    C -->|Pass| D(Verification Agent)
+    C -->|Fail| Z[Error / Retry]
+    D -->|vicky_adder_tb.v| E{Simulation}
+    E -->|Pass| F[OpenLane Integration]
+    E -->|Fail| Z
+    
+    subgraph OpenLane Infrastructure
+    F -->|Docker Mount| G[OpenLane Flow]
+    G -->|flow.tcl| H[Synthesis yosys]
+    H --> I[Floorplan]
+    I --> J[Placement]
+    J --> K[Routing]
+    K --> L[GDSII Layout]
+    end
+    
+    L -->|Output| M[Final GDSII & Reports]
+```
+
+## Directory Structure & Important Files
+
+The workspace is consolidated into two main components:
+
+### 1. AgentIC ( The "Brain" )
+Controls the process.
+- **`main.py`**: The entry point.
+- **`src/agentic/`**: The core Python package.
+    - **`agents/`**: AI engineer definitions.
+    - **`tools/`**: Interfaces to VLSI tools.
+    - **`config.py`**: Configuration settings (paths, LLMs).
+- **`scripts/verify_design.sh`**: A helper script for verification.
+
+### 2. OpenLane ( The "Muscle" )
+The execution engine.
+- **`designs/simple_counter`**: **CRITICAL**. Used as a configuration template for all new AI designs.
+- **`designs/<your_design>`**: Where your new chips will be created.
+- **`flow.tcl`**: The main script run by the Docker container.
+
+## How to Run
+
+### 1. Build a new chip
+```bash
+cd ~/AgentIC
+python main.py build --name vicky_adder --desc "A 4-bit adder with carry out"
+```
+
+### 2. Verify an existing chip
+```bash
+cd ~/AgentIC
+python main.py verify vicky_adder
+```
+
+## Maintenance
+- **Do not delete** `OpenLane/designs/simple_counter` - it is needed for config generation.
+- **Do not delete** the `OpenLane` root files - they are mounted into the Docker container.

app.py

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+import streamlit as st
+import os
+import pandas as pd
+import subprocess
+import glob
+
+# Configuration
+OPENLANE_ROOT = os.environ.get("OPENLANE_ROOT", os.path.expanduser("~/OpenLane"))
+DESIGNS_DIR = os.path.join(OPENLANE_ROOT, "designs")
+
+st.set_page_config(page_title="AgentIC Dashboard", page_icon="チップ", layout="wide")
+
+st.title("🤖 AgentIC: AI Chip Design Studio")
+st.markdown("Monitor your AI-generated silicon designs and metrics.")
+
+# --- Sidebar: Project Selection ---
+if not os.path.exists(DESIGNS_DIR):
+    st.error(f"OpenLane Design Directory not found at: {DESIGNS_DIR}")
+    st.stop()
+
+designs = [d for d in os.listdir(DESIGNS_DIR) if os.path.isdir(os.path.join(DESIGNS_DIR, d))]
+# Filter out standard openlane designs if needed, keeping it simple for now
+selected_design = st.sidebar.selectbox("Select Design", designs)
+
+# --- Main Content ---
+
+if selected_design:
+    design_path = os.path.join(DESIGNS_DIR, selected_design)
+    
+    # 1. Source Code Viewer
+    st.header(f"📦 Design: {selected_design}")
+    
+    verilog_path = os.path.join(design_path, "src", f"{selected_design}.v")
+    if os.path.exists(verilog_path):
+        with open(verilog_path, "r") as f:
+            code = f.read()
+        with st.expander("Show Verilog Source", expanded=False):
+            st.code(code, language="verilog")
+    else:
+        st.warning("No Verilog source found.")
+
+    # 2. Build Status & Metrics
+    st.subheader("🏭 Fabrication Status")
+    
+    # Check for GDS
+    # Note: AgentIC uses tag "agentrun", but users might use others.
+    # We look for the most recent run or 'agentrun'
+    runs_dir = os.path.join(design_path, "runs")
+    gds_path = None
+    report_path = None
+    
+    if os.path.exists(runs_dir):
+        # Prefer 'agentrun' if it exists, else latest
+        if os.path.exists(os.path.join(runs_dir, "agentrun")):
+            run_name = "agentrun"
+        else:
+            # find latest run
+            all_runs = sorted(glob.glob(os.path.join(runs_dir, "*")), key=os.path.getmtime, reverse=True)
+            run_name = os.path.basename(all_runs[0]) if all_runs else None
+            
+        if run_name:
+            st.info(f"Viewing Run: **{run_name}**")
+            
+            # GDS Path
+            possible_gds = os.path.join(runs_dir, run_name, "results", "final", "gds", f"{selected_design}.gds")
+            if os.path.exists(possible_gds):
+                gds_path = possible_gds
+                st.success("✅ GDSII Layout Generated")
+                
+                # Download Button
+                with open(gds_path, "rb") as f:
+                    st.download_button(
+                        label="⬇️ Download GDSII File",
+                        data=f,
+                        file_name=f"{selected_design}.gds",
+                        mime="application/octet-stream"
+                    )
+            else:
+                st.warning("⚠️ No GDSII file found in this run.")
+
+            # Metrics (CSV)
+            # OpenLane typically stores metrics in reports/metrics.csv
+            possible_csv = os.path.join(runs_dir, run_name, "reports", "metrics.csv")
+            if os.path.exists(possible_csv):
+                try:
+                    df = pd.read_csv(possible_csv)
+                    # Transpose for better reading if it's a single row
+                    st.dataframe(df.T)
+                except Exception as e:
+                    st.error(f"Could not read metrics CSV: {e}")
+            else:
+                 st.info("No metrics.csv report found.")
+        else:
+             st.info("No runs found for this design.")
+    else:
+        st.info("No runs directory found.")
+
+# --- New Design Creator ---
+st.markdown("---")
+st.subheader("✨ Create New Design")
+
+with st.form("new_design_form"):
+    new_name = st.text_input("Design Name (no spaces)", "my_new_chip")
+    new_desc = st.text_area("Description", "A 8-bit shift register with enable signal.")
+    submitted = st.form_submit_button("🚀 Launch AI Designer")
+
+    if submitted:
+        if " " in new_name:
+            st.error("Design name cannot contain spaces.")
+        else:
+            cmd = ["python3", "main.py", "build", "--name", new_name, "--desc", new_desc]
+            
+            with st.spinner("AI is thinking and building... (This generally takes 5-10 mins)"):
+                # We run this from the AgentIC root
+                process = subprocess.run(
+                    cmd, 
+                    cwd=os.path.dirname(os.path.abspath(__file__)),
+                    capture_output=True, 
+                    text=True
+                )
+                
+            if process.returncode == 0:
+                st.success(f"Design '{new_name}' created successfully!")
+                st.text_area("Build Output", process.stdout, height=200)
+                st.rerun()
+            else:
+                st.error("Build failed.")
+                st.text_area("Error Log", process.stderr, height=200)

main.py

@@ -0,0 +1,11 @@
+#!/usr/bin/env python3
+import sys
+import os
+
+# Add src to path so we can import the package
+sys.path.insert(0, os.path.join(os.path.dirname(__file__), "src"))
+
+from agentic.cli import app
+
+if __name__ == "__main__":
+    app()

requirements.txt

@@ -0,0 +1,7 @@
+crewai
+crewai-tools
+langchain_openai
+typer
+rich
+streamlit
+pandas

scripts/verify_design.sh

@@ -0,0 +1,91 @@
+#!/bin/bash
+
+# Usage: ./verify_design.sh <design_name>
+
+if [ -z "$1" ]; then
+    echo "Usage: ./verify_design.sh <design_name>"
+    exit 1
+fi
+
+DESIGN=$1
+OPENLANE_ROOT=~/OpenLane
+DESIGN_DIR=$OPENLANE_ROOT/designs/$DESIGN
+
+echo "========================================"
+echo "Verifying Design: $DESIGN"
+echo "========================================"
+
+# 1. Functional Verification (RTL Simulation)
+echo "[1] Functional Verification (Icarus Verilog)"
+if [ -f "$DESIGN_DIR/src/${DESIGN}_tb.v" ]; then
+    echo "    Found Testbench: ${DESIGN}_tb.v"
+    cd $DESIGN_DIR/src
+    iverilog -o sim ${DESIGN}.v ${DESIGN}_tb.v
+    if [ $? -eq 0 ]; then
+        echo "    Compilation Successful."
+        echo "    Running Simulation..."
+        vvp sim > simulation.log
+        cat simulation.log
+        echo "    (Check output above for expected behavior)"
+    else
+        echo "    [ERROR] Compilation Failed."
+    fi
+    cd $OPENLANE_ROOT
+else
+    echo "    [WARNING] No testbench found at $DESIGN_DIR/src/${DESIGN}_tb.v"
+    echo "    Please create one to run functional simulation."
+fi
+
+echo ""
+echo "========================================"
+
+# 2. Physical Verification (OpenLane Reports)
+echo "[2] Physical Verification (Latest Run)"
+LATEST_RUN=$(ls -td $DESIGN_DIR/runs/* | head -1)
+
+if [ -z "$LATEST_RUN" ]; then
+    echo "    [ERROR] No runs found for $DESIGN."
+else
+    echo "    Checking run: $(basename $LATEST_RUN)"
+    
+    # Check DRC
+    DRC_RPT=$(find $LATEST_RUN -name "*drc.rpt" | head -1)
+    if [ -f "$DRC_RPT" ]; then
+        echo "    --- DRC Report ($(basename $DRC_RPT)) ---"
+        COUNT=$(grep -c "violation" $DRC_RPT)
+        if [ "$COUNT" -eq "0" ]; then
+             # Some reports might use different format, check content
+             grep "Count: 0" $DRC_RPT > /dev/null
+             if [ $? -eq 0 ]; then
+                echo "    [PASS] No DRC Violations found."
+             else
+                # Print last few lines
+                tail -n 5 $DRC_RPT
+             fi
+        else
+            echo "    [FAIL] Found potential violations."
+            tail -n 5 $DRC_RPT
+        fi
+    else
+        echo "    [WARNING] DRC Report not found."
+    fi
+
+    echo ""
+    
+    # Check LVS
+    LVS_RPT=$(find $LATEST_RUN -name "*lvs.log" | head -1)
+    if [ -f "$LVS_RPT" ]; then
+        echo "    --- LVS Report ($(basename $LVS_RPT)) ---"
+        if grep -q "Total errors = 0" $LVS_RPT; then
+            echo "    [PASS] LVS Clean. Layout matches Schematic."
+        else
+            echo "    [FAIL] LVS Mismatch."
+             grep "Total errors" $LVS_RPT
+        fi
+    else
+         echo "    [WARNING] LVS Report not found."
+    fi
+fi
+
+echo "========================================"
+echo "Verification Complete."

src/agentic/__init__.py

@@ -0,0 +1,4 @@
+"""
+AgentIC - AI-Driven Chip Design Framework
+"""
+__version__ = "0.1.0"

src/agentic/agents/designer.py

@@ -0,0 +1,14 @@
+# agents/designer.py
+from crewai import Agent
+from ..config import LLM_MODEL
+
+def get_designer_agent():
+    return Agent(
+        role='VLSI Design Engineer',
+        goal='Create optimized Verilog for {design_input}',
+        backstory='Specialist in ECE from Lucknow University. Expert in Sky130 PDK.',
+        # IMPORTANT: Use the "ollama/" prefix so CrewAI doesn't look for OpenAI
+        llm=LLM_MODEL, 
+        verbose=True,
+        allow_delegation=False
+    )

src/agentic/agents/testbench_designer.py

@@ -0,0 +1,15 @@
+# agents/testbench_designer.py
+from crewai import Agent
+
+def get_testbench_agent(llm):
+    """Returns an agent specialized in writing Verilog testbenches."""
+    return Agent(
+        role='Verification Engineer',
+        goal='Create comprehensive Verilog testbenches for {design_name}',
+        backstory='''Expert in digital verification with deep knowledge of 
+        Verilog simulation. Focuses on edge cases, reset behavior, and 
+        timing checks. Always includes $monitor, $dumpfile, and $finish.''',
+        llm=llm,
+        verbose=True,
+        allow_delegation=False
+    )

src/agentic/cli.py

@@ -0,0 +1,232 @@
+#!/usr/bin/env python3
+"""
+AgentIC - Natural Language to GDSII Pipeline
+=============================================
+Uses CrewAI + Ollama (DeepSeek) to generate chips from natural language.
+
+Usage:
+    python main.py build --name counter --desc "8-bit counter with enable and reset"
+"""
+
+import os
+import sys
+import typer
+from rich.console import Console
+from rich.panel import Panel
+from rich.progress import Progress, SpinnerColumn, TextColumn
+from crewai import Agent, Task, Crew, LLM
+
+# Local imports
+from .config import OPENLANE_ROOT, LLM_MODEL, LLM_BASE_URL, LLM_API_KEY
+from .tools.vlsi_tools import (
+    write_verilog, 
+    run_syntax_check,
+    run_simulation, 
+    run_openlane,
+    run_verification
+)
+
+# --- INITIALIZE ---
+app = typer.Typer()
+console = Console()
+
+# Setup Brain
+def get_llm():
+    """Returns the LLM instance for agents."""
+    return LLM(
+        model=LLM_MODEL,
+        base_url=LLM_BASE_URL,
+        api_key=LLM_API_KEY
+    )
+
+# --- THE BUILD COMMAND ---
+@app.command()
+def build(
+    name: str = typer.Option(..., "--name", "-n", help="Design name (e.g., counter)"),
+    desc: str = typer.Option(..., "--desc", "-d", help="Natural language description")
+):
+    """Build a chip from natural language description."""
+    
+    console.print(Panel(
+        f"[bold cyan]AgentIC: Natural Language → GDSII[/bold cyan]\n"
+        f"Design: [yellow]{name}[/yellow]\n"
+        f"Description: {desc}",
+        title="🚀 Starting Pipeline"
+    ))
+
+    llm = get_llm()
+    
+    # ===== STEP 1: Generate RTL =====
+    console.print("\n[bold yellow]━━━ Step 1/5: Generating Verilog RTL ━━━[/bold yellow]")
+    
+    rtl_agent = Agent(
+        role='VLSI Design Engineer',
+        goal=f'Create synthesizable Verilog for: {desc}',
+        backstory='Expert in digital design with Sky130 PDK experience.',
+        llm=llm,
+        verbose=False
+    )
+    
+    rtl_task = Task(
+        description=f'''Design a Verilog module named "{name}" that implements: {desc}
+        
+        CRITICAL REQUIREMENTS:
+        - Module name must be exactly "{name}"
+        - Use VERILOG-2005 ONLY (NOT SystemVerilog)
+        - Use "always @(*)" NOT "always_comb"
+        - Use "reg" for outputs in combinational logic
+        - Include clock (clk) and active-low reset (rst_n) if sequential
+        - Return ONLY the Verilog code wrapped in ```verilog fences
+        - NO explanations, NO comments about the code
+        
+        Example format:
+        ```verilog
+        module {name}(...);
+        ...
+        endmodule
+        ```
+        ''',
+        expected_output='Complete Verilog-2005 module code in markdown fence',
+        agent=rtl_agent
+    )
+    
+    with console.status("[cyan]AI is designing your chip...[/cyan]"):
+        rtl_result = Crew(agents=[rtl_agent], tasks=[rtl_task]).kickoff()
+    
+    rtl_path = write_verilog(name, str(rtl_result))
+    console.print(f"  ✓ RTL saved to: [green]{rtl_path}[/green]")
+    
+    # ===== STEP 2: Syntax Check RTL =====
+    console.print("\n[bold yellow]━━━ Step 2/5: Syntax Verification ━━━[/bold yellow]")
+    
+    success, errors = run_syntax_check(rtl_path)
+    if not success:
+        console.print(f"[bold red]✗ SYNTAX ERROR:[/bold red]\n{errors}")
+        raise typer.Exit(1)
+    console.print("  ✓ Verilog syntax is [green]valid[/green]")
+    
+    # ===== STEP 3: Generate Testbench =====
+    console.print("\n[bold yellow]━━━ Step 3/5: Generating Testbench ━━━[/bold yellow]")
+    
+    # Read the generated RTL for context
+    with open(rtl_path, 'r') as f:
+        rtl_code = f.read()
+    
+    tb_agent = Agent(
+        role='Verification Engineer',
+        goal=f'Create a testbench for {name}',
+        backstory='Expert in Verilog verification and simulation.',
+        llm=llm,
+        verbose=False
+    )
+    
+    tb_task = Task(
+        description=f'''Create a Verilog-2005 testbench for this module:
+        
+```verilog
+{rtl_code}
+```
+
+CRITICAL REQUIREMENTS:
+- Module name must be "{name}_tb"
+- Use VERILOG-2005 ONLY (NOT SystemVerilog)
+- Use explicit port connections: .clk(clk), .a(a), etc.
+- Use integer delays like #5 or #10, NOT #5ns or #10ns
+- Clock: forever #5 clk = ~clk (inside initial block)
+- Put $monitor INSIDE an initial block
+- Use $dumpfile("{name}.vcd") and $dumpvars(0, {name}_tb)
+- End with $finish
+- Return ONLY the testbench code wrapped in ```verilog fences
+
+Example structure:
+```verilog
+module {name}_tb;
+  reg clk, rst_n;
+  // declare inputs as reg, outputs as wire
+  
+  {name} uut(.clk(clk), .rst_n(rst_n), ...);
+  
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
+  
+  initial begin
+    $dumpfile("{name}.vcd");
+    $dumpvars(0, {name}_tb);
+    $monitor(...);
+    // test sequence
+    $finish;
+  end
+endmodule
+```
+''',
+        expected_output='Complete Verilog-2005 testbench in markdown fence',
+        agent=tb_agent
+    )
+    
+    with console.status("[cyan]AI is creating testbench...[/cyan]"):
+        tb_result = Crew(agents=[tb_agent], tasks=[tb_task]).kickoff()
+    
+    tb_path = write_verilog(name, str(tb_result), is_testbench=True)
+    console.print(f"  ✓ Testbench saved to: [green]{tb_path}[/green]")
+    
+    # ===== STEP 4: Run Simulation =====
+    console.print("\n[bold yellow]━━━ Step 4/5: Running Simulation ━━━[/bold yellow]")
+    
+    sim_success, sim_output = run_simulation(name)
+    if not sim_success:
+        console.print(f"[bold red]✗ SIMULATION FAILED:[/bold red]\n{sim_output}")
+        raise typer.Exit(1)
+    
+    # Show last few lines of simulation
+    sim_lines = sim_output.strip().split('\n')
+    for line in sim_lines[-5:]:
+        console.print(f"  [dim]{line}[/dim]")
+    console.print("  ✓ Simulation [green]passed[/green]")
+    
+    # ===== STEP 5: Run OpenLane =====
+    console.print("\n[bold yellow]━━━ Step 5/5: Running OpenLane (RTL → GDSII) ━━━[/bold yellow]")
+    console.print("  [dim]This may take 5-10 minutes...[/dim]")
+    
+    # Create config.tcl from template
+    template_config = f"{OPENLANE_ROOT}/designs/simple_counter/config.tcl"
+    new_config = f"{OPENLANE_ROOT}/designs/{name}/config.tcl"
+    
+    if os.path.exists(template_config) and not os.path.exists(new_config):
+        with open(template_config, 'r') as f:
+            content = f.read().replace("simple_counter", name)
+        with open(new_config, 'w') as f:
+            f.write(content)
+        console.print(f"  ✓ Config created from template")
+    
+    ol_success, ol_result = run_openlane(name)
+    
+    if ol_success:
+        console.print(f"  ✓ GDSII generated: [green]{ol_result}[/green]")
+    else:
+        console.print(f"[bold red]✗ OpenLane failed[/bold red]")
+        console.print(f"  Error: {ol_result[:500]}...")
+        raise typer.Exit(1)
+    
+    # ===== FINAL: Summary =====
+    console.print("\n" + "="*50)
+    console.print(Panel(
+        f"[bold green]✓ CHIP GENERATION COMPLETE![/bold green]\n\n"
+        f"Design: [cyan]{name}[/cyan]\n"
+        f"GDSII: [yellow]{ol_result}[/yellow]\n\n"
+        f"Run verification: [dim]python main.py verify {name}[/dim]",
+        title="🎉 Success"
+    ))
+
+
+@app.command()
+def verify(name: str = typer.Argument(..., help="Design name to verify")):
+    """Run verification on an existing design."""
+    console.print(f"[yellow]Running verification for {name}...[/yellow]")
+    output = run_verification(name)
+    console.print(output)
+
+
+if __name__ == "__main__":
+    app()

src/agentic/config.py

@@ -0,0 +1,16 @@
+import os
+
+# Paths
+WORKSPACE_ROOT = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
+OPENLANE_ROOT = os.environ.get("OPENLANE_ROOT", os.path.expanduser("~/OpenLane"))
+DESIGNS_DIR = os.path.join(OPENLANE_ROOT, "designs")
+SCRIPTS_DIR = os.path.join(WORKSPACE_ROOT, "scripts")
+
+# LLM Configuration
+LLM_MODEL = os.environ.get("LLM_MODEL", "ollama/deepseek-r1")
+LLM_BASE_URL = os.environ.get("LLM_BASE_URL", "http://localhost:11434")
+LLM_API_KEY = os.environ.get("OPENAI_API_KEY", "NA")
+
+# Tool Settings
+PDK_ROOT = os.environ.get('PDK_ROOT', os.path.expanduser('~/.ciel'))
+OPENLANE_IMAGE = "ghcr.io/the-openroad-project/openlane:ff5509f65b17bfa4068d5336495ab1718987ff69-amd64"

src/agentic/tools/vlsi_tools.py

@@ -0,0 +1,133 @@
+# tools/vlsi_tools.py
+import os
+import subprocess
+from ..config import OPENLANE_ROOT, SCRIPTS_DIR, PDK_ROOT, OPENLANE_IMAGE
+
+def write_verilog(design_name, code, is_testbench=False):
+    """Writes Verilog code to the OpenLane design directory."""
+    suffix = "_tb" if is_testbench else ""
+    path = f"{OPENLANE_ROOT}/designs/{design_name}/src/{design_name}{suffix}.v"
+    os.makedirs(os.path.dirname(path), exist_ok=True)
+    
+    # Clean LLM output (remove markdown fences, think tags, etc.)
+    clean_code = code
+    
+    # Remove <think> tags if present (DeepSeek-R1 reasoning)
+    if "<think>" in clean_code:
+        import re
+        clean_code = re.sub(r'<think>.*?</think>', '', clean_code, flags=re.DOTALL)
+    
+    # Extract code from markdown fences
+    if "```verilog" in clean_code:
+        clean_code = clean_code.split("```verilog")[1].split("```")[0].strip()
+    elif "```v" in clean_code:
+        clean_code = clean_code.split("```v")[1].split("```")[0].strip()
+    elif "```" in clean_code:
+        # Find the code block
+        parts = clean_code.split("```")
+        for i, part in enumerate(parts):
+            if i % 2 == 1 and "module" in part:  # Odd indices are inside fences
+                clean_code = part.strip()
+                # Remove language identifier if present
+                lines = clean_code.split('\n')
+                if lines[0].strip() in ['verilog', 'v', 'systemverilog']:
+                    clean_code = '\n'.join(lines[1:])
+                break
+    
+    # Ensure we have a module
+    if "module" not in clean_code:
+        # Try to find module in original
+        if "module" in code:
+            start = code.find("module")
+            end = code.rfind("endmodule")
+            if end > start:
+                clean_code = code[start:end+9]  # +9 for "endmodule"
+    
+    # Sanitize model artifacts and fix common issues
+    import re
+    # Remove model tokens like <｜begin▁of▁sentence｜>
+    clean_code = re.sub(r'<[｜\|][^>]+[｜\|]>', '', clean_code)
+    # Fix SystemVerilog to Verilog-2005
+    clean_code = clean_code.replace('always_comb', 'always @(*)')
+    clean_code = clean_code.replace('always_ff', 'always')
+    clean_code = clean_code.replace('logic', 'reg')
+    # Fix time units: #5ns -> #5, #10ps -> #10
+    clean_code = re.sub(r'#(\d+)(ns|ps|us|ms|s)\b', r'#\1', clean_code)
+    # Fix wildcard port connections (SystemVerilog)
+    clean_code = re.sub(r'\(\s*\.\*\s*\)', '', clean_code)
+    # Remove any leftover special chars
+    clean_code = re.sub(r'[▁｜]', '', clean_code)
+    
+    with open(path, "w") as f:
+        f.write(clean_code)
+    return path
+
+def run_syntax_check(file_path):
+    """Runs iverilog syntax check."""
+    result = subprocess.run(
+        ["iverilog", "-t", "null", file_path], 
+        capture_output=True, text=True
+    )
+    return result.returncode == 0, result.stderr
+
+def run_simulation(design_name):
+    """Compiles and runs the testbench simulation."""
+    src_dir = f"{OPENLANE_ROOT}/designs/{design_name}/src"
+    rtl_file = f"{src_dir}/{design_name}.v"
+    tb_file = f"{src_dir}/{design_name}_tb.v"
+    sim_out = f"{src_dir}/sim"
+    
+    # Compile
+    compile_result = subprocess.run(
+        ["iverilog", "-o", sim_out, rtl_file, tb_file],
+        capture_output=True, text=True
+    )
+    if compile_result.returncode != 0:
+        return False, f"Compilation failed:\n{compile_result.stderr}"
+    
+    # Run
+    run_result = subprocess.run(
+        ["vvp", sim_out],
+        capture_output=True, text=True,
+        timeout=30
+    )
+    return True, run_result.stdout
+
+def run_openlane(design_name):
+    """Triggers the OpenLane flow via Docker."""
+    os.chdir(OPENLANE_ROOT)
+    
+    # Direct Docker command (non-interactive)
+    cmd = [
+        "docker", "run", "--rm",
+        "-v", f"{OPENLANE_ROOT}:/openlane",
+        "-v", f"{PDK_ROOT}:{PDK_ROOT}",
+        "-e", f"PDK_ROOT={PDK_ROOT}",
+        "-e", "PDK=sky130A",
+        OPENLANE_IMAGE,
+        "./flow.tcl", "-design", design_name, "-tag", "agentrun", "-overwrite"
+    ]
+    
+    process = subprocess.run(
+        cmd,
+        capture_output=True,
+        text=True,
+        timeout=900  # 15 min timeout
+    )
+    
+    # Check if GDS was created
+    gds_path = f"{OPENLANE_ROOT}/designs/{design_name}/runs/agentrun/results/final/gds/{design_name}.gds"
+    success = os.path.exists(gds_path)
+    
+    return success, gds_path if success else process.stderr
+
+def run_verification(design_name):
+    """Runs the verify_design.sh script."""
+    script_path = os.path.join(SCRIPTS_DIR, "verify_design.sh")
+    
+    result = subprocess.run(
+        ["bash", script_path, design_name],
+        capture_output=True,
+        text=True
+    )
+    return result.stdout