feat: AgentIC v2.0 - Added strict Verilog syntax rules, auto-fixers, and Groq support. Added INSTALL.md for portability.

INSTALL.md

@@ -0,0 +1,82 @@
+# Installation & Portability Guide
+
+Use this guide to set up **AgentIC** on a new machine.
+
+## 1. System Requirements
+*   **Operating System**: Linux (Ubuntu 20.04/22.04 LTS) or Windows with **WSL2** (Ubuntu).
+    *   *Note: Pure Windows is not supported due to Electronic Design Automation (EDA) tool dependencies.*
+*   **Memory**: 8GB RAM minimum (16GB recommended for Physical Design).
+*   **Disk Space**: ~10GB (mostly for Docker images and PDKs).
+
+## 2. Core Dependencies
+Install the required system tools before setting up the Python environment.
+
+### Ubuntu / Debian / WSL2:
+```bash
+sudo apt update
+sudo apt install -y git make python3 python3-venv python3-pip
+sudo apt install -y iverilog build-essential
+```
+
+### Docker (Critical for OpenLane)
+AgentIC uses OpenLane (running in Docker) to turn Verilog into GDSII layouts.
+1.  **Install Docker Desktop** (Windows/Mac) or **Docker Engine** (Linux).
+2.  **Verify installation**:
+    ```bash
+    docker run hello-world
+    ```
+3.  **Linux/WSL2 users**: Ensure your user is in the docker group so you don't need `sudo`:
+    ```bash
+    sudo usermod -aG docker $USER
+    # Log out and log back in for this to take effect
+    ```
+
+## 3. Python Environment Setup
+
+1.  **Clone the Repository**:
+    ```bash
+    git clone https://github.com/Vickyrrrrrr/AgentIC.git
+    cd AgentIC
+    ```
+
+2.  **Create and Activate Virtual Environment**:
+    ```bash
+    python3 -m venv agentic_env
+    source agentic_env/bin/activate
+    ```
+
+3.  **Install Python Dependencies**:
+    ```bash
+    pip install -r requirements.txt
+    ```
+
+4.  **Install GDSTK (Layout Viewer)**:
+    If `pip install gdstk` fails, you may need cmake:
+    ```bash
+    sudo apt install cmake
+    pip install gdstk
+    ```
+
+## 4. Configuration (.env)
+
+You need to provide your LLM API keys.
+1.  Create a file named `.env` in the root `AgentIC` directory.
+2.  Add your keys (example for Groq):
+    ```ini
+    # .env file
+    OPENAI_API_BASE=https://api.groq.com/openai/v1
+    OPENAI_API_KEY=gsk_your_groq_api_key_here
+    OPENAI_MODEL_NAME=llama-3.3-70b-versatile
+    ```
+
+## 5. Verification
+To ensure everything is working:
+
+1.  **Test the Agent Logic**:
+    ```bash
+    python3 main.py build --name test_counter --desc "A simple 4-bit up counter"
+    ```
+2.  **Test the Web UI**:
+    ```bash
+    streamlit run app.py
+    ```

Makefile

@@ -0,0 +1,68 @@
+# AgentIC Makefile - Structured Verification & Hardening Workflow
+# Usage: make <target> [DESIGN=name]
+
+DESIGN ?= simple_counter
+OPENLANE_ROOT ?= $(HOME)/OpenLane
+DESIGN_SRC = designs/$(DESIGN)/src
+RTL = $(DESIGN_SRC)/$(DESIGN).v
+TB = $(DESIGN_SRC)/$(DESIGN)_tb.v
+PDK_ROOT ?= $(HOME)/.ciel
+OPENLANE_IMAGE ?= ghcr.io/the-openroad-project/openlane:ff5509f65b17bfa4068d5336495ab1718987ff69-amd64
+
+.PHONY: all lint sim verify harden clean help
+
+# Complete flow
+all: lint sim harden verify
+	@echo "=========================================="
+	@echo "  COMPLETE WORKFLOW FINISHED FOR $(DESIGN)"
+	@echo "=========================================="
+
+# Step 1: Lint (syntax check)
+lint:
+	@echo "━━━ [1/4] LINTING $(DESIGN) ━━━"
+	iverilog -t null $(RTL)
+	@echo "✓ Syntax OK"
+
+# Step 2: Simulate (functional verification)
+sim: lint
+	@echo "━━━ [2/4] SIMULATING $(DESIGN) ━━━"
+	iverilog -o $(DESIGN_SRC)/sim $(RTL) $(TB)
+	cd $(DESIGN_SRC) && vvp sim | tee sim.log
+	@grep -q "TEST PASSED" $(DESIGN_SRC)/sim.log && echo "✓ Simulation PASSED" || (echo "✗ Simulation FAILED" && exit 1)
+
+# Step 3: Harden (RTL → GDSII via OpenLane Docker)
+harden:
+	@echo "━━━ [3/4] HARDENING $(DESIGN) → GDSII ━━━"
+	@echo "Copying design to OpenLane..."
+	cp -r designs/$(DESIGN) $(OPENLANE_ROOT)/designs/
+	@echo "Running OpenLane flow (may take 5-15 min)..."
+	docker run --rm \
+		-v $(OPENLANE_ROOT):/openlane \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e PDK=sky130A \
+		-e PWD=/openlane \
+		$(OPENLANE_IMAGE) \
+		./flow.tcl -design $(DESIGN) -tag agent_run_$(shell date +%Y%m%d_%H%M%S) -ignore_mismatches
+	@echo "✓ Hardening complete. Check $(OPENLANE_ROOT)/designs/$(DESIGN)/runs/"
+
+# Step 4: Verify (DRC/LVS)
+verify:
+	@echo "━━━ [4/4] VERIFYING $(DESIGN) (DRC/LVS) ━━━"
+	bash scripts/verify_design.sh $(DESIGN)
+
+# Utilities
+clean:
+	rm -f $(DESIGN_SRC)/sim $(DESIGN_SRC)/sim.log $(DESIGN_SRC)/*.vcd
+	@echo "Cleaned simulation artifacts."
+
+help:
+	@echo "AgentIC Makefile Targets:"
+	@echo "  make lint      - Check Verilog syntax"
+	@echo "  make sim       - Run RTL simulation"
+	@echo "  make harden    - Run OpenLane (RTL→GDSII)"
+	@echo "  make verify    - Run DRC/LVS checks"
+	@echo "  make all       - Run complete flow"
+	@echo "  make clean     - Remove temp files"
+	@echo ""
+	@echo "Override design: make DESIGN=my_counter sim"

README.md

@@ -1,67 +1,97 @@
-# AgentIC Workflow Guide
+# AgentIC: Natural Language to Chip Layout (GDSII)
 
-This document outlines the automated chip design workflow using **AgentIC** and **OpenLane**.
+**AgentIC** is an automated AI Agent framework that transforms natural language descriptions into industry-standard physical chip layouts. It essentially acts as a "Text-to-Silicon" compiler, leveraging LLMs (DeepSeek, Llama 3, etc.) to write RTL, verify it, and drive the OpenLane physical design toolchain.
 
-## Logic Flow
+## 🚀 Capabilities
 
-The system transforms natural language descriptions into physical GDSII manufacturing files through a multi-step agentic pipeline.
+*   **Natural Language → RTL**: Generates synthesizable **SystemVerilog** code based on your prompt.
+*   **Industry Standard Enforced**:
+    *   Automatic usage of `logic`, `always_ff`, and `always_comb`.
+    *   **Flattened I/O Ports**: Ensures compatibility with hardening tools.
+    *   **Scalable Architecture**: Uses `parameters` for bus widths.
+*   **Self-Correcting Agents**:
+    *   **Design Agent**: Writes the code.
+    *   **Verification Agent**: Writes a self-checking Testbench (`_tb.v`).
+    *   **Auto-Fix Loop**: If compilation or simulation fails, the agents read the error logs and patch the code automatically.
+*   **Physical Design (Hardening)**: Integrates directly with [OpenLane](https://github.com/The-OpenROAD-Project/OpenLane) to generate GDSII layouts.
 
-```mermaid
-graph TD
-    User[User Command] -->|main.py build| A[AgentIC]
-    A -->|Step 1: Generated RTL| B(VLSI Design Agent)
-    B -->|vicky_adder.v| C{Syntax Check}
-    C -->|Pass| D(Verification Agent)
-    C -->|Fail| Z[Error / Retry]
-    D -->|vicky_adder_tb.v| E{Simulation}
-    E -->|Pass| F[OpenLane Integration]
-    E -->|Fail| Z
-    
-    subgraph OpenLane Infrastructure
-    F -->|Docker Mount| G[OpenLane Flow]
-    G -->|flow.tcl| H[Synthesis yosys]
-    H --> I[Floorplan]
-    I --> J[Placement]
-    J --> K[Routing]
-    K --> L[GDSII Layout]
-    end
-    
-    L -->|Output| M[Final GDSII & Reports]
-```
+---
 
-## Directory Structure & Important Files
+## 🛠️ Workflow
 
-The workspace is consolidated into two main components:
+The workflow consists of three main stages. You can run them all at once or individually.
 
-### 1. AgentIC ( The "Brain" )
-Controls the process.
-- **`main.py`**: The entry point.
-- **`src/agentic/`**: The core Python package.
-    - **`agents/`**: AI engineer definitions.
-    - **`tools/`**: Interfaces to VLSI tools.
-    - **`config.py`**: Configuration settings (paths, LLMs).
-- **`scripts/verify_design.sh`**: A helper script for verification.
-
-### 2. OpenLane ( The "Muscle" )
-The execution engine.
-- **`designs/simple_counter`**: **CRITICAL**. Used as a configuration template for all new AI designs.
-- **`designs/<your_design>`**: Where your new chips will be created.
-- **`flow.tcl`**: The main script run by the Docker container.
+### 1. Build (Design & Verify)
+This is the main entry point. It invites the AI to design the chip and verify it.
+```bash
+python3 AgentIC/main.py build --name <design_name> --desc "<your description>"
+```
+**Example:**
+```bash
+python3 AgentIC/main.py build --name my_processor --desc "A 4x4 Systolic Array NPU with AXI Stream interface"
+```
+*   **Output**: Generates `src/<name>.v` and `src/<name>_tb.v`.
+*   **Action**: Runs syntax checks and simulations until `TEST PASSED` is confirmed.
 
-## How to Run
+### 2. Simulate (Manual Verification)
+If you have manually modified the Verilog files (or want to re-run verification without triggering the AI to overwrite your files), use this command.
+```bash
+python3 AgentIC/main.py simulate --name <design_name>
+```
 
-### 1. Build a new chip
+### 3. Harden (RTL → GDSII)
+Once your Simulation passes, turn the Verilog into a physical layout using OpenLane. This step runs synthesis, placement, routing, and signoff checks.
 ```bash
-cd ~/AgentIC
-python main.py build --name vicky_adder --desc "A 4-bit adder with carry out"
+python3 AgentIC/main.py harden --name <design_name>
+```
+*   **Output**: A `.gds` file in `OpenLane/designs/<name>/runs/.../results/final/gds/`.
+
+---
+
+## 📂 Project Structure
+
+```text
+/home/vickynishad/
+├── AgentIC/              # The AI Core
+│   ├── main.py           # CLI Entry point
+│   ├── .env              # API Keys & Config
+│   └── src/agentic/      # Source code for Agents & Tools
+│
+├── OpenLane/             # Physical Design Engine
+│   └── designs/
+│       ├── simple_counter/ # Template configuration (DO NOT DELETE)
+│       └── <your_design>/  # Generated chips go here
+│           ├── config.tcl  # Auto-generated OpenLane config
+│           └── src/
+│               ├── <name>.v     # SystemVerilog RTL
+│               └── <name>_tb.v  # Testbench
 ```
 
-### 2. Verify an existing chip
+## 🔌 Setup & Prerequisites
+
+1.  **Python 3.10+** & **Docker** (for OpenLane).
+2.  **Icarus Verilog (`iverilog`)**.
+3.  **LLM Configuration**:
+    You can use a local model (Ollama) or a Cloud API (Groq/DeepSeek) for faster inference.
+    
+    Create a `.env` file in `AgentIC/`:
+    ```dotenv
+    # Option 1: Cloud (Recommended for Speed)
+    GROQ_API_KEY=gsk_...
+    LLM_MODEL=openai/llama-3.3-70b-versatile
+    LLM_BASE_URL=https://api.groq.com/openai/v1
+
+    # Option 2: Local (DeepSeek R1 via Ollama)
+    # LLM_MODEL=ollama/deepseek-r1
+    # LLM_BASE_URL=http://localhost:11434
+    ```
+
+## 🧠 AI Reasoning
+By default, if the model supports "Chain of Thought" (like DeepSeek R1), the tool can show the hidden reasoning process.
 ```bash
-cd ~/AgentIC
-python main.py verify vicky_adder
+python3 AgentIC/main.py build ... --show-thinking
 ```
 
-## Maintenance
-- **Do not delete** `OpenLane/designs/simple_counter` - it is needed for config generation.
-- **Do not delete** the `OpenLane` root files - they are mounted into the Docker container.
+---
+**Author**: Vickyrrrrrr
+**Powered by**: CrewAI & OpenLane

app.py

@@ -412,7 +412,7 @@ elif selected_page == "Design Studio":
                     cmd = ["python3", "AgentIC/main.py", "build", "--name", name.strip().replace(" ", "_"), "--desc", desc]
                     
                     with st.status("🤖 AgentIC is planning silicon...", expanded=True) as status:
-                        st.write("1. Initializing DeepSeek-R1 Agent...")
+                        st.write("1. Initializing AI Agent...")
                         st.write("2. Generating RTL Logic...")
                         
                         try:
@@ -490,7 +490,7 @@ elif selected_page == "Design Studio":
     st.markdown(f"""
     <div class="terminal-window">
     [SYSTEM] Initialized AgentIC Kernel v2.0.<br>
-    [INFO] DeepSeek-R1 Model Loaded (Quantized).<br>
+    [INFO] AI Model Loaded.<br>
     [INFO] Connected to OpenLane Docker Container.<br>
     <span style="color:#00D1FF">vickynishad@agentic:~$</span> Waiting for command...
     </div>
@@ -845,6 +845,6 @@ elif selected_page == "Fabrication":
 st.markdown("---")
 st.markdown("""
 <div style="text-align: center; color: #555; font-size: 12px;">
-    AGENTIC FRAMEWORK © 2026 | POWERED BY DEEPSEEK & OPENLANE
+    AGENTIC FRAMEWORK © 2026 | POWERED BY LLM & OPENLANE
 </div>
 """, unsafe_allow_html=True)

debug_llm.py

@@ -0,0 +1,29 @@
+import os
+import sys
+
+# Add src to path to import config
+sys.path.append(os.path.join(os.path.dirname(__file__), 'src'))
+from agentic.config import LLM_MODEL, LLM_BASE_URL, LLM_API_KEY
+from crewai import LLM
+
+print(f"--- Debugging LLM Configuration ---")
+print(f"Model:    {LLM_MODEL}")
+print(f"Base URL: {LLM_BASE_URL}")
+print(f"API Key:  {'*' * 5}{LLM_API_KEY[-4:] if LLM_API_KEY and len(LLM_API_KEY) > 4 else 'NA'}")
+
+print(f"\n--- Sending Test Prompt to '{LLM_MODEL}' ---")
+
+try:
+    llm = LLM(
+        model=LLM_MODEL,
+        base_url=LLM_BASE_URL,
+        api_key=LLM_API_KEY
+    )
+    # Simple direct generation check
+    resp = llm.call(
+        messages=[{"role": "user", "content": "Hello! Are you ready to design chips?"}]
+    )
+    print(f"✅ Response received:\n{resp}")
+
+except Exception as e:
+    print(f"❌ Error contacting model: {e}")

designs/simple_counter/config.tcl

@@ -0,0 +1,27 @@
+set ::env(DESIGN_NAME) "simple_counter"
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/simple_counter.v"
+
+# Die size 200um x 200um
+set ::env(DIE_AREA) "0 0 200 200"
+set ::env(FP_SIZING) absolute
+
+# Core utilization
+set ::env(FP_CORE_UTIL) 20
+set ::env(PL_TARGET_DENSITY) 0.3
+
+# Power Grid Settings
+set ::env(FP_PDN_VPITCH) 50
+set ::env(FP_PDN_HPITCH) 50
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) 5
+
+# Power Pins / Voltage Sources
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
+# Technology Setup
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "10.0"

designs/simple_counter/src/sim

@@ -0,0 +1,97 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x5ed6c51adfd0 .scope module, "simple_counter_tb" "simple_counter_tb" 2 3;
+ .timescale -9 -12;
+v0x5ed6c51c28a0_0 .var "clk", 0 0;
+v0x5ed6c51c2960_0 .net "count", 7 0, v0x5ed6c51c2580_0;  1 drivers
+v0x5ed6c51c2a30_0 .var "enable", 0 0;
+v0x5ed6c51c2b30_0 .var "rst_n", 0 0;
+S_0x5ed6c51ae160 .scope module, "uut" "simple_counter" 2 14, 3 1 0, S_0x5ed6c51adfd0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst_n";
+    .port_info 2 /INPUT 1 "enable";
+    .port_info 3 /OUTPUT 8 "count";
+v0x5ed6c5175ba0_0 .net "clk", 0 0, v0x5ed6c51c28a0_0;  1 drivers
+v0x5ed6c51c2580_0 .var "count", 7 0;
+v0x5ed6c51c2660_0 .net "enable", 0 0, v0x5ed6c51c2a30_0;  1 drivers
+v0x5ed6c51c2730_0 .net "rst_n", 0 0, v0x5ed6c51c2b30_0;  1 drivers
+E_0x5ed6c51acc50/0 .event negedge, v0x5ed6c51c2730_0;
+E_0x5ed6c51acc50/1 .event posedge, v0x5ed6c5175ba0_0;
+E_0x5ed6c51acc50 .event/or E_0x5ed6c51acc50/0, E_0x5ed6c51acc50/1;
+    .scope S_0x5ed6c51ae160;
+T_0 ;
+    %wait E_0x5ed6c51acc50;
+    %load/vec4 v0x5ed6c51c2730_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0x5ed6c51c2580_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v0x5ed6c51c2660_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.2, 8;
+    %load/vec4 v0x5ed6c51c2580_0;
+    %addi 1, 0, 8;
+    %assign/vec4 v0x5ed6c51c2580_0, 0;
+T_0.2 ;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0x5ed6c51adfd0;
+T_1 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x5ed6c51c28a0_0, 0, 1;
+T_1.0 ;
+    %delay 5000, 0;
+    %load/vec4 v0x5ed6c51c28a0_0;
+    %inv;
+    %store/vec4 v0x5ed6c51c28a0_0, 0, 1;
+    %jmp T_1.0;
+    %end;
+    .thread T_1;
+    .scope S_0x5ed6c51adfd0;
+T_2 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x5ed6c51c2b30_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x5ed6c51c2a30_0, 0, 1;
+    %vpi_call 2 34 "$monitor", "Time=%0t | rst_n=%b | enable=%b | count=%d", $time, v0x5ed6c51c2b30_0, v0x5ed6c51c2a30_0, v0x5ed6c51c2960_0 {0 0 0};
+    %delay 20000, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x5ed6c51c2b30_0, 0, 1;
+    %delay 20000, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x5ed6c51c2a30_0, 0, 1;
+    %delay 200000, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x5ed6c51c2a30_0, 0, 1;
+    %delay 50000, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x5ed6c51c2b30_0, 0, 1;
+    %delay 20000, 0;
+    %vpi_call 2 53 "$display", "TEST PASSED" {0 0 0};
+    %vpi_call 2 54 "$finish" {0 0 0};
+    %end;
+    .thread T_2;
+    .scope S_0x5ed6c51adfd0;
+T_3 ;
+    %vpi_call 2 59 "$dumpfile", "simple_counter.vcd" {0 0 0};
+    %vpi_call 2 60 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x5ed6c51adfd0 {0 0 0};
+    %end;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "designs/simple_counter/src/simple_counter_tb.v";
+    "designs/simple_counter/src/simple_counter.v";

designs/simple_counter/src/simple_counter.v

@@ -0,0 +1,16 @@
+module simple_counter (
+    input wire clk,
+    input wire rst_n,
+    input wire enable,
+    output reg [7:0] count
+);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            count <= 8'b0;
+        end else if (enable) begin
+            count <= count + 1'b1;
+        end
+    end
+
+endmodule

designs/simple_counter/src/simple_counter_tb.v

@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+
+module simple_counter_tb;
+
+    // Inputs
+    reg clk;
+    reg rst_n;
+    reg enable;
+
+    // Outputs
+    wire [7:0] count;
+
+    // Instantiate the Unit Under Test (UUT)
+    simple_counter uut (
+        .clk(clk),
+        .rst_n(rst_n),
+        .enable(enable),
+        .count(count)
+    );
+
+    // Clock generation
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk; // 100MHz clock
+    end
+
+    // Test Sequence
+    initial begin
+        // Initialize Inputs
+        rst_n = 0;
+        enable = 0;
+
+        // Monitoring
+        $monitor("Time=%0t | rst_n=%b | enable=%b | count=%d", $time, rst_n, enable, count);
+
+        // Reset
+        #20;
+        rst_n = 1;
+        #20;
+
+        // Enable Counter
+        enable = 1;
+        #200;
+
+        // Disable Counter
+        enable = 0;
+        #50;
+
+        // Reset again
+        rst_n = 0;
+        #20;
+        
+        $display("TEST PASSED");
+        $finish;
+    end
+    
+    // Waveform dump for GTKWave
+    initial begin
+        $dumpfile("simple_counter.vcd");
+        $dumpvars(0, simple_counter_tb);
+    end
+
+endmodule

main.py

@@ -1,6 +1,10 @@
 #!/usr/bin/env python3
 import sys
 import os
+from dotenv import load_dotenv
+
+# Load environment variables from .env file
+load_dotenv()
 
 # Add src to path so we can import the package
 sys.path.insert(0, os.path.join(os.path.dirname(__file__), "src"))

scripts/verify_design.sh

@@ -8,7 +8,7 @@ if [ -z "$1" ]; then
 fi
 
 DESIGN=$1
-OPENLANE_ROOT=~/OpenLane
+OPENLANE_ROOT="${OPENLANE_ROOT:-$HOME/OpenLane}"
 DESIGN_DIR=$OPENLANE_ROOT/designs/$DESIGN
 
 echo "========================================"

src/agentic/agents/designer.py

@@ -1,14 +1,12 @@
 # agents/designer.py
 from crewai import Agent
-from ..config import LLM_MODEL
 
-def get_designer_agent():
+def get_designer_agent(llm, goal, verbose=False):
     return Agent(
         role='VLSI Design Engineer',
-        goal='Create optimized Verilog for {design_input}',
-        backstory='Specialist in ECE from Lucknow University. Expert in Sky130 PDK.',
-        # IMPORTANT: Use the "ollama/" prefix so CrewAI doesn't look for OpenAI
-        llm=LLM_MODEL, 
-        verbose=True,
+        goal=goal,
+        backstory='Specialist in ECE from Lucknow University. Expert in digital design with Sky130 PDK experience.',
+        llm=llm, 
+        verbose=verbose,
         allow_delegation=False
     )

src/agentic/agents/testbench_designer.py

@@ -1,15 +1,15 @@
 # agents/testbench_designer.py
 from crewai import Agent
 
-def get_testbench_agent(llm):
+def get_testbench_agent(llm, goal, verbose=False):
     """Returns an agent specialized in writing Verilog testbenches."""
     return Agent(
         role='Verification Engineer',
-        goal='Create comprehensive Verilog testbenches for {design_name}',
+        goal=goal,
         backstory='''Expert in digital verification with deep knowledge of 
         Verilog simulation. Focuses on edge cases, reset behavior, and 
         timing checks. Always includes $monitor, $dumpfile, and $finish.''',
         llm=llm,
-        verbose=True,
+        verbose=verbose,
         allow_delegation=False
     )

src/agentic/cli.py

@@ -2,13 +2,15 @@
 """
 AgentIC - Natural Language to GDSII Pipeline
 =============================================
-Uses CrewAI + Ollama (DeepSeek) to generate chips from natural language.
+Uses CrewAI + LLM (DeepSeek/Llama/Groq) to generate chips from natural language.
+
 
 Usage:
     python main.py build --name counter --desc "8-bit counter with enable and reset"
 """
 
 import os
+import re
 import sys
 import typer
 from rich.console import Console
@@ -18,6 +20,8 @@ from crewai import Agent, Task, Crew, LLM
 
 # Local imports
 from .config import OPENLANE_ROOT, LLM_MODEL, LLM_BASE_URL, LLM_API_KEY
+from .agents.designer import get_designer_agent
+from .agents.testbench_designer import get_testbench_agent
 from .tools.vlsi_tools import (
     write_verilog, 
     run_syntax_check,
@@ -39,11 +43,83 @@ def get_llm():
         api_key=LLM_API_KEY
     )
 
+@app.command()
+def simulate(
+    name: str = typer.Option(..., "--name", "-n", help="Design name (e.g., counter)"),
+):
+    """Run simulation on an existing design without regenerating RTL."""
+    console.print(Panel(
+        f"[bold cyan]AgentIC: Manual Simulation Mode[/bold cyan]\n"
+        f"Design: [yellow]{name}[/yellow]",
+        title="🚀 Starting Simulation"
+    ))
+    
+    sim_success, sim_output = run_simulation(name)
+    
+    if not sim_success:
+        console.print(f"[bold red]✗ SIMULATION FAILED:[/bold red]\n{sim_output}")
+        raise typer.Exit(1)
+
+    sim_lines = sim_output.strip().split('\n')
+    for line in sim_lines[-20:]:  # Print last 20 lines of log
+        console.print(f"  [dim]{line}[/dim]")
+    console.print("  ✓ Simulation [green]passed[/green]")
+
+@app.command()
+def harden(
+    name: str = typer.Option(..., "--name", "-n", help="Design name (e.g., counter)"),
+):
+    """Run OpenLane hardening (RTL -> GDSII) on an existing design."""
+    console.print(Panel(
+        f"[bold cyan]AgentIC: Manual Hardening Mode[/bold cyan]\n"
+        f"Design: [yellow]{name}[/yellow]",
+        title="🚀 Starting OpenLane"
+    ))
+    
+    # Check config first
+    template_config = f"{OPENLANE_ROOT}/designs/simple_counter/config.tcl"
+    new_config = f"{OPENLANE_ROOT}/designs/{name}/config.tcl"
+
+    if not os.path.exists(new_config):
+        if os.path.exists(template_config):
+            with open(template_config, 'r') as f:
+                content = f.read().replace("simple_counter", name)
+
+            content = content.replace(
+                "set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]",
+                f"set ::env(VERILOG_FILES) \"$::env(DESIGN_DIR)/src/{name}.v\""
+            )
+            content = content.replace(
+                "set ::env(VERILOG_FILES) \"$::env(DESIGN_DIR)/src/simple_counter.v\"",
+                f"set ::env(VERILOG_FILES) \"$::env(DESIGN_DIR)/src/{name}.v\""
+            )
+
+            os.makedirs(os.path.dirname(new_config), exist_ok=True)
+            with open(new_config, 'w') as f:
+                f.write(content)
+            console.print(f"  ✓ Config written: [green]{new_config}[/green]")
+        else:
+             console.print(f"[bold red]✗ Config not found and template missing.[/bold red]")
+             raise typer.Exit(1)
+    
+    console.print("  [dim]Running OpenLane (this may take 5-10 minutes)...[/dim]")
+    ol_success, ol_result = run_openlane(name)
+    
+    if ol_success:
+        console.print(f"  ✓ GDSII generated: [green]{ol_result}[/green]")
+    else:
+        console.print(f"[bold red]✗ OpenLane failed[/bold red]")
+        console.print(f"  Error: {ol_result[:500]}...")
+        raise typer.Exit(1)
+
 # --- THE BUILD COMMAND ---
 @app.command()
 def build(
     name: str = typer.Option(..., "--name", "-n", help="Design name (e.g., counter)"),
-    desc: str = typer.Option(..., "--desc", "-d", help="Natural language description")
+    desc: str = typer.Option(..., "--desc", "-d", help="Natural language description"),
+    max_retries: int = typer.Option(2, "--max-retries", "-r", min=0, help="Max auto-fix retries for RTL/TB/sim failures"),
+    skip_openlane: bool = typer.Option(False, "--skip-openlane", help="Stop after simulation (no RTL→GDSII hardening)"),
+    show_thinking: bool = typer.Option(True, "--show-thinking", help="Print DeepSeek <think> reasoning for each generation/fix step")
 ):
     """Build a chip from natural language description."""
     
@@ -55,156 +131,366 @@ def build(
     ))
 
     llm = get_llm()
+
+    def log_thinking(raw_text: str, step: str):
+        """Emit DeepSeek <think> content to the console when requested."""
+        if not show_thinking or "<think>" not in raw_text:
+            return
+        thoughts = re.findall(r"<think>(.*?)</think>", raw_text, flags=re.DOTALL)
+        cleaned = [t.strip() for t in thoughts if t.strip()]
+        if not cleaned:
+            return
+        console.print(Panel("\n\n".join(cleaned), title=f"🧠 DeepSeek thinking — {step}", expand=False))
+
+    def _fix_with_llm(agent_role: str, goal: str, prompt: str) -> str:
+        fix_agent = Agent(
+            role=agent_role,
+            goal=goal,
+            backstory='Expert in SystemVerilog and ASIC flows (Sky130/OpenLane).',
+            llm=llm,
+            verbose=show_thinking
+        )
+        
+        # Add explicit instruction to avoid dynamic variable names in loops
+        enhanced_prompt = prompt + "\n\nCRITICAL RULE: Do NOT use variable names like 'input_i' or 'wire_j' inside loops. SystemVerilog does not support dynamic variable names. Use arrays (e.g., input[i]) or generate blocks instead."
+        
+        fix_task = Task(
+            description=enhanced_prompt,
+            expected_output='Corrected SystemVerilog code in a ```verilog fence',
+            agent=fix_agent
+        )
+        with console.status("[cyan]AI is fixing the design...[/cyan]"):
+            result = str(Crew(agents=[fix_agent], tasks=[fix_task]).kickoff())
+            log_thinking(result, step=f"Fix: {agent_role}")
+            return result
     
-    # ===== STEP 1: Generate RTL =====
+    # ===== STEP 1/2: Generate RTL with syntax-fix loop =====
     console.print("\n[bold yellow]━━━ Step 1/5: Generating Verilog RTL ━━━[/bold yellow]")
-    
-    rtl_agent = Agent(
-        role='VLSI Design Engineer',
-        goal=f'Create synthesizable Verilog for: {desc}',
-        backstory='Expert in digital design with Sky130 PDK experience.',
+
+    rtl_agent = get_designer_agent(
         llm=llm,
-        verbose=False
+        goal=f'Create synthesizable SystemVerilog for: {desc}',
+        verbose=show_thinking
     )
-    
+
     rtl_task = Task(
-        description=f'''Design a Verilog module named "{name}" that implements: {desc}
-        
-        CRITICAL REQUIREMENTS:
-        - Module name must be exactly "{name}"
-        - Use VERILOG-2005 ONLY (NOT SystemVerilog)
-        - Use "always @(*)" NOT "always_comb"
-        - Use "reg" for outputs in combinational logic
-        - Include clock (clk) and active-low reset (rst_n) if sequential
-        - Return ONLY the Verilog code wrapped in ```verilog fences
-        - NO explanations, NO comments about the code
-        
-        Example format:
-        ```verilog
-        module {name}(...);
-        ...
-        endmodule
-        ```
-        ''',
-        expected_output='Complete Verilog-2005 module code in markdown fence',
+        description=f'''Design an INDUSTRY STANDARD SystemVerilog module named "{name}" that implements: {desc}
+
+CRITICAL VERILOG RULES (STRICTLY FOLLOW OR COMPILATION WILL FAIL):
+1. **Module & Ports**:
+   - Module name must be exactly "{name}"
+   - ALWAYS include `input logic clk`, `input logic rst_n` (active-low asynchronous reset).
+   - **FLATTENED PORTS**: Do not use multidimensional arrays for top-level ports. Use `input logic [WIDTH*COUNT-1:0] flat_bus`.
+   - Use `parameter` for all bit-widths.
+
+2. **Data Types & Declarations**:
+   - Use `logic` for ALL internal signals and ports (Standard SystemVerilog 2012).
+   - **DECLARE BEFORE USE**: You MUST declare signals (`logic [31:0] my_sig;`) at the top of the module interaction section, BEFORE they are used in any `always` block or `assign`.
+
+3. **Coding Logic Structure**:
+   - **SEPARATE LOGIC**:
+     - Use `always_ff @(posedge clk or negedge rst_n)` ONLY for registers/flip-flops.
+     - Use `assign` statements for renaming wires or simple math (e.g. `assign opcode = ir[6:0];`).
+     - Use `always_comb` ONLY for complex muxing/Next-State-Logic.
+   - **NO CONSTANT SELECTS IN ALWAYS**: Do NOT do `reg_file[ ir[19:15] ]` inside an `always` block. 
+     - CORRECT: 
+       ```verilog
+       wire [4:0] rs1_addr = ir[19:15]; // Create alias wire using assign
+       ...
+       always_comb val = reg_file[rs1_addr];
+       ```
+   - **LOOPS**: For register files, declare `integer i;` OUTSIDE the always block. Use `for(i=0; i<32; i=i+1)`.
+   - **CASTING**: Do NOT use `signed'(x)`. Use `$signed(x)` for signed arithmetic.
+
+4. **Output Format**:
+   - Return ONLY the code wrapped in ```verilog fences
+   - Add comments explaining the architecture.
+
+Example format:
+```verilog
+module {name} #(parameter WIDTH=32) (
+    input logic clk,
+    input logic rst_n
+);
+    // 1. Declarations
+    logic [WIDTH-1:0] data_reg;
+    integer i;
+    
+    // 2. Continuous Assignments
+    assign w_ready = (data_reg != 0);
+
+    // 3. Sequential Logic
+    always_ff @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            data_reg <= 0;
+            // Loop example
+            for (i=0; i<WIDTH; i=i+1) ...
+        end else begin
+            data_reg <= ...;
+        end
+    end
+endmodule
+```
+''',
+        expected_output='Complete SystemVerilog module code in markdown fence',
         agent=rtl_agent
     )
-    
-    with console.status("[cyan]AI is designing your chip...[/cyan]"):
+
+    with console.status("[cyan]AI is designing your chip (this may take 2-5 mins)...[/cyan]"):
         rtl_result = Crew(agents=[rtl_agent], tasks=[rtl_task]).kickoff()
-    
-    rtl_path = write_verilog(name, str(rtl_result))
+
+    rtl_raw = str(rtl_result)
+    log_thinking(rtl_raw, step="RTL generation")
+
+    rtl_path = write_verilog(name, rtl_raw)
     console.print(f"  ✓ RTL saved to: [green]{rtl_path}[/green]")
-    
-    # ===== STEP 2: Syntax Check RTL =====
+
     console.print("\n[bold yellow]━━━ Step 2/5: Syntax Verification ━━━[/bold yellow]")
-    
     success, errors = run_syntax_check(rtl_path)
+    tries = 0
+    while not success and tries < max_retries:
+        tries += 1
+        console.print(f"[bold red]✗ SYNTAX ERROR (attempt {tries}/{max_retries})[/bold red]\n{errors}")
+        fix_prompt = f'''Fix the following SystemVerilog code so it compiles with iverilog -g2012.
+
+CRITICAL FIXING RULES:
+1. **Unresolved Wires**: Declare ALL signals at the top of the file using `logic [width:0] name;`. If a signal is used in `assign` or `always`, it MUST be declared.
+2. **"Constant Selects" Error**: If you see "constant selects in always process", move the slicing logic OUTSIDE the always block into an `assign` statement.
+   - Bad: `always_comb x = reg_file[ addr[4:0] ];`
+   - Good: `wire [4:0] idx = addr[4:0]; always_comb x = reg_file[idx];`
+3. **Loop Syntax**: Use `integer i;` declared outside, and `for(i=0;...)`.
+4. **Logic separation**: Use `always_ff` for registers, `assign` for simple logic.
+
+CRITICAL REQUIREMENTS:
+- Keep module name exactly "{name}"
+- Use Standard SystemVerilog
+- Return ONLY corrected code inside ```verilog fences
+
+Compiler error:
+{errors}
+
+Current code:
+```verilog
+{open(rtl_path,'r').read()}
+```
+'''
+        fixed = _fix_with_llm(
+            agent_role='VLSI Design Engineer',
+            goal=f'Fix SystemVerilog syntax for {name}',
+            prompt=fix_prompt
+        )
+        rtl_path = write_verilog(name, fixed)
+        success, errors = run_syntax_check(rtl_path)
+
     if not success:
         console.print(f"[bold red]✗ SYNTAX ERROR:[/bold red]\n{errors}")
         raise typer.Exit(1)
     console.print("  ✓ Verilog syntax is [green]valid[/green]")
     
-    # ===== STEP 3: Generate Testbench =====
+    # ===== STEP 3: Generate Testbench (self-checking) =====
     console.print("\n[bold yellow]━━━ Step 3/5: Generating Testbench ━━━[/bold yellow]")
-    
-    # Read the generated RTL for context
+
     with open(rtl_path, 'r') as f:
         rtl_code = f.read()
-    
-    tb_agent = Agent(
-        role='Verification Engineer',
-        goal=f'Create a testbench for {name}',
-        backstory='Expert in Verilog verification and simulation.',
+
+    tb_agent = get_testbench_agent(
         llm=llm,
-        verbose=False
+        goal=f'Create a self-checking testbench for {name}',
+        verbose=show_thinking
     )
-    
+
     tb_task = Task(
-        description=f'''Create a Verilog-2005 testbench for this module:
-        
+        description=f'''Create a SystemVerilog self-checking testbench for this module:
+
 ```verilog
 {rtl_code}
 ```
 
-CRITICAL REQUIREMENTS:
-- Module name must be "{name}_tb"
-- Use VERILOG-2005 ONLY (NOT SystemVerilog)
-- Use explicit port connections: .clk(clk), .a(a), etc.
-- Use integer delays like #5 or #10, NOT #5ns or #10ns
-- Clock: forever #5 clk = ~clk (inside initial block)
-- Put $monitor INSIDE an initial block
-- Use $dumpfile("{name}.vcd") and $dumpvars(0, {name}_tb)
-- End with $finish
-- Return ONLY the testbench code wrapped in ```verilog fences
-
-Example structure:
-```verilog
-module {name}_tb;
-  reg clk, rst_n;
-  // declare inputs as reg, outputs as wire
-  
-  {name} uut(.clk(clk), .rst_n(rst_n), ...);
-  
-  initial begin
-    clk = 0;
-    forever #5 clk = ~clk;
-  end
-  
-  initial begin
-    $dumpfile("{name}.vcd");
-    $dumpvars(0, {name}_tb);
-    $monitor(...);
-    // test sequence
-    $finish;
-  end
-endmodule
-```
+CRITICAL VERIFICATION RULES (DO NOT VIOLATE):
+1. **Module Name**: Must be "{name}_tb"
+2. **Signal Directions**:
+   - **DUT INPUTS** must be declared as `logic` (or `reg`) in the Testbench and **DRIVEN** in `initial` blocks.
+   - **DUT OUTPUTS** must be declared as `logic` (or `wire`) in the Testbench and **OBSERVED** only.
+   - **NEVER** assign values to DUT OUTPUT signals in the Testbench (e.g. if `ready` is an output of DUT, do NOT write `ready = 1`).
+3. **Data Types**: Use `logic` for everything.
+4. **Instantiation**: Use explicit name based connection `.port(signal)`.
+5. **Clock/Reset**:
+   - Clock: `initial forever #5 clk = ~clk;`
+   - Reset: Drive `rst_n` low for 20 units, then high.
+6. **Reporting**:
+   - Use `$dumpfile("{name}.vcd")` and `$dumpvars(0, {name}_tb)`.
+   - On success: `$display("TEST PASSED");`
+   - On failure: `$display("TEST FAILED");`
+   - Always end with `$finish;`
+
+Return ONLY the testbench code wrapped in ```verilog fences
 ''',
-        expected_output='Complete Verilog-2005 testbench in markdown fence',
+        expected_output='Complete SystemVerilog testbench in markdown fence',
         agent=tb_agent
     )
-    
+
     with console.status("[cyan]AI is creating testbench...[/cyan]"):
         tb_result = Crew(agents=[tb_agent], tasks=[tb_task]).kickoff()
-    
-    tb_path = write_verilog(name, str(tb_result), is_testbench=True)
+
+    tb_raw = str(tb_result)
+    log_thinking(tb_raw, step="Testbench generation")
+
+    tb_path = write_verilog(name, tb_raw, is_testbench=True)
     console.print(f"  ✓ Testbench saved to: [green]{tb_path}[/green]")
     
-    # ===== STEP 4: Run Simulation =====
+    # ===== STEP 4: Run Simulation with fix loop =====
     console.print("\n[bold yellow]━━━ Step 4/5: Running Simulation ━━━[/bold yellow]")
-    
+
     sim_success, sim_output = run_simulation(name)
+    sim_tries = 0
+    while not sim_success and sim_tries < max_retries:
+        sim_tries += 1
+        console.print(f"[bold red]✗ SIMULATION FAILED (attempt {sim_tries}/{max_retries})[/bold red]")
+
+        sim_output_text = sim_output or ""
+
+        # 1) If compilation failed, fix TB first.
+        if "Compilation failed:" in sim_output_text or "syntax error" in sim_output_text:
+            fix_tb_prompt = f'''Fix this SystemVerilog testbench so it compiles and avoids directionality errors.
+
+CRITICAL FIXING RULES:
+1. **Unresolved Wires**: If you see "Unable to assign to unresolved wires", it means you are driving a DUT OUTPUT. Stop driving it!
+2. **Signal Directions**:
+   - Check the DUT definition.
+   - If a port is `output` in DUT, it is a `wire` in TB (Read-Only).
+   - If a port is `input` in DUT, it is a `reg/logic` in TB (Write-Only).
+3. **Format**: Return ONLY corrected testbench code inside ```verilog fences.
+
+Simulation output / errors:
+{sim_output_text}
+
+Current RTL (do not modify unless absolutely necessary):
+```verilog
+{open(rtl_path,'r').read()}
+```
+
+Current testbench:
+```verilog
+{open(tb_path,'r').read()}
+```
+'''
+            fixed_tb = _fix_with_llm(
+                agent_role='Verification Engineer',
+                goal=f'Fix testbench for {name}',
+                prompt=fix_tb_prompt
+            )
+            tb_path = write_verilog(name, fixed_tb, is_testbench=True)
+            sim_success, sim_output = run_simulation(name)
+            continue
+
+        # 2) If TB ran but failed logically, fix RTL to satisfy TB.
+        if "TEST FAILED" in sim_output_text or "TEST PASSED" not in sim_output_text:
+            fix_rtl_prompt = f'''The simulation did not pass. Fix the RTL (module "{name}") so that the testbench passes.
+
+CRITICAL REQUIREMENTS:
+- Keep module name exactly "{name}"
+- SystemVerilog only
+- Keep ports: clk, rst_n (active-low) present
+- Return ONLY corrected RTL code inside ```verilog fences
+
+Simulation output:
+{sim_output_text}
+
+Current testbench (do not change in this step):
+```verilog
+{open(tb_path,'r').read()}
+```
+
+Current RTL:
+```verilog
+{open(rtl_path,'r').read()}
+```
+'''
+            fixed_rtl = _fix_with_llm(
+                agent_role='VLSI Design Engineer',
+                goal=f'Fix RTL behavior for {name}',
+                prompt=fix_rtl_prompt
+            )
+            rtl_path = write_verilog(name, fixed_rtl)
+
+            success, errors = run_syntax_check(rtl_path)
+            if not success:
+                sim_output = f"RTL fix introduced syntax error:\n{errors}"
+                continue
+
+            sim_success, sim_output = run_simulation(name)
+            continue
+
+        # Default: improve TB robustness
+        fix_tb_prompt = f'''Improve this Verilog-2005 testbench so it robustly checks the design and prints TEST PASSED/TEST FAILED.
+
+CRITICAL REQUIREMENTS:
+- Testbench module name must be "{name}_tb"
+- Must print exactly "TEST PASSED" on success
+- Must print exactly "TEST FAILED" on failure
+- Return ONLY corrected testbench code inside ```verilog fences
+
+Current RTL:
+```verilog
+{open(rtl_path,'r').read()}
+```
+
+Current testbench:
+```verilog
+{open(tb_path,'r').read()}
+```
+'''
+        fixed_tb = _fix_with_llm(
+            agent_role='Verification Engineer',
+            goal=f'Improve testbench for {name}',
+            prompt=fix_tb_prompt
+        )
+        tb_path = write_verilog(name, fixed_tb, is_testbench=True)
+        sim_success, sim_output = run_simulation(name)
+
     if not sim_success:
         console.print(f"[bold red]✗ SIMULATION FAILED:[/bold red]\n{sim_output}")
         raise typer.Exit(1)
-    
-    # Show last few lines of simulation
+
     sim_lines = sim_output.strip().split('\n')
-    for line in sim_lines[-5:]:
+    for line in sim_lines[-8:]:
         console.print(f"  [dim]{line}[/dim]")
     console.print("  ✓ Simulation [green]passed[/green]")
     
+    if skip_openlane:
+        console.print("\n[bold green]✓ Stopped after simulation (--skip-openlane).[/bold green]")
+        return
+
     # ===== STEP 5: Run OpenLane =====
     console.print("\n[bold yellow]━━━ Step 5/5: Running OpenLane (RTL → GDSII) ━━━[/bold yellow]")
     console.print("  [dim]This may take 5-10 minutes...[/dim]")
     
-    # Create config.tcl from template
+    # Create/overwrite config.tcl from template (ensure RTL-only synthesis)
     template_config = f"{OPENLANE_ROOT}/designs/simple_counter/config.tcl"
     new_config = f"{OPENLANE_ROOT}/designs/{name}/config.tcl"
-    
-    if os.path.exists(template_config) and not os.path.exists(new_config):
+
+    if os.path.exists(template_config):
         with open(template_config, 'r') as f:
             content = f.read().replace("simple_counter", name)
-        # Fix: Ensure we only synthesize the design, not the testbench
-        if "[glob $::env(DESIGN_DIR)/src/*.v]" in content:
-            content = content.replace(
-                "[glob $::env(DESIGN_DIR)/src/*.v]", 
-                f'"$::env(DESIGN_DIR)/src/{name}.v"'
-            )
+
+        # Ensure we only synthesize the RTL, not the testbench.
+        # Handle common template patterns.
+        content = content.replace(
+            "set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]",
+            f"set ::env(VERILOG_FILES) \"$::env(DESIGN_DIR)/src/{name}.v\""
+        )
+        content = content.replace(
+            "set ::env(VERILOG_FILES) \"$::env(DESIGN_DIR)/src/simple_counter.v\"",
+            f"set ::env(VERILOG_FILES) \"$::env(DESIGN_DIR)/src/{name}.v\""
+        )
+
+        os.makedirs(os.path.dirname(new_config), exist_ok=True)
         with open(new_config, 'w') as f:
             f.write(content)
-        console.print(f"  ✓ Config created from template")
+        console.print(f"  ✓ Config written: [green]{new_config}[/green]")
+    else:
+        console.print("  [bold red]✗ Missing OpenLane template config (designs/simple_counter/config.tcl)[/bold red]")
+        raise typer.Exit(1)
     
     ol_success, ol_result = run_openlane(name)
     

src/agentic/config.py

@@ -1,15 +1,24 @@
 import os
+from dotenv import load_dotenv
 
 # Paths
 WORKSPACE_ROOT = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
+load_dotenv(os.path.join(WORKSPACE_ROOT, ".env"))
+
 OPENLANE_ROOT = os.environ.get("OPENLANE_ROOT", os.path.expanduser("~/OpenLane"))
 DESIGNS_DIR = os.path.join(OPENLANE_ROOT, "designs")
 SCRIPTS_DIR = os.path.join(WORKSPACE_ROOT, "scripts")
 
 # LLM Configuration
+# To use GROQ (Free Cloud):
+# 1. Get Key from https://console.groq.com
+# 2. export GROQ_API_KEY="gsk_..."
+# 3. export LLM_MODEL="openai/llama-3.3-70b-versatile" (or similar)
+# 4. export LLM_BASE_URL="https://api.groq.com/openai/v1"
+
 LLM_MODEL = os.environ.get("LLM_MODEL", "ollama/deepseek-r1")
 LLM_BASE_URL = os.environ.get("LLM_BASE_URL", "http://localhost:11434")
-LLM_API_KEY = os.environ.get("OPENAI_API_KEY", "NA")
+LLM_API_KEY = os.environ.get("GROQ_API_KEY", os.environ.get("OPENAI_API_KEY", "NA"))
 
 # Tool Settings
 PDK_ROOT = os.environ.get('PDK_ROOT', os.path.expanduser('~/.ciel'))

src/agentic/tools/vlsi_tools.py

@@ -47,16 +47,30 @@ def write_verilog(design_name, code, is_testbench=False):
     import re
     # Remove model tokens like <｜begin▁of▁sentence｜>
     clean_code = re.sub(r'<[｜\|][^>]+[｜\|]>', '', clean_code)
-    # Fix SystemVerilog to Verilog-2005
-    clean_code = clean_code.replace('always_comb', 'always @(*)')
-    clean_code = clean_code.replace('always_ff', 'always')
-    clean_code = clean_code.replace('logic', 'reg')
+    
+    # Allow SystemVerilog constructs (removed forced downgrade)
+    # clean_code = clean_code.replace('always_comb', 'always @(*)')
+    # clean_code = clean_code.replace('always_ff', 'always')
+    # clean_code = clean_code.replace('logic', 'reg')
+    
     # Fix time units: #5ns -> #5, #10ps -> #10
     clean_code = re.sub(r'#(\d+)(ns|ps|us|ms|s)\b', r'#\1', clean_code)
     # Fix wildcard port connections (SystemVerilog)
     clean_code = re.sub(r'\(\s*\.\*\s*\)', '', clean_code)
     # Remove any leftover special chars
     clean_code = re.sub(r'[▁｜]', '', clean_code)
+
+    # --- AUTO-FIXES FOR COMPILER COMPATIBILITY ---
+    # 1. Fix signed casting: signed'(val) -> $signed(val)
+    clean_code = re.sub(r"signed'\s*\((.*?)\)", r"$signed(\1)", clean_code)
+    
+    # 2. Fix Loop Variables: "for (int i=0..." -> "for (i=0..." 
+    # (assuming 'integer i' is declared elsewhere or we strip the type to be safe in blocks)
+    # clean_code = re.sub(r'for\s*\(\s*int\s+(\w+)\s*=', r'for (\1 =', clean_code)
+
+    # 3. Remove unsupported SystemVerilog qualifiers for iverilog
+    clean_code = re.sub(r'\bunique\s+case\b', 'case', clean_code)
+    clean_code = re.sub(r'\bpriority\s+case\b', 'case', clean_code)
     
     with open(path, "w") as f:
         f.write(clean_code)
@@ -65,7 +79,7 @@ def write_verilog(design_name, code, is_testbench=False):
 def run_syntax_check(file_path):
     """Runs iverilog syntax check."""
     result = subprocess.run(
-        ["iverilog", "-t", "null", file_path], 
+        ["iverilog", "-g2012", "-t", "null", file_path], 
         capture_output=True, text=True
     )
     return result.returncode == 0, result.stderr
@@ -79,7 +93,7 @@ def run_simulation(design_name):
     
     # Compile
     compile_result = subprocess.run(
-        ["iverilog", "-o", sim_out, rtl_file, tb_file],
+        ["iverilog", "-g2012", "-o", sim_out, rtl_file, tb_file],
         capture_output=True, text=True
     )
     if compile_result.returncode != 0:
@@ -88,13 +102,34 @@ def run_simulation(design_name):
     # Run
     run_result = subprocess.run(
         ["vvp", sim_out],
-        capture_output=True, text=True,
+        capture_output=True,
+        text=True,
         timeout=30
     )
-    return True, run_result.stdout
+
+    sim_text = (run_result.stdout or "") + ("\n" + run_result.stderr if run_result.stderr else "")
+
+    # Many Verilog testbenches don't set a failing process exit code.
+    # AgentIC requires a clear PASS marker to treat simulation as successful.
+    # If the TB doesn't print TEST PASSED, we'll consider it a failure so the
+    # verification/fix loop can improve the TB.
+    if "TEST PASSED" in sim_text:
+        return True, sim_text
+
+    # Explicit failure marker
+    if "TEST FAILED" in sim_text:
+        return False, sim_text
+
+    # Fallback: if vvp itself failed, fail. Otherwise, still fail due to missing PASS.
+    if run_result.returncode != 0:
+        return False, sim_text
+    return False, sim_text
 
 def run_openlane(design_name):
     """Triggers the OpenLane flow via Docker."""
+    if not PDK_ROOT or not os.path.exists(PDK_ROOT):
+        return False, f"PDK_ROOT not found: {PDK_ROOT}. Set PDK_ROOT env var or install Sky130 PDKs."
+
     os.chdir(OPENLANE_ROOT)
     
     # Direct Docker command (non-interactive)
@@ -106,7 +141,7 @@ def run_openlane(design_name):
         "-e", "PDK=sky130A",
         "-e", "PWD=/openlane",
         OPENLANE_IMAGE,
-        "./flow.tcl", "-design", design_name, "-tag", "agentrun", "-overwrite"
+        "./flow.tcl", "-design", design_name, "-tag", "agentrun", "-overwrite", "-ignore_mismatches"
     ]
     
     process = subprocess.run(
@@ -119,8 +154,14 @@ def run_openlane(design_name):
     # Check if GDS was created
     gds_path = f"{OPENLANE_ROOT}/designs/{design_name}/runs/agentrun/results/final/gds/{design_name}.gds"
     success = os.path.exists(gds_path)
-    
-    return success, gds_path if success else process.stderr
+
+    if success:
+        return True, gds_path
+
+    error_text = (process.stderr or "")
+    if process.stdout:
+        error_text = (process.stdout + "\n" + error_text).strip()
+    return False, error_text
 
 def run_verification(design_name):
     """Runs the verify_design.sh script."""