fix: Add ngrok bypass header and safe fallbacks to prevent white screen crashes

training/agentic_sft_data.jsonl

@@ -78,3 +78,4 @@
 {"job_id": "7b3059c5-022e-42a4-a082-c0c0f0f0bf23", "timestamp": 1772035035, "design_name": "axi4_dma_engine_with", "instruction": "Design a digital chip: AXI4 DMA engine with 4 channels", "input": "\n## Module: axi4_dma_engine_with  \n\n---  \n\n## Chip Family  \n**AXI4 DMA Engine** – a multi‑channel, AXI‑4 compliant Direct Memory Access engine. The core is an AXI master that can initiate independent read and write transactions on each of four channels.  \n\n---  \n\n## Port List  \n\n| Port | Direction | Bit‑Width | Purpose |\n|------|-----------|-----------|---------|\n| `clk` | Input | 1 | System clock. |\n| `rst_n` | Input | 1 | Asynchronous active‑low reset. |\n| `start_i` | Input | 4 | Start transaction for each of the 4 channels. |\n| `stop_i` | Input | 4 | Abort transaction for each of the 4 channels. |\n| `done_o` | Output | 4 | Transaction‑complete flag per channel. |\n| `err_o` | Output | 4 | Error flag per channel (decode or timeout). |\n| **AXI‑4 Master Interface** (shared by all channels) |  |  |  |\n| `axi_awaddr` | Input | 32 | Address for Write (AW) channel. |\n| `axi_awvalid` | Input | 1 | Valid signal for write address. |\n| `axi_awready` | Output | 1 | Ready to accept write address. |\n| `axi_wdata` | Input | 32 | Write data bus. |\n| `axi_wstrb` | Input | 4 | Byte‑lane strobe (1‑bit per 8‑bit). |\n| `axi_wlast` | Input | 1 | Last beat of a burst. |\n| `axi_wvalid` | Output | 1 | Valid signal for write data. |\n| `axi_wready` | Input | 1 | Ready to accept write data. |\n| `axi_bresp` | Output | 2 | Write response (OKAY, SLVERR, DECERR). |\n| `axi_bvalid` | Output | 1 | Valid response on write channel. |\n| `axi_bready` | Input | 1 | Ready to accept write response. |\n| `axi_araddr` | Input | 32 | Address for Read (AR) channel. |\n| `axi_arvalid` | Input | 1 | Valid signal for read address. |\n| `axi_arready` | Output | 1 | Ready to accept read address. |\n| `axi_rdata` | Output | 32 | Read data bus. |\n| `axi_rresp` | Output | 2 | Read response. |\n| `axi_rvalid` | Output | 1 | Valid signal for read data. |\n| `axi_rready` | Input | 1 | Ready to accept read data. |\n| `irq_o` | Output | 1 | Interrupt request to host (active‑high). |\n\n*All AXI‑4 signals are **shared** among the f", "output": "`timescale 1ns / 1psmodule name matches spec: axi4_dma_engine_with\n *  -------------------------------------------------------\n *  Features:\n *    – 4 independent AXI‑4 master channels\n *    – Start/Stop control per channel\n *    – Simple descriptor fetch (addr, length, flags)\n *    – Write‑burst up to MAX_BURST_LEN beats\n *    – Write‑response checking (b.resp == OKAY)\n *    – Completion interrupt (irq_o)\n *    – Asynchronous active‑low reset (rst_n)\n *    – All parameters are configurable via parameters below\n *    – Production‑ready coding style (always_ff, logic, enum, no placeholders)\n ******************************************************************************************/\n\nmodule axi4_dma_engine_with #(\n    parameter int DATA_WIDTH        = 32,\n    parameter int ADDR_WIDTH        = 32,\n    parameter int NUM_CHANNELS      = 4,\n    parameter int MAX_BURST_LEN     = 16,\n    parameter int DESCRIPTOR_DEPTH  = 1024,\n    parameter int RESET_SYNC        = 0,                 // 0 = async reset, 1 = sync reset\n    parameter string INITIAL_FSM_STATE = \"IDLE\"\n) (\n    // System & Reset\n    input  logic               clk,\n    input  logic               rst_n,                    // async active‑low\n\n    // Channel Control Interface\n    input  logic [NUM_CHANNELS-1:0] start_i,\n    input  logic [NUM_CHANNELS-1:0] stop_i,\n    output logic [NUM_CHANNELS-1:0] done_o,\n    output logic [NUM_CHANNELS-1:0] err_o,\n\n    // Shared AXI‑4 Master Interface\n    output logic [ADDR_WIDTH-1:0] axi_aw", "success": false, "strategy": "SystemVerilog Modular (Modern)", "metrics": {}, "coverage": {}, "build_log_excerpt": "[INIT] Starting Build Process for 'axi4_dma_engine_with' using SystemVerilog Modular (Modern)\n[INIT] Logging initialized to /home/vickynishad/OpenLane/designs/axi4_dma_engine_with/axi4_dma_engine_with.log\n[INIT] PDK profile: sky130 (PDK=sky130A, LIB=sky130_fd_sc_hd)\n[INIT] Transitioning: INIT -> SPEC\n[SPEC] Architecture Plan Generated\n[SPEC] Transitioning: SPEC -> RTL_GEN\n[RTL_GEN] No golden template match. Generating from scratch.\n[RTL_GEN] Hierarchical synthesis planner: disabled.\n[RTL_GEN] Transitioning: RTL_GEN -> RTL_FIX\n[RTL_FIX] Fixing Code (Attempt 1/5)\n[RTL_FIX] File Write Error in FIX stage: Error: No Verilog 'module' definition found in the provided code. Please ensure you output the full Verilog code inside ```verilog``` fences.\n[RTL_FIX] Retrying fix (LLM output was unparsable).\n[RTL_FIX] Detected repeated syntax/lint failure fingerprint. Failing closed.", "source": "agentic_web_build"}
 {"job_id": "f6dc0268-20c7-4291-97b9-187e908e324c", "timestamp": 1772036669, "design_name": "axi4_dma_engine_with", "instruction": "Design a digital chip: AXI4 DMA engine with 4 channels", "input": "\n## Module: axi4_dma_engine_with  \n\n## Chip Family  \n**AXI4‑DMA Engine** – A high‑performance, AXI‑4‑stream‑compatible Direct‑Memory Access controller.  \nThe core belongs to the **AXI peripheral** family; it implements a multi‑channel, AXI‑4 master/target datapath surrounding a compact state‑machine that services four independent DMA channels.\n\n---  \n\n## Port List  \n\n| Port Name | Direction | Bit‑Width | Purpose |\n|-----------|-----------|-----------|---------|\n| `clk` | Input | 1 | System clock. All synchronous logic samples on the rising edge. |\n| `rst_n` | Input | 1 | Asynchronous active‑low reset. When asserted the entire engine goes to the **IDLE** reset state. |\n| `axi_araddr` | Input | `ADDR_WIDTH` | Address channel (read) address bus. |\n| `axi_arvalid` | Input | 1 | Valid signal for a read address transaction. |\n| `axi_arready` | Output | 1 | Ready signal for a read address transaction. |\n| `axi_rdata` | Output | `DATA_WIDTH` | Read data returned by the AXI slave. |\n| `axi_rresp` | Output | 2 | Response code for the read transaction (OKAY, SLVERR, etc.). |\n| `axi_rvalid` | Output | 1 | Valid signal indicating that `axi_rdata`/`axi_rresp` are meaningful. |\n| `axi_rready` | Input | 1 | Ready signal for the read data channel. |\n| `axi_awaddr` | Input | `ADDR_WIDTH` | Address channel (write) address bus. |\n| `axi_awvalid` | Input | 1 | Valid signal for a write address transaction. |\n| `axi_awready` | Output | 1 | Ready signal for a write address transaction. |\n| `axi_wdata` | Input | `DATA_WIDTH` | Write data bus supplied by the master. |\n| `axi_wstrb` | Input | `DATA_BYTES` (`DATA_WIDTH/8`) | Byte‑lane strobe signals. |\n| `axi_wvalid` | Input | 1 | Valid signal indicating that `axi_wdata`/`axi_wstrb` are driven. |\n| `axi_wready` | Output | 1 | Ready signal for the write data channel. |\n| `axi_bresp` | Output | 2 | Response code for a write‐back transaction. |\n| `axi_bvalid` | Output | 1 | Valid signal indicating that `axi_bresp` is available. |\n| `axi_bready` |", "output": "", "success": false, "strategy": "SystemVerilog Modular (Modern)", "metrics": {}, "coverage": {}, "build_log_excerpt": "[INIT] Starting Build Process for 'axi4_dma_engine_with' using SystemVerilog Modular (Modern)\n[INIT] Logging initialized to /home/vickynishad/OpenLane/designs/axi4_dma_engine_with/axi4_dma_engine_with.log\n[INIT] PDK profile: sky130 (PDK=sky130A, LIB=sky130_fd_sc_hd)\n[INIT] Transitioning: INIT -> SPEC\n[SPEC] Architecture Plan Generated\n[SPEC] Transitioning: SPEC -> RTL_GEN\n[RTL_GEN] No golden template match. Generating from scratch.\n[RTL_GEN] File Write Error: Error: No Verilog 'module' definition found in the provided code. Please ensure you output the full Verilog code inside ```verilog``` fences.", "source": "agentic_web_build"}
 {"job_id": "3772ce69-1eb1-4fd7-9786-7bd93c1a0e28", "timestamp": 1772037059, "design_name": "axi4_dma_engine_with", "instruction": "Design a digital chip: AXI4 DMA engine with 4 channels", "input": "\n## Module: axi4_dma_engine_with  \n\n## Chip Family  \n**AXI** – This block is a dedicated AXI‑4 peripheral that implements a multi‑channel Direct Memory Access (DMA) engine. It is classified under the AXI family because its primary purpose is to act as an AXI‑4 slave that coordinates memory transfers on behalf of other system masters, while exposing a fully‑featured AXI‑4 interface for configuration and status.\n\n---\n\n## Port List  \n\n| Direction | Name                | Width | Purpose |\n|-----------|---------------------|-------|------------------------------------------------------------|\n| Input     | `aclk`               | 1     | System clock for the DMA engine (single‑cycle synchronous logic). |\n| Input     | `aresetn`            | 1     | Active‑low asynchronous reset for all logic. |\n| Input     | `s_axi_awaddr`       | 32    | Address for AXI write‑address channel. |\n| Input     | `s_axi_awvalid`      | 1     | Valid signal for write‑address channel. |\n| Output    | `s_axi_awready`      | 1     | Ready signal for write‑address channel. |\n| Input     | `s_axi_wdata`        | 32    | Write data bus. |\n| Input     | `s_axi_wstrb`        | 4     | Byte‑lane strobe for write data (byte‑enable). |\n| Input     | `s_axi_wvalid`       | 1     | Valid signal for write‑data channel. |\n| Output    | `s_axi_wready`       | 1     | Ready signal for write‑data channel. |\n| Output    | `s_axi_bresp`        | 2     | Response for write‑address/write data completion. |\n| Output    | `s_axi_bvalid`       | 1     | Valid signal for write‑response channel. |\n| Input     | `s_axi_bready`       | 1     | Ready signal for write‑response channel. |\n| Input     | `s_axi_araddr`       | 32    | Address for AXI read‑address channel. |\n| Input     | `s_axi_arvalid`      | 1     | Valid signal for read‑address channel. |\n| Output    | `s_axi_arready`      | 1     | Ready signal for read‑address channel. |\n| Output    | `s_axi_rdata`        | 32    | Read data returned to the AXI master. |\n", "output": "", "success": false, "strategy": "SystemVerilog Modular (Modern)", "metrics": {}, "coverage": {}, "build_log_excerpt": "[INIT] Starting Build Process for 'axi4_dma_engine_with' using SystemVerilog Modular (Modern)\n[INIT] Logging initialized to /home/vickynishad/OpenLane/designs/axi4_dma_engine_with/axi4_dma_engine_with.log\n[INIT] PDK profile: sky130 (PDK=sky130A, LIB=sky130_fd_sc_hd)\n[INIT] Transitioning: INIT -> SPEC\n[SPEC] Architecture Plan Generated\n[SPEC] Transitioning: SPEC -> RTL_GEN\n[RTL_GEN] No golden template match. Generating from scratch.\n[RTL_GEN] File Write Error: Error: No Verilog 'module' definition found in the provided code. Please ensure you output the full Verilog code inside ```verilog``` fences.", "source": "agentic_web_build"}
+{"job_id": "4028cf78-f5b1-49a2-ab2f-07612b7e8a11", "timestamp": 1772037936, "design_name": "axi4_dma_engine_with", "instruction": "Design a digital chip: AXI4 DMA engine with 4 channels", "input": "\n# Specification: axi4_dma_engine_with  \n\n---  \n\n## Module  \n**axi4_dma_engine_with** – AXI‑4 Lite master with four independent DMA channels that move data between an on‑chip memory space and an external memory bus. The engine is fully AXI‑4‑LITE compliant and generates an interrupt on completion or error.\n\n---  \n\n## Chip Family  \n**AXI**  \n\n*(DMA engines belong to the AXI‑centric family, as they sit on the AHB‑to‑AXI bridge and provide transaction services to the system.)*\n\n---  \n\n## Port List  \n\n| Port | Direction | Bit‑Width | Purpose |\n|------|-----------|----------|----------|\n| `aclk` | Input | 1 | System clock. |\n| `aresetn` | Input | 1 | Active‑low asynchronous reset. |\n| `s_axi_awaddr` | Input | 32 | AXI‑4 Lite read address channel address. |\n| `s_axi_awvalid` | Input | 1 | Valid signal for address handshake. |\n| `s_axi_awready` | Output | 1 | Ready signal for address handshake. |\n| `s_axi_wdata` | Input | 32 | Write data bus. |\n| `s_axi_wstrb` | Input | 4 | Byte/word strobe (byte‑lane mask). |\n| `s_axi_wvalid` | Input | 1 | Valid signal for write data handshake. |\n| `s_axi_wready` | Output | 1 | Ready for incoming write data. |\n| `s_axi_bresp` | Output | 2 | AXI response (OKAY, SLVERR, etc.). |\n| `s_axi_bvalid` | Output | 1 | Valid signal for write‑response handshake. |\n| `s_axi_bready` | Input | 1 | Ready for incoming response. |\n| `s_axi_araddr` | Input | 32 | AXI‑4 Lite read address channel address. |\n| `s_axi_arvalid` | Input | 1 | Valid signal for address handshake. |\n| `s_axi_arready` | Output | 1 | Ready signal for address handshake. |\n| `s_axi_rdata` | Output | 32 | Read data returned to the master. |\n| `s_axi_rresp` | Output | 2 | Read response. |\n| `s_axi_rvalid` | Output | 1 | Valid signal for read data. |\n| `s_axi_rready` | Input | 1 | Ready for incoming read data. |\n| `intr` | Output | 1 | Interrupt output (single vector, active‑high). |\n| `ch0_cfg_valid` | Input | 1 | Enable/disable channel‑0 descriptor loading. |\n| `ch0_cfg_cmd` | Input | 4 ", "output": "`timescale 1ns/1ps\n//==========================================================================\n//  axi4_dma_engine_with\n//  AXI‑4 Lite slave that implements a 4‑channel DMA engine.\n//  All RTL is classic Verilog‑2005 (reg, wire, explicit FSM)\n//==========================================================================\n\nmodule axi4_dma_engine_with (\n\n    //--- Clock and reset -------------------------------------------------\n    input                     aclk,\n    input                     aresetn,\n\n    //--- AXI‑4 Lite master signals (master drives, DMA responds) -------\n    input  [31:0]             s_axi_awaddr,\n    input                     s_axi_awvalid,\n    output                     s_axi_awready,\n\n    input  [31:0]             s_axi_wdata,\n    input  [ 3:0]             s_axi_wstrb,\n    input                     s_axi_wvalid,\n    output                    s_axi_wready,\n\n    output [1:0]              s_axi_bresp,\n    output                     s_axi_bvalid,\n    input                      s_axi_bready,\n\n    input  [31:0]             s_axi_araddr,\n    input                     s_axi_arvalid,\n    output                    s_axi_arready,\n\n    output [31:0]             s_axi_rdata,\n    output [1:0]              s_axi_rresp,\n    output                     s_axi_rvalid,\n    input                      s_axi_rready,\n\n    //--- Interrupt -------------------------------------------------------\n    output                     intr,\n\n    //--- Configuration for channel 0 (channel 1‑3", "success": false, "strategy": "Verilog-2005 (Legacy/Robust)", "metrics": {}, "coverage": {}, "build_log_excerpt": "[INIT] Starting Build Process for 'axi4_dma_engine_with' using SystemVerilog Modular (Modern)\n[INIT] Logging initialized to /home/vickynishad/OpenLane/designs/axi4_dma_engine_with/axi4_dma_engine_with.log\n[INIT] PDK profile: sky130 (PDK=sky130A, LIB=sky130_fd_sc_hd)\n[INIT] Transitioning: INIT -> SPEC\n[SPEC] Architecture Plan Generated\n[SPEC] Transitioning: SPEC -> RTL_GEN\n[RTL_GEN] No golden template match. Generating from scratch.\n[RTL_GEN] Hierarchical synthesis planner: disabled.\n[RTL_GEN] Transitioning: RTL_GEN -> RTL_FIX\n[RTL_FIX] Fixing Code (Attempt 1/5)\n[RTL_FIX] Fixing Code (Attempt 2/5)\n[RTL_FIX] Fixing Code (Attempt 3/5)\n[RTL_FIX] Fixing Code (Attempt 4/5)\n[RTL_FIX] Fixing Code (Attempt 5/5)\n[RTL_FIX] Max Retries Exceeded for Syntax/Lint Fix.\n[RTL_FIX] Attempting Strategy Pivot: SV_MODULAR -> VERILOG_CLASSIC\n[RTL_FIX] Transitioning: RTL_FIX -> RTL_GEN\n[RTL_GEN] No golden template match. Generating from scratch.\n[RTL_GEN] Hierarchical synthesis planner: disabled.\n[RTL_GEN] Transitioning: RTL_GEN -> RTL_FIX\n[RTL_FIX] Fixing Code (Attempt 1/5)\n[RTL_FIX] File Write Error in FIX stage: Error: No Verilog 'module' definition found in the provided code. Please ensure you output the full Verilog code inside ```verilog``` fences.\n[RTL_FIX] Retrying fix (LLM output was unparsable).\n[RTL_FIX] Detected repeated syntax/lint failure fingerprint. Failing closed.", "source": "agentic_web_build"}

web/src/App.tsx

@@ -13,11 +13,14 @@ const App = () => {
   const [designs, setDesigns] = useState<{ name: string, has_gds: boolean }[]>([]);
   const [selectedDesign, setSelectedDesign] = useState<string>('');
 
+  // Bypass Ngrok browser warning for all Axios requests
+  axios.defaults.headers.common['ngrok-skip-browser-warning'] = 'true';
+
   useEffect(() => {
-    const API_BASE_URL = import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000';
+    const API_BASE_URL = (import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000').replace(/\/$/, '');
     axios.get(`${API_BASE_URL}/designs`)
       .then(res => {
-        const data = res.data.designs;
+        const data = res.data?.designs || [];
         setDesigns(data);
         if (data.length > 0) {
           const withGds = data.find((d: any) => d.has_gds);

web/src/components/BuildMonitor.tsx

@@ -2,7 +2,7 @@ import React, { useEffect, useRef } from 'react';
 import { motion } from 'framer-motion';
 import axios from 'axios';
 
-const API = import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000';
+const API = (import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000').replace(/\/$/, '');
 
 const STATES_DISPLAY: Record<string, { label: string; icon: string }> = {
     INIT: { label: 'Initializing Workspace', icon: '🔧' },

web/src/pages/Dashboard.tsx

@@ -17,7 +17,7 @@ export const Dashboard: React.FC<DashboardProps> = ({ selectedDesign }) => {
         setLoading(true);
 
         // Fetch Quick Metrics
-        const API_BASE_URL = import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000';
+        const API_BASE_URL = (import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000').replace(/\/$/, '');
         axios.get(`${API_BASE_URL}/metrics/${selectedDesign}`)
             .then(res => {
                 if (res.data.metrics) setMetrics(res.data.metrics);

web/src/pages/DesignStudio.tsx

@@ -4,7 +4,7 @@ import axios from 'axios';
 import { BuildMonitor } from '../components/BuildMonitor';
 import { ChipSummary } from '../components/ChipSummary';
 
-const API = import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000';
+const API = (import.meta.env.VITE_API_BASE_URL || 'http://localhost:8000').replace(/\/$/, '');
 
 type Phase = 'prompt' | 'building' | 'done';