Update docs: Detailed README and Defense Research Poster context

POSTER_CONTENT.md

@@ -0,0 +1,97 @@
+# Research Poster Content: AgentIC & Defense Challenges
+
+## Title
+**AgentIC: Autonomous Sovereign Silicon Design Framework for Defense Applications**
+
+## Abstract
+Modern defense systems are critically dependent on advanced semiconductors. However, reliance on foreign EDA tools and fabrication supply chains introduces severe risks, including Hardware Trojans, backdoors, and strategic denial of technology. Validating the "Trust" in hardware is expensive and time-consuming. **AgentIC** is a novel, AI-driven "Text-to-Silicon" framework designed to democratize and accelerate the design of secure, sovereign silicon. By leveraging localized Large Language Models (LLMs) and open-source EDA tools (OpenLane), AgentIC automates the RTL-to-GDSII flow, ensuring design secrecy and reducing the "Time-to-Tactical-Edge" for custom hardware solutions.
+
+---
+
+## 1. Problem Statement: The Defense Silicon Gap
+
+### A. Supply Chain Vulnerability
+*   **Dependency:** Over 90% of advanced chips and EDA tools are controlled by non-domestic entities.
+*   **Risk:** In conflict scenarios, access to critical components can be cut off (Sanctions/Blockades).
+
+### B. Hardware Security Threats
+*   **Trojans:** Malicious logic inserted during design or fabrication (e.g., "Kill Switches" or data exfiltration backdoors).
+*   **Opaque IP:** Using closed-source "Black Box" IP cores makes it impossible to verify full security coverage.
+
+### C. Obsolescence & Agility
+*   **Legacy Systems:** Maintaining aging military hardware requires obsolete chips that are no longer manufactured.
+*   **Slow Development:** Traditional ASIC design cycles take 18-24 months, too slow for evolving asymmetric threats.
+
+---
+
+## 2. Proposed Solution: The AgentIC Framework
+
+AgentIC serves as a **Sovereign Design Companion**, allowing defense engineers to generate verified, physically layout-ready silicon from high-level natural language specifications.
+
+### Key Pillars:
+1.  **AI-Agent Crew:** Specialized AI agents act as the Design Team (Architect, RTL Coder, Verification Engineer).
+2.  **Self-Correction:** Closed-loop feedback mechanism where agents fix their own compilation and simulation errors.
+3.  **Local & Secure:** Support for on-premises LLM deployment (e.g., Llama 3 on air-gapped servers) ensures **ZERO** data leakage.
+4.  **Open Source Flow:** output is compatible with the OpenLane/SkyWater 130nm PDK, ensuring a fully auditable toolchain.
+
+---
+
+## 3. Methodology & Architecture
+
+### The Workflow
+1.  **Prompt:** User inputs specs (e.g., *"Design a secure AES-256 accelerator with side-channel attack masking"*).
+2.  **Design Agent:** Generates SystemVerilog RTL.
+3.  **Verification Agent:** Generates a self-checking testbench (randomized stimuli + assertion checking).
+4.  **Simulation & Loop:** 
+    *   Runs `iverilog` simulation.
+    *   If fail: Agents read logs -> Patch Code -> Re-run.
+    *   If pass: Proceed to hardening.
+5.  **Physical Design:** Automates OpenLane scripts to generate GDSII.
+
+### Sovereign Tech Stack
+*   **Logic:** Custom AI Agents (CrewAI/LangChain)
+*   **Simulation:** Icarus Verilog (Open Source)
+*   **Layout:** OpenLane (Open Source)
+*   **PDK:** SkyWater 130nm (Open Google/SkyWater)
+
+---
+
+## 4. Addressing Defense Challenges (Analysis)
+
+| Challenge | AgentIC Solution |
+| :--- | :--- |
+| **IP Theft / Secrecy** | **Local Inference:** Prompts run on secure, air-gapped servers. No cloud APIs required. |
+| **Trojan Insertion** | **Auditable Code:** AI generates human-readable SystemVerilog, not binary blobs. Easier to review. |
+| **Rapid Field Deployment** | **Speed:** Reduces design-to-layout time from months to days for auxiliary chips. |
+| **Talent Shortage** | **Force Multiplier:** Allows non-expert systems engineers to create functional hardware blocks. |
+
+---
+
+## 5. Case Study: Secure Processor Recovery
+
+**Experiment:** 
+We tasked AgentIC to design a "Secure Lockout Mechanism" for a processor (a common need for tamper-proof hardware).
+
+*   **Input:** "Create a state machine that locks the system after 3 failed 4-digit PIN attempts."
+*   **Result:**
+    1.  Agent generated an FSM (Finite State Machine) correctly handling transitions.
+    2.  Initial bug: Reset logic was inverted.
+    3.  **Auto-Fix:** Verification agent caught the timeout error, and the Designer agent corrected the polarity in `always_ff`.
+    4.  **Final Output:** Clean, LVS-clean GDSII layout ready for fabrication.
+
+---
+
+## 6. Conclusion & Future Work
+
+AgentIC demonstrates that Generative AI can bridge the gap between secure requirements and physical silicon. By keeping the "Brain" of the design process local and using open tools, India can achieve true **Atmanirbhar** status in the strategic semiconductor sector. 
+
+**Future Roadmap:**
+*   Integration with formal verification tools for mathematical security proofs.
+*   Support for FPGA bitstream generation for rapid field updates.
+
+---
+
+## References
+1.  *The OpenLane Project Documentation*
+2.  *DeepSeek / Llama 3 Technical Reports*
+3.  *Defense Advanced Research Projects Agency (DARPA) POSH Program*

README.md

@@ -1,111 +1,142 @@
-# AgentIC: Natural Language to Chip Layout (GDSII)
+# AgentIC: Sovereign AI-Powered Silicon Design Framework
 
-**AgentIC** is an automated AI Agent framework that transforms natural language descriptions into industry-standard physical chip layouts. It essentially acts as a "Text-to-Silicon" compiler, leveraging LLMs (DeepSeek, Llama 3, etc.) to write RTL, verify it, and drive the OpenLane physical design toolchain.
+![Status](https://img.shields.io/badge/Status-Beta-orange) ![Python](https://img.shields.io/badge/Python-3.10%2B-blue) ![License](https://img.shields.io/badge/License-MIT-green) ![OpenLane](https://img.shields.io/badge/OpenLane-Integrated-purple)
 
-## 🚀 Capabilities
+**AgentIC** is an automated, sovereign AI Agent framework that transforms natural language descriptions directly into industry-standard physical chip layouts (GDSII). Designed with the **"Atmanirbhar" (Self-Reliant)** philosophy, it empowers engineers to design secure, custom silicon locally, reducing dependency on foreign EDA tools and supply chains.
 
-*   **Natural Language → RTL**: Generates synthesizable **SystemVerilog** code based on your prompt.
-*   **Industry Standard Enforced**:
-    *   Automatic usage of `logic`, `always_ff`, and `always_comb`.
-    *   **Flattened I/O Ports**: Ensures compatibility with hardening tools.
-    *   **Scalable Architecture**: Uses `parameters` for bus widths.
-*   **Self-Correcting Agents**:
-    *   **Design Agent**: Writes the code.
-    *   **Verification Agent**: Writes a self-checking Testbench (`_tb.v`).
-    *   **Auto-Fix Loop**: If compilation or simulation fails, the agents read the error logs and patch the code automatically.
-*   **Physical Design (Hardening)**: Integrates directly with [OpenLane](https://github.com/The-OpenROAD-Project/OpenLane) to generate GDSII layouts.
+It acts as a **"Text-to-Silicon" Compiler**, orchestrating a crew of specialized AI agents to write SystemVerilog RTL, verify it with self-generated testbenches, and harden the design using the OpenLane open-source flow.
 
-## 🖥️ Web Interface (UI)
+---
 
-AgentIC includes a futuristic "Atmanirbhar" Dashboard for monitoring designs, benchmarking against market standards, and analyzing GDSII layouts.
+## 🛡️ Mission: Sovereign Silicon (Atmanirbhar Bharat)
+In the context of national defense and critical infrastructure, reliance on closed-source foreign chips and tools poses significant risks (Hardware Trojans, Supply Chain Denial, Backdoors). 
 
-```bash
-streamlit run AgentIC/app.py
-```
+**AgentIC addresses these challenges by:**
+1.  **Democratizing Design**: Enabling rapid creation of custom functional blocks without a full design team.
+2.  **Open Source Chain**: Utilizing **OpenLane** and standard PDKs (SkyWater 130nm), ensuring the entire flow is auditable.
+3.  **Data Privacy**: Promoting the use of **Local LLMs** (running on premises) so sensitive design prompts and logical structures never leave the secure environment.
+
+---
+
+## 🚀 Key Capabilities
+
+### 🧠 AI-Driven RTL Design
+*   **Natural Language → SystemVerilog**: Simply describe the module (e.g., "A secure 32-bit RISC-V core with encrypted instruction memory").
+*   **Context-Aware Coding**: Agents use proper `logic`, `always_ff`, and `always_comb` blocks and parameterized widths.
+*   **Flattened I/O**: Generates hardware-ready ports compatible with physical implementation tools.
+
+### 🔄 Self-Correcting Verification Loop
+*   **Agent Swarm**:
+    *   **Designer Agent**: Writes the RTL implementation.
+    *   **Testbench Agent**: Writes a comprehensive self-checking testbench (`_tb.v`).
+    *   **Verifier Agent**: Analyzes simulation logs (Icarus Verilog).
+*   **Auto-Fix**: If the simulation fails, the agents analyze the error, rewrite the RTL/Testbench, and retry automatically until `TEST PASSED`.
+
+### 🏭 Physical Design Automation
+*   **One-Click Hardening**: Seamless integration with **OpenLane**.
+*   **GDSII Generation**: Produces the final layout files ready for the foundry.
+*   **Artifacts**: Generates LEF, DEF, GDS, and Mag files automatically.
 
-Features:
-*   **Sci-Fi Themed Dashboard**: Premium "Deep Void" visualization.
-*   **Market Benchmarking**: Compare your design's Cost, Power, and Area against imported chips (Nvidia, STM32, etc.).
-*   **Design Studio**: Interactive RTL editor and AI planner.
-*   **GDSII Viewer**: Download and inspect tapeout files.
+### 🖥️ Secure "Deep Void" Dashboard
+*   **Streamlit Operations Center**: Monitor the entire design process visually.
+*   **Market Benchmarking**: Compare your design's PPA (Power, Performance, Area) against standard metrics.
+*   **GDS Viewer**: Built-in viewer for finalized layouts.
 
 ---
 
-## 🛠️ Workflow
+## 📦 Installation
 
-The workflow consists of three main stages. You can run them all at once or individually.
+### Prerequisites
+*   Python 3.10+
+*   [OpenLane](https://github.com/The-OpenROAD-Project/OpenLane) (installed and configured via Docker)
+*   Icarus Verilog (`iverilog`)
 
-### 1. Build (Design & Verify)
-This is the main entry point. It invites the AI to design the chip and verify it.
-```bash
-python3 AgentIC/main.py build --name <design_name> --desc "<your description>"
-```
-**Example:**
+### Setup
+1.  **Clone the Repository**
+    ```bash
+    git clone https://github.com/Vickyrrrrrr/AgentIC.git
+    cd AgentIC
+    ```
+
+2.  **Create Virtual Environment**
+    ```bash
+    python -m venv venv
+    source venv/bin/activate
+    ```
+
+3.  **Install Dependencies**
+    ```bash
+    pip install -r requirements.txt
+    ```
+
+4.  **Configure Environment**
+    Create a `.env` file in the root directory:
+    ```env
+    # Choose your provider (NVIDIA, GROQ, or OPENAI)
+    # Leave empty if using Local LLM (e.g., Ollama)
+    OPENAI_API_KEY=sk-...
+    NVIDIA_API_KEY=nvapi-...
+    GROQ_API_KEY=gsk_...
+    
+    # Path to OpenLane
+    OPENLANE_ROOT=/path/to/openlane
+    PDK_ROOT=/path/to/pdk
+    ```
+
+---
+
+## 🛠️ Usage
+
+### 1. Command Line Interface (CLI)
+The fastest way to build a specific module.
+
+**Build & Verify (RTL Level):**
 ```bash
-python3 AgentIC/main.py build --name my_processor --desc "A 4x4 Systolic Array NPU with AXI Stream interface"
+python main.py build --name secure_lock --desc "A 4-digit PIN based electronic lock with a lockout timer after 3 failed attempts."
 ```
-*   **Output**: Generates `src/<name>.v` and `src/<name>_tb.v`.
-*   **Action**: Runs syntax checks and simulations until `TEST PASSED` is confirmed.
 
-### 2. Simulate (Manual Verification)
-If you have manually modified the Verilog files (or want to re-run verification without triggering the AI to overwrite your files), use this command.
+**Full Flow (RTL + GDSII):**
+*(Ensure OpenLane is running)*
 ```bash
-python3 AgentIC/main.py simulate --name <design_name>
+python main.py harden --name secure_lock
 ```
 
-### 3. Harden (RTL → GDSII)
-Once your Simulation passes, turn the Verilog into a physical layout using OpenLane. This step runs synthesis, placement, routing, and signoff checks.
+### 2. Interactive Web Dashboard
+Launch the Mission Control interface.
 ```bash
-python3 AgentIC/main.py harden --name <design_name>
+streamlit run app.py
 ```
-*   **Output**: A `.gds` file in `OpenLane/designs/<name>/runs/.../results/final/gds/`.
+*   Navigate to **"Design Studio"** to chat with the AI Agents.
+*   Use **"Fabrication"** tab to trigger OpenLane flows.
+*   Check **"GDS Viewer"** to inspect final chips.
 
 ---
 
 ## 📂 Project Structure
 
 ```text
-/home/vickynishad/
-├── AgentIC/              # The AI Core
-│   ├── main.py           # CLI Entry point
-│   ├── .env              # API Keys & Config
-│   └── src/agentic/      # Source code for Agents & Tools
-│
-├── OpenLane/             # Physical Design Engine
-│   └── designs/
-│       ├── simple_counter/ # Template configuration (DO NOT DELETE)
-│       └── <your_design>/  # Generated chips go here
-│           ├── config.tcl  # Auto-generated OpenLane config
-│           └── src/
-│               ├── <name>.v     # SystemVerilog RTL
-│               └── <name>_tb.v  # Testbench
+AgentIC/
+├── artifacts/          # Generated VCD waveforms & GDSII layouts
+├── designs/            # Source RTL & Testbenches
+│   ├── minicount/
+│   └── secure_lock/
+├── src/
+│   └── agentic/
+│       ├── agents/     # AI Personas (Designer, Verifier)
+│       └── tools/      # Interfaces for compilers & simulators
+├── app.py              # Streamlit Web Dashboard
+├── main.py             # CLI Entry Point
+└── debug_llm.py        # Utility to check LLM connectivity
 ```
 
-## 🔌 Setup & Prerequisites
-
-1.  **Python 3.10+** & **Docker** (for OpenLane).
-2.  **Icarus Verilog (`iverilog`)**.
-3.  **LLM Configuration**:
-    You can use a local model (Ollama) or a Cloud API (Groq/DeepSeek) for faster inference.
-    
-    Create a `.env` file in `AgentIC/`:
-    ```dotenv
-    # Option 1: Cloud (Recommended for Speed)
-    GROQ_API_KEY=gsk_...
-    LLM_MODEL=openai/llama-3.3-70b-versatile
-    LLM_BASE_URL=https://api.groq.com/openai/v1
-
-    # Option 2: Local (DeepSeek R1 via Ollama)
-    # LLM_MODEL=ollama/deepseek-r1
-    # LLM_BASE_URL=http://localhost:11434
-    ```
+---
 
-## 🧠 AI Reasoning
-By default, if the model supports "Chain of Thought" (like DeepSeek R1), the tool can show the hidden reasoning process.
-```bash
-python3 AgentIC/main.py build ... --show-thinking
-```
+## 🔮 Roadmap
+*   Support for Analog/Mixed-Signal descriptions.
+*   Integration with open-source FPGA toolchains (Yosys/Nextpnr).
+*   Formal Verification agent integration.
 
 ---
-**Author**: Vickyrrrrrr
-**Powered by**: CrewAI & OpenLane
+
+## ⚖️ License
+This project is licensed under the MIT License - see the [LICENSE](LICENSE) file for details.