feat: add skip coverage option to Design Studio and Human In Loop Build pages

- Introduced a new state variable `skipCoverage` in both Design Studio and Human In Loop Build components.
- Added a checkbox to toggle the `skipCoverage` option in the UI for both components.
- Updated the API request payload to include `skip_coverage` based on the new state.

README.md

@@ -1,421 +1,344 @@
-<div align="center">
+# AgentIC
 
-<br/>
+AgentIC is an autonomous digital design pipeline that takes a natural-language chip specification and drives it through RTL generation, verification, formal checks, coverage, regression, and optional physical implementation. The system is built as a gated flow around standard EDA tools and AI-assisted generation and debugging.
 
-<!-- ──────────────── WORDMARK ──────────────── -->
-<h1>
-  <img src="https://readme-typing-svg.demolab.com?font=Fira+Code&weight=700&size=42&pause=1000&color=C9643E&center=true&vCenter=true&width=600&lines=AgentIC" alt="AgentIC" />
-</h1>
+This README is written for both technical readers and non-specialists. It explains what the system does, what the build stages mean, and what the repository contains, without exposing internal proprietary logic.
 
-<h3><em>Describe a chip. Get silicon.</em></h3>
+## What AgentIC Actually Does
 
-<br/>
+At a high level, AgentIC performs four jobs:
 
-<!-- ──────────────── BRAND BADGES ──────────────── -->
+1. Turn an ambiguous prose specification into a structured hardware task.
+2. Generate candidate RTL, testbenches, properties, and constraints.
+3. Push those artifacts through quality gates with controlled repair loops.
+4. Stop only when the design either passes the configured flow or fails with a concrete diagnosis.
 
-![](https://img.shields.io/badge/Autonomous%20Silicon%20Compiler-informational?style=for-the-badge&labelColor=1C1A17&color=C9643E)
-![](https://img.shields.io/badge/All%205%20Core%20Modules%20Active-success?style=for-the-badge&labelColor=1C1A17&color=3A7856)
-![](https://img.shields.io/badge/Fail--Closed%20by%20Default-critical?style=for-the-badge&labelColor=1C1A17&color=B83030)
+The system is not a simple code generator. It is a build-and-check pipeline that keeps testing what it generates.
 
-<br/>
+## System Model
 
-![](https://img.shields.io/badge/Python-3.10%2B-C9643E?style=flat-square&logo=python&logoColor=white&labelColor=1C1A17)
-![](https://img.shields.io/badge/PDK-Sky130%20%7C%20GF180-C9643E?style=flat-square&labelColor=1C1A17)
-![](https://img.shields.io/badge/Formal%20Verification-SymbiYosys-C9643E?style=flat-square&labelColor=1C1A17)
-![](https://img.shields.io/badge/Physical%20Flow-OpenLane-C9643E?style=flat-square&labelColor=1C1A17)
-![](https://img.shields.io/badge/License-Proprietary-A67828?style=flat-square&labelColor=1C1A17)
+AgentIC is organized around three layers:
 
-<br/><br/>
+### 1. Orchestration Layer
 
-<table>
-<tr>
-<td align="center" width="220"><b>Natural Language In ⟶</b></td>
-<td align="center" width="60">→</td>
-<td align="center" width="220"><b>⟶ Verified RTL + GDS Out</b></td>
-</tr>
-</table>
+The orchestrator owns stage transitions, retry budgets, artifact routing, and failure handling. It is the source of truth for:
 
-<br/>
+- which stage runs next
+- what inputs each stage is allowed to consume
+- what counts as pass, fail, skip, or tool error
+- how many retries are allowed
+- when the build must halt instead of spinning
 
-</div>
+Core implementation: [orchestrator.py](/home/vickynishad/AgentIC/src/agentic/orchestrator.py)
 
----
+### 2. Tool Layer
 
-## What is AgentIC?
+EDA tool wrappers execute Verilator, Icarus Verilog, Yosys, and SymbiYosys. Intermediate work is staged in temporary directories; human-relevant artifacts remain in the design tree.
 
-AgentIC is a **fully autonomous hardware compiler** that takes a plain-English description of a digital circuit and produces a complete, verified, physically-implemented chip design — with no human in the loop unless you want one.
+Core implementation: [vlsi_tools.py](/home/vickynishad/AgentIC/src/agentic/tools/vlsi_tools.py)
 
-It is not a code-generation copilot. It is not a template filler. It is an **end-to-end autonomous agent system** that reasons, verifies, debugs, repairs, and re-verifies until the design meets every quality gate — then hands you the GDS.
+### 3. Agent Layer
 
-> *"You wrote the spec. We wrote the chip."*
+Specialist AI components assist specific tasks such as RTL generation, testbench creation, failure analysis, and formal-property generation. These components do not bypass the tool checks; their output must still pass the relevant stage gates.
 
----
+## End-to-End Pipeline
 
-## The Problem It Solves
+The full build pipeline is:
 
-Traditional hardware design has two unavoidable costs:
+```text
+Specification
+  -> RTL_GEN
+  -> RTL_FIX
+  -> VERIFICATION
+  -> FORMAL_VERIFY
+  -> COVERAGE_CHECK
+  -> REGRESSION
+  -> HARDENING
+  -> CONVERGENCE
+  -> SIGNOFF
+```
 
-| Problem | Industry Reality | AgentIC's Answer |
-|---------|-----------------|-----------------|
-| **Iteration time** | Hours per RTL-to-sim cycle | Fully automated multi-stage pipeline |
-| **Silent bugs** | Weak checks ship bad silicon | Every gate is fail-closed — if it cannot prove correctness, it does not proceed |
-| **Expert bottleneck** | Needs senior RTL + verification + physical engineers | One prompt, autonomous resolution |
-| **Infinite churn** | Teams retry the same broken strategy | Loop budgets, loop-identity detection, and strategy pivots are baked in |
+Each stage is gated. A stage can only advance if its required checks pass. There is no silent forwarding of a broken artifact.
 
----
+### Stage Intent
 
-<div align="center">
+| Stage | Purpose | Typical Outputs |
+|------|---------|-----------------|
+| `SPECIFICATION` | Normalize the user prompt into a design contract | structured prompt context |
+| `RTL_GEN` | Generate initial RTL and supporting files | `<name>.v`, supporting metadata |
+| `RTL_FIX` | Enforce syntax, lint, and semantic rigor; repair failures | corrected RTL, diagnostics |
+| `VERIFICATION` | Build TB, run simulation, analyze functional failures | `<name>_tb.v`, sim logs, VCD |
+| `FORMAL_VERIFY` | Generate SVA, preflight it, run formal checks | `<name>_sva.sv`, formal summaries |
+| `COVERAGE_CHECK` | Improve or validate coverage after functional success | coverage metrics, coverage JSON |
+| `REGRESSION` | Run directed corner-case validation | regression results |
+| `HARDENING` | Invoke OpenLane flow if enabled | layout flow outputs |
+| `CONVERGENCE` | Recover from physical-flow failures | updated configs or constraints |
+| `SIGNOFF` | Run DRC/LVS/STA/power/equivalence style checks | signoff reports |
 
-## Pipeline at a Glance
+## Reliability Model
 
-</div>
+AgentIC is designed around one rule: every stage must provide enough evidence to justify the next stage.
 
-```
-Your Prompt
-    │
-    ▼
-┌─────────────────────────────────────────────────────────────────┐
-│                        AGENTRIC PIPELINE                         │
-│                                                                  │
-│  ① Specification     →  Structured design contract              │
-│  ② RTL Generation    →  Architecture-aware Verilog              │
-│  ③ RTL Hardening     →  Iterative syntax · lint · semantic fix  │
-│  ④ Verification      →  Testbench compile · simulation          │
-│  ⑤ Formal Proof      →  SVA assertions · SymbiYosys bounded MC  │
-│  ⑥ Coverage          →  Profile-driven closure · anti-regression│
-│  ⑦ Regression        →  Directed corner-case execution          │
-│  ⑧ Physical Flow     →  Floorplan · Hardening · Convergence     │
-│  ⑨ Signoff           →  DRC · LVS · STA · Power · IR · LEC     │
-│                                                                  │
-│              SUCCESS  ──────────────────── GDS + Reports        │
-└─────────────────────────────────────────────────────────────────┘
-```
+### Fail-Closed By Default
 
-Every transition between stages is gated. Nothing proceeds until the previous stage passes cleanly.
-
----
-
-## Five Core Intelligence Modules
-
-AgentIC's reasoning layer is built on five proprietary modules — all active in the current production pipeline.
-
-<br/>
-
-<table>
-<thead>
-<tr>
-<th width="220">Module</th>
-<th>Capability</th>
-<th width="200">When It Activates</th>
-</tr>
-</thead>
-<tbody>
-<tr>
-<td><b>Specification Architect</b></td>
-<td>Converts ambiguous prose into a precise, structured design contract shared by all downstream agents — preventing conflicting interpretations before a single line of RTL is written</td>
-<td>Before RTL generation</td>
-</tr>
-<tr>
-<td><b>Iterative Reasoning Agent</b></td>
-<td>Applies a multi-step Think → Act → Observe loop to reason through RTL issues before committing any repair, reducing unnecessary edits and preserving design intent</td>
-<td>Every RTL repair cycle</td>
-</tr>
-<tr>
-<td><b>Waveform Intelligence</b></td>
-<td>Reads simulation waveforms and traces every incorrectly-driven output back to the exact RTL construct responsible — giving the repair layer deterministic evidence instead of inference</td>
-<td>On any simulation failure</td>
-</tr>
-<tr>
-<td><b>Formal Causal Debugger</b></td>
-<td>Builds a signal causality graph from the failing formal property, applies balanced for-and-against analysis, and returns the root-cause signal, source line, and a confidence score</td>
-<td>On any formal failure</td>
-</tr>
-<tr>
-<td><b>Self-Reflection Recovery</b></td>
-<td>Categorises physical implementation failures, reflects on convergence history, proposes corrective actions, applies them, and tracks whether metrics are improving or stagnating before retrying</td>
-<td>On any hardening failure</td>
-</tr>
-</tbody>
-</table>
-
-<br/>
-
-> **Intellectual Property Notice** — The internal algorithms, decision logic, prompt architecture, repair heuristics, scoring mechanisms, and module interfaces are proprietary and confidential. The table above describes *capabilities*, not *implementations*. No part of AgentIC's core reasoning design is disclosed in this document.
-
----
-
-## Quality Architecture
-
-AgentIC is engineered around one principle: **trust nothing, verify everything.**
-
-### Fail-Closed Gates
-
-Every stage either **passes** or **halts with a diagnosis**. There is no silent forwarding of a broken artifact.
+If syntax, lint, simulation, formal checks, or physical checks fail, the build does not continue unless a replacement artifact passes the relevant gate.
 
-```
-  RTL FIX ──► [Syntax Gate] ──► [Lint Gate] ──► [Semantic Gate] ──► Next Stage
-                   │                 │                  │
-                 FAIL              FAIL              FAIL
-                   └─────────────────┴──────────────────┘
-                                     │
-                             Repair Loop (budgeted)
-                                     │
-                         [Loop-Identity Guard] ◄── prevents infinite churn
-```
+### Deterministic Before Generative
 
-### Layered Autonomous Repair
+Repair is layered:
 
-At every gate, the system applies repair in strict priority order:
+1. deterministic cleanup or mechanical fix
+2. targeted analysis
+3. constrained regeneration
+4. strategy pivot or fail-closed halt
 
-1. **Deterministic pass** — machine-precise corrections with zero LLM involvement
-2. **Reasoned pass** — multi-step agentic reasoning with hardware-specific tool use
-3. **Generative pass** — LLM-guided surgical correction, minimum diff enforced
-4. **Strategy pivot** — if all passes exhaust their budget, the build fails closed; it does not ship a broken artifact
+This ordering matters. The system tries to preserve design intent and minimize uncontrolled rewrites.
 
-### Loop Safety
+### Budgeted Loops
 
-Every repair loop has a hard step budget. Identical repeated artifacts are detected and rejected before an LLM call is made. If the system cannot demonstrate measurable forward progress, it escalates to fail-closed rather than spinning.
+Each repair path is budgeted. The system tracks repeated failures and retry exhaustion to avoid infinite churn.
 
----
+## Core Reasoning Components
 
-## Multi-Agent Collaboration
+AgentIC uses multiple specialized components rather than one undifferentiated "agent".
 
-The generative layer is a collaborative crew of specialised AI agents, each scoped to a single responsibility and equipped with hardware-specific tooling:
+These components are used for tasks such as:
 
-| Agent Role | Responsibility |
-|------------|---------------|
-| **RTL Designer** | Architecture-aware Verilog generation with pre-submission self-verification |
-| **Testbench Designer** | Simulator-safe testbenches with stimulus integrity guarantees |
-| **Failure Analyst** | Signal-level diagnosis — always cites specific RTL line, construct, and expected vs. actual values |
-| **Verification Engineer** | SVA assertion generation tuned for the open-source formal toolchain |
-| **Regression Architect** | Directed corner-case scenario planning |
-| **Physical Constraints** | SDC timing constraint synthesis |
-| **Documentation** | Design specification and IP declaration |
+- RTL generation
+- testbench generation
+- SVA generation
+- constraint generation
+- documentation
 
-All agents operate from the structured design contract established at the Specification stage — eliminating the divergence that occurs when different agents interpret the same prose spec independently.
+These outputs are still stage-gated. AgentIC does not assume that generated code is valid just because an AI model produced it.
 
----
+## How Reliability Is Managed
 
-## Human-in-the-Loop Web Interface
+Reliability work in AgentIC focuses on three practical areas:
 
-<div align="center">
+- clear stage boundaries
+- explicit artifact passing between stages
+- replayable testing from benchmark failures
 
-![](https://img.shields.io/badge/Real--time%20SSE%20Streaming-C9643E?style=for-the-badge&labelColor=1C1A17)
-![](https://img.shields.io/badge/Approval%20Gates-C9643E?style=for-the-badge&labelColor=1C1A17)
-![](https://img.shields.io/badge/Live%20Agent%20Reasoning%20View-C9643E?style=for-the-badge&labelColor=1C1A17)
+The goal is to make failures diagnosable and repeatable, not to hide them behind optimistic retries.
 
-</div>
+## Toolchain
 
-AgentIC ships with a production-grade web application (React 19 + Vite frontend, FastAPI backend). Every pipeline event streams to the UI in real time. Three build modes are available:
+AgentIC is built around open-source digital design tools:
 
-| Mode | Description |
-|------|-------------|
-| **Autonomous** | Zero human checkpoints — fully hands-off |
-| **Supervised** | Pause and approve at user-defined stages |
-| **Interactive** | Full step-by-step control with per-decision approval |
+- Verilator
+- Icarus Verilog (`iverilog`, `vvp`)
+- Yosys
+- SymbiYosys (`sby`)
+- OpenLane for physical implementation
 
-Design artifacts, agent reasoning steps, signal traces, formal proof results, and physical convergence metrics are all visible in the interface as they are produced.
+Formal and physical-flow stages are optional depending on the selected build mode and installed environment.
 
----
+## Repository Structure
 
-## Signoff Coverage
+Top-level layout:
 
-| Domain | What Is Verified |
-|--------|-----------------|
-| **Functional** | Simulation correctness across all generated and directed stimuli |
-| **Formal** | Bounded model checking with SVA property coverage |
-| **Structural** | DRC — design rule compliance for the target PDK |
-| **Physical** | LVS — layout-versus-schematic equivalence |
-| **Timing** | Multi-corner STA — setup and hold across all paths |
-| **Power** | Peak and average power estimation |
-| **IR Drop** | Supply integrity validation |
-| **Equivalence** | LEC — RTL-to-GDS logical equivalence |
+```text
+AgentIC/
+├── src/agentic/          # orchestrator, tool wrappers, agents, CLI
+├── tests/                # unit and reliability tests
+├── benchmark/            # benchmark runner and reports
+├── docs/                 # supporting documentation
+├── web/                  # frontend
+├── server/               # backend/service layer
+├── scripts/              # helper and CI scripts
+├── artifacts/            # generated runtime artifacts
+└── metircs/              # benchmark and design metrics
+```
+
+Key files:
 
----
+- [README.md](/home/vickynishad/AgentIC/README.md)
+- [main.py](/home/vickynishad/AgentIC/main.py)
+- [cli.py](/home/vickynishad/AgentIC/src/agentic/cli.py)
+- [orchestrator.py](/home/vickynishad/AgentIC/src/agentic/orchestrator.py)
+- [vlsi_tools.py](/home/vickynishad/AgentIC/src/agentic/tools/vlsi_tools.py)
+- [USER_GUIDE.md](/home/vickynishad/AgentIC/docs/USER_GUIDE.md)
 
-## Getting Started
+## Installation
 
 ### Prerequisites
 
-```bash
-# Core
-Python 3.10+, Verilator 5.x, Icarus Verilog (iverilog + vvp)
+Minimum verification flow:
+
+```text
+Python 3.10+
+Verilator 5.x
+Icarus Verilog
+Yosys / SymbiYosys via oss-cad-suite
+```
 
-# Formal verification
-oss-cad-suite  — provides sby, yosys, eqy
+Optional physical flow:
 
-# Physical implementation (optional, skip with --skip-openlane)
-OpenLane + Docker
+```text
+OpenLane
+Docker
+Installed PDK (for example sky130 or gf180)
 ```
 
-### Install
+### Setup
 
 ```bash
 git clone https://github.com/Vickyrrrrrr/AgentIC.git
 cd AgentIC
-python3 -m venv .venv && source .venv/bin/activate
+python3 -m venv .venv
+source .venv/bin/activate
 pip install -r requirements.txt
 ```
 
-### Configure `.env`
+### Environment
+
+Typical `.env` values:
 
 ```bash
-# LLM backend — cloud
 NVIDIA_API_KEY="your-key-here"
-
-# LLM backend — local
 LLM_BASE_URL="http://localhost:11434"
-
-# Physical flow roots (only needed for --full-signoff builds)
 OPENLANE_ROOT="/path/to/OpenLane"
 PDK_ROOT="/path/to/pdk"
 ```
 
----
+See [USER_GUIDE.md](/home/vickynishad/AgentIC/docs/USER_GUIDE.md) for model backend selection details.
+
+## CLI Usage
+
+All commands are invoked through `main.py`.
 
-## CLI Reference
+### Build
+
+Fast RTL and verification flow:
 
 ```bash
-# Functional verification only — fast, no physical tools needed
 python3 main.py build \
   --name my_design \
   --desc "32-bit APB timer with interrupt" \
   --skip-openlane
+```
+
+Full flow with signoff-oriented stages:
 
-# Full build through physical signoff
+```bash
 python3 main.py build \
   --name my_design \
   --desc "32-bit APB timer with interrupt" \
   --full-signoff \
   --pdk-profile sky130
+```
 
-# Exploration mode — relaxed gates
+Skip coverage while still continuing from formal to regression:
+
+```bash
 python3 main.py build \
   --name my_design \
-  --desc "32-bit APB timer with interrupt" \
+  --desc "UART transmitter with programmable baud divisor" \
   --skip-openlane \
-  --no-strict-gates
+  --skip-coverage
 ```
 
-### All build flags
-
-```
---strict-gates / --no-strict-gates   Enforce all quality gates (default: strict)
---skip-openlane                      Stop after formal/coverage signoff
---pdk-profile {sky130, gf180}        Target PDK (default: sky130)
---full-signoff                       Run full DRC/LVS/STA/Power/LEC suite
---max-retries N                      Per-stage LLM repair budget
---min-coverage N                     Coverage closure threshold (%)
---max-pivots N                       Physical flow strategy pivot limit
---congestion-threshold FLOAT         Routing congestion abort threshold
---hierarchical {auto, off, on}       Hierarchical flow mode
+Important build flags:
+
+```text
+--skip-openlane
+--skip-coverage
+--full-signoff
+--strict-gates / --no-strict-gates
+--min-coverage
+--max-retries
+--max-pivots
+--pdk-profile {sky130,gf180}
+--hierarchical {auto,off,on}
+--congestion-threshold
 ```
 
----
+### Other Commands
+
+```bash
+python3 main.py simulate --name <design>
+python3 main.py harden --name <design>
+python3 main.py verify <design>
+```
 
 ## Generated Artifacts
 
-Every completed build produces a full artifact set:
+A typical design directory contains:
 
-```
+```text
 designs/<name>/
 ├── src/
-│   ├── <name>.v              # Production RTL
-│   ├── <name>_tb.v           # Verified testbench
-│   ├── <name>_sva.sv         # SVA property suite
-│   └── <name>.sdc            # Timing constraints
+│   ├── <name>.v
+│   ├── <name>_tb.v
+│   ├── <name>_sva.sv
+│   ├── *_formal_result.json
+│   ├── *_coverage_result.json
+│   └── *.vcd
 ├── formal/
-│   └── <name>.sby            # SymbiYosys config + results
-├── <name>.eqy                # Equivalence check config
-├── <name>_eco_patch.tcl      # ECO patch (when signoff required it)
-├── config.tcl                # OpenLane configuration
-├── macro_placement.tcl       # Floorplan
-└── ip_manifest.json          # IP declaration manifest
-
-metircs/<name>/
-├── latest.json               # Machine-readable benchmark snapshot
-└── latest.md                 # Human-readable signoff report
+├── config.tcl
+├── macro_placement.tcl
+└── ip_manifest.json
 ```
 
----
+Design-local `src/` is intended to keep permanent, human-useful artifacts. Tool intermediates such as Verilator build trees, compiled simulators, `.sby` working directories, coverage work products, and Yosys scratch outputs are staged in temporary directories and cleaned automatically.
 
-## CI
+## Benchmarking
 
-```bash
-# PR gate — syntax + unit tests (fast, ~2 min)
-bash scripts/ci/smoke.sh
+The repository includes a benchmark runner for multi-design evaluation:
 
-# Nightly — full build + signoff
-bash scripts/ci/nightly_full.sh
+```bash
+python3 benchmark/run_benchmark.py --design counter8 --attempts 1 --skip-openlane
 ```
 
-Workflow definition: `.github/workflows/ci.yml`
+Generated summaries live under [benchmark/results](/home/vickynishad/AgentIC/benchmark/results).
 
----
+Benchmarking matters here because repeated failures usually point to pipeline issues, validation gaps, or repair-routing problems. Those failures are used to improve the system over time.
 
-## Supported PDKs
+## Web Interface
 
-| PDK | Process Node | Status |
-|-----|-------------|--------|
-| SkyWater Sky130 | 130 nm | Production |
-| GlobalFoundries GF180MCU | 180 nm | Production |
+AgentIC includes a frontend and backend for interactive execution and live streaming of pipeline events. The UI is useful when you want:
 
----
+- stage-by-stage visibility
+- human approval gates
+- real-time log streaming
+- artifact inspection during a build
 
-## Practical Scope
+Frontend and service code:
 
-AgentIC is designed for **OSS PDK prototype tape-out and research-grade autonomous hardware design**. It is not a replacement for a certified commercial foundry sign-off flow. ECO and hierarchical flows produce concrete, functional artifacts but are not tuned for production process corners.
+- [web](/home/vickynishad/AgentIC/web)
+- [server](/home/vickynishad/AgentIC/server)
 
----
+## Scope And Limits
 
-<div align="center">
+AgentIC is aimed at autonomous digital design exploration, verification-heavy iteration, and open-source PDK implementation flows. It is not yet a replacement for a certified commercial signoff stack or a production ASIC team with foundry-qualified internal methodology.
 
-## Design Philosophy
+Practical implications:
 
-<br/>
+- benchmark pass rate still matters more than demo quality
+- hierarchical repair is harder than single-module repair and is treated explicitly
+- formal and coverage stages are valuable, but must be routed correctly to be useful
+- "industry-grade" here means constrained, diagnosable, replayable, and fail-closed
 
-> *The system is only as trustworthy as its most lenient gate.*
->
-> Every component is designed to fail loudly, repair precisely,
-> and proceed only when correctness is demonstrated — not assumed.
+## Design Principles
 
-<br/>
+The project is built around a small number of non-negotiable rules:
 
-| Principle | What It Means in Practice |
-|-----------|--------------------------|
-| **Fail closed** | No stage silently degrades quality |
-| **Minimum diff** | Repairs change the least possible — intent is preserved |
-| **Bounded loops** | Every retry has a hard budget |
-| **Determinism first** | Machine-precise fixes are always attempted before LLM fixes |
-| **Evidence-driven** | Every diagnosis cites signal names and line numbers — never guesses |
+- fail closed
+- prefer deterministic fixes before LLM fixes
+- preserve design intent with minimum-diff repair
+- validate every generated artifact before downstream use
+- treat routing bugs as seriously as model bugs
+- turn observed benchmark failures into regression tests
 
-</div>
+## IP Note
 
----
+This README describes capabilities and workflow at a high level. It does not document the internal prompt architecture, private heuristics, decision policies, or proprietary reasoning logic used inside the system.
 
 ## License
 
-**Proprietary and Confidential.**
+Proprietary and Confidential.
 
 Copyright © 2026 Vicky Nishad. All rights reserved.
 
-This software, its architecture, algorithms, agent designs, internal logic, prompt methodologies, repair heuristics, and all associated intellectual property are the exclusive property of the author. No part of this system — in whole or in part — may be reproduced, decompiled, reverse-engineered, distributed, sublicensed, or used in any derivative work without explicit written permission from the copyright holder.
-
-Unauthorised use is a violation of applicable intellectual property law.
-
----
-
-<div align="center">
-
-<br/>
-
-![](https://img.shields.io/badge/Built%20with%20intention-C9643E?style=for-the-badge&labelColor=1C1A17)
-![](https://img.shields.io/badge/Designed%20to%20last-C9643E?style=for-the-badge&labelColor=1C1A17)
-
-<br/>
-
-*AgentIC — from words to wafers.*
-
-<br/>
-
-</div>
+This repository, including its architecture, algorithms, prompts, agent logic, repair heuristics, and associated intellectual property, may not be reproduced, distributed, reverse-engineered, or used in derivative works without explicit written permission.

server/api.py

@@ -199,6 +199,7 @@ class BuildRequest(BaseModel):
     design_name: str
     description: str
     skip_openlane: bool = False
+    skip_coverage: bool = False
     full_signoff: bool = False
     max_retries: int = 5
     show_thinking: bool = False
@@ -309,6 +310,7 @@ def _run_agentic_build(job_id: str, req: BuildRequest):
             max_retries=req.max_retries,
             verbose=req.show_thinking,
             skip_openlane=req.skip_openlane,
+            skip_coverage=req.skip_coverage,
             full_signoff=req.full_signoff,
             min_coverage=req.min_coverage,
             strict_gates=req.strict_gates,
@@ -554,15 +556,12 @@ def _run_with_approval_gates(job_id: str, orchestrator, req, llm):
                 
                 if not approved:
                     # User rejected — loop back to retry the CURRENT state
-                    # (which is now new_state after transition)
-                    # Actually, set state back to the stage that just completed so it retries
+                    # Reset state back to the completed stage so the next loop iteration
+                    # actually reruns it with the stored rejection feedback.
                     _emit_agent_thought(job_id, "Orchestrator", "decision", 
                         f"Stage {completed_stage} rejected by user. Retrying...", 
                         new_state.name)
-                    # The state already transitioned. If rejected, we need to figure out
-                    # what to do. For most stages, retrying means going back.
-                    # However, the rejection feedback was already stored and will be
-                    # picked up at the top of the next iteration.
+                    orchestrator.state = prev_state
                     continue
             else:
                 # State didn't change — this can happen for retry loops within a stage
@@ -809,6 +808,7 @@ def get_build_options_contract():
                     {"key": "strict_gates", "type": "boolean", "default": True, "description": "Enable strict gate enforcement with bounded self-healing."},
                     {"key": "full_signoff", "type": "boolean", "default": False, "description": "Run full physical signoff checks when available."},
                     {"key": "skip_openlane", "type": "boolean", "default": False, "description": "Skip physical implementation stages for faster RTL-only iteration."},
+                    {"key": "skip_coverage", "type": "boolean", "default": False, "description": "Skip the coverage stage and continue from formal verification to regression."},
                     {"key": "max_retries", "type": "int", "default": 5, "min": 1, "max": 12, "description": "Max repair retries per stage."},
                 ],
             },

src/agentic/cli.py

@@ -438,6 +438,7 @@ def build(
     desc: str = typer.Option(..., "--desc", "-d", help="Natural language description"),
     max_retries: int = typer.Option(5, "--max-retries", "-r", min=0, help="Max auto-fix retries for RTL/TB/sim failures"),
     skip_openlane: bool = typer.Option(False, "--skip-openlane", help="Stop after simulation (no RTL→GDSII hardening)"),
+    skip_coverage: bool = typer.Option(False, "--skip-coverage", help="Bypass COVERAGE_CHECK and continue from formal verification to regression"),
     show_thinking: bool = typer.Option(False, "--show-thinking", help="Print DeepSeek <think> reasoning for each generation/fix step"),
     full_signoff: bool = typer.Option(False, "--full-signoff", help="Run full industry signoff (formal + coverage + regression + DRC/LVS)"),
     min_coverage: float = typer.Option(80.0, "--min-coverage", help="Minimum line coverage percentage to pass verification"),
@@ -496,6 +497,7 @@ def build(
         max_retries=max_retries,
         verbose=show_thinking,
         skip_openlane=skip_openlane,
+        skip_coverage=skip_coverage,
         full_signoff=full_signoff,
         min_coverage=min_coverage,
         strict_gates=strict_gates,

src/agentic/orchestrator.py

@@ -10,7 +10,7 @@ import difflib
 import subprocess
 import threading
 from dataclasses import dataclass, asdict
-from typing import Optional, Dict, Any, List
+from typing import Optional, Dict, Any, List, Tuple
 from rich.console import Console
 from rich.panel import Panel
 from crewai import Agent, Task, Crew, LLM
@@ -34,6 +34,18 @@ from .agents.verifier import get_verification_agent, get_error_analyst_agent, ge
 from .agents.doc_agent import get_doc_agent
 from .agents.sdc_agent import get_sdc_agent
 from .core import ArchitectModule, SelfReflectPipeline, ReActAgent, WaveformExpertModule, DeepDebuggerModule
+from .contracts import (
+    AgentResult,
+    ArtifactRef,
+    FailureClass,
+    FailureRecord,
+    StageResult,
+    StageStatus,
+    extract_json_object,
+    infer_failure_class,
+    materially_changed,
+    validate_agent_payload,
+)
 from .tools.vlsi_tools import (
     write_verilog,
     run_syntax_check,
@@ -157,6 +169,7 @@ class BuildOrchestrator:
         max_retries: int = 5,
         verbose: bool = True,
         skip_openlane: bool = False,
+        skip_coverage: bool = False,
         full_signoff: bool = False,
         min_coverage: float = 80.0,
         strict_gates: bool = True,
@@ -182,6 +195,7 @@ class BuildOrchestrator:
         self.max_retries = max_retries
         self.verbose = verbose
         self.skip_openlane = skip_openlane
+        self.skip_coverage = skip_coverage
         self.full_signoff = full_signoff
         self.min_coverage = min_coverage
         self.strict_gates = strict_gates
@@ -230,6 +244,14 @@ class BuildOrchestrator:
         self.tb_failure_fingerprint_history: Dict[str, int] = {}
         self.tb_recovery_counts: Dict[str, int] = {}
         self.artifacts: Dict[str, Any] = {}  # Store paths to gathered files
+        self.artifact_bus: Dict[str, ArtifactRef] = {}
+        self.stage_contract_history: List[Dict[str, Any]] = []
+        self.retry_metadata: Dict[str, int] = {
+            "stage_retry": 0,
+            "regeneration_retry": 0,
+            "format_retry": 0,
+            "infrastructure_retry": 0,
+        }
         self.history: List[Dict[str, Any]] = []    # Log of state transitions and errors
         self.errors: List[str] = []     # List of error messages
 
@@ -283,6 +305,7 @@ class BuildOrchestrator:
         self.log(f"Transitioning: {self.state.name} -> {new_state.name}", refined=True)
         self.state = new_state
         if not preserve_retries:
+            self.retry_count = 0
             self.state_retry_counts[new_state.name] = 0
         # Emit a dedicated transition event for the web UI checkpoint timeline
         if self.event_sink is not None:
@@ -348,6 +371,308 @@ class BuildOrchestrator:
         fp = hashlib.sha256(base.encode("utf-8", errors="ignore")).hexdigest()
         self.failure_fingerprint_history.pop(fp, None)
 
+    def _set_artifact(
+        self,
+        key: str,
+        value: Any,
+        *,
+        producer: str,
+        consumer: str = "",
+        required: bool = False,
+        blocking: bool = False,
+    ) -> None:
+        self.artifacts[key] = value
+        self.artifact_bus[key] = ArtifactRef(
+            key=key,
+            producer=producer,
+            consumer=consumer,
+            required=required,
+            blocking=blocking,
+            value=value,
+        )
+
+    def _get_artifact(self, key: str, default: Any = None) -> Any:
+        return self.artifacts.get(key, default)
+
+    def _require_artifact(self, key: str, *, consumer: str, message: str) -> Any:
+        if key in self.artifacts and self.artifacts[key] not in (None, "", {}):
+            ref = self.artifact_bus.get(key)
+            if ref is not None:
+                ref.consumer = consumer
+            return self.artifacts[key]
+        self._record_stage_contract(
+            StageResult(
+                stage=self.state.name,
+                status=StageStatus.ERROR,
+                producer=consumer,
+                failure_class=FailureClass.ORCHESTRATOR_ROUTING_ERROR,
+                diagnostics=[message],
+                next_action="fail_closed",
+            )
+        )
+        raise RuntimeError(message)
+
+    def _consume_handoff(self, key: str, *, consumer: str, required: bool = False) -> Any:
+        value = self.artifacts.get(key)
+        if value in (None, "", {}):
+            if required:
+                msg = f"Missing artifact handoff '{key}' for {consumer}."
+                self._record_stage_contract(
+                    StageResult(
+                        stage=self.state.name,
+                        status=StageStatus.ERROR,
+                        producer=consumer,
+                        failure_class=FailureClass.ORCHESTRATOR_ROUTING_ERROR,
+                        diagnostics=[msg],
+                        next_action="fail_closed",
+                    )
+                )
+                raise RuntimeError(msg)
+            return None
+        ref = self.artifact_bus.get(key)
+        if ref is not None:
+            ref.consumer = consumer
+        return value
+
+    def _record_stage_contract(self, result: StageResult) -> None:
+        payload = result.to_dict()
+        self.stage_contract_history.append(payload)
+        self.artifacts["last_stage_result"] = payload
+        if hasattr(self, "logger"):
+            self.logger.info(f"STAGE RESULT:\n{json.dumps(payload, indent=2, default=str)}")
+
+    def _record_retry(self, bucket: str, *, consume_global: bool = False) -> int:
+        count = int(self.retry_metadata.get(bucket, 0)) + 1
+        self.retry_metadata[bucket] = count
+        self.artifacts["retry_metadata"] = dict(self.retry_metadata)
+        if consume_global:
+            self.global_retry_count += 1
+        return count
+
+    def _record_non_consumable_output(self, producer: str, raw_output: str, diagnostics: List[str]) -> None:
+        self._record_retry("format_retry", consume_global=False)
+        self._record_stage_contract(
+            StageResult(
+                stage=self.state.name,
+                status=StageStatus.RETRY,
+                producer=producer,
+                failure_class=FailureClass.LLM_FORMAT_ERROR,
+                diagnostics=diagnostics or ["LLM output could not be consumed."],
+                next_action="retry_generation",
+            )
+        )
+        self._set_artifact(
+            "last_non_consumable_output",
+            {
+                "producer": producer,
+                "raw_output": raw_output[:4000],
+                "diagnostics": diagnostics,
+            },
+            producer=producer,
+            consumer=self.state.name,
+            required=False,
+            blocking=False,
+        )
+
+    @staticmethod
+    def _extract_module_names(code: str) -> List[str]:
+        return re.findall(r"\bmodule\s+([A-Za-z_]\w*)", code or "")
+
+    def _is_hierarchical_design(self, code: str) -> bool:
+        return len(self._extract_module_names(code)) > 1
+
+    def _validate_rtl_candidate(self, candidate_code: str, previous_code: str) -> List[str]:
+        issues: List[str] = []
+        if not validate_llm_code_output(candidate_code):
+            issues.append("RTL candidate is not valid Verilog/SystemVerilog code output.")
+            return issues
+        modules = self._extract_module_names(candidate_code)
+        if self.name not in modules:
+            issues.append(f"RTL candidate is missing top module '{self.name}'.")
+        prev_modules = self._extract_module_names(previous_code)
+        if prev_modules and len(prev_modules) > 1:
+            if sorted(prev_modules) != sorted(modules):
+                issues.append(
+                    "Hierarchical RTL repair changed the module inventory; module-scoped preservation failed."
+                )
+        prev_ports = self._extract_module_interface(previous_code)
+        new_ports = self._extract_module_interface(candidate_code)
+        if prev_ports and new_ports and prev_ports != new_ports:
+            issues.append("RTL candidate changed the top-module interface.")
+        return issues
+
+    def _validate_tb_candidate(self, tb_code: str) -> List[str]:
+        issues: List[str] = []
+        if not validate_llm_code_output(tb_code):
+            issues.append("TB candidate is not valid Verilog/SystemVerilog code output.")
+            return issues
+        module_match = re.search(r"\bmodule\s+([A-Za-z_]\w*)", tb_code)
+        if not module_match or module_match.group(1) != f"{self.name}_tb":
+            issues.append(f"TB module name must be '{self.name}_tb'.")
+        if f'$dumpfile("{self.name}_wave.vcd")' not in tb_code:
+            issues.append("TB candidate is missing the required VCD dumpfile block.")
+        if "$dumpvars(0," not in tb_code:
+            issues.append("TB candidate is missing the required dumpvars block.")
+        if "TEST PASSED" not in tb_code or "TEST FAILED" not in tb_code:
+            issues.append("TB candidate must include TEST PASSED and TEST FAILED markers.")
+        return issues
+
+    def _validate_sva_candidate(self, sva_code: str, rtl_code: str) -> List[str]:
+        issues: List[str] = []
+        if not validate_llm_code_output(sva_code):
+            issues.append("SVA candidate is not valid SystemVerilog code output.")
+            return issues
+        if f"module {self.name}_sva" not in sva_code:
+            issues.append(f"SVA candidate is missing module '{self.name}_sva'.")
+        yosys_code = convert_sva_to_yosys(sva_code, self.name)
+        if not yosys_code:
+            issues.append("SVA candidate could not be translated to Yosys-compatible assertions.")
+            return issues
+        ok, report = validate_yosys_sby_check(yosys_code)
+        if not ok:
+            for issue in report.get("issues", []):
+                issues.append(issue.get("message", "Invalid Yosys preflight assertion output."))
+        signal_inventory = self._format_signal_inventory_for_prompt(rtl_code)
+        if "No signal inventory could be extracted" in signal_inventory:
+            issues.append("RTL signal inventory is unavailable for SVA validation.")
+        return issues
+
+    @staticmethod
+    def _simulation_capabilities(sim_output: str, vcd_path: str) -> Dict[str, Any]:
+        trace_enabled = "without --trace" not in (sim_output or "")
+        waveform_generated = bool(vcd_path and os.path.exists(vcd_path) and os.path.getsize(vcd_path) > 200)
+        return {
+            "trace_enabled": trace_enabled,
+            "waveform_generated": waveform_generated,
+        }
+
+    def _normalize_react_result(self, trace: Any) -> AgentResult:
+        final_answer = getattr(trace, "final_answer", "") or ""
+        code_match = re.search(r"```verilog\s*(.*?)```", final_answer, re.DOTALL)
+        payload = {
+            "code": code_match.group(1).strip() if code_match else "",
+            "self_check_status": "verified" if getattr(trace, "success", False) else "unverified",
+            "tool_observations": [getattr(step, "observation", "") for step in getattr(trace, "steps", []) if getattr(step, "observation", "")],
+            "final_decision": "accept" if code_match else "fallback",
+        }
+        failure_class = FailureClass.UNKNOWN if code_match else FailureClass.LLM_FORMAT_ERROR
+        return AgentResult(
+            agent="ReAct",
+            ok=bool(code_match),
+            producer="agent_react",
+            payload=payload,
+            diagnostics=[] if code_match else ["ReAct did not return fenced Verilog code."],
+            failure_class=failure_class,
+            raw_output=final_answer,
+        )
+
+    def _normalize_waveform_result(self, diagnosis: Any, raw_output: str = "") -> AgentResult:
+        if diagnosis is None:
+            return AgentResult(
+                agent="WaveformExpert",
+                ok=False,
+                producer="agent_waveform",
+                payload={"fallback_reason": "No waveform diagnosis available."},
+                diagnostics=["WaveformExpert returned no diagnosis."],
+                failure_class=FailureClass.UNKNOWN,
+                raw_output=raw_output,
+            )
+        payload = {
+            "failing_signal": diagnosis.failing_signal,
+            "mismatch_time": diagnosis.mismatch_time,
+            "expected_value": diagnosis.expected_value,
+            "actual_value": diagnosis.actual_value,
+            "trace_roots": [
+                {
+                    "signal_name": trace.signal_name,
+                    "source_file": trace.source_file,
+                    "source_line": trace.source_line,
+                    "assignment_type": trace.assignment_type,
+                }
+                for trace in diagnosis.root_cause_traces
+            ],
+            "suggested_fix_area": diagnosis.suggested_fix_area,
+            "fallback_reason": "" if diagnosis.root_cause_traces else "No AST trace roots found.",
+        }
+        return AgentResult(
+            agent="WaveformExpert",
+            ok=True,
+            producer="agent_waveform",
+            payload=payload,
+            diagnostics=[],
+            failure_class=FailureClass.UNKNOWN,
+            raw_output=raw_output,
+        )
+
+    def _normalize_deepdebug_result(self, verdict: Any, raw_output: str = "") -> AgentResult:
+        if verdict is None:
+            return AgentResult(
+                agent="DeepDebugger",
+                ok=False,
+                producer="agent_deepdebug",
+                payload={"usable_for_regeneration": False},
+                diagnostics=["DeepDebugger returned no verdict."],
+                failure_class=FailureClass.UNKNOWN,
+                raw_output=raw_output,
+            )
+        payload = {
+            "root_cause_signal": verdict.root_cause_signal,
+            "root_cause_line": verdict.root_cause_line,
+            "root_cause_file": verdict.root_cause_file,
+            "fix_description": verdict.fix_description,
+            "confidence": verdict.confidence,
+            "balanced_analysis_log": verdict.balanced_analysis_log,
+            "usable_for_regeneration": bool(verdict.root_cause_signal and verdict.fix_description),
+        }
+        return AgentResult(
+            agent="DeepDebugger",
+            ok=True,
+            producer="agent_deepdebug",
+            payload=payload,
+            diagnostics=[],
+            failure_class=FailureClass.UNKNOWN,
+            raw_output=raw_output,
+        )
+
+    def _parse_structured_agent_json(
+        self,
+        *,
+        agent_name: str,
+        raw_output: str,
+        required_keys: List[str],
+    ) -> AgentResult:
+        payload = extract_json_object(raw_output)
+        if payload is None:
+            return AgentResult(
+                agent=agent_name,
+                ok=False,
+                producer=f"agent_{agent_name.lower()}",
+                payload={},
+                diagnostics=["LLM output is not valid JSON."],
+                failure_class=FailureClass.LLM_FORMAT_ERROR,
+                raw_output=raw_output,
+            )
+        errors = validate_agent_payload(payload, required_keys)
+        if errors:
+            return AgentResult(
+                agent=agent_name,
+                ok=False,
+                producer=f"agent_{agent_name.lower()}",
+                payload=payload,
+                diagnostics=errors,
+                failure_class=FailureClass.LLM_FORMAT_ERROR,
+                raw_output=raw_output,
+            )
+        return AgentResult(
+            agent=agent_name,
+            ok=True,
+            producer=f"agent_{agent_name.lower()}",
+            payload=payload,
+            diagnostics=[],
+            failure_class=FailureClass.UNKNOWN,
+            raw_output=raw_output,
+        )
+
     def _build_llm_context(self, include_rtl: bool = True, max_rtl_chars: int = 15000) -> str:
         """Build cumulative context string for LLM calls.
 
@@ -823,6 +1148,97 @@ SPECIFICATION SECTIONS (Markdown):
             )
         return ports
 
+    @staticmethod
+    def _extract_rtl_signal_inventory(rtl_code: str) -> List[Dict[str, str]]:
+        """Extract DUT-visible signals and widths for downstream prompt grounding."""
+        text = rtl_code or ""
+        signals: List[Dict[str, str]] = []
+
+        param_defaults: Dict[str, str] = {}
+        param_pattern = re.compile(
+            r"parameter\s+(?:\w+\s+)?([A-Za-z_]\w*)\s*=\s*([^,;\)\n]+)",
+            re.IGNORECASE,
+        )
+        for pname, pval in param_pattern.findall(text):
+            param_defaults[pname.strip()] = pval.strip()
+
+        def _resolve_width(width: str) -> str:
+            resolved = (width or "").strip()
+            if not resolved:
+                return "[0:0]"
+            for pname, pval in param_defaults.items():
+                if pname not in resolved:
+                    continue
+                try:
+                    expr = resolved[1:-1]
+                    expr = expr.replace(pname, str(pval))
+                    parts = expr.split(":")
+                    evaluated = []
+                    for part in parts:
+                        part = part.strip()
+                        if re.match(r'^[\d\s\+\-\*\/\(\)]+$', part):
+                            evaluated.append(str(int(eval(part))))  # noqa: S307
+                        else:
+                            evaluated.append(part)
+                    resolved = f"[{':'.join(evaluated)}]"
+                except Exception:
+                    pass
+            return resolved
+
+        seen = set()
+        for port in BuildOrchestrator._extract_module_ports(text):
+            key = (port["name"], port["direction"])
+            if key in seen:
+                continue
+            seen.add(key)
+            signals.append(
+                {
+                    "name": port["name"],
+                    "category": port["direction"],
+                    "width": _resolve_width(port.get("width", "")),
+                }
+            )
+
+        scrubbed = re.sub(r"//.*", "", text)
+        scrubbed = re.sub(r"/\*[\s\S]*?\*/", "", scrubbed)
+        internal_pattern = re.compile(
+            r"^\s*(wire|reg|logic)\s*(?:signed\s+)?(\[[^\]]+\])?\s*([^;]+);",
+            re.IGNORECASE | re.MULTILINE,
+        )
+        for kind, width, names_blob in internal_pattern.findall(scrubbed):
+            resolved_width = _resolve_width(width)
+            for raw_name in names_blob.split(","):
+                candidate = raw_name.strip()
+                if not candidate:
+                    continue
+                candidate = candidate.split("=")[0].strip()
+                candidate = re.sub(r"\[[^\]]+\]", "", candidate).strip()
+                if not re.fullmatch(r"[A-Za-z_]\w*", candidate):
+                    continue
+                key = (candidate, kind.lower())
+                if key in seen:
+                    continue
+                seen.add(key)
+                signals.append(
+                    {
+                        "name": candidate,
+                        "category": kind.lower(),
+                        "width": resolved_width,
+                    }
+                )
+        return signals
+
+    @staticmethod
+    def _format_signal_inventory_for_prompt(rtl_code: str) -> str:
+        signals = BuildOrchestrator._extract_rtl_signal_inventory(rtl_code)
+        if not signals:
+            return "No signal inventory could be extracted from the RTL. Use only identifiers explicitly declared in the RTL."
+        lines = [
+            f"- {sig['name']}: category={sig['category']}, width={sig['width']}"
+            for sig in signals
+        ]
+        return "\n".join(lines)
+
     def _tb_gate_strict_enforced(self) -> bool:
         return self.strict_gates or self.tb_gate_mode == "strict"
 
@@ -1089,7 +1505,14 @@ SPECIFICATION SECTIONS (Markdown):
             return
 
         if cycle == 2:
-            self.artifacts["tb_regen_context"] = json.dumps(report, indent=2, default=str)[:5000]
+            self._set_artifact(
+                "tb_regen_context",
+                json.dumps(report, indent=2, default=str)[:5000],
+                producer="orchestrator_tb_gate",
+                consumer="VERIFICATION",
+                required=True,
+                blocking=True,
+            )
             tb_path = self.artifacts.get("tb_path")
             if tb_path and os.path.exists(tb_path):
                 try:
@@ -1763,41 +2186,69 @@ ALWAYS return the COMPLETE code in ```verilog``` fences.
                 self.logger.info(f"SEMANTIC RIGOR: {sem_report}")
                 if not sem_ok:
                     if self.strict_gates:
-                        # --- Mechanical width auto-fix (no LLM) ---
-                        self.log("Semantic rigor gate failed. Attempting mechanical width auto-fix.", refined=True)
-                        fix_ok, fix_report = auto_fix_width_warnings(path)
-                        self.logger.info(f"WIDTH AUTO-FIX: fixed={fix_report.get('fixed_count', 0)}, "
-                                         f"remaining={fix_report.get('remaining_count', 0)}")
-                        if fix_ok:
-                            self.log(f"Width auto-fix resolved all {fix_report['fixed_count']} warnings.", refined=True)
-                            # Re-read the patched RTL into artifacts
-                            with open(path, 'r') as f:
-                                self.artifacts['rtl_code'] = f.read()
-                            # Loop back to re-check syntax/lint on the patched file
-                            return
-                        elif fix_report.get("fixed_count", 0) > 0:
-                            self.log(f"Width auto-fix resolved {fix_report['fixed_count']} warnings; "
-                                     f"{fix_report['remaining_count']} remain. Re-checking.", refined=True)
-                            with open(path, 'r') as f:
-                                self.artifacts['rtl_code'] = f.read()
-                            # Loop back — the remaining warnings may resolve after re-lint
-                            return
-                        # Post-processor couldn't fix anything — fall through to LLM
-                        self.log("Mechanical auto-fix could not resolve width warnings. Routing to LLM fixer.", refined=True)
-                        # If the post-processor gathered rich context for unfixable warnings,
-                        # build a detailed prompt giving the LLM everything it needs.
-                        unfixable = fix_report.get("unfixable_context", [])
-                        if unfixable:
-                            errors = self._format_unfixable_width_errors(unfixable)
-                        else:
+                        width_issues = sem_report.get("width_issues", []) if isinstance(sem_report, dict) else []
+                        if not width_issues:
+                            self.log(
+                                "Semantic rigor failed on non-width issues. Routing directly to LLM fixer.",
+                                refined=True,
+                            )
                             errors = self._format_semantic_rigor_errors(sem_report)
+                        else:
+                            # --- Mechanical width auto-fix (no LLM) ---
+                            self.log("Semantic rigor gate failed. Attempting mechanical width auto-fix.", refined=True)
+                            fix_ok, fix_report = auto_fix_width_warnings(path)
+                            self.logger.info(f"WIDTH AUTO-FIX: fixed={fix_report.get('fixed_count', 0)}, "
+                                             f"remaining={fix_report.get('remaining_count', 0)}")
+                            if fix_ok:
+                                self.log(f"Width auto-fix resolved all {fix_report['fixed_count']} warnings.", refined=True)
+                                # Re-read the patched RTL into artifacts
+                                with open(path, 'r') as f:
+                                    self.artifacts['rtl_code'] = f.read()
+                                # Loop back to re-check syntax/lint on the patched file
+                                return
+                            elif fix_report.get("fixed_count", 0) > 0:
+                                self.log(f"Width auto-fix resolved {fix_report['fixed_count']} warnings; "
+                                         f"{fix_report['remaining_count']} remain. Re-checking.", refined=True)
+                                with open(path, 'r') as f:
+                                    self.artifacts['rtl_code'] = f.read()
+                                # Loop back — the remaining warnings may resolve after re-lint
+                                return
+                            # Post-processor couldn't fix anything — fall through to LLM
+                            self.log("Mechanical auto-fix could not resolve width warnings. Routing to LLM fixer.", refined=True)
+                            # If the post-processor gathered rich context for unfixable warnings,
+                            # build a detailed prompt giving the LLM everything it needs.
+                            unfixable = fix_report.get("unfixable_context", [])
+                            if unfixable:
+                                errors = self._format_unfixable_width_errors(unfixable)
+                            else:
+                                errors = self._format_semantic_rigor_errors(sem_report)
                     else:
                         self.log("Semantic rigor warnings detected (non-blocking).", refined=True)
                         self.artifacts["semantic_report"] = sem_report
+                        self._record_stage_contract(
+                            StageResult(
+                                stage=self.state.name,
+                                status=StageStatus.PASS,
+                                producer="orchestrator_rtl_fix",
+                                consumable_payload={"semantic_report": bool(sem_report)},
+                                artifacts_written=["semantic_report"],
+                                next_action=BuildState.VERIFICATION.name,
+                            )
+                        )
                         self.transition(BuildState.VERIFICATION)
                         return
                 else:
                     self.artifacts["semantic_report"] = sem_report
+                    self._record_stage_contract(
+                        StageResult(
+                            stage=self.state.name,
+                            status=StageStatus.PASS,
+                            producer="orchestrator_rtl_fix",
+                            consumable_payload={"semantic_report": True},
+                            artifacts_written=["semantic_report"],
+                            next_action=BuildState.VERIFICATION.name,
+                        )
+                    )
                     self.transition(BuildState.VERIFICATION)
                     return
 
@@ -1868,15 +2319,31 @@ ALWAYS return the COMPLETE code in ```verilog``` fences.
                 ),
                 context=_react_context,
             )
-            if _react_trace.success and _react_trace.final_answer:
-                _vlog = re.search(r'```verilog\s*(.*?)```', _react_trace.final_answer, re.DOTALL)
-                if _vlog:
-                    _react_fixed_code = _vlog.group(1).strip()
-                    self.logger.info(
-                        f"[ReAct] RTL fix done in {_react_trace.total_steps} steps "
-                        f"({_react_trace.total_duration_s:.1f}s)"
-                    )
+            react_result = self._normalize_react_result(_react_trace)
+            self._set_artifact(
+                "react_last_result",
+                react_result.to_dict(),
+                producer="agent_react",
+                consumer="RTL_FIX",
+            )
+            if react_result.ok:
+                _react_fixed_code = react_result.payload.get("code", "")
+                self.logger.info(
+                    f"[ReAct] RTL fix done in {_react_trace.total_steps} steps "
+                    f"({_react_trace.total_duration_s:.1f}s)"
+                )
             if not _react_fixed_code:
+                self._record_stage_contract(
+                    StageResult(
+                        stage=self.state.name,
+                        status=StageStatus.RETRY,
+                        producer="agent_react",
+                        failure_class=react_result.failure_class,
+                        diagnostics=react_result.diagnostics,
+                        artifacts_written=["react_last_result"],
+                        next_action="fallback_to_single_shot",
+                    )
+                )
                 self.logger.info(
                     f"[ReAct] No valid code produced "
                     f"(success={_react_trace.success}, steps={_react_trace.total_steps}). "
@@ -1939,6 +2406,11 @@ You explain what you changed and why.""",
                     new_code = str(result)
                     # --- Universal code output validation (RTL fix) ---
                     if not validate_llm_code_output(new_code):
+                        self._record_non_consumable_output(
+                            "llm_rtl_fix",
+                            new_code,
+                            ["RTL fix returned prose instead of code."],
+                        )
                         self.log("RTL fix returned prose instead of code. Retrying once.", refined=True)
                         self.logger.warning(f"RTL FIX VALIDATION FAIL (prose detected):\n{new_code[:500]}")
                         new_code = str(Crew(agents=[fixer], tasks=[task]).kickoff())
@@ -1956,6 +2428,20 @@ You explain what you changed and why.""",
                     return
 
         self.logger.info(f"FIXED RTL:\n{new_code}")
+        rtl_validation_issues = self._validate_rtl_candidate(new_code, self.artifacts.get("rtl_code", ""))
+        if rtl_validation_issues:
+            self._record_stage_contract(
+                StageResult(
+                    stage=self.state.name,
+                    status=StageStatus.RETRY,
+                    producer="orchestrator_rtl_validator",
+                    failure_class=FailureClass.LLM_SEMANTIC_ERROR,
+                    diagnostics=rtl_validation_issues,
+                    next_action="retry_rtl_fix",
+                )
+            )
+            self.log(f"RTL candidate rejected: {rtl_validation_issues[0]}", refined=True)
+            return
         
         # --- Inner retry loop for LLM parse errors ---
         # If write_verilog fails (LLM didn't output valid code), re-prompt immediately
@@ -2021,10 +2507,11 @@ Original errors to fix:
         # 1. Generate Testbench (Only if missing)
         # We reuse existing TB to ensure consistent verification targets
         tb_exists = 'tb_path' in self.artifacts and os.path.exists(self.artifacts['tb_path'])
+        regen_context = self._consume_handoff("tb_regen_context", consumer="VERIFICATION", required=False) or ""
         
         if not tb_exists:
             # Check if we have a golden testbench from template matching
-            if self.artifacts.get('golden_tb'):
+            if self.artifacts.get('golden_tb') and not regen_context:
                 self.log("Using Golden Reference Testbench (pre-verified).", refined=True)
                 tb_code = self.artifacts['golden_tb']
                 # Replace template module name with actual design name
@@ -2040,7 +2527,6 @@ Original errors to fix:
                 tb_agent = get_testbench_agent(self.llm, f"Verify {self.name}", verbose=self.verbose, strategy=self.strategy.name)
                 
                 tb_strategy_prompt = self._get_tb_strategy_prompt()
-                regen_context = self.artifacts.pop("tb_regen_context", "")
                 
                 # --- Extract module port signature from RTL ---
                 # This prevents the most common TB failure: port name mismatches
@@ -2116,6 +2602,11 @@ Before returning any testbench code, mentally compile it with strict SystemVeril
                         )
                         # --- Universal code output validation (TB gen) ---
                         if not validate_llm_code_output(tb_code):
+                            self._record_non_consumable_output(
+                                "llm_tb_generation",
+                                tb_code,
+                                ["TB generation returned prose instead of code."],
+                            )
                             self.log("TB generation returned prose instead of code. Retrying once.", refined=True)
                             self.logger.warning(f"TB VALIDATION FAIL (prose detected):\n{tb_code[:500]}")
                             tb_code = self._kickoff_with_timeout(
@@ -2131,6 +2622,20 @@ Before returning any testbench code, mentally compile it with strict SystemVeril
                 if "module" not in tb_code or "endmodule" not in tb_code:
                     self.log("TB generation returned invalid code. Using deterministic fallback TB.", refined=True)
                     tb_code = self._deterministic_tb_fallback(self.artifacts.get("rtl_code", ""))
+                tb_validation_issues = self._validate_tb_candidate(tb_code)
+                if tb_validation_issues:
+                    self._record_stage_contract(
+                        StageResult(
+                            stage=self.state.name,
+                            status=StageStatus.RETRY,
+                            producer="orchestrator_tb_validator",
+                            failure_class=FailureClass.LLM_SEMANTIC_ERROR,
+                            diagnostics=tb_validation_issues,
+                            next_action="deterministic_tb_fallback",
+                        )
+                    )
+                    self.log(f"TB candidate rejected: {tb_validation_issues[0]}. Using deterministic fallback TB.", refined=True)
+                    tb_code = self._deterministic_tb_fallback(self.artifacts.get("rtl_code", ""))
                 self.logger.info(f"GENERATED TESTBENCH:\n{tb_code}")
                 
                 tb_path = write_verilog(self.name, tb_code, is_testbench=True)
@@ -2143,6 +2648,15 @@ Before returning any testbench code, mentally compile it with strict SystemVeril
                         self.state = BuildState.FAIL
                         return
                 self.artifacts['tb_path'] = tb_path
+                self._set_artifact(
+                    "tb_candidate",
+                    {
+                        "tb_path": tb_path,
+                        "regen_context_used": bool(regen_context),
+                    },
+                    producer="orchestrator_verification",
+                    consumer="VERIFICATION",
+                )
                 self._clear_tb_fingerprints()  # New TB → fresh gate attempts
         else:
             self.log(f"Verifying with existing Testbench (Attempt {self.retry_count}).", refined=True)
@@ -2284,11 +2798,8 @@ Before returning any testbench code, mentally compile it with strict SystemVeril
                 "rtl_path",
                 os.path.join(OPENLANE_ROOT, "designs", self.name, "src", f"{self.name}.v"),
             )
-            if (
-                os.path.exists(_vcd_path)
-                and os.path.getsize(_vcd_path) > 200
-                and os.path.exists(_rtl_path)
-            ):
+            sim_caps = self._simulation_capabilities(output, _vcd_path)
+            if sim_caps["trace_enabled"] and sim_caps["waveform_generated"] and os.path.exists(_rtl_path):
                 _waveform_mod = WaveformExpertModule()
                 _diagnosis = _waveform_mod.analyze_failure(
                     rtl_path=_rtl_path,
@@ -2296,6 +2807,13 @@ Before returning any testbench code, mentally compile it with strict SystemVeril
                     sim_log=output,          # 'output' is the sim stdout/stderr
                     design_name=self.name,
                 )
+                waveform_result = self._normalize_waveform_result(_diagnosis, output)
+                self._set_artifact(
+                    "waveform_diagnosis",
+                    waveform_result.to_dict(),
+                    producer="agent_waveform",
+                    consumer="VERIFICATION",
+                )
                 if _diagnosis is not None:
                     _waveform_context = (
                         f"\n\n## WAVEFORM + AST ANALYSIS\n"
@@ -2310,6 +2828,19 @@ Before returning any testbench code, mentally compile it with strict SystemVeril
                     self.logger.info("[WaveformExpert] No signal mismatch found in VCD")
             else:
                 _vcd_size = os.path.getsize(_vcd_path) if os.path.exists(_vcd_path) else 0
+                self._record_stage_contract(
+                    StageResult(
+                        stage=self.state.name,
+                        status=StageStatus.RETRY,
+                        producer="orchestrator_waveform_gate",
+                        failure_class=FailureClass.ORCHESTRATOR_ROUTING_ERROR,
+                        diagnostics=[
+                            f"WaveformExpert gated off: trace_enabled={sim_caps['trace_enabled']}, "
+                            f"waveform_generated={sim_caps['waveform_generated']}, rtl_exists={os.path.exists(_rtl_path)}"
+                        ],
+                        next_action="continue_without_waveform",
+                    )
+                )
                 self.logger.info(
                     f"[WaveformExpert] Skipping — VCD exists={os.path.exists(_vcd_path)}, "
                     f"size={_vcd_size}, rtl_exists={os.path.exists(_rtl_path)}"
@@ -2332,21 +2863,23 @@ CURRENT TESTBENCH (first 3000 chars):
 Use your read_file tool to read the full RTL and TB files if needed.
 
 Classify the failure as ONE of:
-A) TESTBENCH_SYNTAX — TB compilation/syntax error (missing semicolons, undeclared signals, class errors)
-B) RTL_LOGIC_BUG — Functional error in RTL design (wrong state transitions, bad arithmetic, logic errors)
-C) PORT_MISMATCH — TB and RTL have incompatible port names, widths, or missing connections
-D) TIMING_RACE — Clock/reset timing issue in TB stimulus (setup/hold violations, race conditions)
-E) ARCHITECTURAL — Design spec is ambiguous, contradictory, or fundamentally flawed
-
-Reply in this EXACT format (one field per line):
-CLASS: <letter A-E>
-FAILING_OUTPUT: <the exact $display message from the simulation log that indicates failure, e.g. "Data mismatch at pop 0">
-FAILING_SIGNALS: <comma-separated list of signal names whose values are wrong>
-EXPECTED_VS_ACTUAL: <expected value vs actual value if determinable, otherwise "undetermined">
-RESPONSIBLE_CONSTRUCT: <the specific always_ff/always_comb/assign statement and its line number in the RTL that most likely causes the wrong value, e.g. "always_ff block at line 23 driving write_ptr">
-ROOT_CAUSE: <1-line description naming the specific signal and logic error, e.g. "write_ptr increments on push but the counter does not gate on the full flag">
-FIX_HINT: <surgical fix instruction referencing specific line numbers or signal names, e.g. "Change line 25: gate the write_ptr increment with !full">''',
-                expected_output='Structured signal-level failure classification with CLASS, FAILING_OUTPUT, FAILING_SIGNALS, EXPECTED_VS_ACTUAL, RESPONSIBLE_CONSTRUCT, ROOT_CAUSE, and FIX_HINT',
+A) TESTBENCH_SYNTAX
+B) RTL_LOGIC_BUG
+C) PORT_MISMATCH
+D) TIMING_RACE
+E) ARCHITECTURAL
+
+Reply with JSON only, no prose, using this exact schema:
+{{
+  "class": "A|B|C|D|E",
+  "failing_output": "exact failing display or summary",
+  "failing_signals": ["sig1", "sig2"],
+  "expected_vs_actual": "expected vs actual or undetermined",
+  "responsible_construct": "specific RTL construct and line number",
+  "root_cause": "1-line root cause",
+  "fix_hint": "surgical fix hint"
+}}''',
+                expected_output='JSON object with class, failing_output, failing_signals, expected_vs_actual, responsible_construct, root_cause, and fix_hint',
                 agent=analyst
             )
             
@@ -2354,33 +2887,63 @@ FIX_HINT: <surgical fix instruction referencing specific line numbers or signal
                 analysis = str(Crew(agents=[analyst], tasks=[analysis_task]).kickoff()).strip()
             
             self.logger.info(f"FAILURE ANALYSIS:\n{analysis}")
-            
-            # Parse structured response
-            failure_class = "A"  # default fallback
-            root_cause = ""
-            fix_hint = ""
-            failing_output = ""
-            failing_signals = ""
-            expected_vs_actual = ""
-            responsible_construct = ""
-            for line in analysis.split("\n"):
-                line_stripped = line.strip()
-                if line_stripped.startswith("CLASS:"):
-                    letter = line_stripped.replace("CLASS:", "").strip().upper()
-                    if letter and letter[0] in "ABCDE":
-                        failure_class = letter[0]
-                elif line_stripped.startswith("ROOT_CAUSE:"):
-                    root_cause = line_stripped.replace("ROOT_CAUSE:", "").strip()
-                elif line_stripped.startswith("FIX_HINT:"):
-                    fix_hint = line_stripped.replace("FIX_HINT:", "").strip()
-                elif line_stripped.startswith("FAILING_OUTPUT:"):
-                    failing_output = line_stripped.replace("FAILING_OUTPUT:", "").strip()
-                elif line_stripped.startswith("FAILING_SIGNALS:"):
-                    failing_signals = line_stripped.replace("FAILING_SIGNALS:", "").strip()
-                elif line_stripped.startswith("EXPECTED_VS_ACTUAL:"):
-                    expected_vs_actual = line_stripped.replace("EXPECTED_VS_ACTUAL:", "").strip()
-                elif line_stripped.startswith("RESPONSIBLE_CONSTRUCT:"):
-                    responsible_construct = line_stripped.replace("RESPONSIBLE_CONSTRUCT:", "").strip()
+            analyst_result = self._parse_structured_agent_json(
+                agent_name="VerificationAnalyst",
+                raw_output=analysis,
+                required_keys=[
+                    "class",
+                    "failing_output",
+                    "failing_signals",
+                    "expected_vs_actual",
+                    "responsible_construct",
+                    "root_cause",
+                    "fix_hint",
+                ],
+            )
+            if not analyst_result.ok:
+                self._record_non_consumable_output(
+                    "agent_verificationanalyst",
+                    analysis,
+                    analyst_result.diagnostics,
+                )
+                with console.status("[bold red]Retrying Failure Analysis (JSON)...[/bold red]"):
+                    analysis = str(Crew(agents=[analyst], tasks=[analysis_task]).kickoff()).strip()
+                self.logger.info(f"FAILURE ANALYSIS RETRY:\n{analysis}")
+                analyst_result = self._parse_structured_agent_json(
+                    agent_name="VerificationAnalyst",
+                    raw_output=analysis,
+                    required_keys=[
+                        "class",
+                        "failing_output",
+                        "failing_signals",
+                        "expected_vs_actual",
+                        "responsible_construct",
+                        "root_cause",
+                        "fix_hint",
+                    ],
+                )
+                if not analyst_result.ok:
+                    self.log("Verification analysis returned invalid JSON twice. Failing closed.", refined=True)
+                    self.state = BuildState.FAIL
+                    return
+            self._set_artifact(
+                "verification_analysis",
+                analyst_result.to_dict(),
+                producer="agent_verificationanalyst",
+                consumer="VERIFICATION",
+            )
+            analysis_payload = analyst_result.payload
+            failure_class = str(analysis_payload.get("class", "A")).upper()[:1] or "A"
+            root_cause = str(analysis_payload.get("root_cause", "")).strip()
+            fix_hint = str(analysis_payload.get("fix_hint", "")).strip()
+            failing_output = str(analysis_payload.get("failing_output", "")).strip()
+            failing_signals_list = analysis_payload.get("failing_signals", [])
+            if isinstance(failing_signals_list, list):
+                failing_signals = ", ".join(str(x) for x in failing_signals_list)
+            else:
+                failing_signals = str(failing_signals_list)
+            expected_vs_actual = str(analysis_payload.get("expected_vs_actual", "")).strip()
+            responsible_construct = str(analysis_payload.get("responsible_construct", "")).strip()
             
             # Build structured diagnosis string for downstream fix prompts
             structured_diagnosis = (
@@ -2654,10 +3217,27 @@ Return the complete module with ONLY the minimal fix applied.
             
             # Bug 3: Inject DeepDebugger diagnostic context into the SVA generation prompt
             formal_debug = self.artifacts.get("formal_debug_context", "")
+            formal_preflight_error = self._consume_handoff(
+                "formal_preflight_error",
+                consumer="FORMAL_VERIFY",
+                required=False,
+            ) or self.artifacts.get("sva_preflight_error", "")
             if formal_debug:
                 formal_debug_str = f"\n\nPREVIOUS FORMAL VERIFICATION FAILURE DIAGNOSIS:\n{formal_debug}\n\nPlease use this diagnosis to correct the flawed assertions.\n"
             else:
                 formal_debug_str = ""
+            if formal_preflight_error:
+                formal_debug_str += (
+                    "\n\nPREVIOUS YOSYS/SVA PREFLIGHT FAILURE:\n"
+                    f"{formal_preflight_error}\n"
+                    "You must correct the assertions so this exact failure does not recur.\n"
+                )
+            try:
+                with open(rtl_path, "r") as rtl_file:
+                    rtl_for_sva = rtl_file.read()
+            except OSError:
+                rtl_for_sva = self.artifacts.get("rtl_code", "")
+            signal_inventory = self._format_signal_inventory_for_prompt(rtl_for_sva)
             
             verif_agent = get_verification_agent(self.llm, verbose=self.verbose)
             sva_task = Task(
@@ -2667,8 +3247,12 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
                 
                 RTL Code:
                 ```verilog
-                {self.artifacts.get('rtl_code', '')}
+                {rtl_for_sva}
                 ```
+
+                The DUT has the following signals with these exact widths:
+                {signal_inventory}
+                Use only these signals and these exact widths in every assertion. Do not invent signals, aliases, or widths.
                 
                 SPECIFICATION:
                 {self.artifacts.get('spec', '')}
@@ -2700,6 +3284,11 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
             
             # --- Universal code output validation (SVA) ---
             if not validate_llm_code_output(sva_result):
+                self._record_non_consumable_output(
+                    "llm_sva_generation",
+                    sva_result,
+                    ["SVA generation returned prose instead of code."],
+                )
                 self.log("SVA generation returned prose instead of code. Retrying once.", refined=True)
                 self.logger.warning(f"SVA VALIDATION FAIL (prose detected):\n{sva_result[:500]}")
                 sva_result = str(Crew(agents=[verif_agent], tasks=[sva_task]).kickoff())
@@ -2707,6 +3296,23 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
                     self.log("SVA retry also returned invalid output. Skipping formal.", refined=True)
                     self.transition(BuildState.COVERAGE_CHECK)
                     return
+            sva_validation_issues = self._validate_sva_candidate(sva_result, rtl_for_sva)
+            if sva_validation_issues:
+                self._record_stage_contract(
+                    StageResult(
+                        stage=self.state.name,
+                        status=StageStatus.RETRY,
+                        producer="orchestrator_sva_validator",
+                        failure_class=FailureClass.LLM_SEMANTIC_ERROR,
+                        diagnostics=sva_validation_issues,
+                        next_action="retry_sva_generation",
+                    )
+                )
+                self.log(f"SVA candidate rejected: {sva_validation_issues[0]}", refined=True)
+                for stale in (sva_path,):
+                    if os.path.exists(stale):
+                        os.remove(stale)
+                return
             
             self.logger.info(f"GENERATED SVA:\n{sva_result}")
             
@@ -2739,8 +3345,20 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
                 json.dump(preflight_report, f, indent=2)
             self.artifacts["formal_preflight"] = preflight_report
             self.artifacts["formal_preflight_path"] = formal_diag_path
+            self._set_artifact(
+                "formal_preflight_report",
+                preflight_report,
+                producer="orchestrator_formal_preflight",
+                consumer="FORMAL_VERIFY",
+            )
 
             if not preflight_ok:
+                self._set_artifact(
+                    "formal_preflight_error",
+                    json.dumps(preflight_report, indent=2)[:2000],
+                    producer="orchestrator_formal_preflight",
+                    consumer="FORMAL_VERIFY",
+                )
                 self.log(f"Formal preflight failed: {preflight_report.get('issue_count', 0)} issue(s).", refined=True)
                 self.artifacts['formal_result'] = 'FAIL'
                 if self.strict_gates:
@@ -2763,15 +3381,36 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
                 pf = subprocess.run(preflight_cmd, capture_output=True, text=True, timeout=30)
                 if pf.returncode != 0:
                     yosys_err = (pf.stderr or pf.stdout or "").strip()
-                    self.log(f"Yosys SVA preflight failed. Regenerating SVA with error context.", refined=True)
                     self.logger.info(f"YOSYS SVA PREFLIGHT FAIL:\n{yosys_err}")
+                    prev_err = self.artifacts.get("sva_preflight_error_last", "")
+                    if prev_err == yosys_err:
+                        streak = int(self.artifacts.get("sva_preflight_error_streak", 0)) + 1
+                    else:
+                        streak = 1
+                    self.artifacts["sva_preflight_error_last"] = yosys_err
+                    self.artifacts["sva_preflight_error_streak"] = streak
+                    self.artifacts["sva_preflight_error"] = yosys_err[:2000]
+                    self._set_artifact(
+                        "formal_preflight_error",
+                        yosys_err[:2000],
+                        producer="yosys_preflight",
+                        consumer="FORMAL_VERIFY",
+                    )
+                    if streak >= 2:
+                        self.log("Repeated Yosys SVA preflight failure detected. Skipping formal instead of regenerating again.", refined=True)
+                        self.artifacts["formal_result"] = "SKIP"
+                        self.artifacts["sva_preflight_skip_reason"] = yosys_err[:2000]
+                        self.transition(BuildState.COVERAGE_CHECK)
+                        return
+                    self.log("Yosys SVA preflight failed. Regenerating SVA with error context.", refined=True)
                     # Remove stale SVA files so the next iteration regenerates
                     for stale in (sva_path, sby_check_path):
                         if os.path.exists(stale):
                             os.remove(stale)
-                    self.artifacts["sva_preflight_error"] = yosys_err[:2000]
                     # Stay in FORMAL_VERIFY — will regenerate SVA on re-entry
                     return
+                self.artifacts.pop("sva_preflight_error_last", None)
+                self.artifacts.pop("sva_preflight_error_streak", None)
             except Exception as pf_exc:
                 self.logger.warning(f"Yosys SVA preflight exception: {pf_exc}")
 
@@ -2815,6 +3454,13 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
                         design_name=self.name,
                         rtl_code=self.artifacts.get("rtl_code", ""),
                     )
+                    debug_result = self._normalize_deepdebug_result(_verdict, result)
+                    self._set_artifact(
+                        "formal_debug_result",
+                        debug_result.to_dict(),
+                        producer="agent_deepdebug",
+                        consumer="FORMAL_VERIFY",
+                    )
                     if _verdict is not None:
                         _formal_debug_context = (
                             f"\n\nFVDEBUG ROOT CAUSE:\n"
@@ -2836,7 +3482,12 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
                         f"sby_cfg_exists={os.path.exists(_sby_cfg)}, "
                         f"rtl_exists={os.path.exists(_rtl_path_fv)}"
                     )
-                self.artifacts["formal_debug_context"] = _formal_debug_context
+                self._set_artifact(
+                    "formal_debug_context",
+                    _formal_debug_context,
+                    producer="agent_deepdebug",
+                    consumer="FORMAL_VERIFY",
+                )
 
                 self.artifacts['formal_result'] = 'FAIL'
                 if self.strict_gates:
@@ -2866,6 +3517,11 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
                 self.state = BuildState.FAIL
                 return
         
+        if self.skip_coverage:
+            self.log("Skipping Coverage Analysis (--skip-coverage).", refined=True)
+            self.transition(BuildState.REGRESSION)
+            return
+
         self.transition(BuildState.COVERAGE_CHECK)
 
     def do_coverage_check(self):
@@ -2912,6 +3568,15 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
         self.artifacts["coverage"] = coverage_data
         self.artifacts["coverage_backend_used"] = coverage_data.get("backend", self.coverage_backend)
         self.artifacts["coverage_mode"] = coverage_data.get("coverage_mode", "unknown")
+        self._set_artifact(
+            "coverage_improvement_context",
+            {
+                "coverage_data": coverage_data,
+                "sim_output": sim_output[:4000] if isinstance(sim_output, str) else str(sim_output),
+            },
+            producer="orchestrator_coverage",
+            consumer="COVERAGE_CHECK",
+        )
 
         src_dir = os.path.join(OPENLANE_ROOT, "designs", self.name, "src")
         os.makedirs(src_dir, exist_ok=True)
@@ -3048,6 +3713,8 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
         improve_prompt = f"""The current testbench for "{self.name}" does not meet coverage thresholds.
         TARGET: Branch >={branch_target:.1f}%, Line >={float(thresholds['line']):.1f}%.
         Current Coverage Data: {coverage_data}
+        PREVIOUS FAILED ATTEMPTS:
+        {self._format_failure_history()}
         
         Current RTL:
         ```verilog
@@ -3090,9 +3757,28 @@ Generate SVA assertions that are compatible with the Yosys formal verification e
         improved_tb = str(result)
         # --- Universal code output validation (coverage TB improvement) ---
         if not validate_llm_code_output(improved_tb):
+            self._record_non_consumable_output(
+                "llm_coverage_tb",
+                improved_tb,
+                ["Coverage TB improvement returned prose instead of code."],
+            )
             self.log("Coverage TB improvement returned prose instead of code. Retrying once.", refined=True)
             self.logger.warning(f"COVERAGE TB VALIDATION FAIL (prose detected):\n{improved_tb[:500]}")
             improved_tb = str(Crew(agents=[tb_agent], tasks=[improve_task]).kickoff())
+        tb_validation_issues = self._validate_tb_candidate(improved_tb)
+        if tb_validation_issues:
+            self._record_stage_contract(
+                StageResult(
+                    stage=self.state.name,
+                    status=StageStatus.RETRY,
+                    producer="orchestrator_coverage_tb_validator",
+                    failure_class=FailureClass.LLM_SEMANTIC_ERROR,
+                    diagnostics=tb_validation_issues,
+                    next_action="keep_previous_tb",
+                )
+            )
+            self.log(f"Coverage TB candidate rejected: {tb_validation_issues[0]}", refined=True)
+            return
         self.logger.info(f"IMPROVED TB:\n{improved_tb}")
 
         tb_path = write_verilog(self.name, improved_tb, is_testbench=True)

src/agentic/tools/vlsi_tools.py

@@ -4,6 +4,8 @@ import re
 import json
 import hashlib
 import subprocess
+import tempfile
+import glob
 from collections import Counter, defaultdict, deque
 from typing import Dict, Any, List, Tuple
 import shutil
@@ -55,6 +57,162 @@ def _resolve_binary(bin_hint: str) -> str:
     return bin_hint
 
 
+def _build_tool_result(
+    tool: str,
+    *,
+    ok: bool,
+    result: str,
+    returncode: int = -1,
+    stdout: str = "",
+    stderr: str = "",
+    diagnostics: List[str] | None = None,
+    metrics: Dict[str, Any] | None = None,
+) -> Dict[str, Any]:
+    """Build the canonical structured tool result."""
+    return {
+        "ok": bool(ok),
+        "tool": tool,
+        "returncode": int(returncode),
+        "stdout": stdout or "",
+        "stderr": stderr or "",
+        "result": result,
+        "diagnostics": list(diagnostics or []),
+        "metrics": dict(metrics or {}),
+    }
+
+
+def _collect_design_rtl(src_dir: str, include_sv: bool = True) -> List[str]:
+    patterns = [os.path.join(src_dir, "*.v")]
+    if include_sv:
+        patterns.append(os.path.join(src_dir, "*.sv"))
+    rtl_files: List[str] = []
+    for pattern in patterns:
+        rtl_files.extend(glob.glob(pattern))
+    seen = set()
+    ordered = []
+    for path in sorted(rtl_files):
+        if path.endswith("_tb.v") or "regression" in path:
+            continue
+        if path in seen:
+            continue
+        seen.add(path)
+        ordered.append(path)
+    return ordered
+
+
+def _stage_inputs(tmpdir: str, paths: List[str]) -> Dict[str, str]:
+    """Copy required inputs to tmpdir and return original->staged mapping."""
+    staged: Dict[str, str] = {}
+    used_names: set[str] = set()
+    for path in paths:
+        if not path or not os.path.exists(path) or path in staged:
+            continue
+        base = os.path.basename(path)
+        stem, ext = os.path.splitext(base)
+        candidate = base
+        counter = 1
+        while candidate in used_names:
+            candidate = f"{stem}_{counter}{ext}"
+            counter += 1
+        used_names.add(candidate)
+        dst = os.path.join(tmpdir, candidate)
+        shutil.copy2(path, dst)
+        staged[path] = dst
+    return staged
+
+
+def _stage_path(path: str, staged_map: Dict[str, str]) -> str:
+    return staged_map.get(path, path)
+
+
+def _temp_roots_from_stage_map(staged_map: Dict[str, str]) -> Tuple[str, str]:
+    if not staged_map:
+        return "", ""
+    temp_root = os.path.commonpath([os.path.dirname(path) for path in staged_map.values()])
+    original_root = os.path.commonpath([os.path.dirname(path) for path in staged_map.keys()])
+    return temp_root, original_root
+
+
+def _rewrite_temp_paths(text: str, staged_map: Dict[str, str]) -> str:
+    """Rewrite temp paths in diagnostic text back to original source paths."""
+    if not text or not staged_map:
+        return text
+
+    rewritten = text
+    # Exact staged path replacement first.
+    for original, staged in sorted(staged_map.items(), key=lambda item: len(item[1]), reverse=True):
+        rewritten = rewritten.replace(staged, original)
+        staged_norm = os.path.normpath(staged)
+        if staged_norm != staged:
+            rewritten = rewritten.replace(staged_norm, original)
+        basename = os.path.basename(staged)
+        original_base = os.path.basename(original)
+        if basename == original_base:
+            basename_re = re.compile(rf"(?<![\w./-]){re.escape(basename)}(?=(?::\d)|\b)")
+            rewritten = basename_re.sub(original, rewritten)
+
+    temp_root, original_root = _temp_roots_from_stage_map(staged_map)
+    if temp_root and original_root:
+        rewritten = rewritten.replace(temp_root + os.sep, original_root + os.sep)
+        rewritten = rewritten.replace(temp_root, original_root)
+
+    return rewritten
+
+
+def _assert_no_temp_paths(text: str, staged_map: Dict[str, str]):
+    temp_root, _ = _temp_roots_from_stage_map(staged_map)
+    if temp_root and text and temp_root in text:
+        raise AssertionError(f"Temp path leak detected in tool diagnostics: {temp_root}")
+
+
+def _rewrite_result_paths(result_dict: Dict[str, Any], staged_map: Dict[str, str]) -> Dict[str, Any]:
+    """Sanitize tool result payloads so no temp paths leak upstream."""
+    sanitized = dict(result_dict)
+    for key in ("stdout", "stderr"):
+        value = sanitized.get(key, "")
+        if isinstance(value, str):
+            sanitized[key] = _rewrite_temp_paths(value, staged_map)
+            _assert_no_temp_paths(sanitized[key], staged_map)
+
+    diagnostics = sanitized.get("diagnostics", [])
+    if isinstance(diagnostics, list):
+        clean_diags = []
+        for entry in diagnostics:
+            if isinstance(entry, str):
+                clean = _rewrite_temp_paths(entry, staged_map)
+                _assert_no_temp_paths(clean, staged_map)
+                clean_diags.append(clean)
+            else:
+                clean_diags.append(entry)
+        sanitized["diagnostics"] = clean_diags
+    return sanitized
+
+
+def _promote_vcd_artifacts(tmpdir: str, src_dir: str):
+    for entry in os.listdir(tmpdir):
+        if not entry.endswith(".vcd"):
+            continue
+        src = os.path.join(tmpdir, entry)
+        dst = os.path.join(src_dir, entry)
+        try:
+            shutil.copy2(src, dst)
+        except OSError:
+            continue
+
+
+def _collect_diag_lines(raw: str, limit: int = 12) -> List[str]:
+    diag_lines: List[str] = []
+    for line in raw.splitlines():
+        s = line.strip()
+        if not s:
+            continue
+        if s.startswith("%Error") or s.startswith("%Warning") or "syntax error" in s.lower() or "internal error" in s.lower():
+            diag_lines.append(s)
+    if not diag_lines:
+        diag_lines = [x.strip() for x in raw.splitlines() if x.strip()]
+    return diag_lines[:limit]
+
+
 def startup_self_check() -> Dict[str, Any]:
     """Validate required tooling and environment before running the flow."""
     checks: List[Dict[str, Any]] = []
@@ -349,35 +507,37 @@ def run_syntax_check(file_path: str) -> tuple:
     """
     if not os.path.exists(file_path):
         return False, f"File not found: {file_path}"
-    
-    try:
-        # Gather all RTL files to support multi-file compilation
-        import glob
-        src_dir = os.path.dirname(file_path)
-        rtl_files = [f for f in glob.glob(os.path.join(src_dir, "*.v")) + glob.glob(os.path.join(src_dir, "*.sv"))
-                     if not f.endswith("_tb.v") and "regression" not in f]
-        if file_path not in rtl_files and os.path.exists(file_path):
-            rtl_files.append(file_path)
-
-        # --lint-only: check syntax and basic semantics
-        # --sv: force SystemVerilog parsing
-        # --timing: support delays
-        # -Wno-fatal: don't crash on warnings (unless they are errors)
-        cmd = ["verilator", "--lint-only", "--sv", "--timing", "-Wno-fatal"] + rtl_files
-        
-        result = subprocess.run(
-            cmd, 
-            capture_output=True, text=True,
-            timeout=60
-        )
-        # Verilator prints errors/warnings to stderr
-        if result.returncode == 0:
-            return True, "Syntax OK (Verilator)"
-        return False, f"Verilator Syntax Errors:\n{result.stderr}"
-    except subprocess.TimeoutExpired:
-        return False, "Syntax check timed out (>60s)."
-    except FileNotFoundError:
-        return False, "Verilator not found. Please install Verilator 5.0+."
+
+    src_dir = os.path.dirname(file_path)
+    rtl_files = _collect_design_rtl(src_dir)
+    if file_path not in rtl_files:
+        rtl_files.append(file_path)
+
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, rtl_files)
+        cmd = ["verilator", "--lint-only", "--sv", "--timing", "-Wno-fatal"] + [
+            os.path.basename(_stage_path(path, staged_map)) for path in rtl_files
+        ]
+        try:
+            completed = subprocess.run(cmd, capture_output=True, text=True, timeout=60, cwd=tmpdir)
+            tool_result = _build_tool_result(
+                "verilator",
+                ok=completed.returncode == 0,
+                result="PASS" if completed.returncode == 0 else "FAIL",
+                returncode=completed.returncode,
+                stdout=completed.stdout,
+                stderr=completed.stderr,
+                diagnostics=_collect_diag_lines((completed.stderr or completed.stdout or "").strip()),
+                metrics={"mode": "syntax_check"},
+            )
+            tool_result = _rewrite_result_paths(tool_result, staged_map)
+            if tool_result["ok"]:
+                return True, "Syntax OK (Verilator)"
+            return False, f"Verilator Syntax Errors:\n{tool_result['stderr']}"
+        except subprocess.TimeoutExpired:
+            return False, "Syntax check timed out (>60s)."
+        except FileNotFoundError:
+            return False, "Verilator not found. Please install Verilator 5.0+."
 
 def run_lint_check(file_path: str) -> tuple:
     """
@@ -388,67 +548,65 @@ def run_lint_check(file_path: str) -> tuple:
     """
     if not os.path.exists(file_path):
         return False, f"File not found: {file_path}"
-    
-    import glob
+
     src_dir = os.path.dirname(file_path)
-    rtl_files = [f for f in glob.glob(os.path.join(src_dir, "*.v")) + glob.glob(os.path.join(src_dir, "*.sv"))
-                 if not f.endswith("_tb.v") and "regression" not in f]
-    if file_path not in rtl_files and os.path.exists(file_path):
+    rtl_files = _collect_design_rtl(src_dir)
+    if file_path not in rtl_files:
         rtl_files.append(file_path)
 
     # --sv: force SystemVerilog parsing (critical for typedef, logic, always_comb)
     # -Wno-fatal: don't exit on warnings — let us separate real errors from warnings
     # Suppress informational warnings that are not bugs:
-    cmd = [
-        "verilator", "--lint-only", "--sv", "--timing",
-        "-Wno-fatal",          # warnings don't cause non-zero exit
-        "-Wno-UNUSED",         # unused signals (common in AI-generated code)
-        "-Wno-PINMISSING",     # missing port connections
-        "-Wno-CASEINCOMPLETE", # incomplete case (handled by default)
-        "-Wno-WIDTHEXPAND",    # zero-extension (harmless implicit widening)
-        "-Wno-WIDTHTRUNC",     # truncation (flag separately in semantic check)
-    ] + rtl_files
-    
-    try:
-        result = subprocess.run(
-            cmd, 
-            capture_output=True, text=True,
-            timeout=30
-        )
-        stderr = result.stderr.strip()
-        
-        if result.returncode == 0:
-            # Check for remaining warnings (non-fatal)
-            if stderr:
-                # Parse for LATCH warnings — these are fixable and important
-                has_latch = bool(re.search(r'%Warning-LATCH:', stderr))
-                if has_latch:
-                    # LATCH is a real design issue — fail so the LLM can fix it
-                    return False, f"Verilator Lint Errors:\n{stderr}"
-                # Other warnings are informational, pass with report
-                return True, f"Lint OK (with warnings):\n{stderr}"
-            return True, "Lint OK"
-        
-        # Non-zero exit: check if there are REAL %Error lines (not just "Exiting due to N warning(s)")
-        real_errors = [
-            line for line in stderr.splitlines()
-            if line.strip().startswith("%Error") and "Exiting due to" not in line
-        ]
-        
-        if not real_errors:
-            # Only warnings caused the exit — try iverilog fallback
-            iverilog_ok, iverilog_report = run_iverilog_lint(file_path)
-            if iverilog_ok:
-                return True, f"Lint OK (Verilator warnings only, iverilog passed):\n{stderr}"
-            else:
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, rtl_files)
+        cmd = [
+            "verilator", "--lint-only", "--sv", "--timing",
+            "-Wno-fatal",
+            "-Wno-UNUSED",
+            "-Wno-PINMISSING",
+            "-Wno-CASEINCOMPLETE",
+            "-Wno-WIDTHEXPAND",
+            "-Wno-WIDTHTRUNC",
+        ] + [os.path.basename(_stage_path(path, staged_map)) for path in rtl_files]
+
+        try:
+            completed = subprocess.run(cmd, capture_output=True, text=True, timeout=30, cwd=tmpdir)
+            tool_result = _build_tool_result(
+                "verilator",
+                ok=completed.returncode == 0,
+                result="PASS" if completed.returncode == 0 else "FAIL",
+                returncode=completed.returncode,
+                stdout=completed.stdout,
+                stderr=completed.stderr,
+                diagnostics=_collect_diag_lines((completed.stderr or completed.stdout or "").strip()),
+                metrics={"mode": "lint_check"},
+            )
+            tool_result = _rewrite_result_paths(tool_result, staged_map)
+            stderr = tool_result["stderr"].strip()
+
+            if tool_result["returncode"] == 0:
+                if stderr:
+                    has_latch = bool(re.search(r'%Warning-LATCH:', stderr))
+                    if has_latch:
+                        return False, f"Verilator Lint Errors:\n{stderr}"
+                    return True, f"Lint OK (with warnings):\n{stderr}"
+                return True, "Lint OK"
+
+            real_errors = [
+                line for line in stderr.splitlines()
+                if line.strip().startswith("%Error") and "Exiting due to" not in line
+            ]
+            if not real_errors:
+                iverilog_ok, iverilog_report = run_iverilog_lint(file_path)
+                if iverilog_ok:
+                    return True, f"Lint OK (Verilator warnings only, iverilog passed):\n{stderr}"
                 return False, f"Verilator Lint Errors:\n{stderr}\n\niverilog also failed:\n{iverilog_report}"
-        
-        return False, f"Verilator Lint Errors:\n{stderr}"
-        
-    except FileNotFoundError:
-         return True, "Verilator not found (Skipping Lint)"
-    except subprocess.TimeoutExpired:
-         return False, "Lint check timed out."
+
+            return False, f"Verilator Lint Errors:\n{stderr}"
+        except FileNotFoundError:
+            return True, "Verilator not found (Skipping Lint)"
+        except subprocess.TimeoutExpired:
+            return False, "Lint check timed out."
 
 
 def run_iverilog_lint(file_path: str) -> tuple:
@@ -460,44 +618,54 @@ def run_iverilog_lint(file_path: str) -> tuple:
     """
     if not os.path.exists(file_path):
         return False, f"File not found: {file_path}"
-    
-    import glob
+
     src_dir = os.path.dirname(file_path)
-    rtl_files = [f for f in glob.glob(os.path.join(src_dir, "*.v")) if not f.endswith("_tb.v") and "regression" not in f]
-    if file_path not in rtl_files and os.path.exists(file_path):
+    rtl_files = _collect_design_rtl(src_dir, include_sv=False)
+    if file_path not in rtl_files:
         rtl_files.append(file_path)
 
-    # -g2012: IEEE 1800-2012 SystemVerilog standard
-    # -Wall: enable all warnings
-    # -o /dev/null: don't produce output binary (lint-only mode)
-    cmd = ["iverilog", "-g2012", "-Wall", "-o", "/dev/null"] + rtl_files
-    
-    try:
-        result = subprocess.run(
-            cmd,
-            capture_output=True, text=True,
-            timeout=30
-        )
-        combined = (result.stdout + "\n" + result.stderr).strip()
-        
-        # iverilog returns 0 on success, non-zero on errors
-        if result.returncode == 0:
-            if combined:
-                return True, f"iverilog OK (with warnings):\n{combined}"
-            return True, "iverilog OK"
-        
-        return False, f"iverilog Lint Errors:\n{combined}"
-        
-    except FileNotFoundError:
-        return False, "iverilog not found (install with: apt install iverilog)"
-    except subprocess.TimeoutExpired:
-        return False, "iverilog lint check timed out."
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, rtl_files)
+        out_path = os.path.join(tmpdir, "iverilog_lint.out")
+        cmd = ["iverilog", "-g2012", "-Wall", "-o", out_path] + [
+            os.path.basename(_stage_path(path, staged_map)) for path in rtl_files
+        ]
+        try:
+            completed = subprocess.run(cmd, capture_output=True, text=True, timeout=30, cwd=tmpdir)
+            tool_result = _build_tool_result(
+                "iverilog",
+                ok=completed.returncode == 0,
+                result="PASS" if completed.returncode == 0 else "FAIL",
+                returncode=completed.returncode,
+                stdout=completed.stdout,
+                stderr=completed.stderr,
+                diagnostics=_collect_diag_lines(((completed.stdout or "") + "\n" + (completed.stderr or "")).strip()),
+                metrics={"mode": "lint_check"},
+            )
+            tool_result = _rewrite_result_paths(tool_result, staged_map)
+            combined = ((tool_result["stdout"] or "") + "\n" + (tool_result["stderr"] or "")).strip()
+            if tool_result["ok"]:
+                if combined:
+                    return True, f"iverilog OK (with warnings):\n{combined}"
+                return True, "iverilog OK"
+            return False, f"iverilog Lint Errors:\n{combined}"
+        except FileNotFoundError:
+            return False, "iverilog not found (install with: apt install iverilog)"
+        except subprocess.TimeoutExpired:
+            return False, "iverilog lint check timed out."
 
 
 def run_semantic_rigor_check(file_path: str) -> Tuple[bool, Dict[str, Any]]:
     """Deterministic semantic preflight for width-safety and port-shadowing."""
     report: Dict[str, Any] = {
         "ok": True,
+        "tool": "verilator",
+        "returncode": -1,
+        "stdout": "",
+        "stderr": "",
+        "result": "ERROR",
+        "diagnostics": [],
+        "metrics": {},
         "width_issues": [],
         "port_shadowing": [],
         "details": "",
@@ -540,20 +708,36 @@ def run_semantic_rigor_check(file_path: str) -> Tuple[bool, Dict[str, Any]]:
         "signed",
         "truncat",
     )
-    cmd = ["verilator", "--lint-only", "--sv", "--timing", "-Wall", file_path]
-    try:
-        result = subprocess.run(cmd, capture_output=True, text=True, timeout=60)
-        stderr = result.stderr or ""
-        width_lines = []
-        for line in stderr.splitlines():
-            upper = line.upper()
-            if any(p.upper() in upper for p in width_patterns):
-                width_lines.append(line.strip())
-        if width_lines:
-            report["width_issues"] = width_lines[:20]
-            report["details"] = "\n".join(width_lines[:20])
-    except Exception as exc:
-        report["details"] = f"Semantic width scan fallback triggered: {exc}"
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, [file_path])
+        staged_file = _stage_path(file_path, staged_map)
+        cmd = ["verilator", "--lint-only", "--sv", "--timing", "-Wall", os.path.basename(staged_file)]
+        try:
+            completed = subprocess.run(cmd, capture_output=True, text=True, timeout=60, cwd=tmpdir)
+            tool_result = _build_tool_result(
+                "verilator",
+                ok=completed.returncode == 0,
+                result="PASS" if completed.returncode == 0 else "FAIL",
+                returncode=completed.returncode,
+                stdout=completed.stdout,
+                stderr=completed.stderr,
+                diagnostics=_collect_diag_lines((completed.stderr or completed.stdout or "").strip()),
+                metrics={"mode": "semantic_rigor"},
+            )
+            tool_result = _rewrite_result_paths(tool_result, staged_map)
+            report.update(tool_result)
+            stderr = tool_result["stderr"] or ""
+            width_lines = []
+            for line in stderr.splitlines():
+                upper = line.upper()
+                if any(p.upper() in upper for p in width_patterns):
+                    width_lines.append(line.strip())
+            if width_lines:
+                report["width_issues"] = width_lines[:20]
+                report["details"] = "\n".join(width_lines[:20])
+                report["tool_result"] = tool_result
+        except Exception as exc:
+            report["details"] = f"Semantic width scan fallback triggered: {exc}"
 
     report["ok"] = not report["port_shadowing"] and not report["width_issues"]
     return report["ok"], report
@@ -666,20 +850,24 @@ def auto_fix_width_warnings(file_path: str) -> Tuple[bool, Dict[str, Any]]:
 
 def _collect_width_warnings(file_path: str) -> List[str]:
     """Run Verilator -Wall and return only WIDTH-related warning lines."""
-    cmd = ["verilator", "--lint-only", "--sv", "--timing", "-Wall", file_path]
-    try:
-        result = subprocess.run(cmd, capture_output=True, text=True, timeout=60)
-        stderr = result.stderr or ""
-    except Exception:
-        return []
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, [file_path])
+        staged_file = _stage_path(file_path, staged_map)
+        cmd = ["verilator", "--lint-only", "--sv", "--timing", "-Wall", os.path.basename(staged_file)]
+        try:
+            result = subprocess.run(cmd, capture_output=True, text=True, timeout=60, cwd=tmpdir)
+            stderr = _rewrite_temp_paths(result.stderr or "", staged_map)
+            _assert_no_temp_paths(stderr, staged_map)
+        except Exception:
+            return []
 
-    hit_keys = ("WIDTHTRUNC", "WIDTHEXPAND", "WIDTH")
-    out = []
-    for line in stderr.splitlines():
-        upper = line.upper()
-        if any(k in upper for k in hit_keys):
-            out.append(line.strip())
-    return out
+        hit_keys = ("WIDTHTRUNC", "WIDTHEXPAND", "WIDTH")
+        out = []
+        for line in stderr.splitlines():
+            upper = line.upper()
+            if any(k in upper for k in hit_keys):
+                out.append(line.strip())
+        return out
 
 
 def _parse_width_warning_record(warning: str) -> dict | None:
@@ -1281,38 +1469,21 @@ bind {module_name} {module_name}_sby_check sby_inst (.*);
 '''
     return yosys_code
 
-def write_sby_config(design_name, use_sby_check: bool = True):
-    """Writes a default SBY config for the design.
-    
-    Args:
-        design_name: Name of the design
-        use_sby_check: If True, use the Yosys-compatible _sby_check.sv file
-    """
-    import glob as _glob
+
+def _render_sby_config(design_name: str, use_sby_check: bool = True) -> Tuple[str, List[str]]:
     src_dir = f"{OPENLANE_ROOT}/designs/{design_name}/src"
-    formal_dir = f"{OPENLANE_ROOT}/designs/{design_name}/formal"
-    os.makedirs(formal_dir, exist_ok=True)
-    path = f"{formal_dir}/{design_name}.sby"
-    
     sva_file = f"{design_name}_sby_check.sv" if use_sby_check else f"{design_name}_sva.sv"
     sva_abs = f"{src_dir}/{sva_file}"
-    
-    # Glob all RTL files from src/ — same pattern as Verilator multi-file fix
-    # Exclude _sva.sv (raw LLM SVA — not Yosys-compatible) and _tb.v testbenches
     sva_raw = f"{src_dir}/{design_name}_sva.sv"
     rtl_files = sorted(
-        f for f in _glob.glob(os.path.join(src_dir, "*.v")) + _glob.glob(os.path.join(src_dir, "*.sv"))
-        if not f.endswith("_tb.v") and "regression" not in f
-        and f != sva_abs and f != sva_raw
+        f for f in _collect_design_rtl(src_dir)
+        if f != sva_abs and f != sva_raw
     )
-    # Ensure the Yosys-compatible SVA check file is included
     if os.path.exists(sva_abs):
         rtl_files.append(sva_abs)
-    
-    # Build [script] read commands and [files] entries from the globbed list
+
     read_cmds = "\n".join(f"read -formal {os.path.basename(f)}" for f in rtl_files)
-    files_entries = "\n".join(rtl_files)
-    
+    files_entries = "\n".join(os.path.basename(f) for f in rtl_files)
     config = f"""[options]
 mode prove
 
@@ -1326,36 +1497,57 @@ prep -top {design_name}
 [files]
 {files_entries}
 """
-    with open(path, "w") as f:
-        f.write(config)
-    return path
+    return config, rtl_files
+
+
+def write_sby_config(design_name, use_sby_check: bool = True):
+    """Render the default SBY config for compatibility.
+    
+    Args:
+        design_name: Name of the design
+        use_sby_check: If True, use the Yosys-compatible _sby_check.sv file
+    """
+    _render_sby_config(design_name, use_sby_check=use_sby_check)
+    return f"{OPENLANE_ROOT}/designs/{design_name}/formal/{design_name}.sby"
 
 def run_formal_verification(design_name):
     """Runs SymbiYosys (SBY) for formal verification."""
-    formal_dir = f"{OPENLANE_ROOT}/designs/{design_name}/formal"
-    sby_file = f"{formal_dir}/{design_name}.sby"
-    
-    if not os.path.exists(sby_file):
+    sby_cmd = _resolve_binary(SBY_BIN)
+    config_text, rtl_files = _render_sby_config(design_name, use_sby_check=True)
+    if not rtl_files:
         return False, "SBY configuration file not found."
 
-    # Run SBY from formal/ directory to avoid polluting src/
-    sby_cmd = _resolve_binary(SBY_BIN)
-    try:
-        result = subprocess.run(
-            [sby_cmd, "-f", f"{design_name}.sby"],
-            cwd=formal_dir,
-            capture_output=True,
-            text=True,
-            timeout=600  # 10 minute timeout for formal verification
-        )
-        if result.returncode == 0:
-            return True, f"Formal Verification PASSED.\n{result.stdout}"
-        else:
-            return False, f"Formal Verification FAILED:\n{result.stdout}\n{result.stderr}"
-    except subprocess.TimeoutExpired:
-        return False, "Formal Verification timed out (>10 mins). Design may be too complex for bounded model checking."
-    except FileNotFoundError:
-        return False, "SymbiYosys (sby) tool not installed/found in path."
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, rtl_files)
+        sby_file = os.path.join(tmpdir, f"{design_name}.sby")
+        with open(sby_file, "w") as f:
+            f.write(config_text)
+        try:
+            completed = subprocess.run(
+                [sby_cmd, "-f", os.path.basename(sby_file)],
+                cwd=tmpdir,
+                capture_output=True,
+                text=True,
+                timeout=600,
+            )
+            tool_result = _build_tool_result(
+                "sby",
+                ok=completed.returncode == 0,
+                result="PASS" if completed.returncode == 0 else "FAIL",
+                returncode=completed.returncode,
+                stdout=completed.stdout,
+                stderr=completed.stderr,
+                diagnostics=_collect_diag_lines(((completed.stdout or "") + "\n" + (completed.stderr or "")).strip()),
+                metrics={"mode": "formal_verification"},
+            )
+            tool_result = _rewrite_result_paths(tool_result, staged_map)
+            if tool_result["ok"]:
+                return True, f"Formal Verification PASSED.\n{tool_result['stdout']}"
+            return False, f"Formal Verification FAILED:\n{tool_result['stdout']}\n{tool_result['stderr']}"
+        except subprocess.TimeoutExpired:
+            return False, "Formal Verification timed out (>10 mins). Design may be too complex for bounded model checking."
+        except FileNotFoundError:
+            return False, "SymbiYosys (sby) tool not installed/found in path."
 
 def read_file_content(file_path: str):
     """
@@ -1608,9 +1800,14 @@ def run_tb_compile_gate(design_name: str, tb_path: str, rtl_path: str) -> Tuple[
         "design_name": design_name,
         "tb_path": tb_path,
         "rtl_path": rtl_path,
+        "tool": "verilator",
         "returncode": -1,
+        "stdout": "",
+        "stderr": "",
+        "result": "ERROR",
         "issue_categories": [],
         "diagnostics": [],
+        "metrics": {},
         "compile_output": "",
         "timeout": False,
         "fingerprint": "",
@@ -1627,87 +1824,86 @@ def run_tb_compile_gate(design_name: str, tb_path: str, rtl_path: str) -> Tuple[
         report["fingerprint"] = hashlib.sha256(report["compile_output"].encode("utf-8")).hexdigest()[:16]
         return False, report
 
-    import glob
     src_dir = os.path.dirname(rtl_path)
-    all_rtl = [f for f in glob.glob(os.path.join(src_dir, "*.v")) + glob.glob(os.path.join(src_dir, "*.sv"))
-               if not f.endswith("_tb.v") and "regression" not in f]
-    if rtl_path not in all_rtl and os.path.exists(rtl_path):
+    all_rtl = _collect_design_rtl(src_dir)
+    if rtl_path not in all_rtl:
         all_rtl.append(rtl_path)
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, all_rtl + [tb_path])
+        cmd = [
+            "verilator",
+            "--lint-only",
+            "--sv",
+            "--timing",
+            "-Wno-fatal",
+            *[os.path.basename(_stage_path(path, staged_map)) for path in all_rtl],
+            os.path.basename(_stage_path(tb_path, staged_map)),
+            "--top-module",
+            f"{design_name}_tb",
+        ]
+        report["command"] = cmd
 
-    cmd = [
-        "verilator",
-        "--lint-only",
-        "--sv",
-        "--timing",
-        "-Wno-fatal",
-        *all_rtl,
-        tb_path,
-        "--top-module",
-        f"{design_name}_tb",
-    ]
-    report["command"] = cmd
-
-    try:
-        result = subprocess.run(cmd, capture_output=True, text=True, timeout=120)
-    except subprocess.TimeoutExpired:
-        report["timeout"] = True
-        report["compile_output"] = "TB compile gate timed out (>120s)."
-        report["issue_categories"] = ["compile_timeout"]
-        report["fingerprint"] = hashlib.sha256(report["compile_output"].encode("utf-8")).hexdigest()[:16]
-        return False, report
-    except FileNotFoundError:
-        report["compile_output"] = "Verilator binary not found."
-        report["issue_categories"] = ["verilator_missing"]
-        report["fingerprint"] = hashlib.sha256(report["compile_output"].encode("utf-8")).hexdigest()[:16]
-        return False, report
-
-    raw = ((result.stdout or "") + ("\n" + result.stderr if result.stderr else "")).strip()
-    report["returncode"] = result.returncode
-    report["compile_output"] = raw[:16000]
-
-    diag_lines: List[str] = []
-    for line in raw.splitlines():
-        s = line.strip()
-        if not s:
-            continue
-        if s.startswith("%Error") or s.startswith("%Warning") or "syntax error" in s.lower() or "Internal Error" in s:
-            diag_lines.append(s)
-    if not diag_lines:
-        diag_lines = [x.strip() for x in raw.splitlines() if x.strip()][:12]
-    report["diagnostics"] = diag_lines[:12]
+        try:
+            completed = subprocess.run(cmd, capture_output=True, text=True, timeout=120, cwd=tmpdir)
+        except subprocess.TimeoutExpired:
+            report["timeout"] = True
+            report["compile_output"] = "TB compile gate timed out (>120s)."
+            report["issue_categories"] = ["compile_timeout"]
+            report["fingerprint"] = hashlib.sha256(report["compile_output"].encode("utf-8")).hexdigest()[:16]
+            return False, report
+        except FileNotFoundError:
+            report["compile_output"] = "Verilator binary not found."
+            report["issue_categories"] = ["verilator_missing"]
+            report["fingerprint"] = hashlib.sha256(report["compile_output"].encode("utf-8")).hexdigest()[:16]
+            return False, report
 
-    categories = set()
-    low = raw.lower()
-    if result.returncode == 0:
-        categories.add("compile_ok")
-    else:
-        if "internal error" in low:
-            categories.add("parser_internal_state_error")
-        if "syntax error" in low:
-            categories.add("syntax_error")
-        if ("_if" in raw and ("unexpected IDENTIFIER" in raw or "expecting ')'" in raw)) or (
-            "unexpected identifier" in low and "expecting ')'" in low
-        ):
-            categories.add("interface_typing_error")
-        if "function new" in low and "_if" in low:
-            categories.add("constructor_interface_type_error")
-        if "covergroup" in low or "coverpoint" in low:
-            categories.add("covergroup_scope_error")
-        if "pin not found" in low or "pinnotfound" in low:
-            categories.add("pin_mismatch")
-        # Missing interface definition (e.g. UVM-lite fallback references _if not in design)
-        if "cannot find" in low and "interface" in low:
-            categories.add("missing_interface")
-        # Dotted references to missing interfaces (cascade from above)
-        if "dotted reference" in low and ("missing module" in low or "missing interface" in low):
-            categories.add("dotted_ref_missing_interface")
-        if not categories:
-            categories.add("compile_error")
-    report["issue_categories"] = sorted(categories)
-
-    fp_base = "|".join(report["issue_categories"]) + "|" + "\n".join(report["diagnostics"][:6])
-    report["fingerprint"] = hashlib.sha256(fp_base.encode("utf-8", errors="ignore")).hexdigest()[:16]
-    report["ok"] = result.returncode == 0
+        tool_result = _build_tool_result(
+            "verilator",
+            ok=completed.returncode == 0,
+            result="PASS" if completed.returncode == 0 else "FAIL",
+            returncode=completed.returncode,
+            stdout=completed.stdout,
+            stderr=completed.stderr,
+            diagnostics=_collect_diag_lines(((completed.stdout or "") + "\n" + (completed.stderr or "")).strip()),
+            metrics={"mode": "tb_compile_gate"},
+        )
+        tool_result = _rewrite_result_paths(tool_result, staged_map)
+        raw = ((tool_result["stdout"] or "") + ("\n" + tool_result["stderr"] if tool_result["stderr"] else "")).strip()
+        report.update(tool_result)
+        report["returncode"] = tool_result["returncode"]
+        report["compile_output"] = raw[:16000]
+        report["diagnostics"] = list(tool_result["diagnostics"])[:12]
+
+        categories = set()
+        low = raw.lower()
+        if completed.returncode == 0:
+            categories.add("compile_ok")
+        else:
+            if "internal error" in low:
+                categories.add("parser_internal_state_error")
+            if "syntax error" in low:
+                categories.add("syntax_error")
+            if ("_if" in raw and ("unexpected IDENTIFIER" in raw or "expecting ')'" in raw)) or (
+                "unexpected identifier" in low and "expecting ')'" in low
+            ):
+                categories.add("interface_typing_error")
+            if "function new" in low and "_if" in low:
+                categories.add("constructor_interface_type_error")
+            if "covergroup" in low or "coverpoint" in low:
+                categories.add("covergroup_scope_error")
+            if "pin not found" in low or "pinnotfound" in low:
+                categories.add("pin_mismatch")
+            if "cannot find" in low and "interface" in low:
+                categories.add("missing_interface")
+            if "dotted reference" in low and ("missing module" in low or "missing interface" in low):
+                categories.add("dotted_ref_missing_interface")
+            if not categories:
+                categories.add("compile_error")
+        report["issue_categories"] = sorted(categories)
+
+        fp_base = "|".join(report["issue_categories"]) + "|" + "\n".join(report["diagnostics"][:6])
+        report["fingerprint"] = hashlib.sha256(fp_base.encode("utf-8", errors="ignore")).hexdigest()[:16]
+        report["ok"] = completed.returncode == 0
 
     # --- iverilog fallback ---
     # If Verilator rejects the TB (especially for interface/class issues),
@@ -1732,23 +1928,39 @@ def run_tb_compile_gate(design_name: str, tb_path: str, rtl_path: str) -> Tuple[
 
 def _iverilog_compile_tb(tb_path: str, rtl_path: str, design_name: str) -> Tuple[bool, str]:
     """Try compiling TB + RTL with iverilog as a Verilator fallback."""
-    import glob
     src_dir = os.path.dirname(rtl_path)
-    all_rtl = [f for f in glob.glob(os.path.join(src_dir, "*.v")) + glob.glob(os.path.join(src_dir, "*.sv"))
-               if not f.endswith("_tb.v") and "regression" not in f]
-    if rtl_path not in all_rtl and os.path.exists(rtl_path):
+    all_rtl = _collect_design_rtl(src_dir)
+    if rtl_path not in all_rtl:
         all_rtl.append(rtl_path)
-    cmd = ["iverilog", "-g2012", "-Wall", "-o", "/dev/null", *all_rtl, tb_path]
-    try:
-        result = subprocess.run(cmd, capture_output=True, text=True, timeout=60)
-        combined = (result.stdout + "\n" + result.stderr).strip()
-        if result.returncode == 0:
-            return True, f"iverilog compile OK: {combined[:500]}" if combined else "iverilog compile OK"
-        return False, f"iverilog compile failed:\n{combined[:2000]}"
-    except FileNotFoundError:
-        return False, "iverilog not found"
-    except subprocess.TimeoutExpired:
-        return False, "iverilog compile timed out"
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, all_rtl + [tb_path])
+        out_path = os.path.join(tmpdir, f"{design_name}_tb_compile.out")
+        cmd = [
+            "iverilog", "-g2012", "-Wall", "-o", out_path,
+            *[os.path.basename(_stage_path(path, staged_map)) for path in all_rtl],
+            os.path.basename(_stage_path(tb_path, staged_map)),
+        ]
+        try:
+            completed = subprocess.run(cmd, capture_output=True, text=True, timeout=60, cwd=tmpdir)
+            tool_result = _build_tool_result(
+                "iverilog",
+                ok=completed.returncode == 0,
+                result="PASS" if completed.returncode == 0 else "FAIL",
+                returncode=completed.returncode,
+                stdout=completed.stdout,
+                stderr=completed.stderr,
+                diagnostics=_collect_diag_lines(((completed.stdout or "") + "\n" + (completed.stderr or "")).strip()),
+                metrics={"mode": "tb_compile_gate"},
+            )
+            tool_result = _rewrite_result_paths(tool_result, staged_map)
+            combined = ((tool_result["stdout"] or "") + "\n" + (tool_result["stderr"] or "")).strip()
+            if tool_result["ok"]:
+                return True, f"iverilog compile OK: {combined[:500]}" if combined else "iverilog compile OK"
+            return False, f"iverilog compile failed:\n{combined[:2000]}"
+        except FileNotFoundError:
+            return False, "iverilog not found"
+        except subprocess.TimeoutExpired:
+            return False, "iverilog compile timed out"
 
 
 # ---------------------------------------------------------------------------
@@ -2285,57 +2497,87 @@ def run_simulation(design_name: str) -> tuple:
         return False, f"RTL file not found: {rtl_file}"
     if not os.path.exists(tb_file):
         return False, f"Testbench file not found: {tb_file}"
-    
-    import glob
-    rtl_files = [f for f in glob.glob(os.path.join(src_dir, "*.v")) + glob.glob(os.path.join(src_dir, "*.sv"))
-                 if not f.endswith("_tb.v") and "regression" not in f]
 
-    # Compile & Build using Verilator --binary
-    # --binary: Build a binary executable
-    # -j 0: Use all cores
-    # --timing: Enable timing support (essential for delays like #5)
-    # --assert: Enable assertions
-    cmd = [
-        "verilator",
-        "--binary",
-        "--sv",
-        "-j", "0",
-        "--timing",
-        "--assert",
-        "-Wno-fatal", # Don't error out on warnings
-        *rtl_files, tb_file,
-        "--top-module", f"{design_name}_tb",
-        "--Mdir", obj_dir,
-        "-o", "sim_exec"
-    ]
-    
-    try:
-        compile_result = subprocess.run(
-            cmd,
-            capture_output=True, text=True,
-            timeout=120
+    rtl_files = _collect_design_rtl(src_dir)
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, rtl_files + [tb_file])
+        cmd = [
+            "verilator",
+            "--binary",
+            "--sv",
+            "-j", "0",
+            "--timing",
+            "--trace",
+            "--assert",
+            "-Wno-fatal",
+            *[os.path.basename(_stage_path(path, staged_map)) for path in rtl_files],
+            os.path.basename(_stage_path(tb_file, staged_map)),
+            "--top-module", f"{design_name}_tb",
+            "--Mdir", "obj_dir",
+            "-o", "sim_exec",
+        ]
+
+        try:
+            compile_result = subprocess.run(
+                cmd,
+                capture_output=True,
+                text=True,
+                timeout=120,
+                cwd=tmpdir,
+            )
+        except subprocess.TimeoutExpired:
+            return False, "Compilation timed out (>120s)."
+        except FileNotFoundError:
+            return False, "Verilator not found. Please install Verilator 5.0+."
+
+        compile_tool = _rewrite_result_paths(
+            _build_tool_result(
+                "verilator",
+                ok=compile_result.returncode == 0,
+                result="PASS" if compile_result.returncode == 0 else "FAIL",
+                returncode=compile_result.returncode,
+                stdout=compile_result.stdout,
+                stderr=compile_result.stderr,
+                diagnostics=_collect_diag_lines((compile_result.stderr or compile_result.stdout or "").strip()),
+                metrics={"mode": "simulation_compile"},
+            ),
+            staged_map,
         )
-    except subprocess.TimeoutExpired:
-        return False, "Compilation timed out (>120s)."
-    except FileNotFoundError:
-        return False, "Verilator not found. Please install Verilator 5.0+."
-        
-    if compile_result.returncode != 0:
-        return False, f"Verilator Compilation Failed:\n{compile_result.stderr}"
-    
-    # Run the generated binary
-    sim_exec_path = f"{obj_dir}/sim_exec"
-    try:
-        run_result = subprocess.run(
-            [sim_exec_path],
-            capture_output=True,
-            text=True,
-            timeout=300 
+        if compile_result.returncode != 0:
+            return False, f"Verilator Compilation Failed:\n{compile_tool['stderr']}"
+
+        sim_exec_path = os.path.join(tmpdir, "obj_dir", "sim_exec")
+        try:
+            run_result = subprocess.run(
+                [sim_exec_path],
+                capture_output=True,
+                text=True,
+                timeout=300,
+                cwd=tmpdir,
+            )
+        except subprocess.TimeoutExpired:
+            return False, "Simulation Timed Out (Exceeded 300s). Infinite loop likely."
+
+        _promote_vcd_artifacts(tmpdir, src_dir)
+        promoted_wave = os.path.join(src_dir, f"{design_name}_wave.vcd")
+        run_tool = _rewrite_result_paths(
+            _build_tool_result(
+                "verilator",
+                ok=run_result.returncode == 0,
+                result="PASS" if run_result.returncode == 0 else "FAIL",
+                returncode=run_result.returncode,
+                stdout=run_result.stdout,
+                stderr=run_result.stderr,
+                diagnostics=_collect_diag_lines(((run_result.stdout or "") + "\n" + (run_result.stderr or "")).strip(), limit=20),
+                metrics={
+                    "mode": "simulation_run",
+                    "trace_enabled": True,
+                    "waveform_generated": os.path.exists(promoted_wave),
+                },
+            ),
+            staged_map,
         )
-    except subprocess.TimeoutExpired:
-        return False, "Simulation Timed Out (Exceeded 300s). Infinite loop likely."
-    
-    sim_text = (run_result.stdout or "") + ("\n" + run_result.stderr if run_result.stderr else "")
+        sim_text = (run_tool["stdout"] or "") + ("\n" + run_tool["stderr"] if run_tool["stderr"] else "")
 
     if "TEST PASSED" in sim_text:
         return True, sim_text
@@ -2343,7 +2585,7 @@ def run_simulation(design_name: str) -> tuple:
     if "TEST FAILED" in sim_text:
         return False, sim_text
 
-    if run_result.returncode != 0:
+    if run_tool["returncode"] != 0:
         return False, f"Simulation Crashed:\n{sim_text}"
         
     return False, sim_text
@@ -2524,33 +2766,70 @@ def run_gls_simulation(design_name: str) -> tuple:
 
     primitives_v = os.path.join(os.path.dirname(pdk_v_path), "primitives.v")
 
-    # Compile GLS
-    try:
-        cmd = ["iverilog", "-g2012", "-DFUNCTIONAL", "-DUNIT_DELAY=#1", "-o", sim_out, tb_file, gl_netlist, pdk_v_path, primitives_v]
-        compile_result = subprocess.run(
-            cmd,
-            capture_output=True, text=True,
-            timeout=300
-        )
-        if compile_result.returncode != 0:
-            return False, f"GLS Compilation failed:\n{compile_result.stderr}"
-    except subprocess.TimeoutExpired:
-        return False, "GLS Compilation timed out."
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, [tb_file, gl_netlist])
+        sim_out = os.path.join(tmpdir, "gls_sim")
+        try:
+            cmd = [
+                "iverilog", "-g2012", "-DFUNCTIONAL", "-DUNIT_DELAY=#1", "-o", sim_out,
+                os.path.basename(_stage_path(tb_file, staged_map)),
+                os.path.basename(_stage_path(gl_netlist, staged_map)),
+                pdk_v_path,
+                primitives_v,
+            ]
+            compile_result = subprocess.run(
+                cmd,
+                capture_output=True,
+                text=True,
+                timeout=300,
+                cwd=tmpdir,
+            )
+            compile_tool = _rewrite_result_paths(
+                _build_tool_result(
+                    "iverilog",
+                    ok=compile_result.returncode == 0,
+                    result="PASS" if compile_result.returncode == 0 else "FAIL",
+                    returncode=compile_result.returncode,
+                    stdout=compile_result.stdout,
+                    stderr=compile_result.stderr,
+                    diagnostics=_collect_diag_lines(((compile_result.stdout or "") + "\n" + (compile_result.stderr or "")).strip()),
+                    metrics={"mode": "gls_compile"},
+                ),
+                staged_map,
+            )
+            if compile_result.returncode != 0:
+                return False, f"GLS Compilation failed:\n{compile_tool['stderr']}"
+        except subprocess.TimeoutExpired:
+            return False, "GLS Compilation timed out."
 
-    # Run GLS Simulation
-    try:
-        run_result = subprocess.run(
-            ["vvp", sim_out],
-            capture_output=True,
-            text=True,
-            timeout=600
-        )
-        sim_text = (run_result.stdout or "") + ("\n" + run_result.stderr if run_result.stderr else "")
-        if "TEST PASSED" in sim_text:
-            return True, f"GLS Simulation PASSED.\n{sim_text}"
-        return False, f"GLS Simulation FAILED or missing PASS marker.\n{sim_text}"
-    except subprocess.TimeoutExpired:
-        return False, "GLS Simulation Timed Out."
+        try:
+            run_result = subprocess.run(
+                ["vvp", sim_out],
+                capture_output=True,
+                text=True,
+                timeout=600,
+                cwd=tmpdir,
+            )
+            _promote_vcd_artifacts(tmpdir, src_dir)
+            run_tool = _rewrite_result_paths(
+                _build_tool_result(
+                    "vvp",
+                    ok=run_result.returncode == 0,
+                    result="PASS" if run_result.returncode == 0 else "FAIL",
+                    returncode=run_result.returncode,
+                    stdout=run_result.stdout,
+                    stderr=run_result.stderr,
+                    diagnostics=_collect_diag_lines(((run_result.stdout or "") + "\n" + (run_result.stderr or "")).strip(), limit=20),
+                    metrics={"mode": "gls_run"},
+                ),
+                staged_map,
+            )
+            sim_text = (run_tool["stdout"] or "") + ("\n" + run_tool["stderr"] if run_tool["stderr"] else "")
+            if "TEST PASSED" in sim_text:
+                return True, f"GLS Simulation PASSED.\n{sim_text}"
+            return False, f"GLS Simulation FAILED or missing PASS marker.\n{sim_text}"
+        except subprocess.TimeoutExpired:
+            return False, "GLS Simulation Timed Out."
 
 
 def parse_eda_log_summary(log_path: str, kind: str, top_n: int = 10) -> Dict[str, Any]:
@@ -2802,6 +3081,12 @@ def get_coverage_thresholds(profile: str) -> Dict[str, float]:
 def _coverage_shell(design_name: str, backend: str, coverage_mode: str = "full_oss") -> Dict[str, Any]:
     return {
         "ok": False,
+        "tool": backend,
+        "returncode": -1,
+        "stdout": "",
+        "stderr": "",
+        "result": "ERROR",
+        "metrics": {},
         "backend": backend,
         "coverage_mode": coverage_mode,
         "infra_failure": False,
@@ -2853,42 +3138,43 @@ def _parse_verilator_coverage_dat(cov_dat: str, src_dir: str) -> Dict[str, float
     data = {"line_pct": 0.0, "toggle_pct": 0.0, "branch_pct": 0.0, "overall_pct": 0.0}
     if not os.path.exists(cov_dat):
         return data
-    annotate_dir = os.path.join(src_dir, "cov_annotate")
-    try:
-        os.makedirs(annotate_dir, exist_ok=True)
-        subprocess.run(
-            ["verilator_coverage", "--annotate", annotate_dir, cov_dat],
-            capture_output=True,
-            text=True,
-            timeout=60,
-        )
-    except Exception:
-        pass
-
-    total_points = 0
-    hit_points = 0
-    toggle_points = 0
-    toggle_hit = 0
-    if os.path.exists(annotate_dir):
-        for root, _, files in os.walk(annotate_dir):
-            for fname in files:
-                if not fname.endswith((".v", ".sv")):
-                    continue
-                with open(os.path.join(root, fname), "r", errors="ignore") as f:
-                    for line in f:
-                        s = line.strip()
-                        if not s:
-                            continue
-                        m = re.match(r"^(\d+)\s+", s)
-                        if m:
-                            total_points += 1
-                            if int(m.group(1)) > 0:
-                                hit_points += 1
-                        if s.startswith("%"):
-                            toggle_points += 1
-                            p = re.match(r"%0*(\d+)", s)
-                            if p and int(p.group(1)) > 0:
-                                toggle_hit += 1
+    with tempfile.TemporaryDirectory() as tmpdir:
+        annotate_dir = os.path.join(tmpdir, "cov_annotate")
+        try:
+            os.makedirs(annotate_dir, exist_ok=True)
+            subprocess.run(
+                ["verilator_coverage", "--annotate", annotate_dir, cov_dat],
+                capture_output=True,
+                text=True,
+                timeout=60,
+            )
+        except Exception:
+            pass
+
+        total_points = 0
+        hit_points = 0
+        toggle_points = 0
+        toggle_hit = 0
+        if os.path.exists(annotate_dir):
+            for root, _, files in os.walk(annotate_dir):
+                for fname in files:
+                    if not fname.endswith((".v", ".sv")):
+                        continue
+                    with open(os.path.join(root, fname), "r", errors="ignore") as f:
+                        for line in f:
+                            s = line.strip()
+                            if not s:
+                                continue
+                            m = re.match(r"^(\d+)\s+", s)
+                            if m:
+                                total_points += 1
+                                if int(m.group(1)) > 0:
+                                    hit_points += 1
+                            if s.startswith("%"):
+                                toggle_points += 1
+                                p = re.match(r"%0*(\d+)", s)
+                                if p and int(p.group(1)) > 0:
+                                    toggle_hit += 1
 
     if total_points > 0:
         data["line_pct"] = round((hit_points / total_points) * 100.0, 2)
@@ -2903,12 +3189,9 @@ def _parse_verilator_coverage_dat(cov_dat: str, src_dir: str) -> Dict[str, float
 
 def run_verilator_coverage(design_name: str, rtl_file: str, tb_file: str, coverage_mode: str = "full_oss") -> Tuple[bool, str, Dict[str, Any]]:
     src_dir = os.path.dirname(rtl_file)
-    obj_dir = os.path.join(src_dir, "obj_dir_cov")
     sim_exec = "sim_cov_exec"
-    cov_dat = os.path.join(src_dir, "coverage.dat")
-    diag_path = os.path.join(src_dir, f"{design_name}_coverage_verilator.log")
     result = _coverage_shell(design_name, backend="verilator", coverage_mode=coverage_mode)
-    result["raw_diag_path"] = diag_path
+    result["raw_diag_path"] = ""
 
     if not os.path.exists(rtl_file):
         result["infra_failure"] = True
@@ -2924,126 +3207,165 @@ def run_verilator_coverage(design_name: str, rtl_file: str, tb_file: str, covera
     signals, rtl_line_count = _read_rtl_signal_stats(rtl_file)
     result["total_signals"] = len(signals)
     signal_set = set(signals)
-
-    if os.path.exists(cov_dat):
+    rtl_files = _collect_design_rtl(src_dir)
+
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, rtl_files + [tb_file])
+        cov_dat = os.path.join(tmpdir, "coverage.dat")
+        compile_cmd = [
+            "verilator",
+            "--binary",
+            "--coverage",
+            "--trace",
+            "--sv",
+            "--timing",
+            "-Wno-fatal",
+            *[os.path.basename(_stage_path(path, staged_map)) for path in rtl_files],
+            os.path.basename(_stage_path(tb_file, staged_map)),
+            "--top-module",
+            f"{design_name}_tb",
+            "--Mdir",
+            "obj_dir_cov",
+            "-o",
+            sim_exec,
+        ]
+        run_cmd = [os.path.join(tmpdir, "obj_dir_cov", sim_exec), f"+verilator+coverage+file+{cov_dat}"]
         try:
-            os.remove(cov_dat)
-        except OSError:
-            pass
-
-    import glob
-    rtl_files = [f for f in glob.glob(os.path.join(src_dir, "*.v")) + glob.glob(os.path.join(src_dir, "*.sv"))
-                 if not f.endswith("_tb.v") and "regression" not in f]
-
-    compile_cmd = [
-        "verilator",
-        "--binary",
-        "--coverage",
-        "--sv",
-        "--timing",
-        "-Wno-fatal",
-        *rtl_files,
-        tb_file,
-        "--top-module",
-        f"{design_name}_tb",
-        "--Mdir",
-        obj_dir,
-        "-o",
-        sim_exec,
-    ]
-    run_cmd = [os.path.join(obj_dir, sim_exec), f"+verilator+coverage+file+{cov_dat}"]
-    try:
-        comp = subprocess.run(compile_cmd, capture_output=True, text=True, timeout=240, cwd=src_dir)
-    except FileNotFoundError:
-        result["infra_failure"] = True
-        result["error_kind"] = "tool_missing"
-        result["diagnostics"] = ["verilator binary not found."]
-        return False, result["diagnostics"][0], result
-    except subprocess.TimeoutExpired:
-        result["infra_failure"] = True
-        result["error_kind"] = "compile_timeout"
-        result["diagnostics"] = ["Verilator coverage compile timed out (>240s)."]
-        return False, result["diagnostics"][0], result
-
-    if comp.returncode != 0:
-        result["infra_failure"] = True
-        result["error_kind"] = "compile_error"
-        result["diagnostics"] = [x.strip() for x in (comp.stderr or comp.stdout or "").splitlines() if x.strip()][:12]
-        with open(diag_path, "w") as f:
-            f.write(f"COMMAND: {' '.join(compile_cmd)}\n\n{comp.stdout}\n{comp.stderr}\n")
-        return False, (comp.stderr or comp.stdout or "Verilator compile failed")[:1200], result
-
-    try:
-        run = subprocess.run(run_cmd, capture_output=True, text=True, timeout=300, cwd=src_dir)
-    except subprocess.TimeoutExpired:
-        result["infra_failure"] = True
-        result["error_kind"] = "run_timeout"
-        result["diagnostics"] = ["Verilator coverage simulation timed out (>300s)."]
-        return False, result["diagnostics"][0], result
+            comp = subprocess.run(compile_cmd, capture_output=True, text=True, timeout=240, cwd=tmpdir)
+        except FileNotFoundError:
+            result["infra_failure"] = True
+            result["error_kind"] = "tool_missing"
+            result["diagnostics"] = ["verilator binary not found."]
+            return False, result["diagnostics"][0], result
+        except subprocess.TimeoutExpired:
+            result["infra_failure"] = True
+            result["error_kind"] = "compile_timeout"
+            result["diagnostics"] = ["Verilator coverage compile timed out (>240s)."]
+            return False, result["diagnostics"][0], result
+
+        comp_tool = _rewrite_result_paths(
+            _build_tool_result(
+                "verilator",
+                ok=comp.returncode == 0,
+                result="PASS" if comp.returncode == 0 else "FAIL",
+                returncode=comp.returncode,
+                stdout=comp.stdout,
+                stderr=comp.stderr,
+                diagnostics=_collect_diag_lines((comp.stderr or comp.stdout or "").strip()),
+                metrics={"mode": "coverage_compile"},
+            ),
+            staged_map,
+        )
+        result.update(
+            {
+                "tool": comp_tool["tool"],
+                "returncode": comp_tool["returncode"],
+                "stdout": comp_tool["stdout"],
+                "stderr": comp_tool["stderr"],
+                "result": comp_tool["result"],
+                "metrics": dict(comp_tool["metrics"]),
+                "trace_enabled": True,
+            }
+        )
+        if comp.returncode != 0:
+            result["infra_failure"] = True
+            result["error_kind"] = "compile_error"
+            result["diagnostics"] = list(comp_tool["diagnostics"])[:12]
+            return False, ((comp_tool["stderr"] or comp_tool["stdout"] or "Verilator compile failed")[:1200]), result
 
-    sim_text = (run.stdout or "") + ("\n" + run.stderr if run.stderr else "")
-    sim_passed = "TEST PASSED" in sim_text
-    with open(diag_path, "w") as f:
-        f.write(f"COMPILE: {' '.join(compile_cmd)}\n")
-        f.write(f"RUN: {' '.join(run_cmd)}\n\n")
-        f.write(sim_text[:20000])
+        try:
+            run = subprocess.run(run_cmd, capture_output=True, text=True, timeout=300, cwd=tmpdir)
+        except subprocess.TimeoutExpired:
+            result["infra_failure"] = True
+            result["error_kind"] = "run_timeout"
+            result["diagnostics"] = ["Verilator coverage simulation timed out (>300s)."]
+            return False, result["diagnostics"][0], result
+
+        _promote_vcd_artifacts(tmpdir, src_dir)
+        result["waveform_generated"] = os.path.exists(os.path.join(src_dir, f"{design_name}_wave.vcd"))
+        run_tool = _rewrite_result_paths(
+            _build_tool_result(
+                "verilator",
+                ok=run.returncode == 0,
+                result="PASS" if run.returncode == 0 else "FAIL",
+                returncode=run.returncode,
+                stdout=run.stdout,
+                stderr=run.stderr,
+                diagnostics=_collect_diag_lines(((run.stdout or "") + "\n" + (run.stderr or "")).strip(), limit=20),
+                metrics={"mode": "coverage_run"},
+            ),
+            staged_map,
+        )
+        sim_text = (run_tool["stdout"] or "") + ("\n" + run_tool["stderr"] if run_tool["stderr"] else "")
+        sim_passed = "TEST PASSED" in sim_text
+        result.update(
+            {
+                "tool": run_tool["tool"],
+                "returncode": run_tool["returncode"],
+                "stdout": run_tool["stdout"],
+                "stderr": run_tool["stderr"],
+                "result": "PASS" if sim_passed else ("FAIL" if run.returncode != 0 else "ERROR"),
+                "metrics": dict(run_tool["metrics"]),
+                "coverage_metrics_valid": False,
+            }
+        )
 
-    metrics = _parse_verilator_coverage_dat(cov_dat, src_dir)
-    if not os.path.exists(cov_dat):
-        result["infra_failure"] = True
-        result["error_kind"] = "parse_error"
-        result["diagnostics"] = ["coverage.dat not generated by Verilator run."]
+        metrics = _parse_verilator_coverage_dat(cov_dat, tmpdir)
+        if not os.path.exists(cov_dat):
+            result["infra_failure"] = True
+            result["error_kind"] = "parse_error"
+            result["diagnostics"] = ["coverage.dat not generated by Verilator run."]
+            return sim_passed, sim_text, result
+
+        vcd_candidates = [
+            os.path.join(src_dir, f"{design_name}_cov.vcd"),
+            os.path.join(src_dir, f"{design_name}.vcd"),
+            os.path.join(src_dir, "dump.vcd"),
+        ]
+        toggled = 0
+        for vcd in vcd_candidates:
+            if os.path.exists(vcd):
+                toggled = max(toggled, _extract_vcd_toggles(vcd, signal_set))
+        result["signals_toggled"] = toggled
+
+        line_pct = metrics["line_pct"]
+        toggle_pct = metrics["toggle_pct"]
+        branch_pct = metrics["branch_pct"]
+        if toggle_pct <= 0.0 and result["total_signals"] > 0:
+            toggle_pct = round((toggled / result["total_signals"]) * 100.0, 2)
+        functional_pct = round((line_pct * 0.6 + toggle_pct * 0.4), 2) if sim_passed else round((line_pct * 0.3), 2)
+        assertion_pct = 100.0 if sim_passed else 0.0
+
+        result.update(
+            {
+                "ok": True,
+                "line_pct": max(0.0, min(100.0, line_pct)),
+                "branch_pct": max(0.0, min(100.0, branch_pct)),
+                "toggle_pct": max(0.0, min(100.0, toggle_pct)),
+                "functional_pct": max(0.0, min(100.0, functional_pct)),
+                "assertion_pct": assertion_pct,
+                "report_path": "",
+            }
+        )
+        if run.returncode != 0 and not sim_passed:
+            result["ok"] = False
+            result["infra_failure"] = True
+            result["error_kind"] = "run_error"
+            result["diagnostics"] = [x.strip() for x in sim_text.splitlines() if x.strip()][:10]
+        elif rtl_line_count > 0 and result["line_pct"] <= 0.0 and sim_passed:
+            result["ok"] = False
+            result["infra_failure"] = True
+            result["error_kind"] = "parse_error"
+            result["diagnostics"] = ["Coverage metrics are empty despite passing simulation."]
+        else:
+            result["coverage_metrics_valid"] = True
         return sim_passed, sim_text, result
 
-    vcd_candidates = [
-        os.path.join(src_dir, f"{design_name}_cov.vcd"),
-        os.path.join(src_dir, f"{design_name}.vcd"),
-        os.path.join(src_dir, "dump.vcd"),
-    ]
-    toggled = 0
-    for vcd in vcd_candidates:
-        if os.path.exists(vcd):
-            toggled = max(toggled, _extract_vcd_toggles(vcd, signal_set))
-    result["signals_toggled"] = toggled
-
-    line_pct = metrics["line_pct"]
-    toggle_pct = metrics["toggle_pct"]
-    branch_pct = metrics["branch_pct"]
-    if toggle_pct <= 0.0 and result["total_signals"] > 0:
-        toggle_pct = round((toggled / result["total_signals"]) * 100.0, 2)
-    functional_pct = round((line_pct * 0.6 + toggle_pct * 0.4), 2) if sim_passed else round((line_pct * 0.3), 2)
-    assertion_pct = 100.0 if sim_passed else 0.0
-
-    result.update(
-        {
-            "ok": True,
-            "line_pct": max(0.0, min(100.0, line_pct)),
-            "branch_pct": max(0.0, min(100.0, branch_pct)),
-            "toggle_pct": max(0.0, min(100.0, toggle_pct)),
-            "functional_pct": max(0.0, min(100.0, functional_pct)),
-            "assertion_pct": assertion_pct,
-            "report_path": cov_dat,
-        }
-    )
-    if run.returncode != 0 and not sim_passed:
-        result["ok"] = False
-        result["infra_failure"] = True
-        result["error_kind"] = "run_error"
-        result["diagnostics"] = [x.strip() for x in sim_text.splitlines() if x.strip()][:10]
-    elif rtl_line_count > 0 and result["line_pct"] <= 0.0 and sim_passed:
-        result["ok"] = False
-        result["infra_failure"] = True
-        result["error_kind"] = "parse_error"
-        result["diagnostics"] = ["Coverage metrics are empty despite passing simulation."]
-    return sim_passed, sim_text, result
-
 
 def run_iverilog_coverage(design_name: str, rtl_file: str, tb_file: str, coverage_mode: str = "full_oss") -> Tuple[bool, str, Dict[str, Any]]:
     src_dir = os.path.dirname(rtl_file)
-    sim_out = os.path.join(src_dir, "sim_cov")
-    diag_path = os.path.join(src_dir, f"{design_name}_coverage_iverilog.log")
     result = _coverage_shell(design_name, backend="iverilog", coverage_mode=coverage_mode)
-    result["raw_diag_path"] = diag_path
+    result["raw_diag_path"] = ""
 
     with open(tb_file, "r", errors="ignore") as f:
         tb_code = f.read()
@@ -3052,96 +3374,150 @@ def run_iverilog_coverage(design_name: str, rtl_file: str, tb_file: str, coverag
     result["total_signals"] = len(signals)
     signal_set = set(signals)
 
-    import glob
-    rtl_files = [f for f in glob.glob(os.path.join(src_dir, "*.v")) if not f.endswith("_tb.v") and "regression" not in f]
-
-    compile_cmd = ["iverilog", "-g2012", "-o", sim_out, *rtl_files, tb_file]
-    try:
-        comp = subprocess.run(compile_cmd, capture_output=True, text=True, timeout=120, cwd=src_dir)
-    except FileNotFoundError:
-        result["infra_failure"] = True
-        result["error_kind"] = "tool_missing"
-        result["diagnostics"] = ["iverilog binary not found."]
-        return False, result["diagnostics"][0], result
-    except subprocess.TimeoutExpired:
-        result["infra_failure"] = True
-        result["error_kind"] = "compile_timeout"
-        result["diagnostics"] = ["Icarus compile timed out (>120s)."]
-        return False, result["diagnostics"][0], result
+    rtl_files = _collect_design_rtl(src_dir, include_sv=False)
 
-    if comp.returncode != 0:
-        result["infra_failure"] = True
-        result["error_kind"] = "compile_error"
-        result["diagnostics"] = [x.strip() for x in (comp.stderr or comp.stdout or "").splitlines() if x.strip()][:12]
-        if tb_style == "sv_class_based":
-            result["error_kind"] = "unsupported_tb_style"
-            result["diagnostics"].insert(0, "Class-based SV testbench is not supported by iVerilog coverage backend.")
-        with open(diag_path, "w") as f:
-            f.write(f"COMMAND: {' '.join(compile_cmd)}\n\n{comp.stdout}\n{comp.stderr}\n")
-        return False, (comp.stderr or comp.stdout or "Icarus compile failed")[:1200], result
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, rtl_files + [tb_file])
+        sim_out = os.path.join(tmpdir, "sim_cov")
+        compile_cmd = [
+            "iverilog", "-g2012", "-o", sim_out,
+            *[os.path.basename(_stage_path(path, staged_map)) for path in rtl_files],
+            os.path.basename(_stage_path(tb_file, staged_map)),
+        ]
+        try:
+            comp = subprocess.run(compile_cmd, capture_output=True, text=True, timeout=120, cwd=tmpdir)
+        except FileNotFoundError:
+            result["infra_failure"] = True
+            result["error_kind"] = "tool_missing"
+            result["diagnostics"] = ["iverilog binary not found."]
+            return False, result["diagnostics"][0], result
+        except subprocess.TimeoutExpired:
+            result["infra_failure"] = True
+            result["error_kind"] = "compile_timeout"
+            result["diagnostics"] = ["Icarus compile timed out (>120s)."]
+            return False, result["diagnostics"][0], result
+
+        comp_tool = _rewrite_result_paths(
+            _build_tool_result(
+                "iverilog",
+                ok=comp.returncode == 0,
+                result="PASS" if comp.returncode == 0 else "FAIL",
+                returncode=comp.returncode,
+                stdout=comp.stdout,
+                stderr=comp.stderr,
+                diagnostics=_collect_diag_lines(((comp.stdout or "") + "\n" + (comp.stderr or "")).strip()),
+                metrics={"mode": "coverage_compile"},
+            ),
+            staged_map,
+        )
+        result.update(
+            {
+                "tool": comp_tool["tool"],
+                "returncode": comp_tool["returncode"],
+                "stdout": comp_tool["stdout"],
+                "stderr": comp_tool["stderr"],
+                "result": comp_tool["result"],
+                "metrics": dict(comp_tool["metrics"]),
+                "trace_enabled": True,
+            }
+        )
+        if comp.returncode != 0:
+            result["infra_failure"] = True
+            result["error_kind"] = "compile_error"
+            result["diagnostics"] = list(comp_tool["diagnostics"])[:12]
+            if tb_style == "sv_class_based":
+                result["error_kind"] = "unsupported_tb_style"
+                result["diagnostics"].insert(0, "Class-based SV testbench is not supported by iVerilog coverage backend.")
+            return False, ((comp_tool["stderr"] or comp_tool["stdout"] or "Icarus compile failed")[:1200]), result
 
-    try:
-        run = subprocess.run(["vvp", sim_out], capture_output=True, text=True, timeout=300, cwd=src_dir)
-    except subprocess.TimeoutExpired:
-        result["infra_failure"] = True
-        result["error_kind"] = "run_timeout"
-        result["diagnostics"] = ["Icarus simulation timed out (>300s)."]
-        return False, result["diagnostics"][0], result
-    except FileNotFoundError:
-        result["infra_failure"] = True
-        result["error_kind"] = "tool_missing"
-        result["diagnostics"] = ["vvp binary not found."]
-        return False, result["diagnostics"][0], result
+        try:
+            run = subprocess.run(["vvp", sim_out], capture_output=True, text=True, timeout=300, cwd=tmpdir)
+        except subprocess.TimeoutExpired:
+            result["infra_failure"] = True
+            result["error_kind"] = "run_timeout"
+            result["diagnostics"] = ["Icarus simulation timed out (>300s)."]
+            return False, result["diagnostics"][0], result
+        except FileNotFoundError:
+            result["infra_failure"] = True
+            result["error_kind"] = "tool_missing"
+            result["diagnostics"] = ["vvp binary not found."]
+            return False, result["diagnostics"][0], result
+
+        _promote_vcd_artifacts(tmpdir, src_dir)
+        result["waveform_generated"] = os.path.exists(os.path.join(src_dir, f"{design_name}_wave.vcd"))
+        run_tool = _rewrite_result_paths(
+            _build_tool_result(
+                "iverilog",
+                ok=run.returncode == 0,
+                result="PASS" if run.returncode == 0 else "FAIL",
+                returncode=run.returncode,
+                stdout=run.stdout,
+                stderr=run.stderr,
+                diagnostics=_collect_diag_lines(((run.stdout or "") + "\n" + (run.stderr or "")).strip(), limit=20),
+                metrics={"mode": "coverage_run"},
+            ),
+            staged_map,
+        )
+        sim_text = (run_tool["stdout"] or "") + ("\n" + run_tool["stderr"] if run_tool["stderr"] else "")
+        sim_passed = "TEST PASSED" in sim_text
+        result.update(
+            {
+                "tool": run_tool["tool"],
+                "returncode": run_tool["returncode"],
+                "stdout": run_tool["stdout"],
+                "stderr": run_tool["stderr"],
+                "result": "PASS" if sim_passed else ("FAIL" if run.returncode != 0 else "ERROR"),
+                "metrics": dict(run_tool["metrics"]),
+                "coverage_metrics_valid": False,
+            }
+        )
 
-    sim_text = (run.stdout or "") + ("\n" + run.stderr if run.stderr else "")
-    sim_passed = "TEST PASSED" in sim_text
-    with open(diag_path, "w") as f:
-        f.write(sim_text[:20000])
-
-    toggled = 0
-    displayed_signals = set(re.findall(r'(\w+)\s*=\s*[0-9a-fxzXZhHbB_\']+', sim_text))
-    toggled = len(displayed_signals.intersection(signal_set))
-    vcd_candidates = [
-        os.path.join(src_dir, f"{design_name}_cov.vcd"),
-        os.path.join(src_dir, f"{design_name}.vcd"),
-        os.path.join(src_dir, "dump.vcd"),
-    ]
-    for vcd in vcd_candidates:
-        if os.path.exists(vcd):
-            toggled = max(toggled, _extract_vcd_toggles(vcd, signal_set))
-            break
-    result["signals_toggled"] = toggled
-
-    line_pct = 85.0 if sim_passed else 20.0
-    if result["total_signals"] > 0:
-        line_pct += (toggled / result["total_signals"]) * 15.0
-    line_pct = max(0.0, min(100.0, round(line_pct, 2)))
-    toggle_pct = round((toggled / result["total_signals"]) * 100.0, 2) if result["total_signals"] > 0 else 0.0
-    branch_pct = round(line_pct * 0.9, 2) if line_pct > 0 else 0.0
-    functional_pct = round((line_pct * 0.65 + toggle_pct * 0.35), 2) if sim_passed else round(line_pct * 0.3, 2)
-    assertion_pct = 100.0 if sim_passed else 0.0
-    result.update(
-        {
-            "ok": True,
-            "line_pct": line_pct,
-            "branch_pct": max(0.0, min(100.0, branch_pct)),
-            "toggle_pct": max(0.0, min(100.0, toggle_pct)),
-            "functional_pct": max(0.0, min(100.0, functional_pct)),
-            "assertion_pct": assertion_pct,
-            "report_path": diag_path,
-        }
-    )
-    if rtl_line_count > 0 and line_pct <= 0.0 and sim_passed:
-        result["ok"] = False
-        result["infra_failure"] = True
-        result["error_kind"] = "parse_error"
-        result["diagnostics"] = ["Coverage estimate collapsed to zero despite passing simulation."]
-    if run.returncode != 0 and not sim_passed:
-        result["ok"] = False
-        result["infra_failure"] = True
-        result["error_kind"] = "run_error"
-        result["diagnostics"] = [x.strip() for x in sim_text.splitlines() if x.strip()][:10]
-    return sim_passed, sim_text, result
+        toggled = 0
+        displayed_signals = set(re.findall(r'(\w+)\s*=\s*[0-9a-fxzXZhHbB_\']+', sim_text))
+        toggled = len(displayed_signals.intersection(signal_set))
+        vcd_candidates = [
+            os.path.join(src_dir, f"{design_name}_cov.vcd"),
+            os.path.join(src_dir, f"{design_name}.vcd"),
+            os.path.join(src_dir, "dump.vcd"),
+        ]
+        for vcd in vcd_candidates:
+            if os.path.exists(vcd):
+                toggled = max(toggled, _extract_vcd_toggles(vcd, signal_set))
+                break
+        result["signals_toggled"] = toggled
+
+        line_pct = 85.0 if sim_passed else 20.0
+        if result["total_signals"] > 0:
+            line_pct += (toggled / result["total_signals"]) * 15.0
+        line_pct = max(0.0, min(100.0, round(line_pct, 2)))
+        toggle_pct = round((toggled / result["total_signals"]) * 100.0, 2) if result["total_signals"] > 0 else 0.0
+        branch_pct = round(line_pct * 0.9, 2) if line_pct > 0 else 0.0
+        functional_pct = round((line_pct * 0.65 + toggle_pct * 0.35), 2) if sim_passed else round(line_pct * 0.3, 2)
+        assertion_pct = 100.0 if sim_passed else 0.0
+        result.update(
+            {
+                "ok": True,
+                "line_pct": line_pct,
+                "branch_pct": max(0.0, min(100.0, branch_pct)),
+                "toggle_pct": max(0.0, min(100.0, toggle_pct)),
+                "functional_pct": max(0.0, min(100.0, functional_pct)),
+                "assertion_pct": assertion_pct,
+                "report_path": "",
+            }
+        )
+        if rtl_line_count > 0 and line_pct <= 0.0 and sim_passed:
+            result["ok"] = False
+            result["infra_failure"] = True
+            result["error_kind"] = "parse_error"
+            result["diagnostics"] = ["Coverage estimate collapsed to zero despite passing simulation."]
+        else:
+            result["coverage_metrics_valid"] = True
+        if run.returncode != 0 and not sim_passed:
+            result["ok"] = False
+            result["infra_failure"] = True
+            result["error_kind"] = "run_error"
+            result["diagnostics"] = [x.strip() for x in sim_text.splitlines() if x.strip()][:10]
+        return sim_passed, sim_text, result
 
 
 def run_simulation_with_coverage(
@@ -3450,49 +3826,63 @@ def run_cdc_check(file_path: str) -> tuple:
     """
     if not os.path.exists(file_path):
         return False, f"File not found: {file_path}"
-    
-    cmd = [
-        "verilator", "--lint-only", "--timing",
-        "-Wall",
-        "-Wwarn-CDCRSTLOGIC",  # CDC reset logic warnings
-        file_path
-    ]
-    
-    try:
-        result = subprocess.run(
-            cmd,
-            capture_output=True, text=True,
-            timeout=60
-        )
-        
-        stderr = result.stderr or ""
-        
-        # Filter for CDC-specific warnings
-        cdc_warnings = []
-        all_warnings = []
-        for line in stderr.split('\n'):
-            if line.strip():
-                all_warnings.append(line)
-                if any(kw in line.upper() for kw in ['CDC', 'CLOCK', 'DOMAIN', 'SYNC', 'METASTAB', 'CDCRSTLOGIC']):
-                    cdc_warnings.append(line)
-        
-        if not cdc_warnings and result.returncode == 0:
-            return True, f"CDC Analysis: CLEAN (no clock domain crossing issues detected)\nFull lint output:\n{stderr[:1000]}"
-        elif cdc_warnings:
-            report = "CDC Analysis: WARNINGS FOUND\n\n"
-            report += "CDC-Related Issues:\n"
-            for w in cdc_warnings:
-                report += f"  - {w}\n"
-            report += f"\nTotal lint warnings: {len(all_warnings)}"
-            return False, report
-        else:
-            # Non-CDC lint errors
+
+    with tempfile.TemporaryDirectory() as tmpdir:
+        staged_map = _stage_inputs(tmpdir, [file_path])
+        staged_file = _stage_path(file_path, staged_map)
+        cmd = [
+            "verilator", "--lint-only", "--timing",
+            "-Wall",
+            "-Wwarn-CDCRSTLOGIC",
+            os.path.basename(staged_file),
+        ]
+
+        try:
+            completed = subprocess.run(
+                cmd,
+                capture_output=True,
+                text=True,
+                timeout=60,
+                cwd=tmpdir,
+            )
+            tool_result = _rewrite_result_paths(
+                _build_tool_result(
+                    "verilator",
+                    ok=completed.returncode == 0,
+                    result="PASS" if completed.returncode == 0 else "FAIL",
+                    returncode=completed.returncode,
+                    stdout=completed.stdout,
+                    stderr=completed.stderr,
+                    diagnostics=_collect_diag_lines((completed.stderr or completed.stdout or "").strip(), limit=20),
+                    metrics={"mode": "cdc_check"},
+                ),
+                staged_map,
+            )
+            stderr = tool_result["stderr"] or ""
+
+            cdc_warnings = []
+            all_warnings = []
+            for line in stderr.split('\n'):
+                if line.strip():
+                    all_warnings.append(line)
+                    if any(kw in line.upper() for kw in ['CDC', 'CLOCK', 'DOMAIN', 'SYNC', 'METASTAB', 'CDCRSTLOGIC']):
+                        cdc_warnings.append(line)
+
+            if not cdc_warnings and completed.returncode == 0:
+                return True, f"CDC Analysis: CLEAN (no clock domain crossing issues detected)\nFull lint output:\n{stderr[:1000]}"
+            if cdc_warnings:
+                report = "CDC Analysis: WARNINGS FOUND\n\n"
+                report += "CDC-Related Issues:\n"
+                for warning in cdc_warnings:
+                    report += f"  - {warning}\n"
+                report += f"\nTotal lint warnings: {len(all_warnings)}"
+                return False, report
             return True, f"CDC Analysis: CLEAN (lint has non-CDC warnings)\n{stderr[:1000]}"
-            
-    except FileNotFoundError:
-        return True, "Verilator not found (Skipping CDC Check)"
-    except subprocess.TimeoutExpired:
-        return False, "CDC check timed out."
+
+        except FileNotFoundError:
+            return True, "Verilator not found (Skipping CDC Check)"
+        except subprocess.TimeoutExpired:
+            return False, "CDC check timed out."
 
 
 def generate_design_doc(design_name: str, spec: str = "", metrics: dict = None) -> str:
@@ -3839,4 +4229,3 @@ def parse_power_signoff(design_name: str) -> dict:
         return result
     except Exception:
         return result
-

web/src/pages/DesignStudio.tsx

@@ -48,6 +48,7 @@ export const DesignStudio = () => {
 
     // Build Options
     const [skipOpenlane, setSkipOpenlane] = useState(false);
+    const [skipCoverage, setSkipCoverage] = useState(false);
     const [showAdvanced, setShowAdvanced] = useState(false);
     const [fullSignoff, setFullSignoff] = useState(false);
     const [maxRetries, setMaxRetries] = useState(5);
@@ -83,6 +84,7 @@ export const DesignStudio = () => {
                 design_name: designName || slugify(prompt),
                 description: prompt,
                 skip_openlane: skipOpenlane,
+                skip_coverage: skipCoverage,
                 full_signoff: fullSignoff,
                 max_retries: maxRetries,
                 show_thinking: showThinking,
@@ -357,6 +359,10 @@ export const DesignStudio = () => {
                                         </div>
 
                                         <div style={{ display: 'flex', flexWrap: 'wrap', gap: '1.5rem', marginTop: '0.5rem', background: 'var(--bg)', padding: '1rem', borderRadius: 'var(--radius)', border: '1px solid var(--border-mid)' }}>
+                                            <label className="toggle-label" style={{ display: 'flex', alignItems: 'center' }}>
+                                                <input type="checkbox" checked={skipCoverage} onChange={e => setSkipCoverage(e.target.checked)} />
+                                                <span style={{ marginLeft: '0.5rem', color: 'var(--text)', fontWeight: 500 }}>Skip Coverage</span>
+                                            </label>
                                             <label className="toggle-label" style={{ display: 'flex', alignItems: 'center' }}>
                                                 <input type="checkbox" checked={fullSignoff} onChange={e => setFullSignoff(e.target.checked)} />
                                                 <span style={{ marginLeft: '0.5rem', color: 'var(--text)', fontWeight: 500 }}>Full Signoff</span>

web/src/pages/HumanInLoopBuild.tsx

@@ -96,6 +96,7 @@ export const HumanInLoopBuild = () => {
 
     // Build options
     const [skipOpenlane, setSkipOpenlane] = useState(false);
+    const [skipCoverage, setSkipCoverage] = useState(false);
     const [showAdvanced, setShowAdvanced] = useState(false);
     const [maxRetries, setMaxRetries] = useState(5);
     const [showThinking, setShowThinking] = useState(false);
@@ -133,11 +134,13 @@ export const HumanInLoopBuild = () => {
         setError('');
         // Quick RTL mode implies skip_openlane
         const effectiveSkipOpenlane = buildMode === 'quick' || skipOpenlane;
+        const effectiveSkipCoverage = skipCoverage || skipStages.has('COVERAGE_CHECK');
         try {
             const res = await axios.post(`${API}/build`, {
                 design_name: designName || slugify(prompt),
                 description: prompt,
                 skip_openlane: effectiveSkipOpenlane,
+                skip_coverage: effectiveSkipCoverage,
                 max_retries: maxRetries,
                 show_thinking: showThinking,
                 min_coverage: minCoverage,
@@ -354,6 +357,7 @@ export const HumanInLoopBuild = () => {
         setThinkingData(null);
         setBuildMode('verified');
         setSkipStages(new Set(BUILD_MODE_SKIPS.verified));
+        setSkipCoverage(false);
         setShowStageToggles(false);
         setPartialArtifacts([]);
         setShowFullLog(false);
@@ -491,6 +495,10 @@ export const HumanInLoopBuild = () => {
                                 <input type="checkbox" checked={skipOpenlane} onChange={e => setSkipOpenlane(e.target.checked)} />
                                 <span>Skip OpenLane (RTL + Verify only)</span>
                             </label>
+                            <label className="hitl-toggle">
+                                <input type="checkbox" checked={skipCoverage} onChange={e => setSkipCoverage(e.target.checked)} />
+                                <span>Skip Coverage</span>
+                            </label>
                             <button
                                 className="hitl-advanced-toggle"
                                 onClick={() => setShowAdvanced(!showAdvanced)}