Revert "baseline: prompt and benchmark infra"

baseline: prompt and benchmark infra

Fix: multi-file Verilator/sby, width parser, TB stimulus storage, surgical RTL fixer, signal-level analyst, TB regen after RTL fix

feat(core): integrate core modules, update UI and docs

chore: security audit, fix API leak, and update gitignore

fix: Update HTML page title to AgentIC

feat: universal chip support, claude theme, and SFT logging export

Tier-1 upgrade: fail-closed orchestration, CI, and benchmark export

Update modified files and add LICENSE

Update AgentIC: Verification standards, Documentation, and Strict LLM Policy

feat: autonomous self-healing pipeline + pre-synthesis validation

Implement Gate-Level Simulation (GLS) tool and bridge the logic-physical gap

Refactor: Restructure project into docs/ and artifacts/; Update CLI with background hardening and strict Verilog standards

feat: AgentIC v2.0 - Added strict Verilog syntax rules, auto-fixers, and Groq support. Added INSTALL.md for portability.

Initial commit of AgentIC