fix: strict_gates defaults to false, remove dead code

feat: add skip coverage option to Design Studio and Human In Loop Build pages

feat: Introduce a new comprehensive benchmarking suite with metric collection and reports, and remove obsolete design files.

Fix: multi-file Verilator/sby, width parser, TB stimulus storage, surgical RTL fixer, signal-level analyst, TB regen after RTL fix

feat(core): integrate core modules, update UI and docs

chore: security audit, fix API leak, and update gitignore

fix: Remove unused vars to fix Vercel strict TS build

feat: universal chip support, claude theme, and SFT logging export

Tier-1 upgrade: fail-closed orchestration, CI, and benchmark export

Update README with VeriReason benchmarks and functioning details

Update modified files and add LICENSE

Update AgentIC: Verification standards, Documentation, and Strict LLM Policy

feat: autonomous self-healing pipeline + pre-synthesis validation

Added interactive chat command with Groq and exposed VLSI tools

Implement Gate-Level Simulation (GLS) tool and bridge the logic-physical gap

Update source files and scripts

feat: Harden VLSI tools against LLM hallucination and add PPA feedback loop

Refactor: Restructure project into docs/ and artifacts/; Update CLI with background hardening and strict Verilog standards

feat: AgentIC v2.0 - Added strict Verilog syntax rules, auto-fixers, and Groq support. Added INSTALL.md for portability.

Update Dashboard UI: Deep Space Theme, Glassmorphism & Plotly Charts

Initial commit of AgentIC