Commit History
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Move the retired fp8_fast ONNX under onnx/same-s/legacy/
Verified signatureThe SAME-S-only fp8_fast tier pushed fp8 into the attention projections as well, buying +0.08x (1.14 -> 1.22x) at a real quality cost, and was retired. Nothing builds from these graphs and --dec-precision no longer accepts the value.b5182df -
Rename the autoencoder ONNX to match the engine naming scheme
Verified signaturedec_*_chunkable_limiter.onnx -> dec_*_limiter.onnx {enc,dec}_dynamic_triton_swa.onnx -> {enc,dec}_fp16.onnx (SAME-L) {enc,dec}_dynamic_bf16.onnx -> {enc,dec}_bf16.onnx (SAME-S) 'chunkable' was never a property of the ONNX: it is the two optimization profiles the TRT builder adds, so the engines keep the name and the graphs drop it. 'dynamic_triton_swa' named the samel::diff_attn_swa plugin node rather than a precision, which put it out of step with every other file here. Engine filenames are unchanged.4ea87d6 -
Move the retired w8_bf16 ONNX under onnx/*/legacy/
Verified signatureint8 weight-only storage. Its DequantizeLinear nodes sit on constant inputs, so TensorRT folds them at build time and the resulting engine is identical to the one built from the plain bf16 graph -- a file-size format, not a quantisation tier. No build target references them.74cd2b7
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build-ready ONNX: limiter grafted + ceiling baked (decoders), amax-recalibrated activation scales (fp8 encoders)
Verified signatured070aac -
build-ready ONNX: limiter grafted + ceiling baked (decoders), amax-recalibrated activation scales (fp8 encoders)
Verified signature3f689ec -
build-ready ONNX: limiter grafted + ceiling baked (decoders), amax-recalibrated activation scales (fp8 encoders)
Verified signaturef29bd0e
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Add quantized encoder+decoder tier ONNX (fp8 / w8_bf16, padded encoders)
Verified signature4168236
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Decoder ONNX: clip+scale in FP32 before int32 cast
Cortexelus +1: Claude Opus 4.7 (1M context)The PCM-baked tail (audio → clamp → ×32767 → int32) ran in the engine's FP16/BF16 trunk, where 32767 is not representable (rounds up to 32768), causing the int32 output to exceed the int16 range. The consumer code then wrapped 32768 → -32768 on int16 downcast, producing audible clicks on loud transients. Fix: cast audio to FP32 before the clip/scale chain in both build_same_l_decoder.py and build_same_s_decoder.py producers. 32767 is exact in FP32. A trailing clamp(-32767, 32767) is added as belt-and-suspenders against any residual numerical drift. Affected: dec_dynamic_triton_swa.{onnx,trt} (SAME-L), dec_dynamic_bf16.{onnx,trt} (SAME-S). Verified: 0 samples outside [-32767, +32767] on real-music decode (was ~800 with the old engines). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>a429ffa
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Decoder ONNX: bake PCM postprocessing into the graph
CortexelusBoth SAME-S and SAME-L decoder graphs now include the final clamp+scale+ cast(int32)+permute step, so the engine emits PCM-ready int32 tensors of shape (1, T_samples, 2) instead of float32 (1, 2, T_samples) in [-1, 1]. Consumer (sa3_trt.py) detects the new flavor by output tensor name (pcm vs audio) and narrows int32→int16 with a single GPU op — Stage 5 of the inference pipeline goes from ~110ms to ~21ms. Renamed outputs in the .onnx graphs: - audio → pcm - dtype: float32 → int32 - shape: (1, 2, T) → (1, T, 2)459fd8d
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Add ONNX files for per-arch TRT compilation
Cortexelus- onnx/t5gemma/encoder.onnx - onnx/same-s/{enc,dec}_dynamic_bf16.onnx - onnx/same-l/{enc,dec}_dynamic_triton_swa.onnx - onnx/sa3-{m,sm-music,sm-sfx}/dit.onnx opset 17, arch-independent. With these, anyone can compile fresh TRT engines for a new GPU architecture (sm_100, sm_120, ...) without SAT / source ckpts — just TensorRT + torch + huggingface-hub. The sa3-m DiT exceeds protobuf's 2GB limit so its weights live in a single external dit.onnx.data blob alongside the proto (also LFS-tracked).62164ab