Add FP32 SAME-L + SAME-S TRT decoders 773ac48
Cortexelus Claude Opus 4.7 (1M context) commited on
Commit History
Decoder ONNX: clip+scale in FP32 before int32 cast a429ffa
Cortexelus Claude Opus 4.7 (1M context) commited on
DiT engines: replace BF16 with FP16-mixed (FP32 islands) + add FP32 variants 97651ef
Cortexelus Claude Opus 4.7 (1M context) commited on
DiT TRT engines: rebuild with profile min=1 (sm_90) 5f27021
Cortexelus Claude Opus 4.7 (1M context) commited on
T5Gemma: FP16-mixed (FP32 attention island) — fixes BF16 numerical bug 23f5c64
Cortexelus commited on
Decoder TRT engines: PCM-baked-in (sm_90) 106e6fd
Cortexelus commited on
Drop L-range suffix from SAME-L decoder filename 633bd26
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Reorganize tensorRT/ into per-arch subdirs; rebuild DiT engines with conditioner baked in 08c1abe
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Remove padding_embedding.pt — these ship with the inference code repo e8c6e3e
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Remove pipeline_state from tensorRT/ — it ships with the inference code repo, not here f6ada03
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Add pipeline_state + per-model padding_embedding for SA3 TRT pipeline 267e477
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Add SA3 TRT engines (LFS-tracked) e3a5ef0
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