Update README.md

README.md

@@ -77,10 +77,9 @@ The goal of the Chat task is to generate complete Verilog or Chisel code from na
 2. The template of FIM task
 The goal of the FIM task is to fill in the missing parts of the code, generating the middle code based on the prefix and suffix. The input includes language tags, prefix, suffix, and special FIM markers, while the output is the missing middle code snippet.
 ````
-[PRE]```
+[PRE]```[verilog/scala]
 <LanguageTag>
 {prefix}[SUF]{suffix}[MID]
-```
 ````
 It is recommended to use our template during inference.
 ## Paper