Update README.md

README.md

@@ -66,6 +66,15 @@ Our evaluation encompasses Verilog benchmarks, including VerilogEval and RTLLM.
 | **CodeV-R1-distill (ours)** | 7B          | Verilog RTL | 56.2%     |
 | **CodeV-R1 (ours)**         | 7B          | Verilog RTL | **72.9%** |
 
+We also plot the results for RTLLM v1.1, including pass rate against model size and test-time scaling under different token/FLOPs budgets.
+<div style="display: flex; gap: 10px;">
+ <img src="./assets/rtllm_acc_vs_model_size.png" alt="RTLLM TTS Results" width="1200">
+</div>
+<div style="display: flex; gap: 10px;">
+ <img src="./assets/rtllm_tts.png" alt="RTLLM TTS Results" width="500">
+ <img src="./assets/rtllm_tts_flops.png" alt="RTLLM TTS FLOPs Results" width="500">
+</div>
+
 ### 4. Usage
 
 CodeV-R1-Distill-Qwen-7B can be utilized in the same manner as Qwen or Llama models.