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| `timescale 1ns/1ps
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|
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| module async_router #(
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| parameter PACKET_W = 34,
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| parameter COORD_BITS = 4,
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| parameter FIFO_DEPTH = 16,
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| parameter FIFO_PTR_BITS = 4
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| )(
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| input wire clk,
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| input wire rst_n,
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| input wire [COORD_BITS-1:0] my_x,
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| input wire [COORD_BITS-1:0] my_y,
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|
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| input wire local_in_valid,
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| output wire local_in_ready,
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| input wire [PACKET_W-1:0] local_in_data,
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| output wire local_out_valid,
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| input wire local_out_ready,
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| output wire [PACKET_W-1:0] local_out_data,
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|
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| input wire north_in_valid,
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| output wire north_in_ready,
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| input wire [PACKET_W-1:0] north_in_data,
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| output wire north_out_valid,
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| input wire north_out_ready,
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| output wire [PACKET_W-1:0] north_out_data,
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|
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| input wire south_in_valid,
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| output wire south_in_ready,
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| input wire [PACKET_W-1:0] south_in_data,
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| output wire south_out_valid,
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| input wire south_out_ready,
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| output wire [PACKET_W-1:0] south_out_data,
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|
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| input wire east_in_valid,
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| output wire east_in_ready,
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| input wire [PACKET_W-1:0] east_in_data,
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| output wire east_out_valid,
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| input wire east_out_ready,
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| output wire [PACKET_W-1:0] east_out_data,
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|
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| input wire west_in_valid,
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| output wire west_in_ready,
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| input wire [PACKET_W-1:0] west_in_data,
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| output wire west_out_valid,
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| input wire west_out_ready,
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| output wire [PACKET_W-1:0] west_out_data,
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|
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| output wire idle
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| );
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| localparam P_LOCAL = 0, P_NORTH = 1, P_SOUTH = 2, P_EAST = 3, P_WEST = 4;
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|
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| localparam DX_MSB = PACKET_W - 1;
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| localparam DX_LSB = PACKET_W - COORD_BITS;
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| localparam DY_MSB = DX_LSB - 1;
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| localparam DY_LSB = DX_LSB - COORD_BITS;
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|
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| wire [4:0] fifo_empty, fifo_full;
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| wire [PACKET_W-1:0] fifo_head [0:4];
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| wire [4:0] fifo_push;
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| reg [4:0] fifo_pop;
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|
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| assign fifo_push[P_LOCAL] = local_in_valid && !fifo_full[P_LOCAL];
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| assign fifo_push[P_NORTH] = north_in_valid && !fifo_full[P_NORTH];
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| assign fifo_push[P_SOUTH] = south_in_valid && !fifo_full[P_SOUTH];
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| assign fifo_push[P_EAST] = east_in_valid && !fifo_full[P_EAST];
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| assign fifo_push[P_WEST] = west_in_valid && !fifo_full[P_WEST];
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|
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| assign local_in_ready = !fifo_full[P_LOCAL];
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| assign north_in_ready = !fifo_full[P_NORTH];
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| assign south_in_ready = !fifo_full[P_SOUTH];
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| assign east_in_ready = !fifo_full[P_EAST];
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| assign west_in_ready = !fifo_full[P_WEST];
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|
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| wire [PACKET_W-1:0] in_data [0:4];
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| assign in_data[P_LOCAL] = local_in_data;
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| assign in_data[P_NORTH] = north_in_data;
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| assign in_data[P_SOUTH] = south_in_data;
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| assign in_data[P_EAST] = east_in_data;
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| assign in_data[P_WEST] = west_in_data;
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|
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| genvar gi;
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| generate
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| for (gi = 0; gi < 5; gi = gi + 1) begin : gen_fifo
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| spike_fifo #(
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| .ID_WIDTH (PACKET_W),
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| .DEPTH (FIFO_DEPTH),
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| .PTR_BITS (FIFO_PTR_BITS)
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| ) input_fifo (
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| .clk (clk),
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| .rst_n (rst_n),
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| .push (fifo_push[gi]),
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| .pop (fifo_pop[gi]),
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| .clear (1'b0),
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| .push_data (in_data[gi]),
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| .pop_data (fifo_head[gi]),
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| .empty (fifo_empty[gi]),
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| .full (fifo_full[gi])
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| );
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| end
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| endgenerate
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|
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| function [2:0] xy_route;
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| input [COORD_BITS-1:0] dx, dy, cx, cy;
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| begin
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| if (dx > cx) xy_route = P_EAST;
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| else if (dx < cx) xy_route = P_WEST;
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| else if (dy > cy) xy_route = P_NORTH;
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| else if (dy < cy) xy_route = P_SOUTH;
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| else xy_route = P_LOCAL;
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| end
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| endfunction
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|
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| wire [2:0] head_route [0:4];
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| generate
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| for (gi = 0; gi < 5; gi = gi + 1) begin : gen_route
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| assign head_route[gi] = xy_route(
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| fifo_head[gi][DX_MSB:DX_LSB],
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| fifo_head[gi][DY_MSB:DY_LSB],
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| my_x, my_y
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| );
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| end
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| endgenerate
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|
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| reg [4:0] out_valid_r;
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| reg [PACKET_W-1:0] out_data_r [0:4];
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|
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| wire [4:0] out_ready;
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| assign out_ready[P_LOCAL] = local_out_ready;
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| assign out_ready[P_NORTH] = north_out_ready;
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| assign out_ready[P_SOUTH] = south_out_ready;
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| assign out_ready[P_EAST] = east_out_ready;
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| assign out_ready[P_WEST] = west_out_ready;
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|
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| assign local_out_valid = out_valid_r[P_LOCAL];
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| assign local_out_data = out_data_r[P_LOCAL];
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| assign north_out_valid = out_valid_r[P_NORTH];
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| assign north_out_data = out_data_r[P_NORTH];
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| assign south_out_valid = out_valid_r[P_SOUTH];
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| assign south_out_data = out_data_r[P_SOUTH];
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| assign east_out_valid = out_valid_r[P_EAST];
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| assign east_out_data = out_data_r[P_EAST];
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| assign west_out_valid = out_valid_r[P_WEST];
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| assign west_out_data = out_data_r[P_WEST];
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|
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| reg [2:0] arb_ptr;
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|
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| reg [4:0] comb_grant;
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| reg [4:0] comb_out_claim;
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|
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| always @(*) begin : grant_logic
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| integer p, idx;
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| comb_grant = 5'b0;
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| comb_out_claim = 5'b0;
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| for (p = 0; p < 5; p = p + 1) begin
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| idx = arb_ptr + p;
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| if (idx >= 5) idx = idx - 5;
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| if (!fifo_empty[idx] && !comb_grant[idx]) begin
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| if (!out_valid_r[head_route[idx]] && !comb_out_claim[head_route[idx]]) begin
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| comb_grant[idx] = 1'b1;
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| comb_out_claim[head_route[idx]] = 1'b1;
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| end
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| end
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| end
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| end
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|
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| always @(posedge clk or negedge rst_n) begin : seq_logic
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| integer i;
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| if (!rst_n) begin
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| out_valid_r <= 5'b0;
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| arb_ptr <= 3'd0;
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| for (i = 0; i < 5; i = i + 1)
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| out_data_r[i] <= {PACKET_W{1'b0}};
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| end else begin
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| for (i = 0; i < 5; i = i + 1)
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| if (out_valid_r[i] && out_ready[i])
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| out_valid_r[i] <= 1'b0;
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|
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| for (i = 0; i < 5; i = i + 1) begin
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| if (comb_grant[i]) begin
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| out_valid_r[head_route[i]] <= 1'b1;
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| out_data_r[head_route[i]] <= fifo_head[i];
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| end
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| end
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|
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| arb_ptr <= (arb_ptr == 3'd4) ? 3'd0 : arb_ptr + 3'd1;
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| end
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| end
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|
|
| always @(*) fifo_pop = comb_grant;
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|
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| assign idle = (&fifo_empty) &&
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| !out_valid_r[P_NORTH] && !out_valid_r[P_SOUTH] &&
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| !out_valid_r[P_EAST] && !out_valid_r[P_WEST];
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|
|
| endmodule
|
|
|
