EdgeFirst/yolo26-det

YOLO26 Detection — EdgeFirst Model Zoo

YOLO26 Detection models trained on COCO 2017 (80 classes) and validated on real edge hardware through the EdgeFirst Profiler + Validator pipeline. Each row in the tables below cites the EdgeFirst Studio validation session (v-XXXX) that produced the measurement.

Part of the EdgeFirst Model Zoo.

Training experiment: View on EdgeFirst Studio — dataset, training configuration, metrics, and exported artifacts.

End-to-end attention head. end2end=False required for INT8 export.

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Reference accuracy — ONNX FP32

Accuracy ceiling for each size, measured against COCO val2017 (5,000 images) with pycocotools. Quantized and compiled artifacts (TFLite INT8, HEF, etc.) are graded against this reference per the EdgeFirst publication rule.

Size	Params	GFLOPs	mAP@0.5	mAP@0.5-0.95	mAP@0.75	Source
Nano	2.7M	7.6	55.03%	39.68%	42.79%	v-e9c
Small	10.3M	27.0	63.53%	47.12%	51.11%	v-e9f
Medium	24.5M	74.4	68.88%	51.87%	56.40%	v-ea2
Large	42.5M	155.0	—	—	—	—
XLarge	67.5M	244.0	—	—	—	—

Sizes. The EdgeFirst Model Zoo currently validates Nano, Small, and Medium. The Large and XLarge variants are not evaluated at this time — their parameter and GFLOP counts are listed above for reference, with accuracy shown as —.

Accuracy methodology & relation to Ultralytics

Every model in this zoo uses the official Ultralytics pretrained weights, byte-for-byte — there is no re-training. These are the same models Ultralytics ships, measured on the deployment-realistic path: a fixed-input ONNX graph (square letterbox, rect=False), stock pycocotools AP@[maxDets=100], and COCO crowd regions scored as normal detections. Ultralytics' headline COCO numbers use their internal validator (rectangular inference, crowd-ignored, maxDets=300), so a small, fully-explained offset on identical weights is expected — not an accuracy deficit.

Reconciling nano detection (COCO val2017, mAP@0.5:0.95, FP32):

Source	Nano mAP@0.5:0.95	What it measures
EdgeFirst (this zoo)	39.68%	Full deployment path — fixed-input ONNX + pycocotools
Ultralytics-validator proxy	40.22%	Portable re-implementation of the Ultralytics validator
Ultralytics (official)	39.8%	Ultralytics' published COCO figure

The ~1 pp spread decomposes into a ~0.6–0.7 pp methodology leg (square-letterbox / crowd / maxDets) and a ~0.5–0.9 pp deployment-decode leg. The methodology leg is measured, not assumed: a rect=True + crowd-ignored parity pass reproduces the official figure (e.g. YOLOv5n → 34.4 vs 34.3 official). The decode leg shrinks toward zero for the NMS-free YOLO26, which already matches its official number. None of the offset reflects a weight or training difference.

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On-target validation results

Each row is one EdgeFirst Studio validation session. Click the Source link to inspect the full session — model artifact, dataset version, parameters, per-stage Perfetto trace, and the host hardware description (hostname, kernel version, SoC, NPU, profiler version).

Row conventions in the table below:

• Rows whose Δ cell reads ref are the float reference runs each quantized/compiled measurement is graded against.
• Rows without a number under the metric columns are validation sessions currently in progress, or a session not yet linked to its ONNX FP32 reference. The Studio Source link tracks the current status.
• Rows whose Δ vs FP32 cell carries a ⚠ are below our accuracy expectations for that platform (more than 10 percentage points under the float reference). The numbers are real measurements on real hardware, reproducible from the linked Studio session, and we publish them as-is; we are investigating the results to make improvements, and the next snapshot of this card will reflect any recovered accuracy.
• Rows whose metric cells read In progress indicate platforms where this model family already runs on target but accuracy work is still in progress with the silicon vendor, so we withhold the numbers until that work lands. The Studio source link tracks the session; the next snapshot of this card will publish the measured results once resolved.
• Precision varies by target: the ONNX reference rows are FP32; macOS CoreML and NVIDIA Jetson TensorRT run FP16; the NXP i.MX 8M Plus, NXP i.MX 95 Neutron, and Hailo NPUs run INT8. The NXP Ara240 DNPU runs a mixed INT8/INT16 scheme — most of the model is INT8, with the box-regression path (and the ops feeding it) promoted to INT16 to improve localization accuracy.
• Decoder variants. EdgeFirst ships three INT8 split-decoders — smart, logical, and combined (described under Decode below). Every one we have measured is listed; none is headlined over another, because which one wins is a property of the target, not of the variant. Full converter documentation: EdgeFirst model conversion — these are the converters used by this Model Zoo and the EdgeFirst Performance Index report.
• Runtime. Which inference stack executed the model. It is a column of its own because one accelerator can be reached by more than one: on Qualcomm Hexagon HTP, ONNX · QNN EP is an ONNX Runtime EPContext binary while LiteRT is the LiteRT + QNN delegate path, and the two produce measurably different pipelines from the same weights on the same silicon. Compare rows that share a size, platform, precision, and decode to read that difference directly.
• Decode. What the exported graph emits, and therefore what your application has to do with it. Logical keeps the head's outputs separate and named — boxes, scores, and for segmentation the mask prototypes and coefficients — so reading them needs no decoder beyond taking the tensors as they come. Smart cuts the graph further upstream, at a point chosen by dynamic range and sliceability: the operations that quantize worst are lifted out of the model and run outside it, which is what recovers the accuracy, and which is why it needs a decoder implementing that cut (in EdgeFirst deployments, the HAL provides it). Combined fuses the decode into the quantized graph — the standard upstream export. It is the least accurate of the three by construction, and the EdgeFirst converters do not emit it for quantized targets; rows appear only where one was measured. Compare rows sharing a size and platform to see what the cut buys on your target — on detection it is often small, on quantized segmentation masks it is usually decisive. A — means the run carries no quantized decode split at all (float ONNX / TensorRT / CoreML).
• Rows are not ranked. Where a size and platform appear more than once, the rows are competing configurations — a different runtime, precision, decode variant, pipeline mode, or board — not duplicates. Only genuinely repeated measurements of the same configuration are collapsed, newest first.
• Platform-label suffixes. (FRDM) / (Phytec) name the NXP i.MX 95 development board a session ran on. — latency / — throughput mark the two pipeline configurations the NXP i.MX 95 Neutron and NXP Ara240 targets run: the latency pipeline runs inference serially for the lowest per-frame latency; the throughput pipeline runs multiple inference workers for the highest FPS, which raises per-call inference time in exchange. Rows with neither suffix run a single pipeline.
• End-to-end (ms) is the sequential per-image latency of the compute pipeline — preprocess → inference → postprocess. Image acquisition (camera or file load + JPEG decode) overlaps these stages and is excluded from this figure.
• Realized FPS vs Core-throughput ceiling (FPS). Realized FPS is the measured steady-state throughput — the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds 1000 / end-to-end because the runtime overlaps stages across frames, and it is the true, priority number. Core-throughput ceiling (FPS) (shown with a ~) is the accelerator's core ceiling — 1000 / device-compute-time, the rate the NPU/DNPU could sustain if it were the only bottleneck — so it is a possibly-achievable note, not a claim. It is read from the isolated device-compute stage, which (unlike the host capture/preprocess stages, whose measured time inflates when the pipeline is backpressured) is stable and load-independent. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) host bottlenecks — these validation runs decode a JPEG per image, whereas a live camera pipeline skips that decode and can run closer to the ceiling; and (2) confidence threshold — validation runs at 0.001 to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of 0.25–0.75 produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.

Size	Platform	Runtime	Decode	mAP@0.5	Δ vs FP32 (pp)	mAP@0.5-0.95	Inference (ms)	End-to-end (ms)	Realized FPS	Core-throughput ceiling (FPS)	Source
Nano	ONNX FP32 (AWS Graviton · 4-core)	ONNX	—	55.12%	+0.09	39.73%	195.38	204.40	20.1	~5	v-edf
Nano	ONNX FP32 (AWS Graviton4 · 48-core)	ONNX	—	55.13%	+0.10	39.73%	59.52	72.53	203.4	~17	v-eef
Nano	ONNX FP32 (AWS Graviton4 · 8-core)	ONNX	—	55.13%	+0.10	39.73%	166.49	173.53	47.0	~6	v-eee
Nano	ONNX FP32 (Intel Core i9-13900F · 32-core)	ONNX	—	55.03%	+0.00	39.70%	29.24	40.70	93.3	~93	v-a48
Nano	ONNX FP32 (Intel Xeon Platinum 8488C · 24-core)	ONNX	—	55.03%	+0.00	39.69%	55.79	78.80	174.8	~18	v-eba
Nano	ONNX FP32 (Intel Xeon Platinum 8488C · 4-core)	ONNX	—	55.03%	+0.00	39.70%	106.52	117.15	69.6	~9	v-eb1
Nano	ONNX FP32 (CUDA)	ONNX	—	55.03%	ref	39.68%	10.75	20.00	297.7	~298	v-e9c
Nano	ONNX FP32 (CUDA)	ONNX	—	55.04%	+0.01	39.69%	7.89	13.05	356.6	~356	v-a8a
Nano	ONNX FP16 (CUDA)	ONNX	—	55.04%	+0.01	39.65%	6.33	11.62	435.5	~435	v-a9f
Nano	ONNX FP32	ONNX	—	13.26%	-41.77 ⚠	8.08%	30.97	37.78	31.9	~32	v-cf0
Nano	ONNX FP32	ONNX	—	55.03%	+0.00	39.69%	30.08	48.39	115.9	~34	v-cef
Nano	ONNX FP32	ONNX	—	55.03%	+0.00	39.69%	25.97	34.51	35.9	~39	v-cea
Nano	ONNX FP32	ONNX	—	13.26%	-41.77 ⚠	8.08%	25.02	35.74	152.9	~40	v-ce7
Nano	Apple M2 Max — CoreML Neural Engine (FP16)	ONNX	—	54.60%	-0.43	39.35%	1.78	5.23	800.4	~731	v-9c7
Nano	Apple M2 Max — CoreML Metal GPU (FP16)	ONNX	—	54.59%	-0.44	39.36%	6.45	9.93	408.8	~408	v-9c8
Nano	Apple M2 Max — CoreML CPU (FP16)	ONNX	—	54.58%	-0.45	39.32%	14.56	18.50	128.3	~128	v-9ca
Nano	Apple iPhone 17 Pro — CoreML Neural Engine (FP16)	ONNX	—	54.62%	-0.41	39.36%	2.10	6.66	725.3	~299	v-1099
Nano	Apple iPhone 17 Pro — CoreML Metal GPU (FP16)	ONNX	—	54.59%	-0.44	39.36%	6.17	11.76	281.2	~162	v-f48
Nano	Apple iPhone 17 Pro — CoreML CPU (FP16)	ONNX	—	54.58%	-0.45	39.32%	17.09	23.50	111.1	~59	v-f35
Nano	Apple iPhone 15 Pro — CoreML Neural Engine (FP16)	ONNX	—	54.61%	-0.42	39.36%	2.95	12.10	468.0	~149	v-f11
Nano	Apple iPhone 15 Pro — CoreML Metal GPU (FP16)	ONNX	—	54.59%	-0.44	39.36%	19.32	24.37	97.7	~52	v-f17
Nano	Apple iPhone 15 Pro — CoreML CPU (FP16)	ONNX	—	54.55%	-0.48	39.32%	23.41	32.33	81.0	~43	v-f19
Nano	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	ONNX · QNN EP	Smart	52.60%	-2.43	35.66%	2.02	14.11	316.1	~325	v-108f
Nano	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	ONNX · QNN EP	Logical	49.89%	-5.14	32.61%	2.77	7.72	611.2	~630	v-1090
Nano	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT16)	ONNX · QNN EP	Smart	54.02%	-1.01	37.42%	5.07	16.86	270.9	~278	v-108d
Nano	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT16)	ONNX · QNN EP	Logical	53.20%	-1.83	36.88%	6.84	13.10	281.7	~292	v-108e
Nano	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	LiteRT	Smart	54.00%	-1.03	37.92%	6.24	18.02	243.3	~263	v-1059
Nano	Samsung Galaxy S26 Ultra — CPU	LiteRT	Smart	53.72%	-1.31	37.94%	88.03	110.68	62.6	~11	v-105e
Nano	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Combined	47.27%	-7.76	29.10%	105.75	139.49	8.6	~9	v-8ab
Nano	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Logical	47.27%	-7.76	29.10%	105.43	139.00	8.6	~9	v-8b2
Nano	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Smart	50.07%	-4.96	32.39%	104.74	147.11	8.6	~9	v-8b7
Nano	NXP i.MX 8M Plus + VeriSilicon NPU (Verdin)	LiteRT	Logical	47.27%	-7.76	29.10%	106.62	148.76	8.5	~9	v-c81
Nano	NXP i.MX 8M Plus + VeriSilicon NPU (Verdin)	LiteRT	Smart	50.07%	-4.96	32.39%	105.83	163.87	8.5	~9	v-c80
Nano	NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency	LiteRT	Smart	In progress	—	—	—	—	—	—	v-94e
Nano	NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency	LiteRT	Logical	In progress	—	—	—	—	—	—	v-94a
Nano	NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency	LiteRT	Combined	In progress	—	—	—	—	—	—	v-945
Nano	NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput	LiteRT	Smart	In progress	—	—	—	—	—	—	v-950
Nano	NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput	LiteRT	Logical	In progress	—	—	—	—	—	—	v-94c
Nano	NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput	LiteRT	Combined	In progress	—	—	—	—	—	—	v-948
Nano	NXP i.MX 95 + eIQ Neutron NPU (Verdin) — latency	LiteRT	Logical	In progress	—	—	—	—	—	—	v-bcd
Nano	NXP i.MX 95 + eIQ Neutron NPU (Verdin) — throughput	LiteRT	Smart	In progress	—	—	—	—	—	—	v-e0c
Nano	NXP Ara240 (FRDM) — latency	Ara DVM	Smart	51.36%	-3.67	34.67%	6.20	18.12	132.4	~136	v-a16
Nano	NXP Ara240 (FRDM) — throughput	Ara DVM	Smart	51.35%	-3.68	34.65%	6.42	22.23	177.0	~324	v-a17
Nano	Raspberry Pi 5 + Hailo-8L NPU	Hailo HEF	—	52.72%	-2.31	36.61%	21.40	33.45	45.8	~46	v-8dd
Nano	NVIDIA Jetson Orin Nano (TensorRT FP16)	TensorRT	—	55.13%	+0.10	39.71%	9.71	24.06	251.2	~251	v-918
Small	ONNX FP32 (AWS Graviton · 4-core)	ONNX	—	63.56%	+0.03	47.15%	624.36	633.04	6.4	~2	v-eda
Small	ONNX FP32 (AWS Graviton4 · 48-core)	ONNX	—	63.56%	+0.03	47.15%	173.65	184.46	73.3	~6	v-ef1
Small	ONNX FP32 (AWS Graviton4 · 8-core)	ONNX	—	63.56%	+0.03	47.15%	513.19	519.49	15.5	~2	v-ee9
Small	ONNX FP32 (Intel Core i9-13900F · 32-core)	ONNX	—	63.53%	+0.00	47.12%	77.17	89.27	35.8	~36	v-a4f
Small	ONNX FP32 (Intel Xeon Platinum 8488C · 24-core)	ONNX	—	63.53%	+0.00	47.12%	151.77	173.32	80.8	~7	v-ebb
Small	ONNX FP32 (Intel Xeon Platinum 8488C · 4-core)	ONNX	—	63.53%	+0.00	47.12%	315.31	325.16	24.9	~3	v-eb9
Small	ONNX FP32 (CUDA)	ONNX	—	63.53%	ref	47.12%	12.70	21.92	271.0	~271	v-e9f
Small	ONNX FP32 (CUDA)	ONNX	—	63.54%	+0.01	47.12%	15.40	20.83	205.7	~206	v-a91
Small	ONNX FP16 (CUDA)	ONNX	—	63.53%	+0.00	47.09%	10.49	16.07	294.9	~295	v-aa6
Small	ONNX FP32	ONNX	—	13.06%	-50.47 ⚠	7.61%	64.28	74.24	61.7	~16	v-cfa
Small	ONNX FP32	ONNX	—	13.07%	-50.46 ⚠	7.63%	86.20	93.28	11.6	~12	v-cf9
Small	ONNX FP32	ONNX	—	63.53%	+0.00	47.12%	60.31	79.54	62.9	~17	v-cf8
Small	ONNX FP32	ONNX	—	63.53%	+0.00	47.12%	58.82	67.63	16.3	~17	v-cf7
Small	Apple M2 Max — CoreML Neural Engine (FP16)	ONNX	—	62.58%	-0.95	46.31%	5.40	8.82	321.2	~322	v-9d3
Small	Apple M2 Max — CoreML Metal GPU (FP16)	ONNX	—	62.60%	-0.93	46.37%	15.09	18.89	187.6	~188	v-9d4
Small	Apple M2 Max — CoreML CPU (FP16)	ONNX	—	62.56%	-0.97	46.31%	31.28	35.25	61.6	~62	v-9d5
Small	Apple iPhone 17 Pro — CoreML Neural Engine (FP16)	ONNX	—	62.58%	-0.95	46.32%	7.41	11.11	245.7	~135	v-f57
Small	Apple iPhone 17 Pro — CoreML Metal GPU (FP16)	ONNX	—	62.60%	-0.93	46.37%	16.84	21.50	111.7	~59	v-f51
Small	Apple iPhone 17 Pro — CoreML CPU (FP16)	ONNX	—	62.61%	-0.92	46.35%	41.79	48.50	46.7	~24	v-f3c
Small	Apple iPhone 15 Pro — CoreML Neural Engine (FP16)	ONNX	—	62.58%	-0.95	46.32%	8.31	14.41	211.6	~120	v-f18
Small	Apple iPhone 15 Pro — CoreML Metal GPU (FP16)	ONNX	—	62.60%	-0.93	46.38%	45.45	57.53	41.2	~22	v-f24
Small	Apple iPhone 15 Pro — CoreML CPU (FP16)	ONNX	—	62.59%	-0.94	46.36%	55.68	64.47	35.0	~18	v-f27
Small	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	ONNX · QNN EP	Smart	57.66%	-5.87	40.53%	3.33	15.07	303.9	~314	v-1093
Small	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	ONNX · QNN EP	Logical	54.30%	-9.23	36.21%	4.63	11.19	397.8	~415	v-1094
Small	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT16)	ONNX · QNN EP	Smart	59.75%	-3.78	42.70%	5.31	22.14	211.1	~217	v-1091
Small	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT16)	ONNX · QNN EP	Logical	58.85%	-4.68	42.05%	7.65	15.33	250.3	~261	v-1092
Small	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	LiteRT	Smart	62.17%	-1.36	44.80%	13.60	26.02	141.3	~146	v-1065
Small	Samsung Galaxy S26 Ultra — CPU	LiteRT	Smart	62.21%	-1.32	44.85%	165.09	189.15	34.7	~6	v-1072
Small	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Combined	55.13%	-8.40	34.43%	208.54	242.82	4.6	~5	v-904
Small	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Logical	55.13%	-8.40	34.43%	208.21	242.06	4.6	~5	v-913
Small	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Smart	58.83%	-4.70	39.24%	207.31	249.29	4.6	~5	v-928
Small	NXP i.MX 8M Plus + VeriSilicon NPU (Verdin)	LiteRT	Logical	55.13%	-8.40	34.43%	209.84	251.77	4.5	~5	v-c91
Small	NXP i.MX 8M Plus + VeriSilicon NPU (Verdin)	LiteRT	Smart	58.83%	-4.70	39.24%	209.07	266.82	4.5	~5	v-c90
Small	NXP Ara240 (FRDM) — latency	Ara DVM	Smart	59.00%	-4.53	41.07%	10.35	22.16	85.9	~87	v-a24
Small	NXP Ara240 (FRDM) — throughput	Ara DVM	Smart	58.98%	-4.55	41.05%	10.51	24.06	137.6	~138	v-a25
Small	Raspberry Pi 5 + Hailo-8L NPU	Hailo HEF	—	59.61%	-3.92	42.39%	47.35	60.97	20.4	~20	v-8ea
Small	NVIDIA Jetson Orin Nano (TensorRT FP16)	TensorRT	—	63.56%	+0.03	47.14%	24.76	36.73	155.0	~155	v-920
Medium	ONNX FP32 (AWS Graviton · 4-core)	ONNX	—	68.88%	+0.00	51.86%	1877.56	1886.79	2.1	~1	v-edd
Medium	ONNX FP32 (AWS Graviton4 · 48-core)	ONNX	—	68.88%	+0.00	51.86%	504.50	515.87	25.3	~2	v-ef4
Medium	ONNX FP32 (AWS Graviton4 · 8-core)	ONNX	—	68.88%	+0.00	51.86%	1541.76	1547.79	5.2	~1	v-eeb
Medium	ONNX FP32 (Intel Core i9-13900F · 32-core)	ONNX	—	68.88%	+0.00	51.88%	233.65	245.95	12.2	~12	v-a56
Medium	ONNX FP32 (Intel Xeon Platinum 8488C · 24-core)	ONNX	—	68.88%	+0.00	51.88%	431.14	452.33	29.0	~2	v-ec2
Medium	ONNX FP32 (Intel Xeon Platinum 8488C · 4-core)	ONNX	—	68.88%	+0.00	51.88%	1243.76	1256.00	6.4	~1	v-ebc
Medium	ONNX FP32 (CUDA)	ONNX	—	68.88%	ref	51.87%	25.72	33.62	146.5	~146	v-ea2
Medium	ONNX FP32 (CUDA)	ONNX	—	68.88%	+0.00	51.87%	39.74	45.15	88.6	~89	v-a98
Medium	ONNX FP16 (CUDA)	ONNX	—	68.87%	-0.01	51.83%	21.99	27.90	154.0	~154	v-aad
Medium	ONNX FP32	ONNX	—	68.88%	+0.00	51.87%	142.94	161.01	27.3	~7	v-cfb
Medium	ONNX FP32	ONNX	—	68.88%	+0.00	51.88%	184.14	195.10	5.3	~5	v-cf5
Medium	ONNX FP32	ONNX	—	24.95%	-43.93 ⚠	16.31%	173.95	184.13	22.9	~6	v-cf3
Medium	ONNX FP32	ONNX	—	24.97%	-43.91 ⚠	16.31%	242.50	249.57	4.1	~4	v-cf2
Medium	Apple M2 Max — CoreML Neural Engine (FP16)	ONNX	—	67.22%	-1.66	50.44%	18.35	22.44	103.8	~104	v-9d6
Medium	Apple M2 Max — CoreML Metal GPU (FP16)	ONNX	—	67.22%	-1.66	50.45%	41.00	45.61	71.0	~71	v-9d7
Medium	Apple M2 Max — CoreML CPU (FP16)	ONNX	—	67.21%	-1.67	50.39%	65.90	70.04	29.8	~30	v-9d8
Medium	Apple iPhone 17 Pro — CoreML Neural Engine (FP16)	ONNX	—	67.21%	-1.67	50.43%	20.82	27.96	91.7	~48	v-f5e
Medium	Apple iPhone 17 Pro — CoreML Metal GPU (FP16)	ONNX	—	67.20%	-1.68	50.44%	38.76	46.72	49.0	~26	v-f5f
Medium	Apple iPhone 17 Pro — CoreML CPU (FP16)	ONNX	—	67.22%	-1.66	50.38%	103.87	110.78	19.0	~10	v-f45
Medium	Apple iPhone 15 Pro — CoreML Neural Engine (FP16)	ONNX	—	67.21%	-1.67	50.44%	27.25	33.55	70.1	~37	v-f21
Medium	Apple iPhone 15 Pro — CoreML Metal GPU (FP16)	ONNX	—	67.21%	-1.67	50.45%	138.25	154.86	14.0	~7	v-f38
Medium	Apple iPhone 15 Pro — CoreML CPU (FP16)	ONNX	—	67.16%	-1.72	50.41%	135.83	145.25	14.5	~7	v-f3b
Medium	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	ONNX · QNN EP	Smart	64.19%	-4.69	45.26%	6.10	18.24	252.1	~263	v-1097
Medium	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	ONNX · QNN EP	Logical	59.51%	-9.37	39.95%	7.57	12.60	257.9	~264	v-1098
Medium	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT16)	ONNX · QNN EP	Smart	65.76%	-3.12	47.14%	19.10	38.32	101.1	~104	v-1095
Medium	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT16)	ONNX · QNN EP	Logical	65.00%	-3.88	46.59%	16.63	27.49	117.2	~120	v-1096
Medium	Samsung Galaxy S26 Ultra — Qualcomm Hexagon NPU (INT8)	LiteRT	Smart	67.63%	-1.25	49.51%	23.35	37.16	83.4	~86	v-1070
Medium	Samsung Galaxy S26 Ultra — CPU	LiteRT	Smart	67.70%	-1.18	49.56%	362.01	386.20	16.2	~3	v-1086
Medium	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Combined	9.52%	-59.36	5.71%	360.05	393.92	2.7	~3	v-a41
Medium	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Logical	9.52%	-59.36	5.71%	359.87	393.59	2.7	~3	v-a42
Medium	NXP i.MX 8M Plus + VeriSilicon NPU (FRDM)	LiteRT	Smart	10.96%	-57.92 ⚠	7.32%	359.03	401.07	2.7	~3	v-a43
Medium	NXP i.MX 8M Plus + VeriSilicon NPU (Verdin)	LiteRT	Logical	9.52%	-59.36	5.71%	363.32	404.99	2.7	~3	v-ca5
Medium	NXP i.MX 8M Plus + VeriSilicon NPU (Verdin)	LiteRT	Smart	10.96%	-57.92 ⚠	7.32%	362.74	420.10	2.7	~3	v-ca4
Medium	NXP Ara240 (FRDM) — latency	Ara DVM	Smart	63.23%	-5.65	43.63%	24.39	36.29	39.0	~39	v-a32
Medium	NXP Ara240 (FRDM) — throughput	Ara DVM	Smart	63.21%	-5.67	43.62%	24.44	37.10	46.8	~47	v-a33
Medium	Raspberry Pi 5 + Hailo-8L NPU	Hailo HEF	—	64.12%	-4.76	45.88%	88.30	102.16	11.0	~11	v-912
Medium	NVIDIA Jetson Orin Nano (TensorRT FP16)	TensorRT	—	68.88%	+0.00	51.80%	50.39	63.74	76.8	~77	v-929

⚠ Below expectations — under investigation. The rows marked ⚠ above measure more than 10 percentage points below the same training session's float reference: the model accuracy on that platform is below our expectations. We publish the measured numbers rather than hiding them, and we are investigating the results to make improvements — the next snapshot of this card will reflect any recovered accuracy.

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Validation pipeline

These results are produced by the EdgeFirst on-target validation pipeline:

1. EdgeFirst Profiler runs on the target hardware, executes the full inference pipeline (image load → decode → preprocess → inference → postprocess), and emits per-image predictions in EdgeFirst Arrow/Parquet plus a Perfetto trace.
2. EdgeFirst Validator consumes the predictions and trace, computes pycocotools accuracy metrics and per-stage timing summaries, and publishes the results to the Studio validation session.
3. EdgeFirst HAL (open source) provides the hardware-accelerated preprocessing and post-decoding primitives used at both validation and deployment time, so the timings measured here reflect the same accelerated paths a production runtime would take.

Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image latency across the compute pipeline — preprocessing, inference, and postprocessing; image acquisition (file or camera load and JPEG decode) overlaps these stages and is excluded from this figure.

Two throughput figures are reported. Realized FPS is the measured steady-state rate at which final results are emitted, measured directly from the profiler's per-frame result-emission timestamps over the steady-state stream — trace-independent; the Perfetto trace's own FPS is used only as a fallback on sessions where that scalar isn't available. It is the true, priority number and generally exceeds 1000 / end-to-end because the runtime overlaps stages across frames. Core-throughput ceiling (FPS) is the accelerator's core ceiling — 1000 / device-compute-time, i.e. the throughput if the accelerator were the only bottleneck. It is taken from the isolated device-compute stage (on transfer-split runtimes the trace separates host↔device transfers from device compute), which is load-independent — unlike the host capture/preprocess service times, whose measured cost inflates under pipeline backpressure (the same 5000 JPEGs cost ~7.8 ms/frame serialized but far more under throughput backpressure), so the slowest-stage figure would understate a fast accelerator. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a 0.001 confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of 0.25–0.75 (far fewer candidate boxes through NMS) moves realized throughput toward the core-throughput ceiling.

See EdgeFirst Studio for the full validation pipeline.

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Downloads

Artifacts are organized by deployment target. Each model file embeds the EdgeFirst edgefirst.json metadata (training session, dataset version, calibration artifact, converter chain) so a single file is sufficient for deployment — no sidecar configuration required.

Browse and download every artifact from the repository file tree. Files are organized into per-target folders and follow the naming convention yolo26{size}-det-{precision}[-smart]{extension}:

Target	Folder	Format
ONNX FP32	onnx/	.onnx
TFLite INT8	tflite/	.tflite
NXP i.MX 95 (eIQ Neutron)	imx95/	.imx95.tflite
NXP Ara240	ara240/	.dvm
RPi5 + Hailo-8L (13 TOPS)	hailo/	.hailo8l.hef
NVIDIA Jetson (TensorRT)	jetson/	.engine
Snapdragon (Qualcomm Hexagon HTP)	qnn/	.htp-v81.qnn.onnx

Each file embeds its edgefirst.json metadata (training session, dataset version, calibration artifact, converter chain), so a single download is sufficient for deployment — no sidecar configuration required.

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Inference example (Python)

from edgefirst.hal import Model, TensorImage

# Load the model — embedded edgefirst.json carries labels and decoder config
model = Model("yolo26n-det-int8.tflite")

# Run inference on an image
image = TensorImage.from_file("image.jpg")
results = model.predict(image)

# Iterate detections
for det in results.detections:
    print(f"{det.label}: {det.confidence:.2f} at {det.bbox}")

EdgeFirst HAL

Traceability

Every measurement in the tables above is reachable through the EdgeFirst Studio validation framework. The v-XXXX Source link on each row resolves to a public Studio URL of the form:

https://edgefirst.studio/public/validation/v-XXXX/details?mode=charts

The link lands on the Charts view — live system traces (CPU, memory, temperature, power) and per-stage timing recorded during the validation run. The Info and Metrics tabs on the same page carry the configuration and full COCO metric breakdown.

From there, the full provenance chain is one click deeper: training session ID, dataset version, calibration artifact, converter chain (e.g. TFLite quantizer + Neutron compile), validation parameters, and the host hardware description (hostname, kernel version, SoC, NPU, profiler version). The same model file you download from this repository embeds the same chain in its edgefirst.json metadata.

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See also

Other model families in the EdgeFirst Model Zoo:

Model	Task	Link
YOLOv5 Detection	Detection	EdgeFirst/yolov5-det
YOLOv8 Detection	Detection	EdgeFirst/yolov8-det
YOLOv8 Segmentation	Segmentation	EdgeFirst/yolov8-seg
YOLO11 Detection	Detection	EdgeFirst/yolo11-det
YOLO11 Segmentation	Segmentation	EdgeFirst/yolo11-seg
YOLO26 Segmentation	Segmentation	EdgeFirst/yolo26-seg

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Train your own with EdgeFirst Studio

Train on your own dataset with EdgeFirst Studio:

• Free tier includes YOLO training with automatic INT8 quantization and edge deployment.
• Upload datasets via EdgeFirst Recorder or COCO/YOLO format.
• AI-assisted annotation with auto-labeling.
• CameraAdaptor integration for native sensor format training.
• Deploy trained models to edge devices via EdgeFirst Client.

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Technical notes

Quantization pipeline

All TFLite INT8 models are produced by EdgeFirst's quantization pipeline (details):

1. ONNX export — standard Ultralytics export with simplify=True
2. TF-wrapped ONNX — box coordinates normalized to [0, 1] inside DFL decode
3. Split decoder — boxes and scores split into separate output tensors so each receives an independent INT8 quantization scale
4. Smart calibration — calibration samples selected via greedy coverage maximization; the artifact is content-addressed by parameter hash and cached in Studio for deterministic reuse
5. Full integer INT8 — uint8 input, int8 output, MLIR quantizer

Split decoder output format

Detection (e.g. yolo26n):

• boxes — (1, 4, 8400) normalized [0, 1] coordinates
• scores — (1, 80, 8400) per-class probabilities

Each tensor has its own quantization scale and zero point. The EdgeFirst HAL handles dequantization and reassembly automatically; no application code change is required across NPU targets.

Embedded metadata

• TFLite: edgefirst.json and labels.txt embedded in the ZIP-format model file
• ONNX: edgefirst.json embedded in model.metadata_props

No sidecar files required; the model artifact is self-contained.

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Limitations

• COCO bias — models trained on COCO (80 classes) inherit the dataset's biases (Western-centric scenes, particular object distributions, limited weather/lighting diversity).
• Quantization loss — integer quantization introduces accuracy loss relative to FP32: INT8 on the NXP i.MX 8M Plus / i.MX 95 Neutron and Hailo NPUs, and a mixed INT8/INT16 scheme on the NXP Ara240 (the box-regression path is promoted to INT16 for localization accuracy). The magnitude per platform is shown in the Δ vs FP32 column above.
• Configurations under active investigation — a subset of INT8 results measure below expectations and are marked ⚠ above; these are tracked for resolution, not accepted as final. The main cases are YOLO11 / YOLO26 on the NXP i.MX 8M Plus VeriSilicon NPU (the most constrained accelerator, where the newer architectures quantize poorly) and some NXP Ara240 segmentation runs. YOLO11 / YOLO26 on the NXP i.MX 95 eIQ Neutron NPU are not yet supported (a delegate limitation) and render without numbers. Each next card snapshot reflects any recovered accuracy.
• Input resolution — all models expect 640×640 input; other resolutions require letterboxing.

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License

Model weights in this repository are derived from Ultralytics YOLO and remain © Ultralytics Inc., licensed AGPL-3.0 — use requires AGPL-3.0 compliance or an Ultralytics Enterprise License.

The validation results, this model card, and its metadata are Au-Zone Technologies' own contribution, licensed CC BY-NC 4.0 (Attribution — NonCommercial) — see the repository LICENSE for the full text and citation requirements.

---

Citation

@software{edgefirst_yolo26_det,
  title = { {YOLO26 Detection — EdgeFirst Model Zoo} },
  author = {Au-Zone Technologies},
  url = {https://huggingface.co/EdgeFirst/yolo26-det},
  year = {2026},
  license = {CC-BY-NC-4.0},
}

---

_{EdgeFirst Studio · GitHub · Docs · Au-Zone Technologies
Model weights © Ultralytics Inc. (AGPL-3.0) · Validation results & card © 2026 Au-Zone Technologies (CC BY-NC 4.0)
NXP^®, i.MX, eIQ^®, Neutron, and Ara240 are trademarks or products of NXP Semiconductors. Hailo is a trademark of Hailo Technologies Ltd. Jetson is a trademark of NVIDIA Corporation. All other trademarks are the property of their respective owners.}