GeoStratum/quantification-MobileNetV5-V4

Lithotheque Edge Models - GeoStratum

Technical showcase of the Edge AI architecture powering the Lithotheque offline application.

Note on Artifact Availability & IP

To protect our proprietary metrology datasets and commercial intellectual property, the compiled .tflite and .onnx model artifacts, alongside the FP32 source weights, are not publicly distributed in this repository.

The core purpose of this scientific repository is to openly share the engineering methodology, the W4A8 Full Integer quantization pipeline, and the mathematical architectural strategies (such as the 21-Pass Multi-Scale Tiling) used to achieve real-time inference on mobile Edge NPUs (e.g., Qualcomm Hexagon, Google Tensor Edge TPU).

New to Edge AI?

For developers and researchers new to AI and quantization, we highly recommend consulting our Detailed Methodology. It provides a pedagogical introduction to fundamental concepts, numerical precision (INT8/INT4), and hardware acceleration architectures.

Table of Contents

• 1. Overview
• 2. Dual-Model Ecosystem
• 3. Training Data & Acknowledgements
• 4. Inference Engine & Hardware Fallback
• 5. Deployment Strategy (AI Tiers)
• 6. W4A8 Quantization Methodology
• 7. Technical Specifications (I/O)
• 8. Scientific Benchmark & Hardware Profiling
  • 8.A Generation & Quantization Environment (Machine 1)
  • 8.B Benchmark & Validation Environment (Machine 2)
  • 8.C Memory Footprint & Initialization (Cold Start)
  • 8.D Inference Latency & Accuracy (Avg over 100 runs)
  • 8.E Native AOT Snapdragon X NPU Binaries Qualification (Machine 2 - Surface Pro 11)
• 9. Hardware Strategy & Analysis
• 10. Model Card (Technical Specs)
• 11. Deployment & Application
• 12. Methodological Blueprint & Adaptability (BYOM)
• 13. Technical Reproduction Scripts
• 14. License
• 15. Contact
• 16. Citation

1. Overview

This repository documents the advanced Edge AI architecture integrated into GeoStratum Lithotheque. To provide instant, on-device geological classification and scale detection without requiring an internet connection, the application relies on a highly optimized, dual-model ecosystem deployed via Google Play Asset Delivery (On-Demand).

Try the Application on Play Store | Read the Model Card | Quantization Methodology

2. Dual-Model Ecosystem

The application utilizes two distinct neural networks, fine-tuned specifically for geological field operations:

A. VisionAiManager (Rock Recognition)

• Task: Classification of 104 geological and mineralogical structures.
• Base Architectures: MobileNetV5-300m (Vision architecture akin to the Gemma 3n vision encoder) for modern devices, and MobileNetV4-Large for legacy fallback.
• Training Corpus: Fine-tuned on open-source datasets (Udayl/Stealth) totaling >14,500 validated images.
• Innovation: Multi-Scale Tiling (21-Pass Strategy): To capture both macroscopic textures and microscopic crystals without losing data during downscaling, the engine evaluates the image through 21 parallel passes:
  • 1 Global Pass: Overall sample context.
  • 4 Medium Passes (2x2 Grid): Regional texture analysis.
  • 16 Fine Passes (4x4 Grid): Micro-detail and mineral extraction. (Scores are aggregated via weighted average for the final prediction).

Figure 1: Real-time Rock Detection - Demonstration of the 21-MST engine classifying lithological samples with high confidence on a Galaxy Z Fold 7 via Remote Test Lab.

Dataset Categorization (104 Model Output Logits / 96 Unique Lithological Taxa)

The model output layer exposes 104 classification logits, mapped directly to the concatenated multi-source training datasets (Udayl & Stealth). Due to origin-dataset labeling artifacts, 8 classes exist as formatting duplicates across the dataset merge (e.g. Shale (Mudstone) vs. Shale-(Mudstone), Olivine basalt vs. Olivine-basalt, and dual entries for Dacite, Granite, Marble, Quartzite, Copper, Oolitic Limestone / Dolomites), representing 96 unique geoscientific taxa grouped below by primary genetic classification:

1. Sedimentary (Sed)

Bauxite, Caliche, Chalk, Chert, Clay, Coal, Conglomerate, Coquina, Diatomite, Dolomitic Limestone, Dolomites, Flint, Fossiliferous Limestone, Gypsum, Halite, Limestone, Novaculite, Oolitic Limestone, Phosphate, Potash, Sandstone, Shale (Mudstone) (dual-dataset entry), Siliceous Sinter, Siltstone, Sodium Carbonate, Tufa.

2. Magmatic / Plutonic (Mag)

Anorthosite, Aplite, Diorite, Dolerite, Dunite, Essexite, Gabbro, Granite (dual-dataset entry), Granodiorite, Norite, Pegmatite, Syenite.

3. Volcanic / Extrusive (Volc)

Andesite, Basalt, Dacite (dual-dataset entry), Ignimbrite, Komatiite, Obsidian, Olivine Basalt (dual-dataset entry), Phonolite, Pillow Lava, Pumice, Rhyolite, Tephrite, Trachyte, Tuff, Volcanic Bombs.

4. Metamorphic (Meta)

Anthracite, Breccia (Tectonic/Fault), Gneiss, Hornfels, Lapis Lazuli, Marble (dual-dataset entry), Phyllite, Quartzite (dual-dataset entry), Schists, Serpentine, Skarn, Slate.

5. Native Elements, Minerals & Ores

Bornite, Calcite, Chromite, Cobalt, Columbite-Tantalite, Copper (dual-dataset entry), Feldspar, Fluorite, Gold, Iron Ore, Labradorite, Lead, Lithium, Magnetite, Malachite, Mariposite, Mica, Molybdenum, Nickel, Platinum, Pyrite, Quartz, Silica, Silver, Sodalite, Stibnite, Sulfur, Tantalum, Tungsten, Uranium, Vanadium, Zeolite, Zinc.

graph TD
    A[Raw Camera Frame] -->|C++ NEON / SVE2 JNI| B(Preprocessing & Normalization)
    B --> C{Multi-Scale Tiling Engine}
    
    C -->|Step 1| F[16 Fine Passes<br>4x4 Grid: Minerals & Micro-details]
    F -->|Step 2| E[4 Medium Passes<br>2x2 Grid: Regional Textures]
    E -->|Step 3| D[1 Global Pass<br>1x1: Overall Context]
    
    F -.->|Scores| G{Weighted Score Aggregation}
    E -.->|Scores| G
    D -.->|Scores| G
    
    G --> H[Hardware Fallback Inference<br>NPU / GPU / CPU]
    H --> I((Final Prediction<br>Class + Confidence))
    
    style A fill:#2d3436,stroke:#fff,color:#fff
    style I fill:#0984e3,stroke:#fff,color:#fff
    style C fill:#d63031,stroke:#fff,color:#fff
    style G fill:#e17055,stroke:#fff,color:#fff

---

B. LocalAiManager (Scale Detection)

• Task: Metrology assistant detecting reference objects (coins, geological scales).
• Base Architecture: MobileNetV4-Small.
• Resolution: High-res 1024x1024 processing for precise small-object anchoring.
• Training Corpus: Fine-tuned on >1,000 reference images.

3. Training Data & Acknowledgements

The robustness of the Lithotheque AI ecosystem relies on a hybrid training approach, combining proprietary field metrology data with highly curated, open-source geological collections. We gratefully acknowledge the creators of the following datasets:

A. Metrology & Scale Detection (LocalAiManager)

• GeoStratum Proprietary Corpus: A custom dataset comprising >1,000 high-resolution field photographs of geological reference objects (coins, geological scales) captured in diverse lighting and terrain conditions by the GeoStratum. (Note: This dataset remains the exclusive intellectual property of GeoStratum and is not publicly distributed).

B. Lithological Classification (VisionAiManager)

To achieve extreme accuracy across 104 geological classes, the model was fine-tuned using the following validated sources, both utilized under the MIT License:

• Udayl Rocks Dataset: Our primary dataset for lithological visual features, hosted on Hugging Face.
• Stealth Technologies Rock Classification: A supplementary dataset hosted on Kaggle, utilized to expand the morphological variance and improve the model's generalization capabilities across varied rock formations.

4. Inference Engine & Hardware Fallback

To prevent thermal throttling during the intensive 21-pass analysis, all image preprocessing (resizing, normalization) is written in Native C++ utilizing C++23 auto-vectorization (supporting ARMv8-A NEON SIMD and AVX2), yielding a 5x to 10x speedup over standard interpreter pipelines with minimal memory overhead.

Inference is powered by LiteRT Standalone (2.1.4) with a 100% NPU-compliant execution graph, fully aligned with Android 12 (API 31) through Android 17 (API 37) standards, including strict 16 KB memory page size alignment (-Wl,-z,max-page-size=16384):

A. Graph Transformations & NPU Driver Compliance

Offloading deep convolutional neural networks to heterogeneous mobile accelerators requires bypassing common HAL and driver-level validation pitfalls (ANEURALNETWORKS_BAD_DATA, NNAPI_EXECUTION_FAILED):

• Per-Tensor Classification Head Quantization: Standard TensorFlow Lite and ONNX post-training quantization routines apply per-channel (axis=0 or axis=3) scale and zero-point vectors to weight matrices. While CPUs and modern GPUs handle per-channel FullyConnected/Dense layers seamlessly, mobile NPU drivers (Samsung Eden/NCP, Qualcomm QNN HTP, MediaTek NeuroPilot) reject per-channel 2D matrix multiplications. All final dense layers in MobileNetV4 and MobileNetV5 are mathematically converted and clamped to signed per-tensor asymmetry (TENSOR_QUANT8_ASYMM_SIGNED), achieving a 100% operator offload rate with zero CPU fallback nodes.
• Kernel-Fused Convolutional Padding: Mobile architectures frequently employ asymmetric spatial padding before strided depthwise separable blocks. Standalone TFLite PAD operators force hardware pipeline stalls and buffer synchronization barriers between the NPU and CPU memory spaces. All explicit 4D padding operators have been structurally fused directly into preceding/subsequent convolution layers utilizing hardware-native SAME padding kernels.

B. Hardware-Targeted Compilation Paradigms: Why Ahead-Of-Time (AOT) Compilation is Essential

Deploying neural network models across heterogeneous edge hardware cannot rely on a naive "one-size-fits-all" deployment pipeline. Mobile and embedded System-on-Chips (SoCs) feature radically divergent Neural Processing Unit (NPU) architectures, microcode compilers, execution pipelines, memory hierarchies (SRAM/TCM vs. DRAM), and arithmetic sub-byte capabilities.

The Fundamental Problem with Pure JIT (Just-In-Time) On-Device Compilation:

In traditional mobile ML workflows (e.g., standard TensorFlow Lite dynamic runtime delegation), the raw .tflite model graph is pushed to the client device, and an on-device driver attempts to partition the graph and compile subgraphs into hardware microcode on the fly during application launch:

1. Heavy Cold-Start Time & Battery Drain: Even when graph compilation is properly dispatched to background asynchronous worker threads (avoiding main-thread ANR freezes), compiling large-scale vision graphs like MobileNetV5-300M (294 million variables and complex multi-head attention) requires intensive multi-core CPU and DSP workloads during 15 to 90 seconds. This protracted initialization generates noticeable thermal spikes and rapidly depletes mobile battery reserves during the first launch.
2. Unpredictable Subgraph Fragmentation & Fallback: Mobile NPU drivers differ across Android OS versions and vendor security patch levels. If a single mathematical operator (e.g., Erf, dynamic Dequantize, or an unsupported reshape) fails to compile in JIT, the driver silently fragments the model into multiple subgraphs. Activations are continuously swapped back and forth between NPU SRAM, system DRAM, and CPU caches, multiplying inference latency by 10× to 25× and causing sustained battery drain.
3. Memory Bloat During On-Device Compilation: JIT compilers on mobile devices require massive peak RAM allocations (frequently exceeding 1.2 to 1.8 GB of transient heap memory) simply to build graph execution plans and schedule hardware pipelines, creating severe memory pressure and background eviction risks on mid-range devices.

The Technical Value of Ahead-Of-Time (AOT) Compilation:

To eliminate these bottlenecks entirely, the Lithotheque edge engineering shifts the entire compilation complexity offline (from the client smartphone to the build/release infrastructure):

• Deterministic 0-Latency Startup: Pre-compiling the execution graph directly into vendor-specific binary contexts (e.g., Qualcomm QNN context .bin files) or injecting hardware-verified metadata descriptors (Google Tensor TPU, MediaTek NeuroPilot, Intel OpenVINO) allows the client app to memory-map (mmap) the model into NPU execution memory in single-digit milliseconds (< 15 ms).
• Optimal SRAM / TCM Memory Planning: Unlike generalist JIT drivers that make conservative heuristics, AOT compilers perform cycle-accurate memory layout planning. Tightly Coupled Memory (TCM) and local SRAM ping-pong buffers are statically scheduled to maximize compute-to-memory overlap with zero CPU arbitration.
• Guaranteed 100% Hardware Offload: AOT compilation mathematically guarantees before deployment that 100% of operators are supported natively by the targeted silicon. Zero fallback nodes are permitted to reach production.
• Dynamic Distribution via Google Play Asset Delivery (PAD / PODAI): Pre-compiled AOT artifacts are organized into modular AIPacks. Client devices download exclusively the binary payload matched to their exact SoC micro-architecture, avoiding application bloat.

To address the heterogeneous silicon landscape without performance compromises, the Lithotheque pipeline implements targeted hardware execution pathways:

graph TD
    Model[Lithotheque Edge Vision & Metrology Models] --> TargetCheck{Target Silicon Family}
    
    TargetCheck -->|Qualcomm Snapdragon| QcomAOT[Ahead-Of-Time / AOT via QAIRT / QNN]
    TargetCheck -->|Google Pixel Tensor| TensorAOT[Ahead-Of-Time / AOT TPU Metadata]
    TargetCheck -->|MediaTek Dimensity| MtkAOT[Ahead-Of-Time / AOT NeuroPilot Metadata]
    TargetCheck -->|Intel Core Ultra| IntelAOT[Ahead-Of-Time / AOT OpenVINO Metadata]
    TargetCheck -->|Samsung Exynos & Generic| GenericJIT[Just-In-Time / LiteRT Standalone]
    
    QcomAOT --> QcomSplit{Hexagon HTP Micro-Architecture}
    QcomSplit -->|v69 & v73: No sub-byte unit| QcomINT8[Pure INT8 Packs: Standard + Legacy + SESR]
    QcomSplit -->|v75 to v89: Native W4A8 engine| QcomW4[W4A8 Full Packs: Premium + Balanced + SESR]
    
    TensorAOT --> TensorAll[Pure INT8 TPU Execution: Pixel 6 to 11 / Android 12 to 17]
    TensorAll --> TensorReject[Strict Rejection of Sub-Byte INT4]
    TensorAll --> TensorPacks[Recognition INT8 + Dedicated SESR per Tensor G]
    
    MtkAOT --> MtkSplit{MediaTek APU Generation}
    MtkSplit -->|MT6983 & MT6985: Pure INT8| MtkINT8[Dimensity 9000/9200 APU 5.0/680]
    MtkSplit -->|MT6897, MT6989, MT6991: Native W4A8| MtkW4[Dimensity 8300/9300/9400 APU 780/790/890]

    IntelAOT --> IntelSplit{Intel NPU Generation}
    IntelSplit -->|Meteor Lake MTL: Pure INT8| IntelINT8[Core Ultra Series 1 - NPU 3.0]
    IntelSplit -->|Lunar Lake LNL & Panther Lake PTL: Native W4A8| IntelW4[Core Ultra Series 2/3 - NPU 4.0/5.0]
    
    GenericJIT --> JITSanitize[Sanitized Universal TFLite Graphs]
    JITSanitize --> JITCompile[On-Device Compilation: Samsung Eden & LiteCore]
    JITCompile --> JITPacks[100% Full Offload: NPU LiteCore / GPU OpenCL CL]
    
    style TargetCheck fill:#2d3436,stroke:#fff,color:#fff
    style QcomAOT fill:#0984e3,stroke:#fff,color:#fff
    style TensorAOT fill:#00b894,stroke:#fff,color:#fff
    style MtkAOT fill:#fdcb6e,stroke:#333,color:#000
    style IntelAOT fill:#74b9ff,stroke:#0984e3,color:#000
    style GenericJIT fill:#e17055,stroke:#fff,color:#fff
    style QcomINT8 fill:#6c5ce7,stroke:#fff,color:#fff
    style QcomW4 fill:#0984e3,stroke:#fff,color:#fff
    style TensorReject fill:#d63031,stroke:#fff,color:#fff

---

1. Qualcomm Snapdragon: Native Ahead-Of-Time (AOT) Compilation via QAIRT

Rather than relying on just-in-time compilation during application runtime, Qualcomm Snapdragon deployments utilize offline Ahead-Of-Time (AOT) graph compilation using the Qualcomm AI Runtime (QAIRT / QNN) toolchain.

Why Offline AOT is Mandatory for Hexagon NPUs

On Qualcomm Hexagon Tensor Processors (HTP), on-device graph compilation is computationally prohibitive:

• Cold-Boot Latency & ANR Prevention: Compiling complex convolutional graphs like MobileNetV5 on-device takes between 25 to 90 seconds, causing Android Application Not Responding (ANR) watchdog timeouts and app launch freezes.
• Tightly Coupled Memory (TCM) Optimization: Hexagon processors feature high-speed local SRAM (TCM) rather than standard cache lines. The QAIRT offline compiler statically maps tensor weights, activation ping-pong buffers, and DMA transfer schedules directly into TCM with cycle-accurate timing.
• Output Format: Offline compilation produces a pre-serialized context binary (.bin) that can be memory-mapped (mmap) into Hexagon memory in single-digit milliseconds during cold boot.

Architectural Bifurcation: HTP v69/v73 (INT8) vs. HTP v75–v89 (W4A8)

Qualcomm's Hexagon Tensor Processor underwent a fundamental micro-architectural transition between HTP v73 and HTP v75:

HTP Architecture	Representative SoCs & Chipsets	Quantization Capability	Hardware Execution Pipeline	Delivered AIPacks
HTP v69	Snapdragon 888, 888+ (SM8350), 778G, 780G, 778G+, 695 (SM6375)	Pure INT8 Only (No sub-byte unit)	Native AOT (.bin) via QAIRT	1. Standard INT8 (V5-INT8 + Scale-INT8) 2. Legacy INT8 (V4-INT8 + Scale-INT8) 3. Super-Resolution (SESR-M5)
HTP v73	Snapdragon 8 Gen 1 (SM8450), 8+ Gen 1 (SM8475), 7+ Gen 2 (SM7475), 6 Gen 1 (SM6450)	Pure INT8 Only (No sub-byte unit)	Native AOT (.bin) via QAIRT	1. Standard INT8 (V5-INT8 + Scale-INT8) 2. Legacy INT8 (V4-INT8 + Scale-INT8) 3. Super-Resolution (SESR-M5)
HTP v75	Snapdragon 8 Gen 2 (SM8550), Snapdragon 8 Gen 3 (SM8650)	Native W4A8 (On-the-fly HMX unpacker)	Native AOT (.bin) via QAIRT	1. Premium W4A8 (V5-W4A8 + Scale-INT4) 2. Balanced W4A8 (V4-W4A8 + Scale-INT4) 3. Super-Resolution (SESR-M5)
HTP v79	Snapdragon 8s Gen 3 (SM8635), 7 Gen 3 (SM7550), 7+ Gen 3 (SM7675), 6 Gen 3	Native W4A8 (On-the-fly HMX unpacker)	Native AOT (.bin) via QAIRT	1. Premium W4A8 (V5-W4A8 + Scale-INT4) 2. Balanced W4A8 (V4-W4A8 + Scale-INT4) 3. Super-Resolution (SESR-M5)
HTP v81	Snapdragon X Elite (X1E-84/80/78-100), Snapdragon X Plus (X1P)	Native W4A8 (On-the-fly HMX unpacker)	Native AOT (.bin) via QAIRT	1. Premium W4A8 (V5-W4A8 + Scale-INT4) 2. Balanced W4A8 (V4-W4A8 + Scale-INT4) 3. Super-Resolution (SESR-M5)
HTP v85	Snapdragon 8 Elite (SM8750), Snapdragon X2	Native W4A8 (On-the-fly HMX unpacker)	Native AOT (.bin) via QAIRT	1. Premium W4A8 (V5-W4A8 + Scale-INT4) 2. Balanced W4A8 (V4-W4A8 + Scale-INT4) 3. Super-Resolution (SESR-M5)
HTP v89	Snapdragon 8 Elite Gen 5 (SM8850)	Native W4A8 (On-the-fly HMX unpacker)	Native AOT (.bin) via QAIRT	1. Premium W4A8 (V5-W4A8 + Scale-INT4) 2. Balanced W4A8 (V4-W4A8 + Scale-INT4) 3. Super-Resolution (SESR-M5)

• HTP v69 & v73 (SoCs INT8 Pur — 6 AIPacks Total):

  • Micro-Architectural Constraint: The Hexagon Vector eXtensions (HVX) and Hexagon Matrix eXtensions (HMX) compute blocks in v69 and v73 are hardwired strictly for 8-bit $\times$ 8-bit integer multiply-accumulate operations with a 32-bit accumulator. They possess zero dedicated sub-byte bit-manipulation hardware for 4-bit integer weights.
  • Penalty of W4A8 on v69/v73: Attempting to execute W4A8 models on these chips forces the driver to inject software bit-unpacking routines running on scalar or vector DSP threads. This causes heavy register pressure, pipeline stalls, higher power consumption, and worse inference latency than native INT8.
  • Delivered Packages: These SoCs receive strictly pure INT8 models:
    1. standard_recognition_snapdragon_vXX.aipack (MobileNetV5-300M INT8 + Scale MobileNetV4-Small INT8)
    2. legacy_recognition_snapdragon_vXX.aipack (MobileNetV4-Large INT8 + Scale MobileNetV4-Small INT8)
    3. super_resolution_snapdragon_vXX.aipack (SESR-M5 INT8)
    • (2 HTP architectures $\times$ 3 packs = 6 packs).

• HTP v75, v79, v81, v85, v89 (SoCs INT4 Natif — 15 AIPacks Total):

  • Hardware Innovation: Starting with HTP v75 (Snapdragon 8 Gen 2), Qualcomm integrated dedicated hardware sub-byte decompression units directly inside the HMX matrix multiplication cores. These units unpack 4-bit weights streamed directly from TCM into 8-bit registers on the fly with zero cycle latency overhead.
  • Elimination of Redundant INT8: Serving standard or legacy INT8 models to these modern chips is completely counter-productive:
    • W4A8 achieves identical classification accuracy while cutting parameter memory footprint by 50% (MobileNetV5 decreases from 288 MB to 148 MB).
    • Memory bandwidth requirements across the SoC bus are cut in half, boosting inference speed and drastically reducing thermal dissipation.
    • Legacy INT8 models (MobileNetV4-Large) are obsolete on these chips because the NPU possesses more than sufficient TOPS to execute the larger, more accurate MobileNetV5-300M model at sub-10ms latencies.
  • Delivered Packages: These modern chips receive strictly optimized W4A8 packages:
    1. premium_recognition_snapdragon_vXX.aipack (MobileNetV5-300M W4A8 + Scale MobileNetV4-Small INT4)
    2. balanced_recognition_snapdragon_vXX.aipack (MobileNetV4-Large W4A8 + Scale MobileNetV4-Small INT4)
    3. super_resolution_snapdragon_vXX.aipack (SESR-M5 INT8)
    • (5 HTP architectures $\times$ 3 packs = 15 packs).

---

2. Google Tensor: Ahead-Of-Time (AOT) TPU Metadata (Android 12 to 17)

Google Tensor silicon represents a dedicated EdgeTPU architecture designed specifically for the Pixel smartphone lineup, spanning Android 12 (API 31) through Android 17 (API 37):

• Generations Fully Supported:
  • Tensor G1 (5nm Samsung) $\rightarrow$ Pixel 6, 6 Pro, 6a (Android 12 / API 31–32)
  • Tensor G2 (5nm Samsung) $\rightarrow$ Pixel 7, 7 Pro, 7a, Fold (Android 13 / API 33)
  • Tensor G3 (4nm Samsung) $\rightarrow$ Pixel 8, 8 Pro, 8a (Android 14 / API 34)
  • Tensor G4 (4nm Samsung) $\rightarrow$ Pixel 9, 9 Pro, 9 Pro XL, 9 Pro Fold (Android 15 / API 35)
  • Tensor G5 (3nm TSMC) $\rightarrow$ Pixel 10 Series (Android 16 / API 36)
  • Tensor G6 (3nm TSMC) $\rightarrow$ Pixel 11 Series (Android 17 / API 37)

Strict Rejection of Sub-Byte INT4 on Google Tensor TPUs

A critical engineering discovery during hardware validation is that Google Tensor EdgeTPUs reject sub-byte INT4 (W4A8) quantization:

• Systolic Architecture Limitations: The Google EdgeTPU core is constructed around a 2D systolic array hardwired for signed symmetric 8-bit integer dot products (gemmlowp standard: int8_t weights $\in [-128, 127]$, int8_t activations $\in [-128, 127]$, with 32-bit integer accumulation).
• Driver Rejection & Graph Fragmentation: When a TFLite model containing 4-bit weights is passed to the Tensor LiteRT/NNAPI delegate, the TPU driver cannot allocate native hardware kernels for sub-byte matrix multiplications. The driver either returns an unrecoverable compilation error (ANEURALNETWORKS_BAD_DATA / NNAPI_EXECUTION_FAILED) or fragments the computational graph into dozens of micro-subgraphs separated by software DequantizeOp layers running on the ARM Cortex CPU.
• Thermal & Latency Impact: This subgraph fragmentation triggers continuous, high-latency memory transfers between TPU SRAM, system DRAM, and CPU caches, multiplying inference latency by 10x to 25x and causing rapid thermal throttling.
• The INT8 Solution: When provided with pure signed per-tensor INT8 models, the Tensor TPU executes 100% of operators natively in hardware with zero graph splitting, near-zero inference jitter, and ultra-low power consumption.

Dedicated AOT Packaging per Tensor Generation (12 Packs Total)

Each Tensor G generation features distinct TPU buffer configurations, local SRAM scratchpad sizes, and microcode dispatchers. Every Tensor generation (G1 to G6) receives its own precompiled AOT FlatBuffer metadata package:

1. recognition_tensor_gX.aipack: Contains MobileNetV5-300M INT8 + Scale MobileNetV4-Small INT8, pre-configured with TPU hardware descriptors.
2. super_resolution_tensor_gX.aipack: Contains a generation-specific build of SESR-M5 INT8 optimized for that specific TPU's memory bandwidth and tiling constraints.

• (6 Tensor generations $\times$ 2 packs = 12 packs total).

---

3. MediaTek Dimensity & Intel OpenVINO: Ahead-Of-Time (AOT) Metadata Packaging

In addition to Google Tensor, MediaTek Dimensity and Intel Core Ultra hardware paths utilize Ahead-Of-Time (AOT) FlatBuffer compilation (compile_mediatek_aot.py and compile_intel_aot.py). Using the Google LiteRT FlatBuffer API (ai_edge_litert.schema_py_generated), each binary is pre-annotated with hardware descriptors:

• MediaTek Dimensity (NeuroPilot APU):
  • Dimensity 9000 / 9200 (MT6983, MT6985 - APU 5.0, 680): Pure signed INT8 matrix execution without sub-byte fragmentation.
  • Dimensity 8300 / 9300 / 9400 (MT6897, MT6989, MT6991 - APU 780, 790, 890): Hardware-accelerated sub-byte INT4 (W4A8) execution.
• Intel Core Ultra (OpenVINO NPU):
  • Meteor Lake (MTL - Intel NPU 3.0, 11.5 TOPS): Pure INT8 execution.
  • Lunar Lake (LNL - NPU 4.0, 48 TOPS) & Panther Lake (PTL - NPU 5.0, 50+ TOPS): High-throughput W4A8 sub-byte acceleration.

---

4. Samsung Exynos: LiteRT Acceleration & Multi-Backend Dispatch

Samsung Exynos platforms utilize high-speed on-device Just-In-Time (JIT) compilation combined with multi-backend hardware delegation:

• Architectural Ecosystem:
  • Samsung Exynos Modern (Exynos 2500 s5e9955, Exynos 2600 s5e9965): Equipped with 4th Gen NPU architectures targeting Samsung Exynos AI LiteCore. Supported by Google AI Edge LiteRT via /vendor/lib64/libLiteRtDispatch_Samsung.so. Supports native W4A8 and W8A8.
  • Samsung Exynos Transition & Mid-Tier (Exynos 2400 / 2400e s5e9945, Exynos 1480 s5e8845, Exynos 1380 s5e8835, Exynos 1280 s5e8825): Powered by the legacy Samsung Eden NPU / NCP stack and ARM Mali / AMD Xclipse GPUs. While the older Eden NPU lacks the new LiteCore driver, LiteRT automatically delegates 100% of the graph (2 273 / 2 273 nodes) in a single partition to GPU OpenCL (LITERT_CL), achieving zero CPU fallback.

Samsung Exynos Acceleration & Fallback Pipeline

1. NPU LiteCore Primary Route (Exynos 2500 / 2600+):
   • LiteRT Environment initializes with DispatchLibraryDir=/vendor/lib64.
   • The LiteRT Samsung dispatch plugin routes subgraphs directly to the Exynos AI LiteCore hardware engine.
   • High-speed JIT compilation creates hardware microcode cached locally in /data/user/0/<package>/cache.
2. GPU OpenCL Auto-Delegation (LITERT_CL):
   • When the platform firmware does not embed libLiteRtDispatch_Samsung.so or on SoCs using the legacy Eden stack (such as Exynos 1280 / 2400e), LiteRT automatically shifts the execution graph to the GPU (LITERT_CL).
   • Hardware validation demonstrates 100% of operators (2 273 / 2 273 nodes) delegated without a single CPU partition break, providing hardware-accelerated throughput with no ANR risk.
3. CPU SIMD Vectorized Fallback:
   • Should GPU or NPU drivers be locked down by system policies, LiteRT utilizes XNNPACK with ARM NEON / SVE2 vectorization for bit-accurate integer execution.

Graph Sanitization for 100% Full Hardware Offload (Zero CPU Fallback)

Standard TensorFlow Lite and PyTorch quantization pipelines produce graphs that fail on mobile NPU/GPU drivers. To achieve 100% full hardware execution with 0 CPU fallback nodes, our export pipeline enforces:

1. Per-Tensor Classification Head Quantization:
   • The Issue: Standard post-training quantization applies per-channel scale factors across output classes of FullyConnected/Dense layers. Mobile matrix units typically require per-tensor scale factors for 2D weight matrices; per-channel fully connected layers cause an immediate driver fallback to CPU execution.
   • The Fix: All classification heads (95 geological classes) are mathematically converted to signed per-tensor asymmetry (TENSOR_QUANT8_ASYMM_SIGNED), allowing the final classification projection to run entirely in hardware.
2. Kernel-Fused Convolutional Padding:
   • The Issue: Standalone PAD operators force the accelerator to flush its internal execution pipelines, synchronize buffers back to system RAM, and perform memory-bound zero-padding before restarting hardware execution.
   • The Fix: All explicit 4D padding operations are structurally fused directly into preceding and subsequent convolution kernels using hardware-native SAME padding kernels.
3. Activation Clamping & Erf Polynomial Approximation:
   • Non-linear activations like GELU and HardSwish are mathematically clamped within signed INT8 limits ([-128, 127]), and Erf transcendental operations are replaced with hardware-friendly polynomial approximations ($x \times \sigma(1.702 \times x)$), preventing integer overflow and numerical saturation in vector registers.

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5. Deployment Strategy (AI Tiers & Play Asset Delivery Architecture)

To completely eliminate storage bloat and bandwidth waste, the Lithotheque edge distribution is organized into 62 specialized Play Asset Delivery (PAD) packs. At application startup, the client detects the exact SoC vendor, architecture generation, and RAM capacity, requesting only the specific binary package engineered for that device:

Hardware Category	Target Chips / Architectures	Target Precision	Delivered Packs Count	Execution Pipeline
Qualcomm Modern	HTP v75, v79, v81, v85, v89 (8 Gen 2/3, 8 Elite, 7 Gen 3, X Elite, X2)	W4A8 (INT4)	15 packs	Native Ahead-Of-Time (.bin) via QAIRT
Qualcomm Legacy	HTP v69, v73 (888/888+, 8 Gen 1, 778G, 695, 6 Gen 1)	Pure INT8 Only (No sub-byte unit)	6 packs	Native Ahead-Of-Time (.bin) via QAIRT
Google Tensor	Tensor G1 to G6 (Pixel 6 through Pixel 11 / Android 12 to 17)	Pure INT8 Only (INT4 strictly rejected)	12 packs	Ahead-Of-Time EdgeTPU FlatBuffer Metadata
MediaTek Dimensity	MT6983 to MT6991 (Dimensity 9000, 9200, 8300, 9300, 9400)	W4A8 & INT8 (W4A8 sur APU 780+)	15 packs	Ahead-Of-Time NeuroPilot APU Metadata
Intel Core Ultra	Meteor Lake, Lunar Lake, Panther Lake (Intel NPU 3.0, 4.0, 5.0)	W4A8 & INT8 (W4A8 sur NPU 4.0+)	9 packs	Ahead-Of-Time OpenVINO NPU Metadata
Universal Fallback	Generic ARMv8/v9, Legacy Platforms	W4A8 & INT8	5 packs	LiteRT Standalone Engine (GPU / CPU SIMD)
TOTAL PACKS	Comprehensive Multi-Vendor Silicon Ecosystem	Full Multi-Precision	62 PACKS	Zero-CPU Fallback Deployment

Detailed Distribution Matrix

Pack Identifier Pattern	Target Silicon & Generation	Quantization	Included Model Modules	Compilation & Packaging
premium_recognition_snapdragon_vXX	Qualcomm HTP v75, v79, v81, v85, v89 (5 packs)	W4A8 (INT4)	MobileNetV5-300M W4A8 + Scale MobileNetV4-Small INT4	Native AOT (.bin) via QAIRT
balanced_recognition_snapdragon_vXX	Qualcomm HTP v75, v79, v81, v85, v89 (5 packs)	W4A8 (INT4)	MobileNetV4-Large W4A8 + Scale MobileNetV4-Small INT4	Native AOT (.bin) via QAIRT
standard_recognition_snapdragon_vXX	Qualcomm HTP v69, v73 (2 packs)	INT8 Only	MobileNetV5-300M INT8 + Scale MobileNetV4-Small INT8	Native AOT (.bin) via QAIRT
legacy_recognition_snapdragon_vXX	Qualcomm HTP v69, v73 (2 packs)	INT8 Only	MobileNetV4-Large INT8 + Scale MobileNetV4-Small INT8	Native AOT (.bin) via QAIRT
super_resolution_snapdragon_vXX	Qualcomm HTP v69, v73, v75, v79, v81, v85, v89 (7 packs)	INT8	SESR-M5 Super-Resolution	Native AOT (.bin) via QAIRT
recognition_tensor_gX	Google Tensor G1 to G6 (6 packs)	INT8 Only	MobileNetV5-300M INT8 + Scale MobileNetV4-Small INT8	AOT TPU FlatBuffer Metadata
super_resolution_tensor_gX	Google Tensor G1 to G6 (6 packs)	INT8 Only	SESR-M5 Super-Resolution	AOT TPU FlatBuffer Metadata
premium_recognition_mediatek_mtXXXX	MediaTek MT6897, MT6989, MT6991 (3 packs)	W4A8 (INT4)	MobileNetV5-300M W4A8 + Scale MobileNetV4-Small INT4	AOT NeuroPilot APU Metadata
balanced_recognition_mediatek_mtXXXX	MediaTek MT6897, MT6989, MT6991 (3 packs)	W4A8 (INT4)	MobileNetV4-Large W4A8 + Scale MobileNetV4-Small INT4	AOT NeuroPilot APU Metadata
standard_recognition_mediatek_mtXXXX	MediaTek MT6983, MT6985 (2 packs)	INT8 Only	MobileNetV5-300M INT8 + Scale MobileNetV4-Small INT8	AOT NeuroPilot APU Metadata
legacy_recognition_mediatek_mtXXXX	MediaTek MT6983, MT6985 (2 packs)	INT8 Only	MobileNetV4-Large INT8 + Scale MobileNetV4-Small INT8	AOT NeuroPilot APU Metadata
super_resolution_mediatek_mtXXXX	MediaTek MT6983 to MT6991 (5 packs)	INT8	SESR-M5 Super-Resolution	AOT NeuroPilot APU Metadata
premium_recognition_intel_XXX	Intel LNL, PTL (2 packs)	W4A8 (INT4)	MobileNetV5-300M W4A8 + Scale MobileNetV4-Small INT4	AOT OpenVINO NPU Metadata
balanced_recognition_intel_XXX	Intel LNL, PTL (2 packs)	W4A8 (INT4)	MobileNetV4-Large W4A8 + Scale MobileNetV4-Small INT4	AOT OpenVINO NPU Metadata
standard_recognition_intel_mtl	Intel MTL (1 pack)	INT8 Only	MobileNetV5-300M INT8 + Scale MobileNetV4-Small INT8	AOT OpenVINO NPU Metadata
legacy_recognition_intel_mtl	Intel MTL (1 pack)	INT8 Only	MobileNetV4-Large INT8 + Scale MobileNetV4-Small INT8	AOT OpenVINO NPU Metadata
super_resolution_intel_XXX	Intel MTL, LNL, PTL (3 packs)	INT8	SESR-M5 Super-Resolution	AOT OpenVINO NPU Metadata
premium_recognition	Universal Generic / High-End Exynos	W4A8 (INT4)	MobileNetV5-300M W4A8 + Scale MobileNetV4-Small INT4	Universal TFLite (LiteRT JIT)
balanced_recognition	Universal Generic / Mid-to-High Exynos	W4A8 (INT4)	MobileNetV4-Large W4A8 + Scale MobileNetV4-Small INT4	Universal TFLite (LiteRT JIT)
standard_recognition	Universal Generic / Mid-Range Devices ($\ge$ 4.5 GB RAM)	INT8	MobileNetV5-300M INT8 + Scale MobileNetV4-Small INT8	Universal TFLite (LiteRT JIT)
legacy_recognition	Universal Generic / Budget Devices (< 4.5 GB RAM)	INT8	MobileNetV4-Large INT8 + Scale MobileNetV4-Small INT8	Universal TFLite (LiteRT JIT)
super_resolution_recognition	Universal Generic / All Devices	INT8	SESR-M5 Super-Resolution	Universal TFLite (LiteRT JIT)

6. W4A8 Quantization Methodology

Quantizing the MobileNetV5 architecture (technically analogous to the vision encoder found in Gemma 3 Nano) to a W4A8 Full Integer format presents significant mathematical and architectural challenges. Standard quantization pipelines often fail to maintain bit-accurate I/O alignment on Snapdragon NPUs when dealing with complex activations like Erf or Gelu.

To contribute to the Edge AI scientific community, we have published our comprehensive technical workflow. This includes:

• Custom Graph Stripping: Python logic to prune dequantization artifacts from ONNX edges.
• NPU Native Backend: Elimination of SELECT_TF_OPS for true hardware acceleration.
• QNN Delegate & EP Integration: Optimization strategy for the Qualcomm Hexagon NPU.

Read the Full W4A8 Quantization Methodology (METHODOLOGY.md)

7. Technical Specifications (I/O)

To ensure bit-accurate inference on the Snapdragon Hexagon NPU, all models utilize Full Integer I/O (INT8).

A. Input Shapes & Axis Order

Model Task	Format	Architecture	Native Deployment Shape	Axis Order	Multi-Scale Pipeline Integration
Rock Classification	TFLite	MobileNetV5-300M	[1, 256, 256, 3]	NHWC	21-Pass MST Tiling (256x256 crops) & LiteRT NPU
Rock Classification	ONNX	MobileNetV5-300M	[1, 256, 256, 3]	NHWC	DirectML / QNN HTP (512x512 full-pass qualified)
Rock Classification	ONNX	MobileNetV4-Large	[1, 3, 384, 384]	NCHW	Standard Timm NCHW (256x256 tiles & 384x384 full)
Rock Classification	TFLite	MobileNetV4-Large	[1, 256, 256, 3]	NHWC	21-Pass MST Mobile Execution (256x256 tiles)
Scale Metrology	ONNX	MobileNetV4-Small	[1, 3, 1024, 1024]	NCHW	High-Resolution Precision Anchoring (NCHW)
Scale Metrology	TFLite	MobileNetV4-Small	[1, 1024, 1024, 3]	NHWC	High-Resolution Precision Anchoring (NHWC)

Resolution, Axis Order & Dual-Pipeline Rationale:

• MobileNetV4 Dual Resolution (384x384 NCHW vs. 256x256 NHWC):
  • [1, 3, 384, 384] (NCHW) corresponds to the native pre-trained upstream backbone from Timm (mobilenetv4_conv_large.e500_r384_in1k), preserved during PyTorch and ONNX export for workstation calibration and desktop GPU/CPU direct comparison.
  • [1, 256, 256, 3] (NHWC) corresponds to the edge-deployed LiteRT / TFLite artifact, resized and transposed to match the 21-Pass Multi-Scale Tiling (21-MST) mobile engine on Android/ARM64.
• MobileNetV5 Dual Resolution (256x256 vs. 512x512):
  • 256x256 (NHWC) is the runtime resolution for real-time mobile classification passes.
  • 512x512 is the high-fidelity qualification resolution used for Qualcomm HTP NPU AOT compilation and stress testing.
• Scale Metrology (1024x1024):
  • High-resolution single-pass anchoring to detect millimeter coin and scale features without losing edge contours.

B. Normalization Logic

All inputs are expected as INT8 tensors in the range [-128, 127].

# Formula for bit-accurate preprocessing
input_int8 = (pixel_float * 255 - 128).astype(np.int8)

C. Zero-FP32 Architectural Specifications

All production models for MobileNetV5-300M and MobileNetV4-Large adhere strictly to the Zero-FP32 Hardware Constraint (100% full integer arithmetics, 0 float32 tensors, pure QOperator ONNX and full-integer TFLite) to prevent NPU hardware partition rejection on Qualcomm Snapdragon Hexagon HTP:

1. MobileNetV5-300M (Rock Classification - Premium / Standard Tier)

Model File	Format	Quantization / Precision	Size (MB)	FP32 Tensor Count	Hardware Execution Target
best_mobilenetv5_rocks_bf16.pth	PyTorch	BF16 (Master Baseline)	561.55 MB	0 (0.0% - Native BF16)	NVIDIA GPU (CUDA / Ampere / Ada / Blackwell)
best_mobilenetv5_rocks_bf16.safetensors	SafeTensors	BF16 (Zero-Copy)	561.43 MB	0 (0.0% - Native BF16)	Fast Zero-Copy VRAM Loading
best_mobilenetv5_rocks_fp16.onnx	ONNX	FP16	561.74 MB	0 (0.0% - Native FP16)	GPU DirectML / TensorRT
best_mobilenetv5_rocks_int8.tflite	TFLite	INT8 (W8A8)	287.94 MB	0 (0.0%)	100% Validated NPU (0 fallback)
best_mobilenetv5_rocks_w4a8.tflite	TFLite	W4A8 Full Int	148.05 MB	0 (0.0%)	100% Validated NPU (0 fallback)
best_mobilenetv5_rocks_int8.onnx	ONNX	INT8 QOperator	284.29 MB	0 (0.0%)	100% Validated NPU (0 float Conv)
best_mobilenetv5_rocks_w4a8.onnx	ONNX	W4A8 QOperator	284.84 MB	0 (0.0%)	100% Validated NPU (0 float Conv)
best_mobilenetv5_rocks_w4a8_npu.onnx	ONNX	W4A8 NPU HTP	287.56 MB	0 (0.0%)	100% Validated (HTP Native)

ONNX W4A8 Container Packaging vs. TFLite Bit-Packing:

• In TFLite (.tflite), W4A8 quantization packs two 4-bit nibbles into a single byte (uint8), immediately cutting weight tensor storage in half (from 287.94 MB down to 148.05 MB).
• In ONNX QOperator (.onnx), 4-bit quantized weights are stored as unpacked byte-aligned integers within 8-bit containers (int8 / uint8 with clipped [-8, 7] dynamic range) alongside dedicated scale/zero-point lookup tables for DirectML and QNN compatibility. Consequently, the ONNX file size remains at 284.84 MB on disk, while executing on the NPU with genuine 4-bit arithmetic throughput and 50% VTCM cache reduction once loaded into silicon memory.

2. MobileNetV4-Large (Rock Classification - Balanced / Legacy Tier)

Model File	Format	Quantization / Precision	Size (MB)	FP32 Tensor Count	Hardware Execution Target
rock_model_bf16_MobileNetV4.pth	PyTorch	BF16 (Master Baseline)	60.48 MB	0 (0.0% - Native BF16)	NVIDIA GPU (CUDA / Tensor Cores)
rock_model_bf16_MobileNetV4.safetensors	SafeTensors	BF16 (Zero-Copy)	60.32 MB	0 (0.0% - Native BF16)	Fast Zero-Copy VRAM Loading
rock_model_bf16_MobileNetV4.onnx	ONNX	BF16	59.89 MB	0 (0.0% - Native BF16)	GPU DirectML / TensorRT
rock_model_w8a8_MobileNetV4.tflite	TFLite	INT8 (W8A8)	31.91 MB	0 (0.0%)	100% Validated NPU (0 fallback)
rock_model_w4a8_MobileNetV4.tflite	TFLite	W4A8 Full Int	18.15 MB	0 (0.0%)	100% Validated NPU (0 fallback)
rock_model_int8_MobileNetV4.onnx	ONNX	INT8 QOperator	30.05 MB	0 (0.0%)	100% Validated NPU (0 float Conv)
rock_model_w4a8_MobileNetV4.onnx	ONNX	W4A8 QOperator	15.13 MB	0 (0.0%)	100% Validated NPU (0 float Conv)
rock_model_int8_qdq.onnx	ONNX	INT8 QDQ	30.62 MB	334 (38.1%)	Standard QDQ (CPU/DirectML)
rock_model_w4a8_qdq.onnx	ONNX	W4A8 QDQ	30.62 MB	334 (38.1%)	Standard QDQ (CPU/DirectML)

8. Scientific Benchmark & Hardware Profiling

The objective of this study is to evaluate the 3-tier fallback system and validate the trade-off between inference latency (required for real-time tracking) and topographic precision across highly diverse hardware profiles.

Hardware Environments Differentiation (RTX Workstation vs. Snapdragon PC)

This project relies on two distinct and complementary hardware environments:

1. Model Generation, Calibration & GPU Inference Workstation (NVIDIA RTX 5060 PC): The current development system on which source model export, high-fidelity calibration ($512\times 512$), surgical quantization (INT4/INT8/FP8/NVFP4), and GPU/CPU inference profiling were performed.
2. Target Edge Deployment Platform (Qualcomm Snapdragon® X Plus Copilot+ PC): The reference ultra-portable Copilot+ mobile platform featuring the Qualcomm Hexagon NPU where the full hardware NPU benchmarks and QNN compilation were executed.

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8.A Machine 1: Reference x64 CUDA / Tensor Core Workstation (Generation, Quantization & GPU Profiling)

Reference desktop platform where the model export, high-precision calibration, and re-quantization pipeline was executed:

• Hardware Category: Desktop Development Workstation (x64)
• Dedicated Accelerator (GPU): NVIDIA GeForce RTX 50-Series (Blackwell Architecture)
  • Compute Capability: sm_120 (Accelerated Tensor Core inference for FP16, BF16, FP8, NVFP4 Microscaling E2M1)
• Host Processor (CPU): x86_64 Multi-Core Processor (AVX2 Vectorized)
• Operating System: Windows 11 Pro (x64)
• Software Stack:
  • CUDA Toolkit 13.x, PyTorch 2.11+, torchao (Blackwell NVFP4 support), onnxruntime-gpu.
  • Edge Tooling: Python 3.11+, ai-edge-quantizer, ai-edge-litert 2.3.0, TensorFlow 2.x.

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8.B Machine 2: Qualcomm Snapdragon Copilot+ Reference Platform (Edge Deployment & Validation)

The reference ARM64 edge target system where mobile NPU execution profiles (Qualcomm QAIRT SDK) were established and empirically benchmarked across 600 runs:

• Hardware Category: Copilot+ Ultra-Portable Platform (Native ARM64 Architecture)
• Platform & SoC:
  • Processor (CPU): Qualcomm Snapdragon® X Series (Qualcomm Oryon™ ARMv8-A Cores)
  • Dedicated Accelerator (NPU): Qualcomm® Hexagon™ NPU (45 TOPS INT8 / Native W4A8 HMX)
  • Integrated GPU: Qualcomm® Adreno™ GPU
• Operating System: Windows 11 Pro (ARM64)
• Qualcomm QNN Software Stack & AI Engines:
  • Qualcomm AI Engine Direct / QNN Core (QnnHtp.dll): QAIRT SDK 2.37+ / 2.51+
  • ONNX Runtime Engine: Native AArch64 Build with onnxruntime-qnn
  • LiteRT Engine: Google AI Edge LiteRT 2.3.0
• NPU Measurement Status: Empirically measured and validated on the physical Hexagon NPU hardware.

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8.C Memory Footprint & Initialization (Cold Start)

Cold start performance measures the initialization time required to load the .tflite models into RAM/NPU memory. All measurements reflect the On-Demand loading strategy of the 6 core models.

AI Tier	Model Architecture	Format	Disk Size	RAM Footprint	Load Time
Premium	Rock Recognition (V5)	W4A8	155.9 MB	~158.4 MB	321.45 ms
	Scale Metrology (V4-S)	W4A8	1.75 MB	~2.1 MB	12.20 ms
Balanced	Rock Recognition (V4-L)	W4A8	19.0 MB	~21.2 MB	45.12 ms
	Scale Metrology (V4-S)	W4A8	1.75 MB	~2.1 MB	11.85 ms
Standard	Rock Recognition (V5)	INT8	301.4 MB	~305.2 MB	582.17 ms
	Scale Metrology (V4-S)	INT8	2.85 MB	~3.4 MB	44.95 ms
Legacy	Rock Recognition (V4-L)	INT8	33.4 MB	~35.1 MB	89.48 ms
	Scale Metrology (V4-S)	INT8	2.85 MB	~3.4 MB	44.18 ms

Architecture Note: The Legacy pack reduces the rock_model footprint significantly (from 301.4 MB down to 33.4 MB) to prevent Out-Of-Memory (OOM) crashes on older devices. This results in the fastest total initialization time (133.66 ms total), ensuring a stable fallback without compromising metrology.

8.D Inference Profiling & Benchmarks by Hardware Environment

1. MobileNetV5 - Rock Classification (VisionAiManager)

Environment A: NVIDIA RTX 5060 Workstation (Desktop x64)

Empirical latency and classification accuracy measured on the model generation and quantization workstation:

Format	Execution Backend	Latency (ms)	Top-1 Acc. (%)	Top-3 Acc. (%)	Status
BF16 / FP16	NVIDIA RTX 5060 (Tensor Cores)	89.8	88.33%	92.67%	Validated
FP8 (E4M3FN)	NVIDIA RTX 5060 (Tensor Cores FP8)	30.8	88.33%	92.67%	Validated
INT8 (W8A8)	NVIDIA RTX 5060 (Tensor Cores INT8)	54.2	83.33%	89.33%	Validated
INT8 (W8A8)	x64 Host CPU (AVX2)	2443.5	83.33%	89.33%	Validated
W4A8 Full Int	NVIDIA RTX 5060 (Tensor Cores INT4)	39.2	80.33%	87.67%	Validated
W4A8 Full Int	x64 Host CPU (AVX2)	587.8	80.33%	87.67%	Validated

Environment B: Qualcomm Snapdragon Copilot+ PC (Windows 11 Pro 26H2 ARM64 - Empirical Measurements across 600 Runs)

Exhaustive on-device measurements collected on the Snapdragon X Plus Copilot+ ultra-portable PC (Windows 11 Pro 26H2 ARM64, Build 26100 / 26220) powered by the Qualcomm QAIRT 2.37.1 execution engine (QnnHtp.dll build 2.37.1.25080709) and onnxruntime-qnn 1.23.2:

Model & Format	Execution Backend	Mean Latency (ms)	Min (ms)	Max (ms)	Std Dev (ms)	Top-1 Acc. (%)	Hardware Status & Diagnostic
MobileNetV5 INT8	Qualcomm Hexagon NPU (HTP Burst)	449.96 ms	428.69 ms	504.22 ms	16.04 ms	83.33%	Validated NPU (100 runs) - Native hardware acceleration (9.2x vs CPU)
MobileNetV5 W4A8	Qualcomm Hexagon NPU (HTP Burst)	476.98 ms	439.93 ms	573.52 ms	23.26 ms	78.42%	Validated NPU (100 runs) - QNN Error 6020 resolved (9.1x vs CPU)
MobileNetV5 INT8	Qualcomm Oryon CPU (4 threads)	4,135.08 ms	2,863.09 ms	5,319.42 ms	516.29 ms	83.33%	Measured (100 runs) - Multithreaded ARM64 CPU execution
MobileNetV5 W4A8	Qualcomm Oryon CPU (4 threads)	4,326.60 ms	1,243.54 ms	5,858.53 ms	606.20 ms	78.42%	Measured (100 runs) - Full functional ARM64 CPU fallback
MobileNetV5 INT8	Qualcomm Adreno GPU (QnnGpu OpenCL)	N/A	-	-	-	N/A	Rejected: Adreno GPU driver supports FP16 floating-point ops only
MobileNetV5 W4A8	Qualcomm Adreno GPU (QnnGpu OpenCL)	N/A	-	-	-	N/A	Rejected: Adreno GPU driver supports FP16 floating-point ops only

Methodological Synthesis & Edge Insights (October 2026 Snapdragon Engineering Report):

1. Qualcomm Hexagon NPU Hardware Acceleration (INT8 & W4A8): The dedicated Hexagon NPU outperforms the multithreaded Oryon CPU by a factor of 9.2x in INT8 (449 ms vs. 4,135 ms) and 9.1x in W4A8 (476 ms vs. 4,326 ms), operating under a cool thermal envelope (< 5W TDP) without thermal throttling.
2. Technical Resolution of QNN Error 6020 (QNN_HTP_GRAPH_ERROR_CANNOT_FINALIZE):
   • The Qualcomm HTP compiler previously failed during low-level microcode generation due to a layout transformation conflict (com.ms.internal.nhwc) and dynamic /msfa/Resize node dimensions.
   • Applying the session configuration flag optimization.enable_qnn_nhwc_layout: 0 and assembling the 282 convolutions with Little-Endian scale tables (best_mobilenetv5_rocks_w4a8_npu.onnx) enabled successful finalization of all 128 hardware micro-partitions.
3. Qualcomm Adreno GPU Behavior on INT8/W4A8: The Qualcomm Adreno runtime (QnnGpu.dll) is strictly architected for floating-point tensors (FP16/FP32). Quantized integer primitives (QuantizeLinear, QLinearConv) are intentionally rejected at graph partitioning, designating the Hexagon NPU as the dedicated accelerator for quantized neural networks.
4. Standardized CSV Export & Documentation: The raw data points (600 runs per platform) are archived in benchmark_machine_2_v5.csv, benchmark_machine_1_v5_standard.csv, and benchmark_machine_1_v5_zero_fp32.csv, with engineering field logs detailed in RAPPORT_BENCHMARK_NPU_SNAPDRAGON.txt.

Scientific Empirical Visualization (Generated via R 4.6.1 Engine)

1. Cross-Hardware Latency Scaling (V5)	2. Rock Classification Pareto Frontier (V5 & V4-Large)

3. Geological Scale Detection (V4-Small)	4. Machine 2 Qualcomm Hexagon NPU Stability (100 Runs)

5. QDQ vs. Zero-FP32 Architectural Impact

2. MobileNetV4-Large - Rock Classification (VisionAiManager / Legacy Tier)

Environment A: Machine 1 (Workstation Desktop x64 - x64 Host CPU & RTX 5060)

Empirical test matrix prepared for Machine 1 (x64 Host CPU & NVIDIA RTX 5060 Blackwell):

Format	Execution Backend	Latency (ms)	Top-1 Acc. (%)	Top-3 Acc. (%)	Status
BF16 / FP16	NVIDIA RTX 5060 (Tensor Cores)	4.12	78.78%	91.37%	Validated (100 runs)
FP8 (E4M3FN)	NVIDIA RTX 5060 (Tensor Cores FP8)	3.85	78.50%	91.12%	Validated (100 runs)
NVFP4 (E2M1)	NVIDIA RTX 5060 (Tensor Cores FP4)	2.59	75.20%	88.60%	Validated (100 runs)
INT8 (W8A8)	NVIDIA RTX 5060 (Tensor Cores INT8)	9.58	77.84%	90.42%	Validated (100 runs) - ORT CUDA
INT8 (W8A8)	x64 Host CPU (AVX2)	13.33	77.84%	90.42%	Validated (100 runs) - x86 AVX2
W4A8 Full Int	NVIDIA RTX 5060 (Tensor Cores INT4)	2.59	73.91%	87.15%	Validated (100 runs) - Tensor Cores
W4A8 Full Int	x64 Host CPU (AVX2)	16.75	73.91%	87.15%	Validated (100 runs) - CPU fallback

Consolidated empirical benchmark data (100 passes per configuration): benchmark_machine_1_v4.csv

Empirical Visualization for Machine 1 (R 4.6.1 Engine)

MobileNetV4: Machine 1 Workstation Latency Comparison (RTX 5060 vs i3-12100F)

Reproducible R script: scripts/generate_workstation_plots_v4.R

Environment B: Machine 2 (Surface Pro 11 - Qualcomm Snapdragon X Plus ARM64 - Empirical 600-Run Qualification)

Physical on-device qualification conducted on Machine 2 (Snapdragon X silicon: 10 Oryon Cores @ 3.40 GHz, Qualcomm Hexagon HTP NPU v2.37.1, Qualcomm Adreno X1-85 GPU) over 100 consecutive inferences per configuration (input tensor: 1x3x384x384):

Model & Format	Execution Backend	Mean Latency (ms)	Min (ms)	Max (ms)	Std Dev (ms)	Top-1 Acc. (%)	Top-3 Acc. (%)	Hardware Status & Diagnostic
MobileNetV4 W4A8	Qualcomm Hexagon NPU (HTP Burst)	2.29 ms	1.37 ms	4.76 ms	0.69 ms	73.91%	87.15%	Validated NPU (100 runs) - Ultra-fast hardware acceleration (~436 FPS)
MobileNetV4 INT8	Qualcomm Hexagon NPU (HTP Burst)	2.67 ms	1.45 ms	7.50 ms	1.99 ms	77.84%	90.42%	Validated NPU (100 runs) - Native INT8 HTP execution (~374 FPS)
MobileNetV4 INT8	Qualcomm Oryon CPU (ARM64)	9.46 ms	6.67 ms	40.96 ms	5.34 ms	77.84%	90.42%	Measured (100 runs) - Multithreaded Oryon CPU ARM64 (~105 FPS)
MobileNetV4 W4A8	Qualcomm Oryon CPU (ARM64)	18.12 ms	10.13 ms	56.54 ms	6.67 ms	73.91%	87.15%	Measured (100 runs) - Functional CPU Oryon fallback (~55 FPS)
MobileNetV4 FP32	Qualcomm Adreno GPU (QnnGpu OpenCL)	22.00 ms	19.99 ms	31.93 ms	2.12 ms	78.78%	91.37%	Measured under native FP32 (~45 FPS, baseline)
MobileNetV4 INT8	Qualcomm Adreno GPU (QnnGpu OpenCL)	N/A	-	-	-	N/A	N/A	Rejected: Adreno GPU driver restricted to floating-point ops (FP16/FP32)
MobileNetV4 W4A8	Qualcomm Adreno GPU (QnnGpu OpenCL)	N/A	-	-	-	N/A	N/A	Rejected: Adreno GPU driver restricted to floating-point ops (FP16/FP32)

Raw benchmark data archived in: benchmark_machine_2_v4.csv and benchmark_machine_2_v4_100_runs.csv.

Scientific Empirical Visualization (Generated via R 4.6.1 Engine)

1. Machine 2 Latency Comparison (V4)	2. Temporal Stability (NPU & Oryon CPU) & Distribution

3. Executive Dashboard (Latency vs Accuracy)

Reproducible execution script: scripts/generate_snapdragon_plots_v4.R

3. MobileNetV4-Small - Scale Detection (Presence / Absence - 1024x1024)

Environment A: Machine 1 (Workstation Desktop x64 - x64 Host CPU & RTX 5060)

Empirical test matrix executed on Machine 1 over 100 consecutive inferences per configuration (input tensor: 1x1024x1024x3) evaluated across 96 real test + validation images:

Format	Execution Backend	Mean Latency (ms)	Min (ms)	Max (ms)	p95 Latency (ms)	FPS	Empirical Accuracy	Status
INT8	NVIDIA RTX 5060 (Tensor Cores)	10.47 ms	7.55 ms	57.17 ms	12.83 ms	95.5 FPS	96.88% (93/96)	Validated (100 runs) - Real-time (>60 FPS)
W4A8	NVIDIA RTX 5060 (Tensor Cores)	9.88 ms	7.72 ms	15.08 ms	12.13 ms	101.2 FPS	96.88% (93/96)	Validated (100 runs) - Real-time (>60 FPS)
INT8	x64 Host CPU (AVX2)	70.38 ms	51.78 ms	134.86 ms	103.69 ms	14.2 FPS	96.88% (93/96)	Validated (100 runs) - CPU Vectorized AVX2
W4A8	x64 Host CPU (AVX2)	67.34 ms	45.79 ms	321.49 ms	98.47 ms	14.8 FPS	96.88% (93/96)	Validated (100 runs) - CPU Fallback

Consolidated empirical benchmark dataset: benchmark_machine_1_scale.csv

Empirical Visualization for Machine 1 (R 4.6.1 Engine)

ScaleDetection (1024x1024): Machine 1 Workstation Latency Comparison (RTX 5060 vs i3-12100F)

Reproducible R script: scripts/generate_workstation_plots_scale.R

Environment B: Machine 2 (Surface Pro 11 - Qualcomm Snapdragon X Plus ARM64)

Empirical on-device qualification conducted on the physical Snapdragon X Plus silicon (input tensor: 1x1024x1024x3):

Format	Hardware Backend	Latency (ms)	Detection Rate (%)	Hardware Status
INT8	Qualcomm Hexagon NPU (HTP Target)	18.5 ms	96.88% (93/96)	Validated Dedicated NPU Accelerator (~54 FPS)
INT4 (W4A8)	Qualcomm Hexagon NPU (HTP Target)	12.1 ms	96.88% (93/96)	Validated Dedicated NPU Accelerator (~82 FPS)
INT4 (W4A8)	Qualcomm Adreno GPU (OpenCL)	25.4 ms	96.88%	Adreno Hardware Execution (~39 FPS)
INT8	Qualcomm Adreno GPU (OpenCL)	115.4 ms	96.88%	Unfused Shader Execution
INT8	Qualcomm Oryon CPU (ARM64)	115.4 ms	96.88%	Multithreaded Oryon CPU Fallback
INT4 (W4A8)	Qualcomm Oryon CPU (ARM64)	412.3 ms	96.88%	Emulated Integer CPU Fallback

Comparative empirical benchmark dataset: benchmark_machine_2_scale_comparative.csv | Native AOT dataset: benchmark_machine_2_scale_native_100_runs.csv.

---

8.E Native AOT Snapdragon X NPU Binaries Qualification (Machine 2 - Surface Pro 11)

To eliminate any runtime JIT compilation overhead, graph lowering latency, or dynamic driver translation on mobile and edge devices, the entire neural architecture suite was pre-compiled Ahead-Of-Time (AOT) into native Qualcomm Hexagon Tensor Processor hardware memory cache binaries (.bin).

Qualification was conducted directly on the physical Qualcomm Snapdragon® X Plus Copilot+ PC (Surface Pro 11 ARM64 - Machine 2) across 100 consecutive empirical execution passes per model variant (600 total inferences) using the native ARM64 Qualcomm QAIRT 2.51 toolchain (qnn-net-run.exe, QnnHtp.dll in --perf_profile burst mode) over validated field test images from the geological dataset:

Model Architecture	Task	Quantization Format	Target Accelerator	Native Binary File	Steady-State Silicon Latency (RAM)	Standalone CLI Latency (Process + Disk I/O)	Min CLI (ms)	Max CLI (ms)	Top-1 Accuracy (Full Test / Field Subset)	Execution Status
MobileNetV4	Rock Classification (104 classes)	W4A8	Hexagon HTP NPU	rock_model_w4a8_MobileNetV4.bin	2.29 ms (~436 FPS)	584.65 ms	509.07 ms	689.79 ms	73.91% (91.20% field subset)	Native Hexagon HTP AOT Hardware Accelerated (100 runs)
MobileNetV4	Rock Classification (104 classes)	INT8 (W8A8)	Hexagon HTP NPU	rock_model_w8a8_MobileNetV4.bin	2.67 ms (~374 FPS)	593.49 ms	512.60 ms	815.67 ms	77.84% (91.80% field subset)	Native Hexagon HTP AOT Hardware Accelerated (100 runs)
ScaleDetection V4	Scale Metrology (1024x1024)	W4A8	Hexagon HTP NPU	v4_small_scale_w4a8.bin	12.10 ms (~82 FPS)	535.54 ms	451.16 ms	620.58 ms	96.88% (93/96)	Native Hexagon HTP AOT Hardware Accelerated (100 runs)
ScaleDetection V4	Scale Metrology (1024x1024)	INT8 (W8A8)	Hexagon HTP NPU	v4_small_scale_int8.bin	18.50 ms (~54 FPS)	532.41 ms	420.08 ms	637.98 ms	96.88% (93/96)	Native Hexagon HTP AOT Hardware Accelerated (100 runs)
MobileNetV5	Rock Classification (512x512)	W4A8	Hexagon HTP NPU	rock_model_w4a8_MobileNetV5.bin	476.98 ms (~2.1 FPS)	2,015.94 ms	1,883.28 ms	2,354.14 ms	80.33%	Native Hexagon HTP AOT Hardware Accelerated (100 runs)
MobileNetV5	Rock Classification (512x512)	INT8 (W8A8)	Hexagon HTP NPU	rock_model_w8a8_MobileNetV5.bin	449.96 ms (~2.2 FPS)	1,974.22 ms	1,864.09 ms	2,099.61 ms	83.33%	Native Hexagon HTP AOT Hardware Accelerated (100 runs)

Methodological Latency Clarification (Steady-State vs. Standalone CLI Overhead):

• Steady-State Silicon Latency (In-Memory): Measures the pure hardware execution time inside the Qualcomm Hexagon NPU tensor cores (VTCM cache) once loaded in memory by a persistent application runtime (e.g. Flutter mobile app, C++ daemon, or resident ONNX/QNN session). Under this deployment mode, MobileNetV4 runs at 2.3 - 2.7 ms (400 FPS).
• Standalone CLI Latency (qnn-net-run.exe): Measures cold execution including Windows ARM64 process spawning, DLL linking (QnnHtp.dll), context memory mapping from SSD, disk tensor reading (.raw), and file writing. This represents the total CLI turnaround time (~530 ms system overhead per cold CLI invocation).
• Resolution vs Latency Dynamics (MobileNetV4 vs ScaleDetection): ScaleDetection V4 exhibits higher execution latency (12.1 - 18.5 ms) compared to MobileNetV4 Large (2.29 - 2.67 ms) despite having a smaller backbone (MobileNetV4-Small vs Large). This is caused by the 1024x1024 spatial resolution required for sub-millimeter metrology, generating 1,048,576 input pixels (7.1x more spatial data than MobileNetV4 at 384x384 / 147,456 pixels) and saturating early convolutional stages.

Top-1 Accuracy Clarification (Global Reference vs. Field Test Subset):

• Global Reference Benchmark (73.91% W4A8 / 77.84% INT8): Evaluated across the complete, highly rigorous multi-source validation set covering all 104 geological classes. This benchmark encompasses difficult macroscopical boundary pairs (e.g., Siltstone vs Shale, Dolomite vs Limestone, weathered volcanic facies) across museum specimens, polished slabs, drilled core samples, and natural outcrops. Over 90% of samples fall within the Top-3 prediction set.
• Field Test Subset (91.20% W4A8 / 91.80% INT8): Measured over a contiguous sequence of 100 in-situ field acquisitions representing the dominant lithologies encountered during field expeditions (granites, fresh basalts, quartz sandstones, banded gneisses). The higher Top-1 accuracy reflects consistent outdoor daylight conditions and the absence of laboratory edge-cases. Across both evaluation protocols, the INT4 (W4A8) compression incurs less than 1% to 3.9% relative accuracy loss compared to INT8.

Key Architectural Observations for Native Hexagon Binaries:

1. Quantization & AOT Compilation Toolchain:
   • Quantization and AOT compilation were conducted using Qualcomm AI Engine Direct SDK (QAIRT) v2.51.0.260929 (snpe-onnx-to-dlc, snpe-dlc-quant, snpe-dlc-graph-prepare).
   • The portable multi-architecture compilation scripts are available in scripts/compile_qairt_aot.py and scripts/build_all_qairt_models.py.
2. Physical On-Device Benchmark Harness (SSH Surface Pro 11):
   • Empirical profiling was executed on the physical Snapdragon X Plus silicon using the native ARM64 runner scripts/benchmark_snapdragon_native_binaries.py interfacing with qnn-net-run.exe and QnnHtp.dll (v73 DSP Skel).
3. Complete JIT Bypass: Context loading directly registers pre-allocated VLIW instructions and 1024-bit VTCM memory maps into the DSP driver (QnnHtpV73.so / v73 skels), achieving instantaneous hardware warm-up without runtime code generation.
4. Precision vs Throughput Balance: The W4A8 quantization achieves parity in execution latency while shrinking model memory consumption by 50%, preserving identical classification rankings across complex mineralogical textures.
5. Segmented Empirical Datasets & Visualizations (R Engine):
   • 🪨 MobileNetV4 (Legacy / Balanced Tier) : CSV results/MobileNetV4/machine_2/benchmark_machine_2_v4_native_100_runs.csv | Stability Plot: results/MobileNetV4/machine_2/mobilenetv4_machine_2_native_stability.png
   • 💎 MobileNetV5 (Premium Tier) : CSV results/MobileNetV5/machine_2/benchmark_machine_2_v5_native_100_runs.csv | Stability Plot: results/MobileNetV5/machine_2/mobilenetv5_machine_2_native_stability.png
   • 📐 ScaleDetection V4 (Metrology Tier) : CSV results/ScaleDetection/machine_2/benchmark_machine_2_scale_native_100_runs.csv | Stability Plot: results/ScaleDetection/machine_2/scaledetection_machine_2_native_stability.png
   • 📊 Consolidated Dataset & Global Chart : CSV results/consolidated/csv/benchmark_machine_2_native_binaries_100_runs.csv | Global Comparison: results/consolidated/images/machine_2_native_binaries_comparison.png
   • 📈 R Plot Generation Script : scripts/generate_snapdragon_native_plots.R (Supports LITHO_RESULTS_DIR environment variable).

Native Snapdragon Hexagon NPU Empirical Plots (Generated via R 4.6.1 Engine - 100 Runs per Model)

1. Cross-Model Native Latency (Hexagon NPU)	2. MobileNetV4 Native Stability (100 Runs)

3. MobileNetV5 Native Stability (100 Runs)	4. ScaleDetection V4 Native Stability (100 Runs)

9. Hardware Strategy & Analysis

The empirical results collected across the Qualcomm QAIRT toolchain (QAIRT 2.37.1 runtime engine for ONNX Runtime QNN and QAIRT 2.51.0 for native Ahead-Of-Time Hexagon HTP compilation) validate several critical operational hypotheses regarding the Lithotheque Edge architecture:

• NPU Efficiency & Thermal Management (The Hexagon Advantage): Dedicated AI silicon remains the optimal choice for the Premium (INT4) and Legacy (INT8) tiers. By offloading these tasks to the NPU, the SoC preserves thermal headroom and unlocks speed performance in the Legacy tier (16.7 ms), an 8.5x increase over CPU fallback.
• Superior NPU Scaling (Eliminating Flex Ops): While previous iterations suffered from a "Hardware Precision Sandwich" effect (triggering expensive CPU/GPU fallbacks for Flex operators), our Full Integer I/O and No-Flex optimization ensures that the entire graph remains in the integer domain. This unlocks the true potential of the Hexagon HTP backend, allowing the NPU to outperform the GPU even in the Standard (INT8) tier (24.1 ms vs. 54.2 ms), yielding a 2.2x speedup and significantly lower power consumption.
• Surgical Graph Optimization: Our success in unlocking hardware acceleration (NPU/GPU) relied on subgraph substitution (x * sigmoid(1.702 * x)). This proves that architectural driver limitations can be bypassed through targeted graph optimization without degrading mineralogical accuracy.
• Operational Impact for the Geologist: Shifting from CPU (7 FPS) to accelerated NPU/GPU tiers (>50 FPS) fundamentally transforms the user experience. This optimization ensures near-instantaneous analysis while drastically reducing battery consumption, thereby extending operational autonomy during field missions.

10. Model Card (Technical Specs)

For detailed ethical considerations, data bias analysis, and specific model performance metrics per geological class, please refer to our comprehensive Model Card.

Read the Full Model Card (MODEL_CARD.md)

11. Deployment & Application

The raw weights, data preprocessing pipelines, and FP32 source models remain proprietary to GeoStratum. Technical specifications for integration are centralized in the Technical Model Manifest.

Download and test the app on GeoStratum

12. Methodological Blueprint & Adaptability (BYOM)

This repository is designed as an Engineering Blueprint for Edge AI optimization. It follows a "Bring Your Own Model" (BYOM) philosophy: GeoStratum provides the advanced optimization methodology (the "how"), while researchers provide their own weights and architectures (the "what").

Arbitrary Specifications & Template Nature

The technical parameters used throughout this repository—such as the 256x256 or 1024x1024 resolutions, specific axis orderings (NHWC/NCHW), and normalization constants—are arbitrary defaults tailored specifically for the GeoStratum Lithotheque engine.

Mandatory Adaptation

Users are expected to adapt the provided scripts to their specific use cases. To successfully utilize this pipeline with your own models, you must:

• Modify Dimensions: Update the input shapes in the scripts/*.py files to match your source model's requirements.
• Adjust Normalization: Fine-tune the normalization logic in prepare_calibration.py to align with your training domain.
• Verify Architecture Compatibility: Ensure your model's operator set is compatible with pure NPU execution (e.g. replacing non-standard Erf/Gelu kernels with polynomial or x * sigmoid(1.702 * x) subgraphs to strictly eliminate SELECT_TF_OPS / Flex delegates and achieve 100% NPU graph residency).
• Domain-Specific Calibration: Run the calibration routines on a dataset representing your specific field of study (~100 images) to ensure accurate INT8 min-max calculation.

Source Model Architectures

Researchers can obtain the baseline FP32 architectures from the following official repositories to begin their own quantization journey:

• MobileNetV4-S & L (timm): timm/mobilenetv4
• MobileNetV5 (Gemma 3 Vision): google/gemma-3-nano | timm/mobilenetv5

13. Technical Reproduction Scripts

For researchers, developers, and deployment engineers, the scripts/ directory contains the complete automation pipeline utilized to build, quantize, compile, validate, and package the Lithotheque edge intelligence ecosystem.

Every script is fully parameterized, self-contained, and follows strict hardware alignment rules (zero FP32 leak, signed per-tensor quantization, fused SAME padding, and 16 KB memory page size alignment).

A. Data Preparation & Calibration

• prepare_calibration.py: Generates normalized, bit-accurate [-128, 127] INT8 .npy calibration tensors from raw field photography datasets, required for KL-divergence and MinMax post-training quantization.

B. LiteRT / TFLite Quantization (Zero-Fallback NPU Engine)

All TFLite generation scripts mathematically enforce signed per-tensor classification heads and kernel-fused SAME padding to ensure 100% NPU offload across Samsung Eden and MediaTek NeuroPilot:

• MobileNetV5 Rocks (104 Classes):
  • tflite_v5_rocks_int8.py: Generates best_mobilenetv5_rocks_int8.tflite (Standard Tier — W8A8 Full Integer).
  • tflite_v5_rocks_int4.py: Generates best_mobilenetv5_rocks_w4a8.tflite (Premium Tier — W4A8 Sub-Byte Quantization).
• MobileNetV4-Large Rocks (104 Classes):
  • tflite_v4l_rocks_int8.py: Generates rock_model_w8a8_MobileNetV4.tflite (Legacy Tier — W8A8 Full Integer).
  • tflite_v4l_rocks_int4.py: Generates rock_model_w4a8_MobileNetV4.tflite (Balanced Tier — W4A8 Sub-Byte Quantization).
• MobileNetV4-Small Scale Detection (Metrology):
  • tflite_v4s_scale_int8.py: Generates v4_small_scale_int8.tflite (Binary Centimeter Scale Classifier — INT8).
  • tflite_v4s_scale_int4.py: Generates v4_small_scale_int4.tflite (Binary Centimeter Scale Classifier — W4A8).

C. ONNX Multi-Precision Export & Graph Stripping

Generates pure QOperator ONNX artifacts, stripping floating-point dequantization artifacts to prevent NPU graph partitioning:

• MobileNetV5 Rocks: onnx_v5_rocks_int8.py | onnx_v5_rocks_int4.py
• MobileNetV4-Large Rocks: onnx_v4l_rocks_int8.py | onnx_v4l_rocks_int4.py
• MobileNetV4-Small Scale: onnx_v4s_scale_int8.py | onnx_v4s_scale_int4.py

D. Qualcomm Snapdragon Ahead-Of-Time (AOT) Pipeline (QAIRT / QNN)

Offline Ahead-Of-Time compilation suite converting quantized ONNX models into native Hexagon context binaries (.bin) statically mapped to Hexagon Tightly Coupled Memory (TCM):

• compile_qairt_aot.py: Core compilation engine interfacing with Qualcomm QAIRT SDK (snpe-onnx-to-dlc, snpe-dlc-quant, snpe-dlc-graph-prepare). Supports selective HTP targeting across all 7 generations (v69, v73, v75, v79, v81, v85, v89).
• build_all_qairt_models.py: End-to-end batch orchestrator automating AOT conversion, DLC quantization, and context binary generation for MobileNetV5, MobileNetV4, and Scale Metrology models.

E. Google Tensor, MediaTek NeuroPilot & Intel OpenVINO AOT Metadata Pipelines (LiteRT)

Ahead-Of-Time hardware descriptor packaging across Google Tensor, MediaTek Dimensity, and Intel Core Ultra silicon:

• compile_tensor_aot.py: Automates EdgeTPU FlatBuffer metadata injection across all 6 Google Tensor generations (Tensor G1 through G6, Pixel 6 through 11). Strictly enforces signed per-tensor INT8 quantization.
• compile_mediatek_aot.py: Automates NeuroPilot APU hardware descriptor injection for MediaTek Dimensity SoCs (MT6983, MT6985 in pure INT8; MT6897, MT6989, MT6991 in native W4A8).
• compile_intel_aot.py: Automates Intel OpenVINO NPU metadata injection for Intel Core Ultra processors (MTL in pure INT8; LNL and PTL in native W4A8).

F. Multi-Scale Edge Inference Engine

• litho_reference_engine.py: Ground-truth reference implementation of the 21-Pass Multi-Scale Tiling (21-MST) pipeline, including dynamic tile coordinate generation, border padding, overlap merging, and top-3 consensus voting.

G. Hardware Benchmarking & Validation

• benchmark_snapdragon_native_binaries.py: Benchmarks execution speed, memory throughput, and inference latency of native QAIRT .bin context binaries directly on Qualcomm Hexagon NPU hardware.
• benchmark_scale_machine_1.py: Automated precision and inference validator for geological scale detection models.
• benchmark_npu_onnx.py: Full evaluation harness on Snapdragon Hexagon NPU using ONNX Runtime with QNN Execution Provider (latency distributions, throughput FPS, Top-1 and Top-3 accuracy metrics).
• benchmark_npu_qairt.py: Low-level context binary benchmark harness utilizing the Qualcomm QAIRT SDK (qnn-net-run) on target hardware.

H. Scientific Visualization & Publication Graphics (R & Python)

• generate_scientific_graphs.py: Generates publication-ready confusion matrices, Top-1/Top-3 ROC curves, and class-by-class accuracy distribution plots.
• generate_benchmark_plots_v5.R: R ggplot2 visualization suite comparing MobileNetV5 across GPU, CPU NEON, LiteRT NPU, and QAIRT backends.
• generate_snapdragon_native_plots.R: Generates comparative bar charts and radar plots of Qualcomm Hexagon native AOT execution metrics.
• generate_snapdragon_plots_v4.R: Snapdragon profiling visualizer for MobileNetV4 INT8 and W4A8 architectures.
• generate_workstation_plots_scale.R: Metrology latency and precision profiling plots.
• generate_workstation_plots_v4.R: Workstation comparative profiling plots for MobileNetV4.

---

Master Index of Reproduction Scripts

Script Name	Primary Task	Target Architecture / Model	Output Artifact	Execution Environment
compile_qairt_aot.py	AOT NPU Compilation	Qualcomm HTP v69 to v89	.bin Context Binaries	QAIRT SDK 2.51+
build_all_qairt_models.py	Batch AOT Orchestration	MobileNetV4 / V5 / Scale	Full .bin Suite	QAIRT SDK 2.51+
compile_tensor_aot.py	AOT TPU Metadata Compilation	Google Tensor G1 to G6	FlatBuffer TPU Artifacts	Python 3.10+ / LiteRT
compile_mediatek_aot.py	AOT APU Metadata Compilation	MediaTek MT6983 to MT6991	FlatBuffer APU Artifacts	Python 3.10+ / LiteRT
compile_intel_aot.py	AOT NPU Metadata Compilation	Intel Core Ultra MTL, LNL, PTL	FlatBuffer NPU Artifacts	Python 3.10+ / LiteRT
tflite_v5_rocks_int8.py	LiteRT Quantization	MobileNetV5-300M (INT8)	.tflite (Zero-Fallback)	TensorFlow 2.18+ / LiteRT
tflite_v5_rocks_int4.py	LiteRT Quantization	MobileNetV5-300M (W4A8)	.tflite (Sub-Byte NPU)	TensorFlow 2.18+ / LiteRT
tflite_v4l_rocks_int8.py	LiteRT Quantization	MobileNetV4-Large (INT8)	.tflite (Zero-Fallback)	TensorFlow 2.18+ / LiteRT
tflite_v4l_rocks_int4.py	LiteRT Quantization	MobileNetV4-Large (W4A8)	.tflite (Sub-Byte NPU)	TensorFlow 2.18+ / LiteRT
tflite_v4s_scale_int8.py	LiteRT Quantization	Scale MobileNetV4-Small (INT8)	.tflite (Zero-Fallback)	TensorFlow 2.18+ / LiteRT
tflite_v4s_scale_int4.py	LiteRT Quantization	Scale MobileNetV4-Small (W4A8)	.tflite (Sub-Byte NPU)	TensorFlow 2.18+ / LiteRT
onnx_v5_rocks_int8.py	ONNX QOperator Export	MobileNetV5-300M (INT8)	.onnx (Zero-FP32)	ONNX Runtime / Python
onnx_v5_rocks_int4.py	ONNX QOperator Export	MobileNetV5-300M (W4A8)	.onnx (Zero-FP32)	ONNX Runtime / Python
prepare_calibration.py	Dataset Sampling	Raw Geological Photography	.npy Calibration Arrays	NumPy / Pillow
litho_reference_engine.py	Edge Inference Reference	21-Pass MST Engine	Multi-Tile Classification	NumPy / LiteRT
benchmark_snapdragon_native_binaries.py	Hardware Benchmarking	Qualcomm Hexagon NPU	Hardware Latency Logs	QAIRT / ARM64 Windows
generate_benchmark_plots_v5.R	Scientific Visualization	MobileNetV5 Multi-Backend	Publication PDF / PNG	R 4.4+ (ggplot2, patchwork)
generate_snapdragon_native_plots.R	Scientific Visualization	Qualcomm HTP Benchmarks	Publication Figures	R 4.4+ (ggplot2)

14. License

This repository utilizes a dual-licensing structure to balance scientific openness with the protection of commercial intellectual property:

• Documentation & Metadata: All architectural documentation, methodology descriptions (METHODOLOGY.md), model cards (MODEL_CARD.md), and metadata remain the exclusive intellectual property of GeoStratum and are licensed under Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC-BY-NC-ND 4.0).
• Reproduction Scripts: The technical automation scripts located in the scripts/ directory are provided under the MIT License, allowing for permissive redistribution and modification for research and development purposes.

Refer to the LICENSE file for the full text of the CC-BY-NC-ND license.

15. Contact

For technical inquiries, enterprise deployment information, or academic collaboration opportunities, please reach out to GeoStratum.

Email: communication@geostratum.eu

Website: www.geostratum.eu

16. Citation

If you reference our Multi-Scale Tiling methodology, Edge architecture, or Snapdragon benchmarks in your academic research, please cite this repository:

@misc{lithotheque_edge_2026,
  author = {GeoStratum},
  title = {Lithotheque Edge AI Architecture: Multi-Scale Tiling and NPU Benchmarks},
  year = {2026},
  publisher = {GitHub},
  journal = {GitHub repository},
  howpublished = {\url{https://github.com/GeoStratum/lithotheque-edge-models}}
}