Neural AArch64 — verified datapath unit weights
These are the verified neural slice units that the Neural AArch64 (ARMv8-A) CPU composes its datapath from. Each unit is a small MLP trained and verified exhaustively (N/N) against a golden reference over its entire finite input domain, so the composed CPU is bit-identical to a conventional reference.
The AArch64 integer datapath reuses the architecture-neutral byte-slice units (shared with the i386, rv32ima and ARMv7 cores — the slices don't know which ISA they serve) plus two AArch64-specific units:
| unit | role |
|---|---|
ADC8 / SBB8 |
8-bit add/sub-with-carry slices (rippled for 32/64-bit X-regs, NZCV) |
AND8 / OR8 / XOR8 |
logic slices (AND/ORR/EOR/ANDS) |
NOT8 |
bitwise NOT slice |
SHL1 / SHR1 |
1-bit shift slices (LSL/LSR/ASR/ROR composed from these) |
MASK8 |
partial-product slice for MUL/MADD/UMULH/SMULH and UDIV/SDIV trees |
CONDEXEC |
cond(4) × NZCV(4) → execute(1); drives B.cond / CSEL / CCMP (shared with ARMv7) |
DECODE_BITMASK |
the AArch64 logical-immediate decoder: N:immr:imms (13 bits) → 64-bit bitmask, verified exact on all 8192 inputs |
FLAGS8, PREFIX, MODRM, SIB are included because the shared loader builds
the full slice set; they are x86-decode units and are not used by the AArch64
composition.
Load with build_arm64_units() from the project's arm64_units.py (place these
files in the loader's models/ cache dir). Companion Space:
NeuralVerified/neural-aarch64.
Now hosted by NeuralVerified.
This repo was moved into the NeuralVerified organization to help organize my profile. Originally published at
Quazim0t0/neural-aarch64-units.