neural-ddr — verified DDR5 memory-logic units

Repositories: GitHub · 🤗 HuggingFace

Small neural nets that emulate DDR5 memory logic, each verified bit-identical to a golden reference over its entire finite input domain (N/N) — the same methodology as neural-aarch64-units.

A dev tool: present DDR5 behaviour (bus encoding, addressing, command decode, write-CRC, on-die ECC) on a machine that only has DDR3/DDR4. The bytes live in the host's real RAM; the neural nets emulate the logic.

Honest by design: no capacity or speed is invented. This models the data-path logic; it does not turn DDR3 silicon into DDR5.

Units

unit	role	verification
DBI	data-bus-inversion encode/decode (DDR4/5)	256/256 · 512/512
ADDR_MAP	address → bank-group/bank/row/column	4096/4096
CMD_DECODE	control lines → DDR command	32/32
WR_CRC	write-CRC bit-slice (rippled)	512/512
ODECC	DDR5 on-die ECC — corrects a single-bit flip	256/256 · 3328/3328
DDR5Bridge	composes the units over real host RAM	2048/2048 faults corrected

Use

pip install torch
python step1_train_verify.py      # DBI + memory bridge
python step2to6_train_verify.py   # DDR5 units + ECC-correcting bridge

Weights: DBI.pt, DDR5_units.pt.

Create your own verified unit (template: neural_ddr/dbi.py): write the exact golden finite function → enumerate the domain (decompose big/linear ones into bit/byte slices, see crc.py/ecc.py) → common.train → common.verify must be bit-exact on 100% of inputs → compose (ddr5_bridge.py).

Citation

@misc{byrne2026neuralddr,
  title  = {neural-ddr: Verified DDR5 Memory Logic Units},
  author = {Byrne, Dean (Quazim0t0)},
  year   = {2026},
  howpublished = {\url{https://huggingface.co/Quazim0t0/neural-ddr}}
}

Dean Byrne (Quazim0t0) · 2026