ShuffleNetV2 x0.5 (ONNX) – Renesas X5H
Introduction
This repository hosts ShuffleNetV2 x0.5, targeting the Renesas R-Car X5H platform for image-classification inference on the NPX6 NPU.
- Model Architecture: ShuffleNetV2 (0.5x width multiplier) — an efficient CNN using pointwise group convolutions and channel shuffle operations to reduce computation cost while preserving accuracy, targeted at very low compute budgets
- Source Model: torchvision/shufflenet_v2_x0_5
- Task: image-classification (dataset: imagenet-1k)
Deployment Flow
The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.
shufflenet_v2_x0_5.onnx (FP32)
│
└─▶ MWMX Runtime ──▶ INT8 auto-cast ──▶ NPX6 NPU
Provided Artifacts
| Artifact | Status | Notes |
|---|---|---|
| FP32 (ONNX) | ⏳ Pending | fp32/shufflenet_v2_x0_5.onnx — to be added; will be auto-cast to INT8 by the MWMX toolchain at compile time (see Deployment Flow above); no separate INT8 file will be shipped |
Performance
Measured on Renesas R-Car X5H via the MWMX runtime (APM80 ship-performance CI pipeline).
Benchmark configuration: Single NPU · Batch size: 1 · Input: 3 × 224 × 224
| AI Cores | Runtime | Precision | Device | Latency (ms) | Type |
|---|---|---|---|---|---|
| 1 | MWMX Runtime | INT8 (auto) | X5H · 1× NPU · 1 Core · 850 MHz | 1.06 | Measured |
| 3 | MWMX Runtime | INT8 (auto) | X5H · 1× NPU · 3 Core · 850 MHz | 1.09 | Measured |
| 4 | MWMX Runtime | INT8 (auto) | X5H · 1× NPU · 4 Core · 850 MHz | 1.11 | Measured |
| 6 | MWMX Runtime | INT8 (auto) | X5H · 1× NPU · 6 Core · 850 MHz | 1.27 | Measured |
| 12 | MWMX Runtime | INT8 (auto) | X5H · 1× NPU · 12 Core · 850 MHz | 1.44 | Measured |
Accuracy
TBD — not yet measured/published for this repo.
ONNX Runtime – Renesas EP v2.1.0 (MWMX 2.2 ENG4)
Measured on R-Car X5H with ONNX Runtime + Renesas Execution Provider (INT8 auto-cast); nodes the NPU cannot run fall back to the CPU EP. Batch size 1, 1 NPU. Source: ORT Renesas EP test report, status 2026-09-30. This section supersedes earlier ORT figures in this card.
| Component | AI Cores | Latency (ms) | Throughput (fps) | NPU Inference (ms) | NPU % | CPU + Overhead % | Portable pkg NPU-only (ms) |
|---|---|---|---|---|---|---|---|
| Full model | 1 | 1.732 | 577.4 | 1.063 | 61.4 % | 38.6 % | 1.05263 |
| Full model | 12 | 2.634 | 379.7 | 1.44 | 54.7 % | 45.3 % | 1.43149 |
12-core latency is not always lower than 1-core: small models are dominated by CPU-side overhead.
Graph partitioning (NPU vs CPU nodes)
| Component | Total Nodes | NPU Nodes | CPU Nodes (Q/DQ inserted) | NPU % | CPU % |
|---|---|---|---|---|---|
| Full model | 156 | 155 | 1 (1) | 99.4 % | 0.6 % |
Runtime Details
MWMX Runtime
- Engine: Renesas MWMX (Middleware MX) native inference runtime
- Input format: FP32 ONNX (compiled by the MWMX toolchain)
- NPU execution precision: INT8 (auto-cast by MWMX toolchain)
- Execution target: NPX6-48K NPU on R-Car X5H
Prerequisites
To run inference on Renesas R-Car X5H, you need:
- Renesas R-Car X5H board with NPX6 NPU
- Renesas MWMX Runtime
- Hugging Face CLI to download the model
Download
hf download Renesas/ShuffleNetV2-x0.5-ONNX --repo-type=model --include "fp32/*"
Benchmark Methodology
- HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX
runtime (
metawaremx_runtimeCI pipeline, "APM80" ship-performance target) - Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)