| # H100 Hardware Substrate & GCP A3 Deployment |
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| ## Executive Summary |
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| The BSH extends from x86_64 bare-metal to **NVIDIA H100 (GH100 SM 90) GPU compute**, eliminating all container runtimes and CUDA driver abstractions. Interaction occurs directly through Linux kernel device interfaces (`/dev/nvidia0`, `/dev/nvidia-uvm`). |
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| --- |
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| ## 1. Elimination Stack |
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| ``` |
| [PyTorch / TRT-LLM / vLLM] βββΊ ELIMINATED |
| [Docker / containerd / NVIDIA Container Toolkit] βββΊ ELIMINATED |
| [CUDA Runtime (libcudart.so) / Driver API (libcuda.so)] βββΊ ELIMINATED |
| [PTX JIT Compiler / NVVM / NVCC Engine] βββΊ ELIMINATED |
| βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ |
| SUBSTRATE BOUNDARY: GH100 / SM 90 |
| ββ Kernel Device Interface: /dev/nvidiactl, /dev/nvidia0..7, /dev/nvidia-uvm |
| ββ Direct Hardware Engines: TMA (Tensor Memory Accelerator) & WGMMA |
| ββ Native ISA Execution: SASS Machine Code & NVLink 4 Fabric |
| ``` |
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| --- |
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| ## 2. GCP A3 H100 Hardware |
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| **Physical Configuration**: |
| - 8Γ NVIDIA H100 SXM5 GPUs |
| - 80 GB HBM3 per GPU @ 3.35 TB/s |
| - 18 NVLink 4 ports per GPU @ 900 GB/s bidirectional |
| - NVSwitch Fabric (all-to-all topology) |
| - PCIe Gen5 to host root complex |
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| --- |
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| ## 3. Kernel Driver ioctl Boundary |
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| Instead of CUDA Driver API calls, interaction via raw ioctl syscalls to NVIDIA kernel drivers. |
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| **Device Nodes**: |
| ``` |
| /dev/nvidiactl # System-wide control plane |
| /dev/nvidia0..7 # Per-GPU BAR0/BAR1 MMIO mappings |
| /dev/nvidia-uvm # Unified Virtual Memory engine |
| ``` |
| |
| **Core ioctl Commands**: |
| ``` |
| NV_ESC_CARD_INFO 0x200 # Query GPU specs |
| NV_UVM_INITIALIZE 0x30000001 # Initialize UVM driver |
| NV_UVM_ALLOC_MEMORY 0x30000002 # Allocate HBM3 pages |
| NV_UVM_MAP_REMOTE 0x30000003 # Zero-copy peer mapping |
| NV_UVM_SUBMIT_WORK 0x30000004 # Submit compute work |
| ``` |
| |
| **C Interface** (No CUDA Wrapper): |
| ```c |
| int fd_gpu = open("/dev/nvidia0", O_RDWR | O_SYNC); |
| int fd_uvm = open("/dev/nvidia-uvm", O_RDWR | O_SYNC); |
| |
| void* hbm_arena = mmap(NULL, 1GB, PROT_READ | PROT_WRITE, |
| MAP_SHARED, fd_uvm, 0); |
| ``` |
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| --- |
|
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| ## 4. Hardware Instruction Lowering: TMA + WGMMA |
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| ### TMA (Tensor Memory Accelerator) |
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| **Purpose**: Transfer 2D/3D tensor tiles from HBM3 β Shared Memory asynchronously. |
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| **PTX Assembly**: |
| ```asm |
| cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes |
| [smem_tile], |
| [%rd1, {%r1, %r2}], ; Descriptor & coordinates |
| [%smem_mbar]; ; Completion mbarrier |
| ``` |
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| **Advantage**: Single instruction, zero software loop overhead. Hardware handles all coordination. |
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| ### WGMMA (Warp-Group Matrix Multiply-Accumulate) |
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| **Purpose**: Perform 128-thread asynchronous matrix multiply using Tensor Cores. |
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| **PTX Assembly**: |
| ```asm |
| wgmma.mma_async.sync.aligned.m64n64k32.f32.e4m3.e4m3 |
| {%f0, %f1, %f2, %f3, %f4, %f5, %f6, %f7, |
| %f8, %f9, %f10, %f11, %f12, %f13, %f14, %f15}, |
| %descA, %descB, |
| 1, 1; |
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| wgmma.commit_group.sync.aligned; |
| wgmma.wait_group.sync.aligned 0; |
| ``` |
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| **Execution Model**: |
| - Thread 0 issues wgmma.mma_async (1 instruction) |
| - Hardware broadcasts to 128 threads (4 warps) |
| - ~500 cycles latency @ 2.5 GHz = 200 ns |
| - No spin-lock, no software synchronization |
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| --- |
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| ## 5. NVLink 4 Peer-to-Peer Interconnect |
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| **Topology**: |
| ``` |
| GPU 0 βββββ NVLink 4 (900 GB/s) βββββΊ GPU 1 |
| β β |
| ββββββββββββ NVSwitch Fabric βββββββββ |
| β (All-to-All Connectivity) β |
| ... |
| ``` |
| |
| **Zero-Copy BAR1 Mapping**: |
| ```c |
| /* Map GPU 1's physical HBM3 into GPU 0's pointer space */ |
| void* peer_hbm = mmap(NULL, 1GB, PROT_READ | PROT_WRITE, |
| MAP_SHARED, gpu1_fd, BAR1_OFFSET); |
| |
| /* Direct memory operations work across NVLink */ |
| float val = ((float*)peer_hbm)[i]; /* Loads over NVLink 4 */ |
| ``` |
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| Latency: ~200 ns (vs ~15 ΞΌs for PCIe Gen5) |
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| --- |
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| ## 6. Bare-Metal H100 Initialization Harness |
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| ```c |
| #include <fcntl.h> |
| #include <sys/mman.h> |
| #include <unistd.h> |
| |
| int main(void) { |
| int gpu_fd = open("/dev/nvidia0", O_RDWR | O_SYNC); |
| int uvm_fd = open("/dev/nvidia-uvm", O_RDWR | O_SYNC); |
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| if (gpu_fd < 0 || uvm_fd < 0) return 1; |
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| void* hbm_arena = mmap(NULL, 1024*1024*1024, |
| PROT_READ | PROT_WRITE, |
| MAP_SHARED, uvm_fd, 0); |
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| write(1, "β SUBSTRATE_H100_INITIALIZED\n", 30); |
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| munmap(hbm_arena, 1024*1024*1024); |
| close(gpu_fd); |
| close(uvm_fd); |
| return 0; |
| } |
| ``` |
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| --- |
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| ## 7. Dependency Minimization Report |
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| | Layer | Initial | Terminal | Reduction | |
| |-------|---------|----------|-----------| |
| | Container | Docker/OCI | Bare Kernel | **100% Removed** | |
| | GPU Driver | libcuda.so | /dev/nvidia* | **100% Removed** | |
| | Memory Transfer | mma.sync (software) | TMA+WGMMA (hardware) | **Hardware Native** | |
| | Inter-GPU Network | TCP/IP/NCCL | NVLink 4 BAR1 | **Zero-Copy P2P** | |
| | Precision | FP16 | FP8 | **2Γ Density** | |
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| --- |
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| ## 8. Multi-GPU Scaling (8 GPUs) |
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| ``` |
| Global Memory: 640 GB HBM3 (8 Γ 80 GB) |
| Aggregate Compute: ~11 PFLOPS FP8 |
| Aggregate NVLink: 16.2 TB/s (all GPU-GPU channels) |
| Latency: <1 ms inference (transformer, seq_len=512) |
| ``` |
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| --- |
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| **Last Updated**: 2026-09-27 |
| **Version**: 1.0 |
| **Target Hardware**: GCP A3 (8x H100 SXM5) |
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