Improve model card: Add metadata, links, description, and citation

This PR significantly enhances the model card for `TabCanNotTab/SALV-Qwen2.5-Coder-7B-Instruct` by:

- Adding essential metadata: `pipeline_tag: text-generation`, `library_name: transformers` (as evidenced by the provided usage snippet and `config.json`), and `license: apache-2.0`.
- Including descriptive tags like `code-generation` and `verilog` for better searchability.
- Providing a clear introductory description based on the paper's abstract and GitHub README.
- Adding explicit links to the paper ([QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation](https://huggingface.co/papers/2510.19296)), the project page (https://zy1xxx.github.io/SALV), the GitHub repository (https://github.com/zy1xxx/SALV), and the associated dataset.
- Retaining the existing and validated sample usage code snippet.
- Adding the BibTeX citation for proper attribution.

These changes will make the model more informative, discoverable, and user-friendly for the Hugging Face community.

README.md

@@ -1,4 +1,29 @@
-## Example
+---
+pipeline_tag: text-generation
+library_name: transformers
+license: apache-2.0
+tags:
+- code-generation
+- verilog
+---
+
+# QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
+
+This repository contains the `SALV-Qwen2.5-Coder-7B-Instruct` model, an advanced model for Verilog code generation presented in the paper [QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation](https://huggingface.co/papers/2510.19296).
+
+QiMeng-SALV introduces a novel framework for Verilog code generation that shifts reinforcement learning optimization from module-level to signal-level rewards. By leveraging Abstract Syntax Tree (AST) analysis and signal-aware verification, it extracts functionally correct code segments from partially incorrect modules, enabling more effective RL training. This method addresses the issue of insufficient functional rewards and achieves state-of-the-art performance on VerilogEval and RTLLM.
+
+## Resources
+
+*   **Paper**: [https://huggingface.co/papers/2510.19296](https://huggingface.co/papers/2510.19296)
+*   **Project Page**: [https://zy1xxx.github.io/SALV](https://zy1xxx.github.io/SALV)
+*   **Code**: [https://github.com/zy1xxx/SALV](https://github.com/zy1xxx/SALV)
+*   **Dataset**: [https://huggingface.co/datasets/TabCanNotTab/SALV-dataset](https://huggingface.co/datasets/TabCanNotTab/SALV-dataset)
+
+## Usage
+
+You can use this model with the `transformers` library:
+
 ```python
 from transformers import AutoModelForCausalLM, AutoTokenizer
 import torch
@@ -63,4 +88,20 @@ if matches:
     print(code)
 else:
     print("No Verilog code found in the response!")
+```
+
+## Citation
+
+If you find QiMeng-SALV useful, please cite our paper:
+
+```bibtex
+@misc{zhang2025qimengsalvsignalawarelearningverilog,
+  title={QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation}, 
+  author={Yang Zhang and Rui Zhang and Jiaming Guo and Lei Huang and Di Huang and Yunpu Zhao and Shuyao Cheng and Pengwei Jin and Chongxiao Li and Zidong Du and Xing Hu and Qi Guo and Yunji Chen},
+  year={2025},
+  eprint={2510.19296},
+  archivePrefix={arXiv},
+  primaryClass={cs.LG},
+  url={https://arxiv.org/abs/2510.19296}, 
+}
 ```