Add pipeline tag, code-translation tag, project page link and improve description

#1
by nielsr HF Staff - opened
Files changed (1) hide show
  1. README.md +8 -5
README.md CHANGED
@@ -1,19 +1,22 @@
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  ---
 
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  library_name: transformers
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  license: apache-2.0
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- base_model: Qwen/Qwen2.5-Coder-1.5B-Instruct
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  tags:
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  - llama-factory
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  - full
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  - generated_from_trainer
 
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  model-index:
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  - name: ex33_armv8
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  results: []
 
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  ---
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  Check out more datails here:
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  - Paper: https://arxiv.org/abs/2506.14606
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  - Code: https://github.com/ahmedheakl/Guaranteed-Guess
 
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  # ex33_armv8
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@@ -21,15 +24,15 @@ This model is a fine-tuned version of [Qwen/Qwen2.5-Coder-1.5B-Instruct](https:/
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  ## Model description
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- More information needed
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  ## Intended uses & limitations
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- More information needed
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  ## Training and evaluation data
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- More information needed
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  ## Training procedure
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@@ -59,4 +62,4 @@ The following hyperparameters were used during training:
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  - Transformers 4.50.0
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  - Pytorch 2.6.0+cu124
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  - Datasets 3.4.1
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- - Tokenizers 0.21.0
 
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  ---
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+ base_model: Qwen/Qwen2.5-Coder-1.5B-Instruct
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  library_name: transformers
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  license: apache-2.0
 
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  tags:
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  - llama-factory
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  - full
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  - generated_from_trainer
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+ - code-translation
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  model-index:
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  - name: ex33_armv8
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  results: []
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+ pipeline_tag: translation
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  ---
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  Check out more datails here:
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  - Paper: https://arxiv.org/abs/2506.14606
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  - Code: https://github.com/ahmedheakl/Guaranteed-Guess
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+ - Project page: https://ahmedheakl.github.io/Guaranteed-Guess/
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  # ex33_armv8
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  ## Model description
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+ This model is part of the Guaranteed Guess (GG) pipeline, which tackles the challenging problem of CISC-to-RISC transpilation. GG combines the power of pre-trained large language models (LLMs) with software testing to generate and validate code translations between instruction set architectures (ISAs). This model is fine-tuned to translate from x86 (CISC) to ARMv8 (RISC).
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  ## Intended uses & limitations
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+ This model is intended for researchers and developers interested in ISA transpilation, particularly CISC-to-RISC translation. It can be used to translate x86 assembly code to ARMv8 assembly code. However, the model's performance may vary depending on the complexity and optimization level of the input code.
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  ## Training and evaluation data
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+ The model was trained and evaluated on the anghabench_armv8_O2_p1, the anghabench_armv8_O2_p2 and the stack_armv8_O2 datasets. These datasets include code snippets and programs designed to test the model's ability to translate between x86 and ARMv8 architectures.
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  ## Training procedure
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  - Transformers 4.50.0
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  - Pytorch 2.6.0+cu124
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  - Datasets 3.4.1
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+ - Tokenizers 0.21.0