README.md

---
base_model: Qwen/Qwen3.5-9B
license: apache-2.0
pipeline_tag: text-generation
tags:
- rtl
- verilog
- multi-agent
- code-generation
---

# ChipMATE-P-9B

- **Website:** https://chipmate.picasso-lab.com
- **GitHub:** https://github.com/zhongkaiyu/ChipMATE
- **Paper:** [ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation](https://huggingface.co/papers/2605.12857)

This is the **Python reference-model generation agent** of **ChipMATE**, released as the final checkpoint after the multi-agent reinforcement-learning stage described in the paper.

ChipMATE is a self-trained multi-agent framework for RTL generation that pairs a Verilog agent with a Python reference-model agent. The two agents cross-verify each other's outputs to produce high-quality RTL code **without relying on any golden testbench** -- matching the way correctness is established in real industrial chip-design flows.

## Model details

- **Track:** Python reference-model generation
- **Backbone:** Qwen3.5-9B
- **Training stage:** Stage 2 (multi-agent RL) -- final checkpoint
- **Companion agent:** [core12345/ChipMATE-V-9B](https://huggingface.co/core12345/ChipMATE-V-9B)

## Usage

To use this model as part of the ChipMATE framework, you can serve it using [vLLM](https://github.com/vllm-project/vllm) as an OpenAI-compatible endpoint:

```bash
# Serve the Python reference-model agent
vllm serve core12345/ChipMATE-P-9B --port 8002
```

Then, you can interface with it using the `chipmate` library:

```python
from chipmate import make_backend, run_problem

# Note: This agent is designed to work in tandem with a Verilog agent
p_backend = make_backend(model="core12345/ChipMATE-P-9B",
                         base_url="http://localhost:8002/v1", api_key="dummy")

v_backend = make_backend(model="core12345/ChipMATE-V-9B",
                         base_url="http://localhost:8001/v1", api_key="dummy")

result = run_problem(
    task_id="my_problem",
    question="Implement a Verilog module that ...",
    ref_sv="module top_module(input clk, ...);
endmodule
",
    v_backend=v_backend,
    p_backend=p_backend,
)
print(result.verilog)             # final Verilog implementation
```

## The ChipMATE model series

| | Verilog agent | Python ref-model agent |
|---|---|---|
| 4B | [core12345/ChipMATE-V-4B](https://huggingface.co/core12345/ChipMATE-V-4B) | [core12345/ChipMATE-P-4B](https://huggingface.co/core12345/ChipMATE-P-4B) |
| 9B | [core12345/ChipMATE-V-9B](https://huggingface.co/core12345/ChipMATE-V-9B) | [core12345/ChipMATE-P-9B](https://huggingface.co/core12345/ChipMATE-P-9B) |

## Citation

```bibtex
@article{yu2025chipmate,
  title={ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation},
  author={Yu, Zhongkai and Lin, Yichen and others},
  journal={arXiv preprint arXiv:2605.12857},
  year={2025}
}
```