cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_R12C12F12X62_465steps Text Generation • Updated Jan 4 • 3
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_200steps-native8gpu_ep2 Text Generation • Updated Jan 3 • 3
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_traineval_native8gpu_ep4 Text Generation • Updated Jan 3 • 3
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_R12C12F12X62_865steps_merged 8B • Updated Dec 31, 2025 • 2
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_traineval_native8gpu_ep2 Text Generation • Updated Dec 27, 2025 • 3
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_R12C12F12X62_865steps Text Generation • Updated Dec 22, 2025 • 3
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_R12C12F12X62_400steps Text Generation • Updated Dec 20, 2025 • 3
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_200steps-native8gpu Text Generation • Updated Dec 12, 2025 • 4
cvis-tmu/qwen2_5vl-7b-lora-sft-SQA3Devery24_1000steps-1gpu Text Generation • Updated Dec 12, 2025 • 4