repo_name stringlengths 6 79 | path stringlengths 6 236 | copies int64 1 472 | size int64 137 1.04M | content stringlengths 137 1.04M | license stringclasses 15
values | hash stringlengths 32 32 | alpha_frac float64 0.25 0.96 | ratio float64 1.51 17.5 | autogenerated bool 1
class | config_or_test bool 2
classes | has_no_keywords bool 1
class | has_few_assignments bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
malkadi/FGPU | RTL/floating_point/fadd_fsub.vhd | 1 | 10,878 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-3.0 | 7ec009ef245c034a20100e54443ff73c | 0.63348 | 3.231729 | false | false | false | false |
preusser/q27 | src/vhdl/queens/expand_blocking.vhdl | 1 | 3,953 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 9434a74a3feb897e0162ed5e5f98ea5c | 0.555527 | 3.134814 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fsqrt_uitofp_max.vhd | 1 | 23,658 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | e1bda023edb0999061fc00a0a8ffbe7d | 0.56818 | 3.721567 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_wb_controller.vhd | 1 | 10,257 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | df4b226c34c50bceba6de3762129dacc | 0.303695 | 5.421247 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_decoder.vhd | 2 | 24,873 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | b88805ba380927fd850c88de23296379 | 0.943593 | 1.869026 | false | false | false | false |
joalcava/sparcv8-monocicle | control_unit.vhd | 1 | 12,657 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control_unit is
Port (
op : in STD_LOGIC_VECTOR (1 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
cond: in STD_LOGIC_VECTOR (3 downto 0);
Aluop: out... | gpl-3.0 | f4536f822ec50b8eadf707bf992ac871 | 0.547523 | 3.460087 | false | false | false | false |
chrreisinger/OpenVC | document/Masterarbeit/src/astTransformation2To.vhd | 1 | 152 | case expression is
when choiceList1 => target := expr1;
when choiceList2 => target := expr2;
...
when choiceListN => target := exprN;
end case;
| gpl-3.0 | 8fe3cbeb3b6149de8030514f5269c77b | 0.664474 | 3.534884 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/adder_2_to_1/adder_2_to_1.srcs/sources_1/dyplo_user_logic_adder_2_to_1.vhd | 1 | 4,369 | -- File: dyplo_user_logic_adder_2_to_1.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual p... | gpl-2.0 | c928851de6da0b24291434f98a6e8d74 | 0.612474 | 3.686391 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | d62f3309561709e3f7ab9f0e089e1052 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_2AXI_2CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 1ebb6504a9727d5ed52dcfdeb3b66410 | 0.567707 | 3.729005 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip_wb_if.vhd | 1 | 11,200 | -------------------------------------------------------------------------------
--! @file nanofip_wb_if.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2013-10-24
--! @brief NanoFIP Wishbone bus interface.
----------------------------------------... | mit | 38faa933baeb8ff9a4fd6d58477da5b7 | 0.455714 | 3.682999 | false | false | false | false |
malkadi/FGPU | RTL/floating_point/fslt.vhd | 1 | 10,483 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-3.0 | d36c93ea028ffd7a627de4728c6a6ce0 | 0.628064 | 3.228519 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_dualram_512x8_clka_rd_clkb_wr.vhd | 1 | 8,330 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 5d2fb7d10873c84b587dd4891eb0f7d1 | 0.307923 | 6.452363 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/vc707_queens_uart.vhdl | 1 | 4,883 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 74d86dd246ac751df86bfc31394b746f | 0.518329 | 4.032205 | false | false | false | false |
preusser/q27 | src/vhdl/top/altera/de4_queens_uart.vhdl | 1 | 7,770 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 1a25e0be42f283be32c13901c1a5beba | 0.550193 | 3.808824 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2CACHE_W.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | eddcf87c5bf2c73c01f99df57f32bf8a | 0.567707 | 3.729005 | false | false | false | false |
dtysky/LD3320_AXI | hdl/LD3320_AXI_v1_0_S00_AXI.vhd | 1 | 22,043 | ----¼Ä´æÆ÷0£ºÖ¸Áî----
----¼Ä´æÆ÷1£º·µ»ØÖµ=ʶ±ðÍê³É·ñ+ʶ±ð½á¹û----
----¼Ä´æÆ÷2£º³õʼ»¯RAMдÈëÓÃ----
----¼Ä´æÆ÷3£º·µ»ØRAMдÈë״̬----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity LD3320_AXI_v1_0_S00_AXI is
generic (
-- ... | mit | 5baddb4fad8637eff41f8b3f27dc11d3 | 0.560132 | 3.547313 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_Atomic_4AXI.vhd | 1 | 23,372 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | f09b2cd98ff16f70d7da5c6ea5507656 | 0.568971 | 3.706899 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_8_2_1_2.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 3627509d0bd967cc382ce61ce5639691 | 0.567707 | 3.729005 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_input_block.vhd | 2 | 45,404 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | efae6c5ba1d408afe64c700def490413 | 0.94941 | 1.844042 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/FSM.vhd | 1 | 1,499 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
use IEEE.NUMERIC_STD.ALL;
entity FSM is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
b_done : in STD_LOGIC_VECTOR (7 downto 0);
stop : in std_logic;
doneVGA : in std_logic;
start : out STD_LOGIC;
start... | gpl-3.0 | bb10861bfc299df2885b59921e14337d | 0.662442 | 2.980119 | false | false | false | false |
viccuad/fpga-thingies | pong/pong.vhd | 1 | 20,826 | -- Hecho para ser visto con tab size = 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pong is
port (
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
segs: OUT std_logic_vector (6 dow... | gpl-3.0 | 65ac3377d7517cc461ead1ff558ae001 | 0.586286 | 3.240896 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/field_bus_serial.vhd | 1 | 6,801 | -------------------------------------------------------------------------------
--! @file field_bus_serial.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-12-01
--! @brief Field-bus serial interface.
-----------------------------------------------... | mit | 25d6aefb74cdc3119877fec30f2ae061 | 0.449493 | 3.587025 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 071a7c9dbdbc46c2d5bc5c59e6ca1aa2 | 0.567707 | 3.729005 | false | false | false | false |
jcowgill/cs-dacs-robot | Common/DataChangeDetectorTest.vhd | 1 | 1,530 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DataChangeDetectorTest IS
END DataChangeDetectorTest;
ARCHITECTURE behavioral OF DataChangeDetectorTest IS
COMPONENT DataChangeDetector
PORT ( SEND : OUT STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_... | apache-2.0 | f2a9183925634b6d3417ff887a0db875 | 0.538562 | 3.787129 | false | false | false | false |
joalcava/sparcv8-monocicle | psr_modifier.vhd | 1 | 1,430 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity psr_modifier is
Port( crs1 : in std_logic;
ope2 : in std_logic;
alur : in STD_LOGIC_VECTOR(31 downto 0);
aluop : in std_logic_vector(5 downto 0);
nzvc : out std_logic_vector(3 downto 0)
);
end psr_modifier;
architecture psr_modArq of psr_modifier is... | gpl-3.0 | 3a1659abfc29cdaf00a9990e686157a7 | 0.598601 | 2.609489 | false | false | false | false |
preusser/q27 | src/vhdl/queens/queens_chain.vhdl | 1 | 7,997 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 587d9d5d1f65995b7591cf5223ad1a75 | 0.552457 | 3.066334 | false | false | false | false |
malkadi/FGPU | RTL/init_alu_en_ram.vhd | 1 | 5,188 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... | gpl-3.0 | 5b6bf8082eae014d7030b1ec5d8c2e18 | 0.495952 | 3.084423 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/io/io_FrequencyCounter.vhdl | 2 | 3,850 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
... | agpl-3.0 | 222fd6b56733a25893e70a366ba89194 | 0.604416 | 3.588071 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 69957a8946f24f03a2334b7e3b6d6f85 | 0.567707 | 3.729005 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/var1_rx.vhd | 1 | 4,233 | -------------------------------------------------------------------------------
--! @file var1_rx.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2013-10-24
--! @brief NanoFIP VAR1 receiver controlling JTAG TRST.
---------------------------------... | mit | 15120a2c3fb8739d088a5d8820e57f19 | 0.395228 | 4.53212 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_rx_deserializer.vhd | 1 | 34,328 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 8216b7090d027233d8bf4cbca5160f19 | 0.377564 | 4.730329 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/cf_pkg.vhd | 1 | 1,130 | -------------------------------------------------------------------------------
--! @file cf_pkg.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-12-01
--! @brief Critical FPGA package.
--------------------------------------------------------------... | mit | e2c687cc7cb9ca3ed8c6527d8a242884 | 0.485841 | 4.556452 | false | false | false | false |
malkadi/FGPU | RTL/floating_point/frsqrt.vhd | 1 | 10,206 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-3.0 | eed0d7f3cb76b34f4030165f109774e4 | 0.626004 | 3.250318 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_6Stations.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 19fef7ee9174447d8e0fb391a2fa1f93 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_6Stations_2AXI_2TAGM.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 664ebfccb750a5865747d71dcb1a88c8 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fdiv.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 1737168fdbac8c54c3bb02ebeb4d0f5f | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_4CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 87792657787444a3f3840f3fc0bdcae7 | 0.567707 | 3.729005 | false | false | false | false |
joalcava/sparcv8-monocicle | windows_manager.vhd | 1 | 3,034 | library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.ALL;
entity windows_manager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR(4 downto 0);
rs2 : in STD_LOGIC_VECTOR(4 downto 0);
rd : in STD... | gpl-3.0 | 1d109da7e771cd1c74ef7aded0e46bd4 | 0.605471 | 2.908917 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM_4_CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | bad7f64df357891e2bb7369fc279b515 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_2CUs_min_area.vhd | 2 | 23,421 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 89a3edc16566820da70b6dbefdd22b1b | 0.569105 | 3.711139 | false | false | false | false |
malkadi/FGPU | RTL/DSP48E1.vhd | 1 | 1,615 | --
-- File: macc.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DSP48E1 is
generic (
SIZE_A : natural := 16;
SIZE_B : natural := 16;
SUB : boolean := false
); port (
clk, ce : in std_logic;
ain ... | gpl-3.0 | 7c6414c06caec29df218e44e173f8814 | 0.512693 | 3.473118 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/ml506_queens_uart.vhdl | 1 | 4,404 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | e6a3107b64f95506028b97b98abef1b6 | 0.50931 | 4.12746 | false | false | false | false |
joalcava/sparcv8-monocicle | Test_sum32b.vhd | 1 | 1,147 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Test_sum32b IS
END Test_sum32b;
ARCHITECTURE behavior OF Test_sum32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sum32b
PORT(
Op1 : IN std_logic_vector(31 downto 0);
Op2 : IN std_logic_vector(31 downto 0)... | gpl-3.0 | 96c475bf1bf6fc7a9cc38afb91f12c48 | 0.583261 | 3.562112 | false | true | false | false |
mohamed/fsl_perf_counter | hw/perf_counter_v1_00_a/hdl/vhdl/perf_counter_tb.vhd | 1 | 3,433 | -- Testbench of Performance Counter for MicroBlaze
-- Author: Mohamed A. Bamakhrama <m.a.m.bamakhrama@liacs.leidenuniv.nl>
-- Copyrights (c) 2010 by Universiteit Leiden
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity perf_counter_tb is
end perf_counter_tb;
architecture sim of perf_count... | bsd-3-clause | 992361d659a098af85146ff17dffc90e | 0.566851 | 3.04614 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_jtag_controller.vhd | 1 | 26,343 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | c0cd9f7557ef7195936935ee3744b6ef | 0.36932 | 4.68987 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_status_bytes_gen.vhd | 1 | 26,557 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | a93081e438468f7ec9c016cc0ec1a463 | 0.327898 | 4.646081 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_package.vhd | 1 | 53,662 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 3015df9275956f90d4317b852b3f5e3f | 0.376784 | 4.612119 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_prod_permit.vhd | 1 | 8,163 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 171746912d0fb0d524111465b6567e6b | 0.290579 | 6.535629 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_engine_control.vhd | 1 | 51,040 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | d0ec95f83ffee22c24cfb67416b999de | 0.373707 | 4.170957 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fdiv.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 7a4f5154b026da226ca924c0f85e7de6 | 0.567707 | 3.729005 | false | false | false | false |
quicky2000/falling_edge_detector | falling_edge_detector.vhd | 1 | 1,733 | --
-- This file is part of falling edge_detector
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... | gpl-3.0 | f0c4f726f80e41c2ba38b11a28b15c12 | 0.673399 | 3.911964 | false | false | false | false |
malkadi/FGPU | RTL/FGPU_simulation_pkg.vhd | 1 | 2,168 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}... | gpl-3.0 | f1c4c40dcb820380b0d4d95ff948d883 | 0.491697 | 3.992634 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_3Stations.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 2ca95b4b9c2a074064c361ef75e70df1 | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/queens/queens_slice_tb.vhdl | 1 | 23,501 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | b87f193b6e3c5876baad3786c88c6814 | 0.380069 | 2.674824 | false | false | false | false |
malkadi/FGPU | RTL/float_units.vhd | 1 | 10,052 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
library xil_defaultlib; -- necessray for synthesis
use xil_defaultlib.all;
---------... | gpl-3.0 | 897cb4864d6f300100decf3678f7d014 | 0.511142 | 3.54693 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nf_top.vhd | 1 | 15,669 | -------------------------------------------------------------------------------
--! @file nf_top.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-02-24
--! @brief FGClite NanoFIP FPGA (NF) top-level.
------------------------------------------------... | mit | 81f709a3fb00f9d56e08896b4aefd883 | 0.504308 | 2.97099 | false | false | false | false |
malkadi/FGPU | RTL/mult_add_sub.vhd | 1 | 7,036 | -- libraries -------------------------------------------------------------------------------------------{{{
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
---------------------------------------------------------------------------------------------------------}}}
... | gpl-3.0 | 7d757a5183373bd89492cd6e7efca813 | 0.453951 | 3.258916 | false | false | false | false |
touilleMan/scrips | datamemory.vhd | 1 | 3,243 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:55:03 05/08/2012
-- Design Name:
-- Module Name: datamemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Re... | mit | 0290dfa38af998bbe2b77bb02f8dc1ed | 0.608079 | 3.784131 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/adder/adder.srcs/sources_1/dyplo_hdl_node.vhd | 1 | 10,285 | -- File: dyplo_hdl_node.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
-... | gpl-2.0 | f466adbcdb668a13aaddd317f728267e | 0.581834 | 3.751551 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node_package.vhd | 3 | 9,725 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
uS9Fi... | gpl-2.0 | 73c64094aecb93c1c16848601dc6609a | 0.943753 | 1.875603 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd | 2 | 20,893 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | a810a305547b2ebfa5a27be0aea8fe96 | 0.94132 | 1.871127 | false | false | false | false |
jpidancet/mips | rtl/cpu_writeback.vhd | 1 | 863 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_writeback is
port (regwrite : in std_logic;
memtoreg : in std_logic;
aluout : in std_logic_vector(31 downto 0);
readdata : in std_logic_ve... | isc | 84a2a20dc38c401e9ab83b4e714d6106 | 0.597914 | 3.67234 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_6_1_1_2.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 348451ba02621d1014ec3196af6da8d5 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_float_2AXI.vhd | 1 | 23,540 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 0c49a9ff012230fb962e2df07288356b | 0.568734 | 3.717038 | false | false | false | false |
dtysky/LD3320_AXI | hdl/VOICE.vhd | 1 | 16,919 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity VOICE is
port
(
start:in std_logic;
inclk,inclk_n:in std_logic;
init_clk:in std_logic;
init_wea:in std_logic_vector(0 downto 0);
init_addr:in std_logic_vector(5 downto 0);
init_din:in std_... | mit | d3bcf5c2c46b5ab7d8ba1c18f6c97b46 | 0.493824 | 2.778617 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/Iterator.vhd | 1 | 1,948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Iterator is
Port ( go : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
x0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y0 : in STD_LOGIC_VECTOR (XY_RANGE-1 ... | gpl-3.0 | f6dbf84b8358e743e43da55c709d132e | 0.656057 | 2.847953 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_2AXI_4CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | c01b7c53c7496067714b23f3485464b9 | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/ml605_queens_uart.vhdl | 1 | 4,783 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 736151bbfc6c3a3f06792d82f8d3da59 | 0.513694 | 4.056828 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_getinit_pkg.vhd | 2 | 62,911 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 6b7006e5d5f836d44bca915626292252 | 0.951551 | 1.8373 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 722173d7425ae4f9aa5feb488840fe2f | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | RTL/cache.vhd | 1 | 12,075 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... | gpl-3.0 | 4c3b59826f32957602ea4bddb206957c | 0.504679 | 3.157688 | false | false | false | false |
joalcava/sparcv8-monocicle | Test_signExtUnit.vhd | 1 | 2,189 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:42 10/06/2016
-- Design Name:
-- Module Name: C:/Users/utp.CRIE/Desktop/sparcv8-monocicle/Test_signExtUnit.vhd
-- Project Name: monocicle-sparcv8
-- Target Device:
-- Tool versio... | gpl-3.0 | 92c7beacd814348e5830de8493ad9e3c | 0.612152 | 4.130189 | false | true | false | false |
dtysky/LD3320_AXI | hdl/LD3320_AXI_v1_0.vhd | 1 | 4,445 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LD3320_AXI_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI... | mit | a66e3021052302a7621f1ffb1bda129a | 0.648369 | 2.405303 | false | false | false | false |
jpidancet/mips | rtl/cpu_memory.vhd | 1 | 1,370 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_memory is
port (regwrite : in std_logic;
memtoreg : in std_logic;
memread : in std_logic;
memwrite : in std_logic;
aluout ... | isc | d3e92e4ea227a35042063aa5c672ad43 | 0.552555 | 3.614776 | false | false | false | false |
dtysky/LD3320_AXI | src/LIST/LIST_funcsim.vhdl | 1 | 47,409 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
-- Date : Wed Sep 10 03:38:08 2014
-- Host : Dtysky running 64-bit major release ... | mit | 2481037c204c30d64a14aa84ada41625 | 0.660086 | 3.120656 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/mux2.vhd | 1 | 1,563 |
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
entity muxandcpt is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
i_iters1 : in STD_LOGIC_VECTOR (ITER_RANGE-1... | gpl-3.0 | e0e8b7b6af42f4e9a464d48ce12af5bd | 0.590531 | 2.878453 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/adder_2_to_1/adder_2_to_1.srcs/sources_1/dyplo_hdl_node.vhd | 1 | 10,306 | -- File: dyplo_hdl_node.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
-... | gpl-2.0 | 9aad261290fd4054fafd32f840bf4158 | 0.581813 | 3.734686 | false | false | false | false |
chrreisinger/OpenVC | document/Masterarbeit/src/reg4Behv.vhd | 1 | 412 | architecture behav of reg4 is
begin
storage : process is
variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
begin
wait until clk;
if en then
stored_d0 := d0;
stored_d1 := d1;
stored_d2 := d2;
stored_d3 := d3;
end if;
q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns;
q2 <= store... | gpl-3.0 | 9d951e2b04e9bb3170364e7c604d60f2 | 0.650485 | 2.559006 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/fetch_page/fetch_page_sram_dim.vhd | 1 | 5,225 | -------------------------------------------------------------------------------
--! @file fetch_page_sram_dim.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare SRAM page with DIM data for NanoFIP communication.
-------------... | mit | d10177d3b84bc6382355dcb61b91ebd1 | 0.426603 | 4.009977 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_fsm.vhd | 2 | 83,900 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 2db592b151e8cd320525a14dce293868 | 0.952336 | 1.833279 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | cf6e15861d2694ab5e267c7e610e36f6 | 0.567707 | 3.729005 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_reset_unit.vhd | 1 | 39,205 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 370e3a728439d660437ac0ddef78786e | 0.33687 | 4.789859 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_no_fmul_area_estimation.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 4245c0a220d4c64585eb8f2763fe9a05 | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/uart/uart_rx.vhdl | 3 | 3,702 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
--
-- Authors: Thomas B. Preusser
--
-- Module: uart_rx
--
-- Desc... | agpl-3.0 | 8369197e6429d95455debd1b5906d5fd | 0.540249 | 3.512334 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/ocram/ocram_sdp.vhdl | 2 | 5,084 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patri... | agpl-3.0 | fd8273abd0867a73f88a63b679ca772b | 0.626082 | 3.652299 | false | false | false | false |
malkadi/FGPU | RTL/CU.vhd | 1 | 10,854 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
-----------------------------------------------------------------------------... | gpl-3.0 | 00f751a1729b535b0495eef1d83bb5be | 0.467662 | 3.577456 | false | false | false | false |
preusser/q27 | src/vhdl/queens/unframe.vhdl | 1 | 6,302 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | d020645bb3c55768c3a13e38fc4554ba | 0.494446 | 2.71404 | false | false | false | false |
malkadi/FGPU | RTL/floating_point/fdiv.vhd | 1 | 10,489 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-3.0 | 816237af6c7861b56478a5c51dfe4dbd | 0.628277 | 3.230366 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | d310987e1cb3d25c46786cc0c8f4944e | 0.567707 | 3.729005 | false | false | false | false |
jpidancet/mips | tests/rom.vhd | 1 | 1,395 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity rom is
generic (FILENAME : string;
DATA_WIDTH : integer;
ADDR_WIDTH : integer);
port (addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data : out std_logic_vec... | isc | 61238ab1e67d0c302dba19688e49da1c | 0.549104 | 3.632813 | false | false | false | false |
malkadi/FGPU | RTL/global_mem.vhd | 1 | 71,074 | -- libraries -------------------------------------------------------------------------------------------{{{
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
use ieee.numeric_std.ALL;
use ieee.math_real.all;
use ieee.math_complex.all;
library work;
use work.all;
use work.FGPU_definitions.all;
use work.... | gpl-3.0 | 19dca3e367c2a6f003171ca0e3ed8a9b | 0.500943 | 3.425748 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf_top.vhd | 1 | 14,885 | -------------------------------------------------------------------------------
--! @file cf_top.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-05-06
--! @brief FGClite Critical FPGA (CF) top-level.
-----------------------------------------------... | mit | 3df2efea406024b113a7867e3160bfb0 | 0.494189 | 2.930695 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_6Stations_8Banks.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | d98562cbe414ad065cbebe0db2beaf9a | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/sync/sync_Bits_Xilinx.vhdl | 2 | 4,417 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Xilinx
--
-- D... | agpl-3.0 | d99da8cec4ee3305cbb33c31e35dc377 | 0.623727 | 3.379495 | false | false | false | false |
malkadi/FGPU | RTL/loc_indcs_generator.vhd | 1 | 15,098 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
-----------------------------------------------------------------------------... | gpl-3.0 | 8113c1ff1d15bd41fd6ab4a7d9e9302b | 0.421778 | 3.0196 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/nf/nf_rx_registers.vhd | 1 | 4,375 | -------------------------------------------------------------------------------
--! @file nf_rx_registers.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-22
--! @brief NanoFIP receiver registers.
------------------------------------------------... | mit | bf43a068b3d08043f2170aa0c7bcddee | 0.469486 | 3.661088 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fdiv_LMEM.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 172caeda3b92f7eb5789cd5488591d84 | 0.567707 | 3.729005 | false | false | false | false |
joalcava/sparcv8-monocicle | MuxDWR.vhd | 1 | 607 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxDWR is
Port ( DM : in STD_LOGIC_VECTOR(31 downto 0);
AluR : in STD_LOGIC_VECTOR(31 downto 0);
PC: in STD_LOGIC_VECTOR(31 downto 0);
RFSource: in STD_LOGIC_VECTOR(1 downto 0);
DTRF : out STD_LOGIC_VECTOR(31 downto 0)
);
en... | gpl-3.0 | 798c623d54a3a949bbf7152cf933a7f9 | 0.629325 | 2.918269 | false | false | false | false |
viccuad/fpga-thingies | cronometer/cronometer.vhd | 1 | 9,479 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cronometer is
port (
startStop: IN std_logic;
puesta0: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
ampliacion: IN std_logic;
rightSegs: OUT std_logic_vector(6 downto 0);
left... | gpl-3.0 | cd70edf660f8f415ce2c6f8902234561 | 0.590885 | 3.099738 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.