repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
values |
|---|---|---|---|---|---|
dh1dm/q27 | src/vhdl/PoC/arith/arith_counter_free.vhdl | 2 | 2946 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: Poc.arith_counter_free
--
-- Authors: Thomas B. Preusser... | agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/queens_slice.vhdl | 1 | 8378 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/unframe.vhdl | 1 | 6282 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
UnofficialRepos/OSVVM | ResolutionPkg.vhd | 1 | 16067 | --
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
-- resolved resolution functions f... | artistic-2.0 |
hterkelsen/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: ... | mpl-2.0 |
hterkelsen/mal | vhdl/stepA_mal.vhdl | 11 | 17057 | entity stepA_mal is
end entity stepA_mal;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of stepA_mal is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in ... | mpl-2.0 |
foresterre/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: ... | mpl-2.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/tg_status.vhd | 20 | 5700 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... | cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/example_design/rtl/memc1_wrapper.vhd | 2 | 47712 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... | cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/wr_data_gen.vhd | 20 | 18946 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... | cc0-1.0 |
qu1x/fsio | src/lib/fsio_put.vhd | 1 | 1412 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 Novem... | agpl-3.0 |
chastell/art-decomp | kiss/opus_nov.vhd | 1 | 3496 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_nov;
architecture behaviour of opus_nov is
constant init0: std_logic_vector(3 downto 0) :=... | agpl-3.0 |
chastell/art-decomp | kiss/ex6_rnd.vhd | 1 | 4231 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_rnd;
architecture behaviour of ex6_rnd is
constant s1: std_logic_vector(2 downto 0) := "101"... | agpl-3.0 |
chastell/art-decomp | kiss/dk16_jed.vhd | 1 | 12212 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_jed;
architecture behaviour of dk16_jed is
constant state_1: std_logic_vector(4 downto 0) ... | agpl-3.0 |
chastell/art-decomp | kiss/dk512_hot.vhd | 1 | 4742 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_hot;
architecture behaviour of dk512_hot is
constant state_1: std_logic_vector(14 downto... | agpl-3.0 |
chastell/art-decomp | kiss/sse_jed.vhd | 1 | 6957 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_jed;
architecture behaviour of sse_jed is
constant st11: std_logic_vector(3 downto 0) := "00... | agpl-3.0 |
chastell/art-decomp | kiss/dk27_nov.vhd | 1 | 2406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_nov;
architecture behaviour of dk27_nov is
constant START: std_logic_vector(2 downto 0) :=... | agpl-3.0 |
chastell/art-decomp | kiss/s27_jed.vhd | 1 | 3869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_jed;
architecture behaviour of s27_jed is
constant s000: std_logic_vector(2 downto 0) := "11... | agpl-3.0 |
chastell/art-decomp | kiss/lion_jed.vhd | 1 | 1832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_jed;
architecture behaviour of lion_jed is
constant st0: std_logic_vector(1 downto 0) := "... | agpl-3.0 |
chastell/art-decomp | kiss/shiftreg_nov.vhd | 1 | 2558 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_nov;
architecture behaviour of shiftreg_nov is
constant st0: std_logic_vector(2 do... | agpl-3.0 |
chastell/art-decomp | kiss/dk14_jed.vhd | 1 | 6084 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_jed;
architecture behaviour of dk14_jed is
constant state_1: std_logic_vector(2 downto 0) ... | agpl-3.0 |
chastell/art-decomp | kiss/train4_jed.vhd | 1 | 2066 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_jed;
architecture behaviour of train4_jed is
constant st0: std_logic_vector(1 downto 0... | agpl-3.0 |
chastell/art-decomp | kiss/bbara_rnd.vhd | 1 | 6275 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_rnd;
architecture behaviour of bbara_rnd is
constant st0: std_logic_vector(3 downto 0) :... | agpl-3.0 |
chastell/art-decomp | kiss/s1_nov.vhd | 1 | 11803 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_nov;
architecture behaviour of s1_nov is
constant st0: std_logic_vector(4 downto 0) := "10110"... | agpl-3.0 |
chastell/art-decomp | kiss/ex3_rnd.vhd | 1 | 4215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_rnd;
architecture behaviour of ex3_rnd is
constant s1: std_logic_vector(3 downto 0) := "1101... | agpl-3.0 |
chastell/art-decomp | kiss/styr_rnd.vhd | 1 | 18712 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_rnd;
architecture behaviour of styr_rnd is
constant st0: std_logic_vector(4 downto 0) := "... | agpl-3.0 |
chastell/art-decomp | kiss/s510_jed.vhd | 1 | 13167 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_jed is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_jed;
architecture behaviour of s510_jed is
constant s000000: std_logic_vector(5 downto 0)... | agpl-3.0 |
chastell/art-decomp | kiss/tbk_nov.vhd | 1 | 133046 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tbk_nov is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(2 downto 0)
);
end tbk_nov;
architecture behaviour of tbk_nov is
constant st0: std_logic_vector(4 downto 0) := "000... | agpl-3.0 |
chastell/art-decomp | kiss/keyb_nov.vhd | 1 | 16319 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_nov;
architecture behaviour of keyb_nov is
constant st0: std_logic_vector(4 downto 0) := "... | agpl-3.0 |
chastell/art-decomp | kiss/ex2_hot.vhd | 1 | 8089 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_hot;
architecture behaviour of ex2_hot is
constant s1: std_logic_vector(18 downto 0) := "100... | agpl-3.0 |
chastell/art-decomp | kiss/ex7_hot.vhd | 1 | 4287 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_hot;
architecture behaviour of ex7_hot is
constant s1: std_logic_vector(9 downto 0) := "1000... | agpl-3.0 |
chastell/art-decomp | kiss/scf_nov.vhd | 1 | 39256 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_nov is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_nov;
architecture behaviour of scf_nov is
constant state1: std_logic_vector(6 downto 0) :=... | agpl-3.0 |
chastell/art-decomp | kiss/dk27_rnd.vhd | 1 | 2406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_rnd;
architecture behaviour of dk27_rnd is
constant START: std_logic_vector(2 downto 0) :=... | agpl-3.0 |
JimLewis/OSVVM | TbUtilPkg.vhd | 1 | 37308 | --
-- File Name: TbUtilPkg.vhd
-- Design Unit Name: TbUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
--
-- Developed... | artistic-2.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/lib/mux/mux4_bit.vhd | 1 | 517 | --Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4_bit is
port(
bit3 : in std_logic;
bit2 : in std_logic;
bit1 : in std_logic;
bit0 : in std_logic;
S : in std_logic_vector(1 downto 0);
R : out std_logic
... | agpl-3.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/lib/add_sub/cl_logic.vhd | 2 | 2085 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... | agpl-3.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/alu.vhd | 1 | 1816 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity alu_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (5 downto 0);
R : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end alu_4_bit;
arc... | agpl-3.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/lib/comparator/comparator.vhd | 1 | 3008 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--NOTE: the "diff" input comes from the output of the add_sub module.
--the way the opcodes are defined, the output is always the difference
--of A and B if the user is requesting a comparison operation. Otherwise,
--the output of this module will technically be undefined/w... | agpl-3.0 |
eggcar/time-holdover-cycloneIV-board-old | TimeHoldOver_Qsys/TimeHoldOver_Qsys_inst.vhd | 1 | 13558 | component TimeHoldOver_Qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
epcs_flash_controller_dclk : out std_logic; -- dclk
epcs_flash_controller_sce : out std_lo... | agpl-3.0 |
mpwillson/mal | vhdl/printer.vhdl | 17 | 3030 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package printer is
procedure pr_str(ast: inout mal_val_ptr; readable: in boolean; result: out line);
procedure pr_seq(start_ch: in string; end_ch: in string; delim: in string; a_seq: inout mal_seq_ptr; readable: in boolean; result: out line);
end p... | mpl-2.0 |
mpwillson/mal | vhdl/pkg_readline.vhdl | 17 | 928 | library STD;
use STD.textio.all;
package pkg_readline is
procedure mal_printline(l: string);
procedure mal_readline(prompt: string; eof_detected: out boolean; l: inout line);
end package pkg_readline;
package body pkg_readline is
type charfile is file of character;
file stdout_char: charfile open write_mode i... | mpl-2.0 |
kraigher/axi_bfm | src/axi_memory.vhd | 1 | 6868 | -- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2015, Olof Kraigher olof.kraigher@gmail.com
library ieee;
use ieee.std_logic_1164.all;
use ieee.n... | mpl-2.0 |
preusser/q27 | src/vhdl/PoC/fifo/fifo_cc_got.vhdl | 2 | 12858 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Mar... | agpl-3.0 |
preusser/q27 | src/vhdl/PoC/common/my_config_KC705.vhdl | 2 | 1751 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... | agpl-3.0 |
preusser/q27 | src/vhdl/queens/queens_chain.vhdl | 1 | 7997 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
preusser/q27 | src/vhdl/PoC/uart/uart_tx.vhdl | 3 | 2785 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module:
--
-- Authors: Thomas B. Preusser
--
-- Description: UAR... | agpl-3.0 |
preusser/q27 | src/vhdl/top/xilinx/ml605_queens_uart.vhdl | 1 | 4783 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
preusser/q27 | src/vhdl/PoC/fifo/fifo.pkg.vhdl | 2 | 9509 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Ma... | agpl-3.0 |
preusser/q27 | src/vhdl/queens/msg_funnel.vhdl | 2 | 4246 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
BBN-Q/APS2-Comms | src/tcp_demux.vhd | 1 | 5203 | -- Cross from tcp clock domain
-- Demux tcp stream between AXI memory and CPLD
-- Packetize by adding tlast to stream
-- Adapt to 32bit wide data path
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tcp_bridge_... | mpl-2.0 |
sils1297/HWPrak14 | task_2/project_2/project_2.srcs/sim_1/new/LEDPWM_tb.vhd | 1 | 476 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LEDPWM_tb is
end LEDPWM_tb;
architecture Behavioral of LEDPWM_tb is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
begin
uut : entity work.Dimmer(DimmerArchitecture)
generic map (WIDTH => 25)
port map (
... | agpl-3.0 |
sils1297/HWPrak14 | task_1/task_1.srcs/sim_1/new/FlasherTestBench.vhd | 1 | 529 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FlasherTestBench is
end FlasherTestBench;
architecture Behavioral of FlasherTestBench is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
begin
uut : entity work.Flasher(FlasherArchitecture)
generic map (WIDTH => 6)
port map (
LED =... | agpl-3.0 |
BBN-Q/APS2-Comms | test/eprom_cfg_reader_tb.vhd | 1 | 6247 | -- Testbench for the eprom_cfg_reader
-- Tests:
-- * default values until done
-- * request sent
-- * response processed and addresses set
-- * done asserted
-- * AXIS pass through after done asserted
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_11... | mpl-2.0 |
sils1297/HWPrak14 | task_1/task_1.srcs/sources_1/new/Flasher.vhd | 1 | 719 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Toggles the LED state every half second
entity Flasher is
generic (
WIDTH : integer := 25
);
port (
LED : out std_ulogic_vector(3 downto 0);
CLK_66MHZ : in std_ulogic
);
end;
architecture FlasherArchitecture of Flasher is
signal cou... | agpl-3.0 |
sils1297/HWPrak14 | task_3/task_3.srcs/sources_1/new/i2c.vhd | 1 | 11526 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ... | agpl-3.0 |
BBN-Q/APS2-TDM | src/TDM_top.vhd | 1 | 20095 | -- TDM_top.vhd
--
-- This is the top level module of the ATM firmware.
-- It instantiates the main BD with the comms., 9 SATA outputs, and one SATA input.
-- Original authors: Colm Ryan and Blake Johnson
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.a... | mpl-2.0 |
BBN-Q/VHDL-Components | test/PCG_XSH_RR_tb.vhd | 1 | 2737 | -- test bench for the PCG pseudorandom number generator
--
-- Original author: Blake Johnson
-- Copyright 2017 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PCG_XSH_RR_tb is
end;
architecture bench of PCG_XSH_RR_tb is
signal clk : std_logic :... | mpl-2.0 |
nxt4hll/roccc-2.0 | roccc-compiler/src/llvm-2.3/include/rocccLibrary/BurstAddressGen.vhdl | 1 | 6930 | library IEEE ;
use IEEE.STD_LOGIC_1164.all ;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.HelperFunctions.all;
use work.HelperFunctions_Unsigned.all;
use work.HelperFunctions_Signed.all;
entity BurstAddressGen is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--input burst data
base_... | epl-1.0 |
gtarciso/INE5406 | decodificador2x4.vhd | 1 | 635 | library ieee;
use ieee.std_logic_1164.all;
entity decodificador2x4 is
port(
inpt: in std_logic_vector(1 downto 0);
enable: in std_logic;
outp: out std_logic_vector(3 downto 0)
);
end decodificador2x4;
architecture decoder of decodificador2x4 is
begin
process(inpt, enable)
beg... | cc0-1.0 |
jwalsh/mal | vhdl/types.vhdl | 17 | 13485 | library STD;
use STD.textio.all;
package types is
procedure debugline(l: inout line);
procedure debug(str: in string);
procedure debug(ch: in character);
procedure debug(i: in integer);
type mal_type_tag is (mal_nil, mal_true, mal_false, mal_number,
mal_symbol, mal_string, mal_keywo... | mpl-2.0 |
jwalsh/mal | vhdl/step5_tco.vhdl | 17 | 6767 | entity step5_tco is
end entity step5_tco;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step5_tco is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out ... | mpl-2.0 |
xdsopl/vhdl | max10_10M08E144_eval_test3.vhd | 1 | 3089 | -- test3 - post pll clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed w... | cc0-1.0 |
ahammer/MySaasa | server/src/main/webapp/ace/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
... | agpl-3.0 |
JimLewis/OSVVM | demo/AlertLog_Demo_Hierarchy.vhd | 2 | 8410 | --
-- File Name: AlertLog_Demo_Hierarchy.vhd
-- Design Unit Name: AlertLog_Demo_Hierarchy
-- Revision: STANDARD VERSION, 2015.01
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- ... | artistic-2.0 |
dh1dm/q27 | src/vhdl/top/xilinx/s3sk_queens_uart.vhdl | 1 | 5228 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
dh1dm/q27 | src/vhdl/PoC/common/my_config_KC705.vhdl | 2 | 1751 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... | agpl-3.0 |
dh1dm/q27 | src/vhdl/PoC/common/my_config_VC707.vhdl | 2 | 1750 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... | agpl-3.0 |
UnofficialRepos/OSVVM | AlertLogPkg.vhd | 1 | 300689 | --
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
-- Rob Gaddi Highland Technology. Inspired SetAlertLogPrefix /... | artistic-2.0 |
UnofficialRepos/OSVVM | VendorCovApiPkg_Aldec.vhd | 2 | 4020 | --
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capabili... | artistic-2.0 |
UnofficialRepos/OSVVM | ScoreboardPkg_slv_c.vhd | 1 | 137840 | --
-- File Name: ScoreBoardPkg_slv.vhd
-- Design Unit Name: ScoreBoardPkg_slv
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis email: jim@synthworks.com
--
--
-- Description:
-- Defines types and met... | artistic-2.0 |
hterkelsen/mal | vhdl/reader.vhdl | 10 | 10133 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package reader is
procedure read_str(s: in string; result: out mal_val_ptr; err: out mal_val_ptr);
end package reader;
package body reader is
type token_list is array(natural range <>) of line;
type token_list_ptr is access token_list;
funct... | mpl-2.0 |
cite-sa/xwcps | xwcps-parser-ui/libs/ace/ace_all/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
... | agpl-3.0 |
foresterre/mal | vhdl/reader.vhdl | 10 | 10133 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package reader is
procedure read_str(s: in string; result: out mal_val_ptr; err: out mal_val_ptr);
end package reader;
package body reader is
type token_list is array(natural range <>) of line;
type token_list_ptr is access token_list;
funct... | mpl-2.0 |
sdenel/An-N-bits-pipelined-addsub-using-VHDL | src/fullAdderWithRegisters.vhd | 1 | 2177 | library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity fullAdderWithRegisters is
-- fullAdderWithRegisters
-- Prend a, b, en entrée
-- Prend c NREGSBEFORE coups d'horloge après
-- Rend s au bout de NREGSBEFORE+NREGSAFTER+1 coups d'horloge
-- NREGSBEFORE+NREGSAFTER+1
generic (
NREGSBEFORE: n... | mit |
Zunth5/LED-CLOCK | LEDgrid/DATA_CONSTRUCT.vhd | 1 | 3617 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DATA_CONSTRUCT is
port ( CLKin : in std_logic; --system clock
UPDATEin : in std_logic; --uart update signal
UARTin : in std_logic_vector(7 downto 0); --uart data in
COL... | mit |
fkmclane/AutoPidact | vhdl/ClockGenerator.vhd | 1 | 596 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ClockGenerator is
generic(
count : natural := 50000000
);
port(
clk : in std_logic;
rst : in std_logic;
q : out std_logic
);
end entity ClockGenerator;
architecture RTL of ClockGenerator is
begin
process(clk, rst)
variable va... | mit |
Zunth5/LED-CLOCK | LEDgrid/ipcore_dir/CHAR_ROM/simulation/bmg_stim_gen.vhd | 1 | 12571 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... | mit |
FearlessJojo/COPproject | project/main.vhd | 1 | 15307 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:24:26 11/18/2016
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... | mit |
corywalker/vhdl_fft | cap_controller.vhd | 3 | 4363 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cap_controller is
generic (
N : positive := 16;
ADDRWIDTH : positive := 10;
SIZE : positive := 64;
SIZELOG : positive := 6;
INT_EXT_SEL: std_logic;
SPI_2X_CLK_DIV: positive;
DA_RESET_... | mit |
corywalker/vhdl_fft | ft_controller_tb.vhd | 3 | 3130 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:26:21 10/22/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/ft_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
-... | mit |
FearlessJojo/COPproject | project/maintester.vhd | 1 | 3919 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:53:20 11/25/2016
-- Design Name:
-- Module Name: Z:/Documents/COP/COPproject/project/maintester.vhd
-- Project Name: project
-- Target Device:
-- Tool versions:
-- Descr... | mit |
Hyvok/KittLights | kitt_lights_top.vhd | 1 | 1484 | library ieee;
library work;
use ieee.std_logic_1164.all;
entity kitt_lights_top is
generic
(
LIGHTS_N : positive := 8;
ADVANCE_VAL : positive := 5000000;
PWM_BITS_N : positive := 8;
DECAY_VAL : positive := 52000
);
... | mit |
jchromik/hpi-vhdl-2016 | pue4/Audio/audio_scancode_to_divisor.vhd | 1 | 1582 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:51:13 07/09/2016
-- Design Name:
-- Module Name: audio_scancode_to_divisor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... | mit |
mjpatter88/fundamentals | 01-logic_gates/xor/myXor2_tb.vhdl | 1 | 1029 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myXor2_tb is
end myXor2_tb;
architecture behavorial of myXor2_tb is
component myXor2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
signal s1: std_logic;
signal s2: std_logic;
signal o1: std_logic;
begin
my... | mit |
mjpatter88/fundamentals | 01-logic_gates/and/myAnd2_tb.vhdl | 1 | 1111 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd2_tb is
end myAnd2_tb;
architecture behavioral of myAnd2_tb is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal s2: std_logic;
sign... | mit |
mjpatter88/fundamentals | 01-logic_gates/not/myNot.vhdl | 1 | 389 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myNot is
port(a: in std_logic; s: out std_logic);
end myNot;
architecture behavioral of myNot is
component myNand2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
signal one: std_logic;
begin
one <= '1';
myN... | mit |
mjpatter88/fundamentals | 01-logic_gates/or/myOr16_tb.vhdl | 1 | 1361 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myOr16_tb is
end myOr16_tb;
architecture behavioral of myOr16_tb is
component myOr16
port(a: in std_logic_vector(15 downto 0); b: in std_logic_vector(15 downto 0); s: out std_logic_vector(15 downto 0));
end component;
-- signals used for testing
... | mit |
mjpatter88/fundamentals | 01-logic_gates/mux/myMux2_tb.vhdl | 1 | 1797 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myMux2_tb is
end myMux2_tb;
architecture behavioral of myMux2_tb is
component myMux2
port(a: in std_logic; b: in std_logic; sel: in std_logic; s: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal s2: ... | mit |
GSimas/EEL5105 | AULA6/reg4.vhd | 3 | 406 | library ieee;
use ieee.std_logic_1164.all;
entity D_4FF is port (
CLK, RST: in std_logic;
EN: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end D_4FF;
architecture behv of D_4FF is
begin
process(CLK, D, RST)
begin
if RST = '0' then
Q <= "0000";
elsif (CLK'event and ... | mit |
bertuccio/ARQ | Practica3/procesador.vhd | 1 | 13702 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity procesador is
port(
Clk : in std_logic;
Reset : in std_logic;
-- Instruction memory
I_Addr : out std_logic_vector(31 downto 0);
I_RdStb : out std_logic;
I_WrStb : out std_logic;
I_AddrStb : out std_... | mit |
GSimas/EEL5105 | PROJETO-EEL5105/Projeto/FSM_control.vhd | 1 | 1900 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--FSM de controle de estados do jogo
entity FSM_control is port(
CLK, RESET, END_BONUS, END_TIME, ENTER, TARGET: in std_logic;
SEL_DISP: out std_logic_vector(1 downto 0);
STATESS: out std_logic_vector(4 downto 0);
SEL_LED, SET_ROLL, EN_TIM... | mit |
UVVM/uvvm_vvc_framework | uvvm_vvc_framework/src_target_dependent/td_queue_pkg.vhd | 3 | 2199 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
UVVM/uvvm_vvc_framework | bitvis_vip_sbi/src/vvc_cmd_pkg.vhd | 3 | 6948 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
UVVM/uvvm_vvc_framework | bitvis_vip_gpio/src/vvc_cmd_pkg.vhd | 3 | 6886 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
UVVM/uvvm_vvc_framework | xConstrRandFuncCov/src/SortListPkg_int.vhd | 3 | 13743 | --
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
-- Description:
-- Sorting utility for array of scalars
-... | mit |
UVVM/uvvm_vvc_framework | bitvis_vip_clock_generator/src/clock_generator_vvc.vhd | 1 | 16223 | --========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ie... | mit |
UVVM/uvvm_vvc_framework | uvvm_vvc_framework/src/ti_vvc_framework_support_pkg.vhd | 1 | 22598 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit |
UVVM/uvvm_vvc_framework | uvvm_vvc_framework/src/ti_data_queue_pkg.vhd | 2 | 26776 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit |
UVVM/uvvm_vvc_framework | xConstrRandFuncCov/src/MessagePkg.vhd | 2 | 5845 | --
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-li... | mit |
UVVM/uvvm_vvc_framework | bitvis_irqc/src/irqc_pif_pkg.vhd | 3 | 3063 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
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