repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
values |
|---|---|---|---|---|---|
ptracton/Picoblaze | Picoblaze/UART_and_PicoTerm/uart_tx6.vhd | 1 | 15872 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... | mit |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/spwlink.vhd | 2 | 10334 | --
-- SpaceWire Exchange Level Controller.
--
-- This entity implements exchange level aspects of the SpaceWire protocol.
-- It handles connection setup, error detection and flow control.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwlink is
generic (
... | mit |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Filter_Top_Level.vhd | 1 | 8396 | ---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... | mit |
ObKo/USBCore | Extra/blk_ep_in_ctl.vhdl | 1 | 6039 | --
-- USB Full-Speed/Hi-Speed Device Controller core - blk_ep_in_ctl.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restricti... | mit |
ObKo/USBCore | Extra/extra_pkg.vhdl | 1 | 3447 | --
-- USB Full-Speed/Hi-Speed Device Controller core - extra_pkg.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, ... | mit |
timtian090/Playground | UVM/UVMExamples/mod01_sv_for_vhdlers/SystemVerilog_for_VHDL_Engineers_Primer/primer_examples/datatypes/width_depth/width_depth_rtl.vhd | 1 | 616 | --
-- VHDL Architecture width_depth.width_depth.rtl
--
-- Created:
-- by - Ray.UNKNOWN (WRITINGMACHINE)
-- at - 07:46:00 05/ 4/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.STD_LOGIC_UNSIGNED.all... | mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/input_output.vhd | 3 | 5695 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_... | mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/input_output.vhd | 3 | 5695 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_... | mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/ds1722.vhd | 3 | 3623 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DS1722 is
Port( CLK_I: in std_logic;
RST_I: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_logic_vector(7 downto 0);
... | mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/cpu_engine.vhd | 1 | 12526 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_en... | mit |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_never_unknown_rtl.vhd | 1 | 5190 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_never_unknown is
constant assert_name : string := "OVL_NEVER_UNKNOWN";
con... | mit |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_cycle_sequence_rtl.vhd | 1 | 10459 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_cycle_sequence is
constant assert_name : string := "OVL_CYCLE_SEQUENCE";
... | mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/opcode_fetch.vhd | 1 | 1454 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode... | mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/uart._baudgen.vhd | 3 | 2497 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_baudgen is
PORT( CLK_I ... | mit |
bluemurder/chaotic-rngs | rng07-vhdl/chaoticMap.vhd | 2 | 1546 | -- This block describes the chaotic map used for the random generator --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.randgen_package.all;
entity chaoticMap is
Port ( clk : in std_logic;
reset : in std_logic;
output : out std_logic);
end chaoticMap;
architecture ... | mit |
bluemurder/chaotic-rngs | rng02-vhdl/CaosAlAl.vhd | 1 | 1808 | ----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- ... | mit |
bluemurder/chaotic-rngs | rng06-vhdl/test_randgen.vhd | 2 | 1675 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
use work.randgen_package.all;
ENTITY test_randgen IS
END test_randgen;
ARCHITECTURE behavior OF test_randgen IS
-- Component Declaration for the Unit Under Test (UUT)
component randgen is
... | mit |
bluemurder/chaotic-rngs | rng08-vhdl/testCaosComb.vhd | 1 | 2587 | --------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 16:27:59 10/06/2011
-- Design Name:
-- Module Name: testCaosComb.vhd
-- Project Name: Caos
-- Target Device:
-- Tool ver... | mit |
bluemurder/chaotic-rngs | rng08-vhdl/test.vhd | 1 | 3060 | --------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 15:44:18 09/19/2011
-- Design Name:
-- Module Name: test.vhd
-- Project Name: NewCaos
-- Target Device:
-- Tool versions... | mit |
bluemurder/chaotic-rngs | rng06-vhdl/vonNeumannCorrector.vhd | 2 | 1603 | -- This block performs a Von Neumann correction --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.randgen_package.all;
entity vonNeumannCorrector is
Port ( clk : in std_logic;
reset : in std_logic;
data_in : in std_logic;
ready_in : in std_logic;
data_out : out std_logic;
... | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/a27f5e107e0af35c/ila_0_sim_netlist.vhdl | 1 | 4901485 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/f5a61c81241cd760/srio_gen2_0_stub.vhdl | 1 | 6142 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Oct 18 11:58:34 2017
-- Host : vldmr-PC running 64-bit Service ... | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/33e25e2781fab1df/srio_gen2_0_sim_netlist.vhdl | 1 | 8383546 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/678f058b09cf6220/srio_gen2_0_sim_netlist.vhdl | 1 | 8140888 | null | mit |
superboy0712/MIPS | MIPS_main_controller_sincle_cycle_redesign.vhd | 1 | 6128 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:30:31 10/19/2014
-- Design Name:
-- Module Name: MIPS_main_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dep... | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/7b44e6d6f6ec9fee/dbg_ila_stub.vhdl | 1 | 2721 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 25 13:52:36 2017
-- Host : vldmr-PC running 64-bit Service ... | mit |
superboy0712/MIPS | pipeline files/MEMWB_register.vhd | 1 | 1883 | library ieee;
use ieee.std_logic_1164.all;
entity EXMEM_register is
port(Clk, reset : in std_logic;
ALU_ressult_i, data_mem_i: in std_logic_vector(31 downto 0);
ALU_ressult_o, data_mem_o: out std_logic_vector(31 downto 0);
register_address_i: in std_logic_vec... | mit |
GOOD-Stuff/srio_test | srio_test.ip_user_files/ip/srio_gen2_0/srio_gen2_0_stub.vhdl | 1 | 6019 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:31:45 2017
-- Host : vldmr-PC running 64-bit Service ... | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/4768f0820c8fb678/fifo_generator_rx_inst_stub.vhdl | 1 | 1927 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:10:43 2017
-- Host : vldmr-PC running 64-bit Service ... | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/335f9682d9b26dcb/ila_0_sim_netlist.vhdl | 1 | 3666186 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/4768f0820c8fb678/fifo_generator_rx_inst_sim_netlist.vhdl | 1 | 309175 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:10:43 2017
-- Host : vldmr-PC running 64-bit Service Pack... | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/31a2bbcb305771f0/fifo_generator_rx_inst_sim_netlist.vhdl | 1 | 179161 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 26 17:01:25 2017
-- Host : vldmr-PC running 64-bit Service Pack... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_atanlut.vhd | 10 | 165265 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_exp2_s5.vhd | 10 | 180176 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_sgn_mul3s.vhd | 10 | 5383 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fpc_library_sv.vhd | 10 | 100780 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/dp_lnlutpow.vhd | 10 | 230947 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_div_est.vhd | 10 | 6558 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_lsftpipe36.vhd | 10 | 4409 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/dotProduct64_safe_path_sv.vhd | 10 | 410 | -- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGI... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_normfp1x.vhd | 10 | 10480 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... | mit |
richjyoung/lfsr-package | src/LFSR/lfsr_components.vhd | 1 | 490 | library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package lfsr_components is
component pulse is
generic (
G_lfsr_width : natural := 3;
G_period : natural := 7
);
port(
CLK... | mit |
pedabraham/MDSM | crs/bitsToNumbers.vhd | 1 | 948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitsToNumbers is
port(
cadenaOriginalDeBits: IN STD_LOGIC_VECTOR(8 downto 0);
numero : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end bitsToNumbers;
architecture Behavioral of bitsToNumbers is
begin
process(cadenaO... | mit |
peteg944/music-fpga | Experimental/Zedboard UART/i2c.vhd | 3 | 2393 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC... | mit |
thoralt/KCVGA | FPGA/ColorGenerator.vhd | 1 | 2392 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ColorGenerator IS PORT
(
SIGNAL pixel : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL r, g, b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ColorGenerator;
ARCHITECTURE Behavioral OF ColorGenerator IS
TYPE RGB_type IS RECORD R, G, B : STD... | mit |
migueljiarr/RV32I | src/left_XLEN_barrel_shifter.vhd | 1 | 1157 | library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity left_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end left_XLEN_barrel_shifter;
architecture structural of left_XL... | mit |
ou-cse-378/vhdl-tetris | whypcore.vhd | 1 | 7449 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: Whypcore.vhd
-- // Date: 12/9/2004
-- // Description: WHYP Core
-- // Class: CSE 378
-- ===================================================... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_mul5418s.vhd | 10 | 4973 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... | mit |
Reiuiji/ECE368-Lab | Lab 3/Keyboard/keycode_to_ascii.vhd | 1 | 6905 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
--... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_mulufp54.vhd | 10 | 5016 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_clz23.vhd | 10 | 4166 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_usgnpos_sv.vhd | 20 | 6063 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp2x.vhd | 10 | 13893 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
Reiuiji/ECE368-Lab | Lab 2/ALU/alu_tb.vhd | 10 | 7649 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_TB
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: ... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/hcc_castytof.vhd | 10 | 3181 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
rtucker/nios_codebreaker | vhdl/lfsr_peripheral.vhd | 1 | 7660 | --************************** VHDL Source Code ****************************
--*************************************************************************
-- vim: set ts=2 sw=2 tw=78 et :
--
-- DESIGNER NAME: Ryan S. Tucker <rst7983@rit.edu>
--
-- LAB NAME: Lab 7: Game System
--
-- FILE NAME: lfsr_periphera... | mit |
Reiuiji/ECE368-Lab | Lab 2/ALU/alu_toplevel.vhd | 7 | 2688 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versi... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/dp_lsftpipe64x64.vhd | 10 | 4921 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/dp_lsftpipe64x64.vhd | 10 | 4921 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_divfp2x.vhd | 10 | 22387 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... | mit |
Reiuiji/ECE368-Lab | Lab 3/VGA Part 2/clk25MHz.vhd | 11 | 2102 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_pos51.vhd | 10 | 6864 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/fp_del_var.vhd | 10 | 3103 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_invsqr_core.vhd | 10 | 8541 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fpc_library_sv.vhd | 10 | 100780 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... | mit |
ou-cse-378/vhdl-tetris | ctr2bit.vhd | 1 | 860 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: ctr2bit.vhd
-- // Date: 12/9/2004
-- // Description: Display component
-- // Class: CSE 378
-- ============================================... | mit |
danielcardoso/html-pages | example/All-Icons/file.vhdl | 12226531 | 0 | mit | |
rflamino/StellaBlue | core/A6532/src/A6532.vhd | 1 | 7554 | -- A6532 RAM-I/O-Timer (RIOT)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any... | mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/single_rate.vhd | 2 | 370178 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/cntrl_delay.vhd | 2 | 9440 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/fir_compiler_v7_1/hdl/components.vhd | 2 | 77934 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
okaxaki/vm2413 | AttackTable.vhd | 2 | 2045 | --
-- AttackTable.vhd
-- Envelope attack shaping table for VM2413
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity AttackTable is
port (
clk : in std_logic;
addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
data : o... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulsen1Altr.vhd | 8 | 3102 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_clock.vhd | 10 | 2158 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_testbench_clock.vhd | 10 | 2218 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/Instruct_Memory/simulation/checker.vhd | 69 | 5607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietar... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_capture_GNQX2JTRTZ.vhd | 20 | 1755 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic ( XFILE : string... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_pipelined_adder_GNWEIMU3MK.vhd | 8 | 1300 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic ( width : natural := 0;
pipeline : integer := 0)... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_cast_GNCCZ56SYK.vhd | 4 | 855 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNCCZ56SYK.vhd | 4 | 855 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/Data Path/Fetch/fetch_tb.vhd | 1 | 2984 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:39:38 04/22/2015
-- Design Name:
-- Module Name: U:/Desktop/ECE368-RISC16-master/368RISC/fetch_tb.vhd
-- Project Name: RISC16
-- Target Device:
-- Tool versions:
-- Description: ... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_decoder.vhd | 2 | 2462 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_dividerAltr.vhd | 4 | 4072 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_if_statement_GNJ7D74ANQ.vhd | 4 | 1401 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural :... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_MultAdd.vhd | 12 | 23128 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_constant_GNLJWFEWBD.vhd | 5 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNLJWFEWBD is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_constant_GNLJWFEWBD.vhd | 5 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNLJWFEWBD is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd | 2 | 45577 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out s... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNCPEUNC4M.vhd | 5 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCPEUNC4M is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_sImpulse1nAltr.vhd | 8 | 2837 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_constant_GNZEH3JAKA.vhd | 20 | 592 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_vcc_GN.vhd | 20 | 373 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_vcc_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilde... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_port_GNEPKLLZKY.vhd | 17 | 489 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_log... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_if_statement_GNWHMBR6GA.vhd | 4 | 1493 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNWHMBR6GA is
generic ( use_else_output : natural := 0;
bwr : natural :... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNMMXHT3UH.vhd | 4 | 852 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMMXHT3UH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd | 2 | 34606 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
data_en : in std_logic ... | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator.vhd | 2 | 2091 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_case_statement_GNWMX2GCN2.vhd | 4 | 837 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic ( number_outputs : integer := 2;
hasDefault : nat... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_counter_GNKAA2ZBZG.vhd | 4 | 1632 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNKAA2ZBZG is
generic ( use_usr_aclr : string := "false";
use_ena : string := ... | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_decoder.vhd | 2 | 1567 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
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