source stringclasses 1
value | dataset stringclasses 2
values | id stringlengths 7 9 | file stringlengths 12 40 | task_type stringclasses 2
values | content stringlengths 36 3.73k | metadata dict |
|---|---|---|---|---|---|---|
verilog_eval_v2 | dataset_spec-to-rtl | veval_0 | Prob009_popcount3_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (3 bits)
- output out (2 bits)
The module should implement a "population count" circuit that counts the
number of '1's in the input vector.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob009_popcount3_prompt.txt",
"file_size": 311
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_1 | Prob037_review2015_count1k_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (10 bits)
The module should implement a counter that counts from 0 to 999,
inclusive, with a period of 1000 cycles. Assume ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob037_review2015_count1k_prompt.txt",
"file_size": 469
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_2 | Prob064_vector3_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (5 bits)
- input b (5 bits)
- input c (5 bits)
- input d (5 bits)
- input e (5 bits)
- input f (5 bits)
- output w (8 bits)
- output x (8 bits... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob064_vector3_prompt.txt",
"file_size": 767
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_3 | Prob047_dff8ar_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops with active high asynchronous
reset. The ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob047_dff8ar_prompt.txt",
"file_size": 408
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_4 | Prob035_count1to10_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (4 bits)
The module should implement a decade counter that counts 1 through 10,
inclusive. Assume all sequential logic is t... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob035_count1to10_prompt.txt",
"file_size": 444
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_5 | problems-temp.txt | spec_to_rtl | Prob001_zero
Prob016_m2014_q4j
Prob030_popcount255
Prob033_ece241_2014_q1c
Prob036_ringer
Prob042_vector4
Prob050_kmap1
Prob060_m2014_q4k
Prob092_gatesv100
Prob098_circuit7
Prob103_circuit2
Prob107_fsm1s
Prob108_rule90
Prob112_always_case2
Prob115_shift18
Prob122_kmap4
Prob127_lemmings1
Prob128_fsm_ps2
Prob135_m2014_q6... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/problems-temp.txt",
"file_size": 341
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_6 | Prob125_kmap3_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output out
The module should implement the Karnaugh map below. d is don't-care,
which means you may choose to outp... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob125_kmap3_prompt.txt",
"file_size": 491
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_7 | Prob126_circuit6_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a ( 3 bits)
- output q (16 bits)
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the circuit does, th... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob126_circuit6_prompt.txt",
"file_size": 659
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_8 | Prob052_gates100_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (100 bits)
- output out_and
- output out_or
- output out_xor
The module should implement a combinational circuit with 100 inputs,
in[99:0]. There are... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob052_gates100_prompt.txt",
"file_size": 475
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_9 | Prob007_wire_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should behave like a wire.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob007_wire_prompt.txt",
"file_size": 221
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_10 | Prob113_2012_q1g_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x (4 bits)
- output f
The module should implement the function f shown in the Karnaugh map
below.
x[0]x[1]
x[2]x[3] 00 01 11 10
00 ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob113_2012_q1g_prompt.txt",
"file_size": 421
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_11 | Prob140_fsm_hdlc_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in
- output disc
- output flag
- output err
Synchronous HDLC framing involves decoding a continuous bit stream of
data to ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob140_fsm_hdlc_prompt.txt",
"file_size": 1302
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_12 | Prob034_dff8_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops. All DFFs should be triggered by
the positive edge of clock.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob034_dff8_prompt.txt",
"file_size": 318
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_13 | Prob145_circuit8_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clock
- input a
- output p
- output q
The module should implement a sequential circuit. Read the simulation
waveforms to determine what the circuit doe... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob145_circuit8_prompt.txt",
"file_size": 1424
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_14 | Prob131_mt2015_q4_prompt.txt | spec_to_rtl |
Module A implements the boolean function z = (x^y) & x.
Module B can be described by the following simulation waveform:
time x y z
0ns 0 0 1
5ns 0 0 1
10ns 0 0 1
15ns 0 0 1
20ns 0 0 1
25ns 1 0 0
30ns 1 0 0
35ns 0 1 0
40ns 0 1 0
45ns 1 1 1
50ns 1 1 1
55n... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob131_mt2015_q4_prompt.txt",
"file_size": 1015
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_15 | Prob033_ece241_2014_q1c_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (8 bits)
- input b (8 bits)
- output s (8 bits)
- output overflow
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0].
The modul... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob033_ece241_2014_q1c_prompt.txt",
"file_size": 422
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_16 | Prob098_circuit7_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input a
- output q
This is a sequential circuit. Read the simulation waveforms to determine
what the circuit does, then implement it.
time clk... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob098_circuit7_prompt.txt",
"file_size": 747
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_17 | Prob075_counter_2bc_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input train_valid
- input train_taken
- output state (2 bits)
The module should implement a two-bit saturating counter. The cou... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob075_counter_2bc_prompt.txt",
"file_size": 791
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_18 | Prob056_ece241_2013_q7_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input j
- input k
- output Q
The module should implement a JK flip-flop with the following truth
table. Note: Qold is the output of the flip-flo... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob056_ece241_2013_q7_prompt.txt",
"file_size": 423
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_19 | Prob151_review2015_fsm_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input data
- input done_counting
- input ack
- output shift_ena
- output counting
- output done
The module should implement ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob151_review2015_fsm_prompt.txt",
"file_size": 1476
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_20 | Prob124_rule110_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input load
- input data (512 bits)
- output q (512 bits)
The module should implement Rule 110, a one-dimensional cellular
automaton with inte... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob124_rule110_prompt.txt",
"file_size": 1355
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_21 | Prob087_gates_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out_and
- output out_or
- output out_xor
- output out_nand
- output out_nor
- output out_xnor
- output out_anotb
The module s... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob087_gates_prompt.txt",
"file_size": 613
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_22 | Prob065_7420_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input p1a
- input p1b
- input p1c
- input p1d
- input p2a
- input p2b
- input p2c
- input p2d
- output p1y
- output p2y
The 7400-series integrate... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob065_7420_prompt.txt",
"file_size": 502
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_23 | Prob084_ece241_2013_q12_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input enable
- input S
- input A
- input B
- input C
- output Z
The module should implement a circuit for an 8x1 memory, where writing to
... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob084_ece241_2013_q12_prompt.txt",
"file_size": 1106
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_24 | Prob042_vector4_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output out (32 bits)
One common place to see a replication operator is when sign-extending a
smaller number to a larger one, while preserv... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob042_vector4_prompt.txt",
"file_size": 792
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_25 | Prob103_circuit2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output q
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob103_circuit2_prompt.txt",
"file_size": 795
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_26 | Prob129_ece241_2013_q8_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input aresetn
- input x
- output z
The module should implement a Mealy-type finite state machine that
recognizes the sequence "101" on an input ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob129_ece241_2013_q8_prompt.txt",
"file_size": 691
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_27 | Prob133_2014_q3fsm_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input s
- input w
- output z
The module should implement a finite state machine with inputs s and w.
Assume that the FSM begins ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob133_2014_q3fsm_prompt.txt",
"file_size": 991
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_28 | Prob070_ece241_2013_q2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output out_sop
- output out_pos
The module should implement a digital system with four inputs (a,b,c,d)
tha... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob070_ece241_2013_q2_prompt.txt",
"file_size": 717
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_29 | Prob082_lfsr32_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (32 bits)
A linear feedback shift register is a shift register usually with a few
XOR gates to produce the next state of th... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob082_lfsr32_prompt.txt",
"file_size": 813
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_30 | Prob071_always_casez_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output pos (3 bits)
The module should implement a priority encoder for an 8-bit input. Given
an 8-bit vector, the output should report the ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob071_always_casez_prompt.txt",
"file_size": 532
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_31 | Prob135_m2014_q6b_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input y (3 bits)
- input w
- output Y1
The module should implement the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob135_m2014_q6b_prompt.txt",
"file_size": 667
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_32 | Prob001_zero_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output zero
The module should always outputs a LOW.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob001_zero_prompt.txt",
"file_size": 211
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_33 | Prob099_m2014_q6c_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input y (6 bits)
- input w
- output Y1
- output Y3
Consider the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1-->... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob099_m2014_q6c_prompt.txt",
"file_size": 972
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_34 | Prob083_mt2015_q4b_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x
- input y
- output z
The module can be described by the following simulation waveform:
time x y z
0ns 0 0 1
5ns 0 0 1
10ns 0 0 ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob083_mt2015_q4b_prompt.txt",
"file_size": 579
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_35 | Prob069_truthtable1_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x3
- input x2
- input x1
- output f
The module should implement a combinational circuit for the following
truth table:
x3 | x2 | x1 | f
0 | 0 |... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob069_truthtable1_prompt.txt",
"file_size": 462
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_36 | Prob139_2013_q2bfsm_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input resetn
- input x
- input y
- output f
- output g
Consider a finite state machine that is used to control some type of
motor. The FSM ha... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob139_2013_q2bfsm_prompt.txt",
"file_size": 1311
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_37 | Prob080_timer_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk,
- input load,
- input data (10 bits)
- output tc
The module should implement a timer that counts down for a given number
of clock cycles, then as... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob080_timer_prompt.txt",
"file_size": 1159
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_38 | Prob104_mt2015_muxdff_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input L
- input q_in
- input r_in
- output Q
Consider this Verilog module "full_module":
module full_module (
input [2:0] r,
in... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob104_mt2015_muxdff_prompt.txt",
"file_size": 932
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_39 | Prob107_fsm1s_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in
- output out
Implement the following Moore state machine with two states, one input,
and one output. The reset state is B... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob107_fsm1s_prompt.txt",
"file_size": 457
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_40 | Prob110_fsm2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input j
- input k
- output out
The module should implement a Moore state machine with two states, two
inputs, and one output ac... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob110_fsm2_prompt.txt",
"file_size": 521
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_41 | Prob155_lemmings4_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input bump_left
- input bump_right
- input ground
- input dig
- output walk_left
- output walk_right
- output aaah
- outp... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob155_lemmings4_prompt.txt",
"file_size": 2906
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_42 | Prob013_m2014_q4e_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in1
- input in2
- output out
The module should implement a 2-input NOR gate.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob013_m2014_q4e_prompt.txt",
"file_size": 246
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_43 | Prob148_2013_q2afsm_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input resetn
- input r (3 bits)
- output g (3 bits)
The module should implement the FSM described by the state diagram shown
below:
A ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob148_2013_q2afsm_prompt.txt",
"file_size": 1997
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_44 | Prob077_wire_decl_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output out
- output out_n
The module should implement the following circuit. Create two
intermediate wires (named... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob077_wire_decl_prompt.txt",
"file_size": 933
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_45 | Prob081_7458_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input p1a
- input p1b
- input p1c
- input p1d
- input p1e
- input p1f
- input p2a
- input p2b
- input p2c
- input p2d
- output p1y
- output p2... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob081_7458_prompt.txt",
"file_size": 964
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_46 | Prob120_fsm3s_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in
- output out
The module should implement a Moore state machine with the following
state transition table with one input, ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob120_fsm3s_prompt.txt",
"file_size": 739
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_47 | Prob143_fsm_onehot_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- input state (10 bits)
- output next_state (10 bits)
- output out1
- output out2
Given the follow state machine with 1 input and 2 outputs (the ou... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob143_fsm_onehot_prompt.txt",
"file_size": 1660
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_48 | Prob051_gates4_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (4 bits)
- output out_and
- output out_or
- output out_xor
The module should implement a combinational circuit with four inputs,
in[3:0]. There are 3... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob051_gates4_prompt.txt",
"file_size": 467
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_49 | Prob095_review2015_fsmshift_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output shift_ena
This module is a part of the FSM for controlling a shift register, we
want the ability to enable the shift register... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob095_review2015_fsmshift_prompt.txt",
"file_size": 600
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_50 | Prob021_mux256to1v_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (1024 bits)
- input sel ( 8 bits)
- output out ( 4 bits)
The module should implement a 4-bit wide, 256-to-1 multiplexer. The 256
4-bit inputs ar... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob021_mux256to1v_prompt.txt",
"file_size": 467
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_51 | Prob002_m2014_q4i_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output out
The module should always drive 0 (or logic low).
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob002_m2014_q4i_prompt.txt",
"file_size": 219
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_52 | Prob006_vectorr_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output out (8 bits)
The module should reverse the bit ordering of the input port and write
the result to the output port.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob006_vectorr_prompt.txt",
"file_size": 304
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_53 | Prob074_ece241_2014_q4_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input x
- output z
The module should implement a finite state machine with the following
behavior. Input x goes to three different two-input gates... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob074_ece241_2014_q4_prompt.txt",
"file_size": 911
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_54 | Prob127_lemmings1_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input bump_left
- input bump_right
- output walk_left
- output walk_right
The module should implement a simple game called Lem... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob127_lemmings1_prompt.txt",
"file_size": 1208
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_55 | Prob010_mt2015_q4a_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x
- input y
- output z
The module should implement the boolean function z = (x^y) & x.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob010_mt2015_q4a_prompt.txt",
"file_size": 256
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_56 | Prob141_count_clock_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input ena
- output pm
- output hh (8 bits)
- output mm (8 bits)
- output ss (8 bits)
Create a set of counters suitable for use ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob141_count_clock_prompt.txt",
"file_size": 964
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_57 | Prob128_fsm_ps2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in (8 bits)
- output done
The PS/2 mouse protocol sends messages that are three bytes long.
However, within a continuous byt... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob128_fsm_ps2_prompt.txt",
"file_size": 1097
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_58 | Prob112_always_case2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (4 bits)
- output pos (2 bits)
The module should implement a priority encoder. A priority encoder is a
combinational circuit that, when given an input... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob112_always_case2_prompt.txt",
"file_size": 692
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_59 | Prob043_vector5_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- input e
- output out (25 bits)
Implement a module that given five 1-bit signals (a, b, c, d, and e),
compute all... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob043_vector5_prompt.txt",
"file_size": 551
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_60 | Prob058_alwaysblock2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input a
- input b
- output out_assign
- output out_always_comb
- output out_always_ff
The module should implement an XOR gate three ways, usin... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob058_alwaysblock2_prompt.txt",
"file_size": 678
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_61 | Prob028_m2014_q4a_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input d
- input ena
- output q
The module should impement a D latch using an always block.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob028_m2014_q4a_prompt.txt",
"file_size": 254
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_62 | Prob045_edgedetect2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input in (8 bits)
- output anyedge (8 bits)
Implement a module that for each bit in an 8-bit input vector, detect
when the input signal change... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob045_edgedetect2_prompt.txt",
"file_size": 568
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_63 | Prob108_rule90_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk,
- input load,
- input data (512 bits)
- output q (512 bits)
The module should implement Rule 90, a one-dimensional cellular automaton
with int... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob108_rule90_prompt.txt",
"file_size": 1110
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_64 | Prob030_popcount255_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (255 bits)
- output out ( 8 bits)
A "population count" circuit counts the number of '1's in an input
vector. The module should implement a population... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob030_popcount255_prompt.txt",
"file_size": 364
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_65 | Prob086_lfsr5_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (5 bits)
A linear feedback shift register is a shift register usually with a few
XOR gates to produce the next state of the... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob086_lfsr5_prompt.txt",
"file_size": 1011
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_66 | Prob156_review2015_fancytimer_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input data
- output count (4 bits)
- output counting
- output done
- input ack
The module should implement a timer with one in... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob156_review2015_fancytimer_prompt.txt",
"file_size": 1925
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_67 | Prob055_conditional_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (8 bits)
- input b (8 bits)
- input c (8 bits)
- input d (8 bits)
- output min (8 bits)
The module should find the minimum of the four inp... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob055_conditional_prompt.txt",
"file_size": 409
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_68 | Prob079_fsm3onehot_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- input state (4 bits)
- output next_state (4 bits)
- output out
The module should implement the state transition table for a Moore state
machine wi... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob079_fsm3onehot_prompt.txt",
"file_size": 902
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_69 | Prob016_m2014_q4j_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x (4 bits)
- input y (4 bits)
- output sum (5 bits)
Implement a 4-bit adder with full adders. The output sum should include
the overflow bit.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob016_m2014_q4j_prompt.txt",
"file_size": 315
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_70 | Prob073_dff16e_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input resetn
- input byteena ( 2 bits)
- input d (16 bits)
- output q (16 bits)
The module should include 16 D flip-flops. It's so... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob073_dff16e_prompt.txt",
"file_size": 682
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_71 | Prob048_m2014_q4c_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d
- input r
- output q
The module should implement a simple D flip flop with active high
synchronous reset (reset output to 0).
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob048_m2014_q4c_prompt.txt",
"file_size": 311
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_72 | Prob014_andgate_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out
The module should implement a 2-input AND gate.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob014_andgate_prompt.txt",
"file_size": 242
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_73 | Prob116_m2014_q3_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x (4 bits)
- output f
The module should implement the function f shown in the Karnaugh map
below. d is don't-care, which means you may choose to output wh... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob116_m2014_q3_prompt.txt",
"file_size": 519
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_74 | Prob005_notgate_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should implement a NOT gate.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob005_notgate_prompt.txt",
"file_size": 223
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_75 | Prob144_conwaylife_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input load
- input data (256 bits)
- output q (256 bits)
The module should implemement a "game" played on a two-dimensional grid
of cells, where... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob144_conwaylife_prompt.txt",
"file_size": 1420
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_76 | Prob147_circuit10_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input a
- input b
- output q
- output state
The module should implement a sequential circuit. The circuit consists of
combinational logic and o... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob147_circuit10_prompt.txt",
"file_size": 1763
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_77 | Prob091_2012_q2b_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input y (6 bits)
- input w
- output Y1
- output Y3
Consider the following finite-state machine:
A (0) --1--> B
A (0) --0--> A
B (0) --1--> C
B (0) -... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob091_2012_q2b_prompt.txt",
"file_size": 893
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_78 | Prob024_hadd_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output sum
- output cout
The module should implement a half adder. A half adder adds two bits
(with no carry-in) and produces a sum and c... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob024_hadd_prompt.txt",
"file_size": 331
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_79 | Prob046_dff8p_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input d (8 bits)
- output q (8 bits)
Implement a module that includes 8 D flip-flops with active high
synchronous reset. The flip-... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob046_dff8p_prompt.txt",
"file_size": 425
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_80 | Prob031_dff_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d
- input q
The module should implement a single D flip-flop. Assume all sequential
logic is triggered on the positive edge of the clock.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob031_dff_prompt.txt",
"file_size": 317
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_81 | Prob044_vectorgates_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (3 bits)
- input b (3 bits)
- output out_or_bitwise (3 bits)
- output out_or_logical
- output out_not (6 bits)
Impl... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob044_vectorgates_prompt.txt",
"file_size": 593
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_82 | Prob088_ece241_2014_q5b_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input x
- output z
The module should implement the following Mealy finite-state machine
which is an implementation of the 2's com... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob088_ece241_2014_q5b_prompt.txt",
"file_size": 589
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_83 | Prob017_mux2to1v_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (100 bits)
- input b (100 bits)
- input sel
- output out (100 bits)
The module should implement a 2-1 multiplexer. When sel=0, choose a. When
se... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob017_mux2to1v_prompt.txt",
"file_size": 336
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_84 | Prob050_kmap1_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- output out
The module should implement the circuit described by the Karnaugh map
below.
a
bc 0 1
00 | 0 |... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob050_kmap1_prompt.txt",
"file_size": 374
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_85 | Prob097_mux9to1v_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (16 bits)
- input b (16 bits)
- input c (16 bits)
- input d (16 bits)
- input e (16 bits)
- input f (16 bits)
- input g (16 bits... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob097_mux9to1v_prompt.txt",
"file_size": 586
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_86 | Prob130_circuit5_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (4 bits)
- input b (4 bits)
- input c (4 bits)
- input d (4 bits)
- input e (4 bits)
- output q (4 bits)
The module should implement a combinati... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob130_circuit5_prompt.txt",
"file_size": 921
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_87 | Prob057_kmap2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output out
The module should implement the circuit described by the Karnaugh map
below.
ab
cd ... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob057_kmap2_prompt.txt",
"file_size": 432
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_88 | Prob023_vector100r_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (100 bits)
- output out (100 bits)
The module should reverse the bit ordering of the input and write to the
output.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob023_vector100r_prompt.txt",
"file_size": 287
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_89 | problems.txt | spec_to_rtl | Prob001_zero
Prob002_m2014_q4i
Prob003_step_one
Prob004_vector2
Prob005_notgate
Prob006_vectorr
Prob007_wire
Prob008_m2014_q4h
Prob009_popcount3
Prob010_mt2015_q4a
Prob011_norgate
Prob012_xnorgate
Prob013_m2014_q4e
Prob014_andgate
Prob015_vector1
Prob016_m2014_q4j
Prob017_mux2to1v
Prob018_mux256to1
Prob019_m2014_q4f
Pr... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/problems.txt",
"file_size": 2814
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_90 | Prob100_fsm3comb_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- input state (2 bits)
- output next_state (2 bits)
- output out
The module should implement the following is the state transition table
for a Moore... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob100_fsm3comb_prompt.txt",
"file_size": 918
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_91 | Prob122_kmap4_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output out
The module should implement the Karnaugh map below.
ab
cd 00 01 11 10
00 | 0 | 1... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob122_kmap4_prompt.txt",
"file_size": 401
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_92 | Prob015_vector1_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (16 bits)
- output out_hi ( 8 bits)
- output out_lo ( 8 bits)
The module should implement a combinational circuit that splits an input
half-word (... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob015_vector1_prompt.txt",
"file_size": 380
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_93 | Prob062_bugs_mux2_prompt.txt | spec_to_rtl |
Consider the following implementation of an 8-bit 2-to-1 mux:
module TopModule (
input sel,
input [7:0] a,
input [7:0] b,
output out
);
assign out = (~sel & a) | (sel & b);
endmodule
Unfortunately, this module has a bug. Implement a new version of this
module that... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob062_bugs_mux2_prompt.txt",
"file_size": 337
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_94 | Prob114_bugs_case_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input code (8 bits)
- output out (4 bits)
- output valid
The module should recognize 8-bit keyboard scancodes for keys 0 through
9. It should indicate whether... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob114_bugs_case_prompt.txt",
"file_size": 695
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_95 | Prob090_circuit1_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output q
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the circuit does, then imple... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob090_circuit1_prompt.txt",
"file_size": 651
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_96 | Prob049_m2014_q4b_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input ar
- input d
- output q
The module should implement a D flip flop, positive edge triggered, with
an asynchronous reset "ar".
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob049_m2014_q4b_prompt.txt",
"file_size": 308
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_97 | Prob118_history_shift_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input predict_valid
- input predict_taken
- input train_mispredicted
- input train_taken
- input train_history (32 bits)
... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob118_history_shift_prompt.txt",
"file_size": 1466
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_98 | Prob078_dualedge_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d
- output q
A dual-edge triggered flip-flop is triggered on both edges of the clock.
However, FPGAs don't have dual-edge triggered flip-flo... | {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob078_dualedge_prompt.txt",
"file_size": 500
} |
verilog_eval_v2 | dataset_spec-to-rtl | veval_99 | Prob004_vector2_prompt.txt | spec_to_rtl |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (32 bits)
- output out (32 bits)
The module should reverse the byte order of a 32-bit vector.
| {
"file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob004_vector2_prompt.txt",
"file_size": 265
} |
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