source stringclasses 1
value | dataset stringclasses 2
values | id stringlengths 7 9 | file stringlengths 12 40 | task_type stringclasses 2
values | content stringlengths 36 3.73k | metadata dict |
|---|---|---|---|---|---|---|
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_200 | Prob053_m2014_q4d_ifc.txt | code_completion |
module TopModule (
input clk,
input in,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ifc.txt",
"file_size": 67
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_201 | Prob084_ece241_2013_q12_prompt.txt | code_completion |
In this question, you will design a circuit for an 8x1 memory, where
writing to the memory is accomplished by shifting-in bits, and reading is
"random access", as in a typical RAM. You will then use the circuit to
realize a 3-input logic function. First, create an 8-bit shift register
with 8 D-type flip-flops. Label t... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob084_ece241_2013_q12_prompt.txt",
"file_size": 902
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_202 | Prob069_truthtable1_ifc.txt | code_completion |
module TopModule (
input x3,
input x2,
input x1,
output f
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob069_truthtable1_ifc.txt",
"file_size": 70
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_203 | Prob042_vector4_prompt.txt | code_completion |
One common place to see a replication operator is when sign-extending a
smaller number to a larger one, while preserving its signed value. This
is done by replicating the sign bit (the most significant bit) of the
smaller number to the left. For example, sign-extending 4'b0101 (5) to 8
bits results in 8'b00000101 (5),... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob042_vector4_prompt.txt",
"file_size": 648
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_204 | Prob103_circuit2_prompt.txt | code_completion |
This is a combinational circuit. Read the simulation waveforms to
determine what the circuit does, then implement it.
time a b c d q
0ns 0 0 0 0 1
5ns 0 0 0 0 1
10ns 0 0 0 0 1
15ns 0 0 0 0 1
20ns 0 0 0 1 0
25ns 0 0 1 0 0
30ns 0 0 1 1 1
35ns 0 1 0 0 0
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob103_circuit2_prompt.txt",
"file_size": 639
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_205 | Prob129_ece241_2013_q8_prompt.txt | code_completion |
Implement a Mealy-type finite state machine that recognizes the sequence
"101" on an input signal named x. Your FSM should have an output signal,
z, that is asserted to logic-1 when the "101" sequence is detected. Your
FSM should also have a negative edge triggered asynchronous reset. You
may only have 3 states in you... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob129_ece241_2013_q8_prompt.txt",
"file_size": 466
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_206 | Prob016_m2014_q4j_ifc.txt | code_completion |
module TopModule (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob016_m2014_q4j_ifc.txt",
"file_size": 76
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_207 | Prob133_2014_q3fsm_prompt.txt | code_completion |
Consider a finite state machine with inputs s and w. Assume that the FSM
begins in a reset state called A, as depicted below. The FSM remains in
state A as long as s = 0, and it moves to state B when s = 1. Once in
state B the FSM examines the value of the input w in the next three clock
cycles. If w = 1 in exactly tw... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob133_2014_q3fsm_prompt.txt",
"file_size": 764
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_208 | Prob070_ece241_2013_q2_prompt.txt | code_completion |
A single-output digital system with four inputs (a,b,c,d) generates a
logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1,
4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers
3, 8, 11, and 12 never occur in this system. For example, 7 corresponds
to a,b,c,d being set to 0,1,1,1,... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob070_ece241_2013_q2_prompt.txt",
"file_size": 556
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_209 | Prob082_lfsr32_prompt.txt | code_completion |
A linear feedback shift register is a shift register usually with a few
XOR gates to produce the next state of the shift register. A Galois LFSR
is one particular arrangement that shifts right, where a bit position with
a "tap" is XORed with the LSB output bit (q[0]) to produce its next value,
while bit positions with... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob082_lfsr32_prompt.txt",
"file_size": 581
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_210 | Prob046_dff8p_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob046_dff8p_ifc.txt",
"file_size": 89
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_211 | Prob122_kmap4_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
input d,
output reg out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob122_kmap4_ifc.txt",
"file_size": 84
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_212 | Prob071_always_casez_prompt.txt | code_completion |
Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the
output should report the first (least significant) bit in the vector that
is 1. Report zero if the input vector has no bits that are high. For
example, the input 8'b10010000 should output 3'd4, because bit[4] is
first bit that is high.
module TopMo... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob071_always_casez_prompt.txt",
"file_size": 372
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_213 | Prob090_circuit1_ifc.txt | code_completion |
module TopModule (
input a,
input b,
output q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob090_circuit1_ifc.txt",
"file_size": 56
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_214 | Prob135_m2014_q6b_prompt.txt | code_completion |
Consider the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1--> D
C (0) --0--> E
C (0) --1--> D
D (0) --0--> F
D (0) --1--> A
E (1) --0--> E
E (1) --1--> D
F (1) --0--> C
F (1) --1--> D
Assume that you want to Implement the FSM using three flip-flops and
stat... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob135_m2014_q6b_prompt.txt",
"file_size": 543
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_215 | Prob132_always_if2_ifc.txt | code_completion |
module TopModule (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob132_always_if2_ifc.txt",
"file_size": 146
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_216 | Prob001_zero_prompt.txt | code_completion |
Build a circuit that always outputs a LOW.
module TopModule (
output zero
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob001_zero_prompt.txt",
"file_size": 82
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_217 | Prob076_always_case_ifc.txt | code_completion |
module TopModule (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob076_always_case_ifc.txt",
"file_size": 191
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_218 | Prob099_m2014_q6c_prompt.txt | code_completion |
Consider the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1--> D
C (0) --0--> E
C (0) --1--> D
D (0) --0--> F
D (0) --1--> A
E (1) --0--> E
E (1) --1--> D
F (1) --0--> C
F (1) --1--> D
Resets into state A. For this part, assume that a one-hot code is used
wi... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob099_m2014_q6c_prompt.txt",
"file_size": 676
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_219 | Prob054_edgedetect_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob054_edgedetect_ifc.txt",
"file_size": 79
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_220 | Prob083_mt2015_q4b_prompt.txt | code_completion |
The module can be described by the following simulation waveform:
time x y z
0ns 0 0 1
5ns 0 0 1
10ns 0 0 1
15ns 0 0 1
20ns 0 0 1
25ns 1 0 0
30ns 1 0 0
35ns 0 1 0
40ns 0 1 0
45ns 1 1 1
50ns 1 1 1
55ns 0 0 1
60ns 0 1 0
65ns 0 1 0
70ns 1 1... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob083_mt2015_q4b_prompt.txt",
"file_size": 445
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_221 | Prob059_wire4_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
output w,
output x,
output y,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob059_wire4_ifc.txt",
"file_size": 103
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_222 | Prob069_truthtable1_prompt.txt | code_completion |
Create a combinational circuit that implements the truth table.
x3 | x2 | x1 | f
0 | 0 | 0 | 0
0 | 0 | 1 | 0
0 | 1 | 0 | 1
0 | 1 | 1 | 1
1 | 0 | 0 | 0
1 | 0 | 1 | 1
1 | 1 | 0 | 0
1 | 1 | 1 | 1
module TopModule (
input x3,
input x2,
input x1,
output f
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob069_truthtable1_prompt.txt",
"file_size": 308
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_223 | Prob139_2013_q2bfsm_prompt.txt | code_completion |
Consider a finite state machine that is used to control some type of
motor. The FSM has inputs x and y, which come from the motor, and
produces outputs f and g, which control the motor. There is also a clock
input called clk and a reset input (synchronous, active low) called
resetn. The FSM has to work as follows. As ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob139_2013_q2bfsm_prompt.txt",
"file_size": 1099
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_224 | Prob012_xnorgate_ifc.txt | code_completion |
module TopModule (
input a,
input b,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob012_xnorgate_ifc.txt",
"file_size": 58
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_225 | Prob080_timer_prompt.txt | code_completion |
Implement a timer that counts down for a given number of clock cycles,
then asserts a signal to indicate that the given duration has elapsed. A
good way to implement this is with a down-counter that asserts an output
signal when the count becomes 0. At each clock cycle:
(1) If load = 1, load the internal counter wi... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob080_timer_prompt.txt",
"file_size": 873
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_226 | Prob104_mt2015_muxdff_prompt.txt | code_completion |
Consider this Verilog module "full_module":
module full_module (
input [2:0] r, // load value
input L, // load
input clk, // clock
output reg [2:0] q // output
always @(posedge clk) begin
if (L) begin
q <= r;
end else begin
q <= {q[1] ^ q[2], q[0], q[2]};
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_prompt.txt",
"file_size": 837
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_227 | Prob123_bugs_addsubz_ifc.txt | code_completion |
module TopModule (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob123_bugs_addsubz_ifc.txt",
"file_size": 125
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_228 | Prob107_fsm1s_prompt.txt | code_completion |
This is a Moore state machine with two states, one input, and one output.
Implement this state machine in Verilog. The reset state is B and reset
is active-high synchronous.
B (out=1) --in=0--> A
B (out=1) --in=1--> B
A (out=0) --in=0--> B
A (out=0) --in=1--> A
module TopModule (
input clk,
input in,
i... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob107_fsm1s_prompt.txt",
"file_size": 349
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_229 | Prob006_vectorr_ifc.txt | code_completion |
module TopModule (
input [7:0] in,
output [7:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob006_vectorr_ifc.txt",
"file_size": 60
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_230 | Prob110_fsm2_prompt.txt | code_completion |
This is a Moore state machine with two states, two inputs, and one
output. Implement this state machine in Verilog. Reset is an active-high
asynchronous reset to state OFF.
OFF (out=0) --j=0--> OFF
OFF (out=0) --j=1--> ON
ON (out=1) --k=0--> ON
ON (out=1) --k=1--> OFF
module TopModule (
input clk,
inpu... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob110_fsm2_prompt.txt",
"file_size": 369
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_231 | Prob155_lemmings4_prompt.txt | code_completion |
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In pa... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob155_lemmings4_prompt.txt",
"file_size": 2691
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_232 | Prob033_ece241_2014_q1c_ifc.txt | code_completion |
module TopModule (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob033_ece241_2014_q1c_ifc.txt",
"file_size": 93
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_233 | Prob139_2013_q2bfsm_ifc.txt | code_completion |
module TopModule (
input clk,
input resetn,
input x,
input y,
output f,
output g
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob139_2013_q2bfsm_ifc.txt",
"file_size": 97
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_234 | Prob013_m2014_q4e_prompt.txt | code_completion |
Implement a 2-input NOR gate.
module TopModule (
input in1,
input in2,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob013_m2014_q4e_prompt.txt",
"file_size": 100
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_235 | Prob107_fsm1s_ifc.txt | code_completion |
module TopModule (
input clk,
input in,
input reset,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob107_fsm1s_ifc.txt",
"file_size": 76
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_236 | Prob148_2013_q2afsm_prompt.txt | code_completion |
Consider the FSM described by the state diagram shown below:
A --r1=0,r2=0,r3=0--> A
A --r1=1--> B
A --r1=0,r2=1--> C
A --r1=0,r2=0,r3=0--> D
B (g1=1) --r1=1--> B
B (g1=1) --r1=0--> A
C (g2=1) --r2=1--> C
C (g2=1) --r2=0--> A
Resetn is an active-low synchronous reset that resets into state A. This
FS... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob148_2013_q2afsm_prompt.txt",
"file_size": 1687
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_237 | Prob077_wire_decl_prompt.txt | code_completion |
Implement the following circuit. Create two intermediate wires (named
anything you want) to connect the AND and OR gates together. Note that
the wire that feeds the NOT gate is really wire `out`, so you do not
necessarily need to declare a third wire here. Notice how wires are
driven by exactly one source (output of a... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob077_wire_decl_prompt.txt",
"file_size": 779
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_238 | Prob081_7458_prompt.txt | code_completion |
The 7458 is a chip with four AND gates and two OR gates. Create a module
in Verilog with the same functionality as the 7458 chip. It has 10 inputs
and 2 outputs. You may choose to use an `assign` statement to drive each
of the output wires, or you may choose to declare (four) wires for use as
intermediate signals, whe... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob081_7458_prompt.txt",
"file_size": 830
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_239 | Prob126_circuit6_ifc.txt | code_completion |
module TopModule (
input [2:0] a,
output reg [15:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob126_circuit6_ifc.txt",
"file_size": 62
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_240 | Prob120_fsm3s_prompt.txt | code_completion |
The following is the state transition table for a Moore state machine
with one input, one output, and four states. Implement this state
machine. Include a synchronous active high reset that resets the FSM to
state A.
State | Next state in=0, Next state in=1 | Output
A | A, B | 0
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob120_fsm3s_prompt.txt",
"file_size": 536
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_241 | Prob143_fsm_onehot_prompt.txt | code_completion |
Given the follow state machine with 1 input and 2 outputs (the outputs
are given as "(out1, out2)"):
S0 (0, 0) --0--> S0
S0 (0, 0) --1--> S1
S1 (0, 0) --0--> S0
S1 (0, 0) --1--> S2
S2 (0, 0) --0--> S0
S2 (0, 0) --1--> S3
S3 (0, 0) --0--> S0
S3 (0, 0) --1--> S4
S4 (0, 0) --0--> S0
S4 (0, 0) --1--> ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob143_fsm_onehot_prompt.txt",
"file_size": 1145
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_242 | Prob144_conwaylife_ifc.txt | code_completion |
module TopModule (
input clk,
input load,
input [255:0] data,
output reg [255:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob144_conwaylife_ifc.txt",
"file_size": 95
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_243 | Prob026_alwaysblock1_ifc.txt | code_completion |
module TopModule (
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob026_alwaysblock1_ifc.txt",
"file_size": 95
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_244 | Prob051_gates4_prompt.txt | code_completion |
Build a combinational circuit with four inputs, in[3:0]. There are 3
outputs:
(1) out_and: output of a 4-input AND gate.
(2) out_or: output of a 4-input OR gate.
(3) out_xor: output of a 4-input XOR gate.
module TopModule (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob051_gates4_prompt.txt",
"file_size": 307
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_245 | Prob095_review2015_fsmshift_prompt.txt | code_completion |
This module is a part of the FSM for controlling the shift register, we
want the ability to enable the shift register for exactly 4 clock cycles
whenever the proper bit pattern is detected. Whenever the FSM is reset,
assert shift_ena for 4 cycles, then 0 forever (until reset). Reset should
be active high synchronous.
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob095_review2015_fsmshift_prompt.txt",
"file_size": 391
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_246 | Prob021_mux256to1v_prompt.txt | code_completion |
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all
packed into a single 1024-bit input vector. sel=0 should select bits
in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.
module TopModule (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob021_mux256to1v_prompt.txt",
"file_size": 296
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_247 | Prob093_ece241_2014_q3_ifc.txt | code_completion |
module TopModule (
input c,
input d,
output [3:0] mux_in
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob093_ece241_2014_q3_ifc.txt",
"file_size": 67
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_248 | Prob030_popcount255_ifc.txt | code_completion |
module TopModule (
input [254:0] in,
output reg [7:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob030_popcount255_ifc.txt",
"file_size": 66
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_249 | Prob029_m2014_q4g_ifc.txt | code_completion |
module TopModule (
input in1,
input in2,
input in3,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob029_m2014_q4g_ifc.txt",
"file_size": 81
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_250 | Prob104_mt2015_muxdff_ifc.txt | code_completion |
module TopModule (
input clk,
input L,
input q_in,
input r_in,
output reg Q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ifc.txt",
"file_size": 90
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_251 | Prob118_history_shift_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input predict_valid,
input predict_taken,
output logic [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob118_history_shift_ifc.txt",
"file_size": 216
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_252 | Prob002_m2014_q4i_prompt.txt | code_completion |
Build a circuit with no inputs and one output. That output should always
drive 0 (or logic low).
module TopModule (
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob002_m2014_q4i_prompt.txt",
"file_size": 135
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_253 | Prob006_vectorr_prompt.txt | code_completion |
Given an 8-bit input vector [7:0], reverse its bit ordering.
module TopModule (
input [7:0] in,
output [7:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob006_vectorr_prompt.txt",
"file_size": 123
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_254 | Prob074_ece241_2014_q4_prompt.txt | code_completion |
Given the finite state machine circuit described below, assume that the D
flip-flops are initially reset to zero before the machine begins.
Build this circuit in Verilog.
Input x goes to three different two-input gates: a XOR, an AND, and a OR
gate. Each of the three gates is connected to the input of a D flip-flop
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob074_ece241_2014_q4_prompt.txt",
"file_size": 703
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_255 | Prob127_lemmings1_prompt.txt | code_completion |
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In pa... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob127_lemmings1_prompt.txt",
"file_size": 930
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_256 | Prob143_fsm_onehot_ifc.txt | code_completion |
module TopModule (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob143_fsm_onehot_ifc.txt",
"file_size": 112
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_257 | Prob124_rule110_ifc.txt | code_completion |
module TopModule (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob124_rule110_ifc.txt",
"file_size": 95
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_258 | Prob019_m2014_q4f_ifc.txt | code_completion |
module TopModule (
input in1,
input in2,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob019_m2014_q4f_ifc.txt",
"file_size": 68
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_259 | Prob007_wire_ifc.txt | code_completion |
module TopModule (
input in,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob007_wire_ifc.txt",
"file_size": 48
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_260 | Prob085_shift4_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob085_shift4_ifc.txt",
"file_size": 120
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_261 | Prob150_review2015_fsmonehot_ifc.txt | code_completion |
module TopModule (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob150_review2015_fsmonehot_ifc.txt",
"file_size": 270
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_262 | Prob010_mt2015_q4a_prompt.txt | code_completion |
Implement the boolean function z = (x^y) & x.
module TopModule (
input x,
input y,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob010_mt2015_q4a_prompt.txt",
"file_size": 104
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_263 | Prob011_norgate_ifc.txt | code_completion |
module TopModule (
input a,
input b,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob011_norgate_ifc.txt",
"file_size": 58
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_264 | Prob099_m2014_q6c_ifc.txt | code_completion |
module TopModule (
input [6:1] y,
input w,
output Y2,
output Y4
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob099_m2014_q6c_ifc.txt",
"file_size": 76
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_265 | Prob141_count_clock_prompt.txt | code_completion |
Create a set of counters suitable for use as a 12-hour clock (with am/pm
indicator). Your counters are clocked by a fast-running clk, with a pulse
on ena whenever your clock should increment (i.e., once per second, while
"clk" is much faster than once per second). The signal "pm" is asserted
if the clock is PM, or is ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob141_count_clock_prompt.txt",
"file_size": 760
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_266 | Prob128_fsm_ps2_prompt.txt | code_completion |
The PS/2 mouse protocol sends messages that are three bytes long.
However, within a continuous byte stream, it's not obvious where messages
start and end. The only indication is that the first byte of each three
byte message always has in[3]=1 (but in[3] of the other two bytes may be
1 or 0 depending on data). We want... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob128_fsm_ps2_prompt.txt",
"file_size": 862
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_267 | Prob115_shift18_ifc.txt | code_completion |
module TopModule (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob115_shift18_ifc.txt",
"file_size": 128
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_268 | Prob098_circuit7_ifc.txt | code_completion |
module TopModule (
input clk,
input a,
output reg q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob098_circuit7_ifc.txt",
"file_size": 62
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_269 | Prob047_dff8ar_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] d,
input areset,
output reg [7:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob047_dff8ar_ifc.txt",
"file_size": 90
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_270 | Prob088_ece241_2014_q5b_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input x,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob088_ece241_2014_q5b_ifc.txt",
"file_size": 74
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_271 | Prob112_always_case2_ifc.txt | code_completion |
module TopModule (
input [3:0] in,
output reg [1:0] pos
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob112_always_case2_ifc.txt",
"file_size": 64
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_272 | Prob112_always_case2_prompt.txt | code_completion |
A priority encoder is a combinational circuit that, when given an input
bit vector, outputs the position of the first 1 bit in the vector. For
example, a 8-bit priority encoder given the input 8'b10010000 would
output 3'd4, because bit[4] is first bit that is high. Build a 4-bit
priority encoder. For this problem, if ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob112_always_case2_prompt.txt",
"file_size": 508
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_273 | Prob043_vector5_prompt.txt | code_completion |
Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise
one- bit comparisons in the 25-bit output vector. The output should be 1
if the two bits being compared are equal. Example: out[24] = ~a ^ a;
out[23] = ~a ^ b; out[22] = ~a ^ c; ... out[ 1] = ~e ^ d; out[ 0] = ~e ^
e.
module TopModule (
input a,
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob043_vector5_prompt.txt",
"file_size": 388
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_274 | Prob058_alwaysblock2_prompt.txt | code_completion |
Build an XOR gate three ways, using an assign statement (output
out_assign), a combinational always block (output out_always_comb), and a
clocked always block (output out_always_ff). Note that the clocked always
block produces a different circuit from the other two: There is a flip-
flop so the output is delayed.
mod... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob058_alwaysblock2_prompt.txt",
"file_size": 453
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_275 | Prob045_edgedetect2_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob045_edgedetect2_ifc.txt",
"file_size": 81
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_276 | Prob092_gatesv100_ifc.txt | code_completion |
module TopModule (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob092_gatesv100_ifc.txt",
"file_size": 123
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_277 | Prob038_count15_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob038_count15_ifc.txt",
"file_size": 72
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_278 | Prob063_review2015_shiftcount_ifc.txt | code_completion |
module TopModule (
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob063_review2015_shiftcount_ifc.txt",
"file_size": 109
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_279 | Prob128_fsm_ps2_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] in,
input reset,
output done
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob128_fsm_ps2_ifc.txt",
"file_size": 83
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_280 | Prob010_mt2015_q4a_ifc.txt | code_completion |
module TopModule (
input x,
input y,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob010_mt2015_q4a_ifc.txt",
"file_size": 56
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_281 | Prob028_m2014_q4a_prompt.txt | code_completion |
Implement a D latch using an always block.
module TopModule (
input d,
input ena,
output logic q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob028_m2014_q4a_prompt.txt",
"file_size": 109
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_282 | Prob045_edgedetect2_prompt.txt | code_completion |
For each bit in an 8-bit vector, detect when the input signal changes
from one clock cycle to the next (detect any edge). The output bit should
be set the cycle after a 0 to 1 or 1 to 0 transition occurs.
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob045_edgedetect2_prompt.txt",
"file_size": 288
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_283 | Prob108_rule90_prompt.txt | code_completion |
Rule 90 is a one-dimensional cellular automaton with interesting
properties. The rules are simple. There is a one-dimensional array of
cells (on or off). At each time step, the next state of each cell is the
XOR of the cell's two current neighbours:
Left | Center | Right | Center's next state
1 | 1 | 1 ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob108_rule90_prompt.txt",
"file_size": 866
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_284 | Prob080_timer_ifc.txt | code_completion |
module TopModule (
input clk,
input load,
input [9:0] data,
output tc
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob080_timer_ifc.txt",
"file_size": 82
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_285 | Prob030_popcount255_prompt.txt | code_completion |
A "population count" circuit counts the number of '1's in an input
vector. Build a population count circuit for a 255-bit input vector.
module TopModule (
input [254:0] in,
output reg [7:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob030_popcount255_prompt.txt",
"file_size": 204
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_286 | Prob086_lfsr5_prompt.txt | code_completion |
A linear feedback shift register is a shift register usually with a few
XOR gates to produce the next state of the shift register. A Galois LFSR
is one particular arrangement that shifts right, where a bit position with
a "tap" is XORed with the LSB output bit (q[0]) to produce its next value,
while bit positions with... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob086_lfsr5_prompt.txt",
"file_size": 778
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_287 | Prob156_review2015_fancytimer_prompt.txt | code_completion |
We want to create a timer with one input that:
(1) is started when a particular input pattern (1101) is detected,
(2) shifts in 4 more bits to determine the duration to delay,
(3) waits for the counters to finish counting, and
(4) notifies the user and waits for the user to acknowledge the timer.
The serial ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob156_review2015_fancytimer_prompt.txt",
"file_size": 1733
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_288 | Prob055_conditional_prompt.txt | code_completion |
Given four unsigned numbers, find the minimum. Unsigned numbers can be
compared with standard comparison operators (a < b).
module TopModule (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output reg [7:0] min
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob055_conditional_prompt.txt",
"file_size": 240
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_289 | Prob096_review2015_fsmseq_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
input data,
output start_shifting
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob096_review2015_fsmseq_ifc.txt",
"file_size": 89
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_290 | Prob079_fsm3onehot_prompt.txt | code_completion |
The following is the state transition table for a Moore state machine
with one input, one output, and four states. Use the following one-hot
state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000. Derive state
transition and output logic equations by inspection assuming a one-hot
encoding. Implement only the state... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob079_fsm3onehot_prompt.txt",
"file_size": 755
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_291 | Prob067_countslow_ifc.txt | code_completion |
module TopModule (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob067_countslow_ifc.txt",
"file_size": 89
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_292 | Prob016_m2014_q4j_prompt.txt | code_completion |
Implement a 4-bit adder with full adders. The output sum should include
the overflow bit.
module TopModule (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob016_m2014_q4j_prompt.txt",
"file_size": 168
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_293 | Prob040_count10_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob040_count10_ifc.txt",
"file_size": 72
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_294 | Prob073_dff16e_prompt.txt | code_completion |
Create 16 D flip-flops. It's sometimes useful to only modify parts of a
group of flip-flops. The byte-enable inputs control whether each byte of
the 16 registers should be written to on that cycle. byteena[1] controls
the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].
resetn is a synchronous, act... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob073_dff16e_prompt.txt",
"file_size": 509
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_295 | Prob083_mt2015_q4b_ifc.txt | code_completion |
module TopModule (
input x,
input y,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob083_mt2015_q4b_ifc.txt",
"file_size": 56
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_296 | Prob001_zero_ifc.txt | code_completion |
module TopModule (
output zero
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob001_zero_ifc.txt",
"file_size": 37
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_297 | Prob111_fsm2s_ifc.txt | code_completion |
module TopModule (
input clk,
input j,
input k,
input reset,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob111_fsm2s_ifc.txt",
"file_size": 86
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_298 | Prob134_2014_q3c_ifc.txt | code_completion |
module TopModule (
input clk,
input x,
input [2:0] y,
output reg Y0,
output reg z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob134_2014_q3c_ifc.txt",
"file_size": 96
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_299 | Prob145_circuit8_ifc.txt | code_completion |
module TopModule (
input clock,
input a,
output reg p,
output reg q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob145_circuit8_ifc.txt",
"file_size": 80
} |
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