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One of the first programs to run on the Mark I was initiated on 29 March 1944 by John von Neumann. At that time, von Neumann was working on the Manhattan Project, and needed to determine whether implosion was a viable choice to detonate the atomic bomb that would be used a year later. The Mark I also computed and printed mathematical tables, which had been the initial goal of British inventor Charles Babbage for his "analytical engine" in 1837.
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According to Edmund Berkeley, the operators of the Mark I often called the machine “Bessy, the Bessel engine,” after Bessel functions.
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The Mark I was disassembled in 1959; part of it was given to IBM, part went to the Smithsonian Institution, and part entered the Harvard Collection of Historical Scientific Instruments. For decades, Harvard's portion was on display in the lobby of the Aiken Computation Lab. About 1997, it was moved to the Harvard Science Center. In 2021, it was moved again, to the lobby of Harvard's new Science and Engineering Complex in Allston, Massachusetts.
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The original concept was presented to IBM by Howard Aiken in November 1937. After a feasibility study by IBM engineers, the company chairman Thomas Watson Sr. personally approved the project and its funding in February 1939.
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Howard Aiken had started to look for a company to design and build his calculator in early 1937. After two rejections, he was shown a demonstration set that Charles Babbage’s son had given to Harvard University 70 years earlier. This led him to study Babbage and to add references to the Analytical Engine to his proposal; the resulting machine "brought Babbage’s principles of the Analytical Engine almost to full realization, while adding important new features."
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The ASCC was developed and built by IBM at their Endicott plant and shipped to Harvard in February 1944. It began computations for the US Navy Bureau of Ships in May and was officially presented to the university on August 7, 1944.
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Although not the first working computer, the machine was the first to automate the execution of complex calculations, making it a significant step forward for computing.
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The ASCC was built from switches, relays, rotating shafts, and clutches. It used 765,000 electromechanical components and hundreds of miles of wire, comprising a volume of 816 cubic feet – 51 feet in length, 8 feet in height, and 2 feet deep. It weighed about 9,445 pounds . The basic calculating units had to be synchronized and powered mechanically, so they were operated by a 50-foot drive shaft coupled to a 5 horsepower electric motor, which served as the main power source and system clock. From the IBM Archives:
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The enclosure for the Mark I was designed by futuristic American industrial designer Norman Bel Geddes at IBM's expense. Aiken was annoyed that the cost was not used to build additional computer equipment.
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The Mark I had 60 sets of 24 switches for manual data entry and could store 72 numbers, each 23 decimal digits long. It could do 3 additions or subtractions in a second. A multiplication took 6 seconds, a division took 15.3 seconds, and a logarithm or a trigonometric function took over one minute.
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The Mark I read its instructions from a 24-channel punched paper tape. It executed the current instruction and then read the next one. A separate tape could contain numbers for input, but the tape formats were not interchangeable. Instructions could not be executed from the storage registers. Because instructions were not stored in working memory, it is widely claimed that the Harvard Mark I was the origin of the Harvard architecture. However, this is disputed in The Myth of the Harvard Architecture published in the IEEE Annals of History of Computing, which shows the term 'Harvard architecture' did not come into use until the 1970s and was only retrospectively applied to the Harvard machines, and that the term could only be applied to the Mark III and IV, not to the Mark I or II.
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The main sequence mechanism was unidirectional. This meant that complex programs had to be physically lengthy. A program loop was accomplished by loop unrolling or by joining the end of the paper tape containing the program back to the beginning of the tape . At first, conditional branching in Mark I was performed manually. Later modifications in 1946 introduced automatic program branching . The first programmers of the Mark I were computing pioneers Richard Milton Bloch, Robert Campbell, and Grace Hopper. There was also a small technical team whose assignment was to actually operate the machine; some had been IBM employees before being required to join the Navy to work on the machine. This technical team was not informed of the overall purpose of their work while at Harvard.
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The 24 channels of the input tape were divided into three fields of eight channels. Each storage location, each set of switches, and the registers associated with the input, output, and arithmetic units were assigned a unique identifying index number. These numbers were represented in binary on the control tape. The first field was the binary index of the result of the operation, the second was the source datum for the operation and the third field was a code for the operation to be performed.
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In 1928 L.J. Comrie was the first to turn IBM "punched-card equipment to scientific use: computation of astronomical tables by the method of finite differences, as envisioned by Babbage 100 years earlier for his Difference Engine". Very soon after, IBM started to modify its tabulators to facilitate this kind of computation. One of these tabulators, built in 1931, was The Columbia Difference Tabulator.
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John von Neumann had a team at Los Alamos that used "modified IBM punched-card machines" to determine the effects of the implosion. In March 1944, he proposed to run certain problems regarding implosion of the Mark I, and in 1944 he arrived with two mathematicians to write a simulation program to study the implosion of the first atomic bomb.
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"Von Neumann joined the Manhattan Project in 1943, working on the immense number of calculations needed to build the atomic bomb. He showed that the implosion design, which would later be used in the Trinity and Fat Man bombs, was likely faster and more efficient than the gun design."
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Aiken published a press release announcing the Mark I listing himself as the sole “inventor”. James W. Bryce was the only IBM person mentioned, even though several IBM engineers including Clair Lake and Frank Hamilton had helped to build various elements. IBM chairman Thomas J. Watson was enraged, and only reluctantly attended the dedication ceremony on August 7, 1944. Aiken, in turn, decided to build further machines without IBM's help, and the ASCC came to be generally known as the "Harvard Mark I". IBM went on to build its Selective Sequence Electronic Calculator to both test new technology and provide more publicity for the company's efforts.
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The Mark I was followed by the Harvard Mark II , Mark III/ADEC , and Harvard Mark IV – all the work of Aiken. The Mark II was an improvement over the Mark I, although it still was based on electromechanical relays. The Mark III used mostly electronic components—vacuum tubes and crystal diodes—but also included mechanical components: rotating magnetic drums for storage, plus relays for transferring data between drums. The Mark IV was all-electronic, replacing the remaining mechanical components with magnetic core memory. The Mark II and Mark III were delivered to the US Navy base at Dahlgren, Virginia. The Mark IV was built for the US Air Force, but it stayed at Harvard.
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The Mark I was disassembled in 1959, and portions of it went on display in the Science Center, as part of the Harvard Collection of Historical Scientific Instruments. It was relocated to the new Science and Engineering Complex in Allston in July 2021. Other sections of the original machine had much earlier been transferred to IBM and the Smithsonian Institution.
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In computing, an opcode is the portion of a machine language instruction that specifies the operation to be performed. Beside the opcode itself, most instructions also specify the data they will process, in the form of operands. In addition to opcodes used in the instruction set architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
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Specifications and format of the opcodes are laid out in the instruction set architecture of the processor in question, which may be a general CPU or a more specialized processing unit. Opcodes for a given instruction set can be described through the use of an opcode table detailing all possible opcodes. Apart from the opcode itself, an instruction normally also has one or more specifiers for operands on which the operation should act, although some operations may have implicit operands, or none at all. There are instruction sets with nearly uniform fields for opcode and operand specifiers, as well as others with a more complicated, variable-length structure. Instruction sets can be extended through the use of opcode prefixes which add a subset of new instructions made up of existing opcodes following reserved byte sequences.
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Depending on architecture, the operands may be register values, values in the stack, other memory values, I/O ports , etc., specified and accessed using more or less complex addressing modes. The types of operations include arithmetic, data copying, logical operations, and program control, as well as special instructions .
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Assembly language, or just assembly, is a low-level programming language, which uses mnemonic instructions and operands to represent machine code. This enhances the readability while still giving precise control over the machine instructions. Most programming is currently done using high-level programming languages, which are typically easier for humans to understand and write. These languages need to be compiled by a system-specific compiler, or run through other compiled programs.
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Opcodes can also be found in so-called byte codes and other representations intended for a software interpreter rather than a hardware device. These software-based instruction sets often employ slightly higher-level data types and operations than most hardware counterparts, but are nevertheless constructed along similar lines. Examples include the byte code found in Java class files which are then interpreted by the Java Virtual Machine , the byte code used in GNU Emacs for compiled Lisp code, .NET Common Intermediate Language , and many others.
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In computer programming, machine code is computer code consisting of machine language instructions, which are used to control a computer's central processing unit . Although decimal computers were once common, the contemporary marketplace is dominated by binary computers; for those computers, machine code is "the binary representation of a computer program which is actually read and interpreted by the computer. A program in machine code consists of a sequence of machine instructions ."
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Each instruction causes the CPU to perform a very specific task, such as a load, a store, a jump, or an arithmetic logic unit operation on one or more units of data in the CPU's registers or memory.
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Early CPUs had specific machine code that might break backward compatibility with each new CPU released. The notion of an instruction set architecture defines and specifies the behavior and encoding in memory of the instruction set of the system, without specifying its exact implementation. This acts as an abstraction layer, enabling compatibility within the same family of CPUs, so that machine code written or generated according to the ISA for the family will run on all CPUs in the family, including future CPUs.
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In general, each architecture family has its own ISA, and hence its own specific machine code language. There are exceptions, such as the VAX architecture, which included optional support of the PDP-11 instruction set and IA-64, which included optional support of the IA-32 instruction set. Another example is the PowerPC 615, a processor designed to natively process both PowerPC and x86 instructions.
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Machine code is a strictly numerical language, and is the lowest-level interface to the CPU intended for a programmer. Assembly language provides a direct mapping between the numerical machine code and a human-readable version where numerical opcodes and operands are replaced by readable strings . While it is possible to write programs directly in machine code, managing individual bits and calculating numerical addresses and constants manually is tedious and error-prone. For this reason, programs are very rarely written directly in machine code in modern contexts, but may be done for low-level debugging, program patching and assembly language disassembly.
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The majority of practical programs today are written in higher-level languages. Those programs are either translated into machine code by a compiler, or are interpreted by an interpreter, usually after being translated into an intermediate code, such as a bytecode, that is then interpreted.
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Machine code is by definition the lowest level of programming detail visible to the programmer, but internally many processors use microcode or optimize and transform machine code instructions into sequences of micro-ops. Microcode and micro-ops are not generally considered to be machine code; except on some machines, the user cannot write microcode or micro-ops, and the operation of microcode and the transformation of machine-code instructions into micro-ops happens transparently to the programmer except for performance related side effects.
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Every processor or processor family has its own instruction set. Instructions are patterns of bits, digits, or characters that correspond to machine commands. Thus, the instruction set is specific to a class of processors using the same architecture. Successor or derivative processor designs often include instructions of a predecessor and may add new additional instructions. Occasionally, a successor design will discontinue or alter the meaning of some instruction code , affecting code compatibility to some extent; even compatible processors may show slightly different behavior for some instructions, but this is rarely a problem. Systems may also differ in other details, such as memory arrangement, operating systems, or peripheral devices. Because a program normally relies on such factors, different systems will typically not run the same machine code, even when the same type of processor is used.
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A processor's instruction set may have fixed-length or variable-length instructions. How the patterns are organized varies with the particular architecture and type of instruction. Most instructions have one or more opcode fields that specify the basic instruction type , the operation , and other fields that may give the type of the operand, the addressing mode, the addressing offset or index, or the operand value itself .
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Not all machines or individual instructions have explicit operands. On a machine with a single accumulator, the accumulator is implicitly both the left operand and result of most arithmetic instructions. Some other architectures, such as the x86 architecture, have accumulator versions of common instructions, with the accumulator regarded as one of the general registers by longer instructions. A stack machine has most or all of its operands on an implicit stack. Special purpose instructions also often lack explicit operands; for example, CPUID in the x86 architecture writes values into four implicit destination registers. This distinction between explicit and implicit operands is important in code generators, especially in the register allocation and live range tracking parts. A good code optimizer can track implicit as well as explicit operands which may allow more frequent constant propagation, constant folding of registers and other code enhancements.
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A computer program is a list of instructions that can be executed by a central processing unit . A program's execution is done in order for the CPU that is executing it to solve a problem and thus accomplish a result. While simple processors are able to execute instructions one after another, superscalar processors are able under certain circumstances of executing two or more instructions simultaneously. As an example, the original Intel Pentium from 1993 can execute at most two instructions per clock cycle when its pipeline is full.
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Program flow may be influenced by special 'jump' instructions that transfer execution to an address other than the next numerically sequential address. Whether these conditional jumps occur is dependent upon a condition such as a value being greater than, less than, or equal to another value.
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A much more human friendly rendition of machine language, called assembly language, uses mnemonic codes to refer to machine code instructions, rather than using the instructions' numeric values directly, and uses symbolic names to refer to storage locations and sometimes registers. For example, on the Zilog Z80 processor, the machine code 00000101, which causes the CPU to decrement the B general-purpose register, would be represented in assembly language as DEC B.
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The MIPS architecture provides a specific example for a machine code whose instructions are always 32 bits long.: 299 The general type of instruction is given by the op field, the highest 6 bits. J-type and I-type instructions are fully specified by op. R-type instructions include an additional field funct to determine the exact operation. The fields used in these types are:
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rs, rt, and rd indicate register operands; shamt gives a shift amount; and the address or immediate fields contain an operand directly.: 299–301
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For example, adding the registers 1 and 2 and placing the result in register 6 is encoded:: 554
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Load a value into register 8, taken from the memory cell 68 cells after the location listed in register 3:: 552
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Jumping to the address 1024:: 552
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On processor architectures with variable-length instruction sets it is, within the limits of the control-flow resynchronizing phenomenon known as the Kruskal count, sometimes possible through opcode-level programming to deliberately arrange the resulting code so that two code paths share a common fragment of opcode sequences. These are called overlapping instructions, overlapping opcodes, overlapping code, overlapped code, instruction scission, or jump into the middle of an instruction, and represent a form of superposition.
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In the 1970s and 1980s, overlapping instructions were sometimes used to preserve memory space. One example were in the implementation of error tables in Microsoft's Altair BASIC, where interleaved instructions mutually shared their instruction bytes. The technique is rarely used today, but might still be necessary to resort to in areas where extreme optimization for size is necessary on byte-level such as in the implementation of boot loaders which have to fit into boot sectors.
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It is also sometimes used as a code obfuscation technique as a measure against disassembly and tampering.
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The principle is also utilized in shared code sequences of fat binaries which must run on multiple instruction-set-incompatible processor platforms.
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This property is also used to find unintended instructions called gadgets in existing code repositories and is utilized in return-oriented programming as alternative to code injection for exploits such as return-to-libc attacks.
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In some computers, the machine code of the architecture is implemented by an even more fundamental underlying layer called microcode, providing a common machine language interface across a line or family of different models of computer with widely different underlying dataflows. This is done to facilitate porting of machine language programs between different models. An example of this use is the IBM System/360 family of computers and their successors. With dataflow path widths of 8 bits to 64 bits and beyond, they nevertheless present a common architecture at the machine language level across the entire line.
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Using microcode to implement an emulator enables the computer to present the architecture of an entirely different computer. The System/360 line used this to allow porting programs from earlier IBM machines to the new family of computers, e.g. an IBM 1401/1440/1460 emulator on the IBM S/360 model 40.
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Machine code is generally different from bytecode , which is either executed by an interpreter or itself compiled into machine code for faster execution. An exception is when a processor is designed to use a particular bytecode directly as its machine code, such as is the case with Java processors.
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Machine code and assembly code are sometimes called native code when referring to platform-dependent parts of language features or libraries.
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From the point of view of the CPU, machine code is stored in RAM, but is typically also kept in a set of caches for performance reasons. There may be different caches for instructions and data, depending on the architecture.
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The CPU knows what machine code to execute, based on its internal program counter. The program counter points to a memory address and is changed based on special instructions which may cause programmatic branches. The program counter is typically set to a hard coded value when the CPU is first powered on, and will hence execute whatever machine code happens to be at this address.
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Similarly, the program counter can be set to execute whatever machine code is at some arbitrary address, even if this is not valid machine code. This will typically trigger an architecture specific protection fault.
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The CPU is oftentimes told, by page permissions in a paging based system, if the current page actually holds machine code by an execute bit — pages have multiple such permission bits for various housekeeping functionality. E.g. on Unix-like systems memory pages can be toggled to be executable with the mprotect system call, and on Windows, VirtualProtect can be used to achieve a similar result. If an attempt is made to execute machine code on a non-executable page, an architecture specific fault will typically occur. Treating data as machine code, or finding new ways to use existing machine code, by various techniques, is the basis of some security vulnerabilities.
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Similarly, in a segment based system, segment descriptors can indicate whether a segment can contain executable code and in what rings that code can run.
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From the point of view of a process, the code space is the part of its address space where the code in execution is stored. In multitasking systems this comprises the program's code segment and usually shared libraries. In multi-threading environment, different threads of one process share code space along with data space, which reduces the overhead of context switching considerably as compared to process switching.
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Pamela Samuelson wrote that machine code is so unreadable that the United States Copyright Office cannot identify whether a particular encoded program is an original work of authorship; however, the US Copyright Office does allow for copyright registration of computer programs and a program's machine code can sometimes be decompiled in order to make its functioning more easily understandable to humans. However, the output of a decompiler or disassembler will be missing the comments and symbolic references, so while the output may be easier to read than the object code, it will still be more difficult than the original source code. This problem does not exist for object-code formats like SQUOZE, where the source code is included in the file.
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Cognitive science professor Douglas Hofstadter has compared machine code to genetic code, saying that "Looking at a program written in machine language is vaguely comparable to looking at a DNA molecule atom by atom."
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MIPS is a family of reduced instruction set computer instruction set architectures : A-1 : 19 developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.
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There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 . The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.
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The MIPS architecture has several optional extensions. MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room, and MIPS MT, which adds multithreading capability.
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Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as Alpha. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to RISC-V.
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The first version of the MIPS architecture was designed by MIPS Computer Systems for its R2000 microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985. When MIPS II was introduced, MIPS was renamed MIPS I to distinguish it from the new version.: 32
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MIPS Computer Systems' R6000 microprocessor was the first MIPS II implementation.: 8 Designed for servers, the R6000 was fabricated and sold by Bipolar Integrated Technology, but was a commercial failure. During the mid-1990s, many new 32-bit MIPS processors for embedded systems were MIPS II implementations because the introduction of the 64-bit MIPS III architecture in 1991 left MIPS II as the newest 32-bit MIPS architecture until MIPS32 was introduced in 1999.: 19
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MIPS Computer Systems' R4000 microprocessor was the first MIPS III implementation. It was designed for use in personal, workstation, and server computers. MIPS Computer Systems aggressively promoted the MIPS architecture and R4000, establishing the Advanced Computing Environment consortium to advance its Advanced RISC Computing standard, which aimed to establish MIPS as the dominant personal computing platform. ARC found little success in personal computers, but the R4000 were widely used in workstation and server computers, especially by its largest user, Silicon Graphics. Other uses of the R4000 included high-end embedded systems and supercomputers. MIPS III was eventually implemented by a number of embedded microprocessors. Quantum Effect Design's R4600 and its derivatives was widely used in high-end embedded systems and low-end workstations and servers. MIPS Technologies' R4200 , was designed for embedded systems, laptop, and personal computers. A derivative, the R4300i, fabricated by NEC Electronics, was used in the Nintendo 64 game console. The Nintendo 64, along with the PlayStation, were among the highest volume users of MIPS architecture processors in the mid-1990s.
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The first MIPS IV implementation was the MIPS Technologies R8000 microprocessor chipset . The design of the R8000 began at Silicon Graphics, Inc. and it was only used in high-end workstations and servers for scientific and technical applications where high performance on large floating-point workloads was important. Later implementations were the MIPS Technologies R10000 and the Quantum Effect Devices R5000 and RM7000 . The R10000, fabricated and sold by NEC Electronics and Toshiba, and its derivatives were used by NEC, Pyramid Technology, Silicon Graphics, and Tandem Computers in workstations, servers, and supercomputers. The R5000 and R7000 found use in high-end embedded systems, personal computers, and low-end workstations and servers. A derivative of the R5000 from Toshiba, the R5900, was used in Sony Computer Entertainment's Emotion Engine, which powered its PlayStation 2 game console.
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Announced on October 21, 1996, at the Microprocessor Forum 1996 alongside the MIPS Digital Media Extensions extension, MIPS V was designed to improve the performance of 3D graphics transformations. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from Silicon Graphics. MIPS V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications. MIPS V implementations were never introduced. On May 12, 1997, Silicon Graphics announced the H1 and H2 microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in the first half of 1999. The H1 and H2 projects were later combined and eventually canceled in 1998. While there have not been any MIPS V implementations, MIPS64 Release 1 was based on MIPS V and retains all of its features as an optional Coprocessor 1 feature called Paired-Single.
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When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Through MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem, and the architecture definition was changed to define a 32-bit and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999. MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V. NEC, Toshiba and SiByte each obtained licenses for MIPS64 as soon as it was announced. Philips, LSI Logic, IDT, Raza Microelectronics, Inc., Cavium, Loongson Technology and Ingenic Semiconductor have since joined them. MIPS32/MIPS64 Release 5 was announced on December 6, 2012. According to the Product Marketing Director at MIPS, Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures.
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In December 2018, Wave Computing, the new owner of the MIPS architecture, announced that MIPS ISA would be open-sourced in a program dubbed the MIPS Open initiative. The program was intended to open up access to the most recent versions of both the 32-bit and 64-bit designs making them available without any licensing or royalty fees as well as granting participants licenses to existing MIPS patents.
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In March 2019, one version of the architecture was made available under a royalty-free license, but later that year the program was shut down again.
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In March 2021, Wave Computing announced that the development of the MIPS architecture has ceased. The company has joined the RISC-V foundation and future processor designs will be based on the RISC-V architecture. In spite of this, some licensees such as Loongson continue with new extension of MIPS-compatible ISAs on their own.
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In January 2024, Loongson won a case over rights to use MIPS architecture.
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MIPS is a modular architecture supporting up to four coprocessors . In MIPS terminology, CP0 is the System Control Coprocessor , CP1 is an optional floating-point unit and CP2/3 are optional implementation-defined coprocessors . For example, in the PlayStation video game console, CP2 is the Geometry Transformation Engine , which accelerates the processing of geometry in 3D computer graphics.
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MIPS is a load/store architecture ; except for the load/store instructions used to access memory, all instructions operate on the registers.
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MIPS I has thirty-two 32-bit general-purpose registers . Register $0 is hardwired to zero and writes to it are discarded. Register $31 is the link register. For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers, HI and LO, are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers.
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The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries.
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Instructions are divided into three types: R , I , and J . Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.: A-174
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The following are the three formats used for the core instruction set:
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MIPS I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words. Only one addressing mode is supported: base + displacement. Since MIPS I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either sign-extended or zero-extended to 32 bits. The load instructions suffixed by "unsigned" perform zero extension; otherwise sign extension is performed. Load instructions source the base from the contents of a GPR and write the result to another GPR . Store instructions source the base from the contents of a GPR and the store data from another GPR . All load and store instructions compute the memory address by summing the base with the sign-extended 16-bit immediate. MIPS I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled. To support efficient unaligned memory accesses, there are load/store word instructions suffixed by "left" or "right". All load instructions are followed by a load delay slot. The instruction in the load delay slot cannot use the data loaded by the load instruction. The load delay slot can be filled with an instruction that is not dependent on the load; a nop is substituted if such an instruction cannot be found.
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MIPS I has instructions to perform addition and subtraction. These instructions source their operands from two GPRs , and write the result to a third GPR . Alternatively, addition can source one of the operands from a 16-bit immediate . The instructions for addition and subtraction have two variants: by default, an exception is signaled if the result overflows; instructions with the "unsigned" suffix do not signal an exception. The overflow check interprets the result as a 32-bit two's complement integer. MIPS I has instructions to perform bitwise logical AND, OR, XOR, and NOR. These instructions source their operands from two GPRs and write the result to a third GPR. The AND, OR, and XOR instructions can alternatively source one of the operands from a 16-bit immediate . The Set on relation instructions write one or zero to the destination register if the specified relation is true or false. These instructions source their operands from two GPRs or one GPR and a 16-bit immediate , and write the result to a third GPR. By default, the operands are interpreted as signed integers. The variants of these instructions that are suffixed with "unsigned" interpret the operands as unsigned integers .
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The Load Immediate Upper instruction copies the 16-bit immediate into the high-order 16 bits of a GPR. It is used in conjunction with the Or Immediate instruction to load a 32-bit immediate into a register.
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MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. The operand is obtained from a GPR , and the result is written to another GPR . The shift distance is obtained from either a GPR or a 5-bit "shift amount" .
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2,184
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MIPS I has instructions for signed and unsigned integer multiplication and division. These instructions source their operands from two GPRs and write their results to a pair of 32-bit registers called HI and LO, since they may execute separately from the other CPU instructions. For multiplication, the high- and low-order halves of the 64-bit product is written to HI and LO . For division, the quotient is written to LO and the remainder to HI. To access the results, a pair of instructions is provided to copy the contents of HI or LO to a GPR. These instructions are interlocked: reads of HI and LO do not proceed past an unfinished arithmetic instruction that will write to HI and LO. Another pair of instructions copies the contents of a GPR to HI and LO. These instructions are used to restore HI and LO to their original state after exception handling. Instructions that read HI or LO must be separated by two instructions that do not write to HI or LO.
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2,185
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All MIPS I control flow instructions are followed by a branch delay slot. Unless the branch delay slot is filled by an instruction performing useful work, an nop is substituted. MIPS I branch instructions compare the contents of a GPR against zero or another GPR as signed integers and branch if the specified condition is true. Control is transferred to the address computed by shifting the 16-bit offset left by two bits, sign-extending the 18-bit result, and adding the 32-bit sign-extended result to the sum of the program counter and 810. Jumps have two versions: absolute and register-indirect. Absolute jumps compute the address to which control is transferred by shifting the 26-bit instr_index left by two bits and concatenating the 28-bit result with the four high-order bits of the address of the instruction in the branch delay slot. Register-indirect jumps transfer control to the instruction at the address sourced from a GPR . The address sourced from the GPR must be word-aligned, else an exception is signaled after the instruction in the branch delay slot is executed. Branch and jump instructions that link save the return address to GPR 31. The "Jump and Link Register" instruction permits the return address to be saved to any writable GPR.
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2,186
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MIPS I has two instructions for software to signal an exception: System Call and Breakpoint. System Call is used by user mode software to make kernel calls; and Breakpoint is used to transfer control to a debugger via the kernel's exception handler. Both instructions have a 20-bit Code field that can contain operating environment-specific information for the exception handler.
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2,187
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MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair, resulting in 16 usable registers for most instructions .
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2,188
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Single precision is denoted by the .s suffix, while double precision is denoted by the .d suffix.
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2,189
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MIPS II removed the load delay slot: 41 and added several sets of instructions. For shared-memory multiprocessing, the Synchronize Shared Memory, Load Linked Word, and Store Conditional Word instructions were added. A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given branch-likely versions that executed the instruction in the branch delay slot only if the branch is taken.: 40 These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot.: 212 Doubleword load and store instructions for COP1–3 were added. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned.
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2,190
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The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the Floating Point Control and Status Register.
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2,191
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MIPS III is a backwards-compatible extension of MIPS II that added support for 64-bit memory addressing and integer operations. The 64-bit data type is called a doubleword, and MIPS III extended the general-purpose registers, HI/LO registers, and program counter to 64 bits to support it. New instructions were added to load and store doublewords, to perform integer addition, subtraction, multiplication, division, and shift operations on them, and to move doubleword between the GPRs and HI/LO registers. For shared-memory multiprocessing, the Load Linked Double Word, and Store Conditional Double Word instructions were added. Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. Among those instructions redefined was Load Word. In MIPS III it sign-extends words to 64 bits. To complement Load Word, a version that zero-extends was added.
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2,192
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The R instruction format's inability to specify the full shift distance for 64-bit shifts required MIPS III to provide three 64-bit versions of each MIPS I shift instruction. The first version is a 64-bit version of the original shift instructions, used to specify constant shift distances of 0–31 bits. The second version is similar to the first, but adds 3210 the shift amount field's value so that constant shift distances of 32–63 bits can be specified. The third version obtains the shift distance from the six low-order bits of a GPR.
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2,193
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MIPS III added a supervisor privilege level in between the existing kernel and user privilege levels. This feature only affected the implementation-defined System Control Processor .
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2,194
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MIPS III removed the Coprocessor 3 support instructions, and reused its opcodes for the new doubleword instructions. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. The floating general registers were extended to 64 bits and the requirement for instructions to use even-numbered register only was removed. This is incompatible with earlier versions of the architecture; a bit in the floating-point control/status register is used to operate the MIPS III floating-point unit in a MIPS I- and II-compatible mode. The floating-point control registers were not extended for compatibility. The only new floating-point instructions added were those to copy doublewords between the CPU and FPU convert single- and double-precision floating-point numbers into doubleword integers and vice versa.
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2,195
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MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS.: A-1 MIPS IV was designed to mainly improve floating-point performance. To improve access to operands, an indexed addressing mode for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints .
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2,196
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MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing the total to eight. FP comparison and branch instructions were redefined so they could specify which condition bit was written or read ; and the delay slot in between an FP branch that read the condition bit written to by a prior FP comparison was removed. Support for partial predication was added in the form of conditional move instructions for both GPRs and FPRs; and an implementation could choose between having precise or imprecise exceptions for IEEE 754 traps.
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2,197
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MIPS IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root. The FP fused-multiply add or subtract instructions perform either one or two roundings , to exceed or meet IEEE 754 accuracy requirements . The FP reciprocal and reciprocal square-root instructions do not comply with IEEE 754 accuracy requirements, and produce results that differ from the required accuracy by one or two units of last place . These instructions serve applications where instruction latency is more important than accuracy.
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2,198
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MIPS V added a new data type, the Paired Single , which consisted of two single-precision floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data.: 426–429 It was the first instruction set to exploit floating-point SIMD with existing resources.
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2,199
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The first release of MIPS32, based on MIPS II, added conditional moves, prefetch instructions, and other features from the R4000 and R5000 families of 64-bit processors. The first release of MIPS64 adds a MIPS32 mode to run 32-bit code. The MUL and MADD instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were cache control instructions. For the purpose of cache control, both SYNC and SYNCI instructions were prepared.
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2,200
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MIPS32/MIPS64 Release 6 in 2014 added the following:
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