Number
int64 1
7.61k
| Text
stringlengths 2
3.11k
|
|---|---|
4,801
|
Among the ultimate implementations of microcode in microprocessors is the Motorola 68000. This offered a highly orthogonal instruction set with a wide variety of addressing modes, all implemented in microcode. This did not come without cost, according to early articles, about 20% of the chip's surface area is the microcode system. and later estimates suggest approximately 23,000 of the systems 68,000 gates were part of the microcode system.
|
4,802
|
While companies continued to compete on the complexity of their instruction sets, and the use of microcode to implement these was unquestioned, in the mid-1970s an internal project in IBM was raising serious questions about the entire concept. As part of a project to develop a high-performance all-digital telephone switch, a team led by John Cocke began examining huge volumes of performance data from their customer's 360 programs. This led them to notice a curious pattern: when the ISA presented multiple versions of an instruction, the compiler almost always used the simplest one, instead of the one most directly representing the code. They learned that this was because those instructions were always implemented in hardware, and thus run the fastest. Using the other instruction might offer higher performance on some machines, but there was no way to know what machine they were running on, that was the whole reason for using microcode in the first place, to hide these distinctions.
|
4,803
|
The team came to a radical conclusion: "Imposing microcode between a computer and its users imposes an expensive overhead in performing the most frequently executed instructions."
|
4,804
|
The result of this discovery was what is today known as the RISC concept. The complex microcode engine and its associated ROM is reduced or eliminated completely, and those circuits instead dedicated to things like additional registers or a wider ALU, which increases the performance of every program. When complex sequences of instructions are needed, this is left to the compiler, which is the entire purpose of using a compiler in the first place. The basic concept was soon picked up by university researchers in California, where simulations suggested such designs would trivially outperform even the fastest conventional designs. It was one such project, at the University of California, Berkeley, that introduced the term RISC.
|
4,805
|
The industry responded to the concept of RISC with both confusion and hostility, including a famous dismissive article by the VAX team at Digital. A major point of contention was that implementing the instructions outside of the processor meant it would spend much more time reading those instructions from memory, thereby slowing overall performance no matter how fast the CPU itself ran. Proponents pointed out that simulations clearly showed the number of instructions was not much greater, especially when considering compiled code.
|
4,806
|
The debate raged until the first commercial RISC designs emerged in the second half of the 1980s, which easily outperformed the most complex designs from other companies. By the late 1980s it was over; even DEC was abandoning microcode for their DEC Alpha designs, and CISC processors switched to using hardwired circuitry, rather than microcode, to perform many functions. For example, the Intel 80486 uses hardwired circuitry to fetch and decode instructions, using microcode only to execute instructions; register-register move and arithmetic instructions required only one microinstruction, allowing them to be completed in one clock cycle. The Pentium Pro's fetch and decode hardware fetches instructions and decodes them into series of micro-operations that are passed on to the execution unit, which schedules and executes the micro-operations, possibly doing so out-of-order. Complex instructions are implemented by microcode that consists of pre-defined sequences of micro-operations.
|
4,807
|
Some processor designs use machine code that runs in a special mode, with special instructions, available only in that mode, that have access to processor-dependent hardware, to implement some low-level features of the instruction set. The DEC Alpha, a pure RISC design, used PALcode to implement features such as translation lookaside buffer miss handling and interrupt handling, as well as providing, for Alpha-based systems running OpenVMS, instructions requiring interlocked memory acces that are similar to instructions provided by the VAX architecture. CMOS IBM System/390 CPUs, starting with the G4 processor, and z/Architecture CPUs use millicode to implement some instructions.
|
4,808
|
Each microinstruction in a microprogram provides the bits that control the functional elements that internally compose a CPU. The advantage over a hard-wired CPU is that internal CPU control becomes a specialized form of a computer program. Microcode thus transforms a complex electronic design challenge into a less complex programming challenge. To take advantage of this, a CPU is divided into several parts:
|
4,809
|
There may also be a memory address register and a memory data register, used to access the main computer storage. Together, these elements form an "execution unit". Most modern CPUs have several execution units. Even simple computers usually have one unit to read and write memory, and another to execute user code. These elements could often be brought together as a single chip. This chip comes in a fixed width that would form a "slice" through the execution unit. These are known as "bit slice" chips. The AMD Am2900 family is one of the best known examples of bit slice elements. The parts of the execution units and the whole execution units are interconnected by a bundle of wires called a bus.
|
4,810
|
Programmers develop microprograms, using basic software tools. A microassembler allows a programmer to define the table of bits symbolically. Because of its close relationship to the underlying architecture, "microcode has several properties that make it difficult to generate using a compiler." A simulator program is intended to execute the bits in the same way as the electronics, and allows much more freedom to debug the microprogram. After the microprogram is finalized, and extensively tested, it is sometimes used as the input to a computer program that constructs logic to produce the same data. This program is similar to those used to optimize a programmable logic array. Even without fully optimal logic, heuristically optimized logic can vastly reduce the number of transistors from the number needed for a read-only memory control store. This reduces the cost to produce, and the electricity used by, a CPU.
|
4,811
|
Microcode can be characterized as horizontal or vertical, referring primarily to whether each microinstruction controls CPU elements with little or no decoding or requires extensive decoding by combinatorial logic before doing so . Consequently, each horizontal microinstruction is wider and occupies more storage space than a vertical microinstruction.
|
4,812
|
"Horizontal microcode has several discrete micro-operations that are combined in a single microinstruction for simultaneous operation." Horizontal microcode is typically contained in a fairly wide control store; it is not uncommon for each word to be 108 bits or more. On each tick of a sequencer clock a microcode word is read, decoded, and used to control the functional elements that make up the CPU.
|
4,813
|
In a typical implementation a horizontal microprogram word comprises fairly tightly defined groups of bits. For example, one simple arrangement might be:
|
4,814
|
For this type of micromachine to implement a JUMP instruction with the address following the opcode, the microcode might require two clock ticks. The engineer designing it would write microassembler source code looking something like this:
|
4,815
|
For each tick it is common to find that only some portions of the CPU are used, with the remaining groups of bits in the microinstruction being no-ops. With careful design of hardware and microcode, this property can be exploited to parallelise operations that use different areas of the CPU; for example, in the case above, the ALU is not required during the first tick, so it could potentially be used to complete an earlier arithmetic instruction.
|
4,816
|
In vertical microcode, each microinstruction is significantly encoded, that is, the bit fields generally pass through intermediate combinatory logic that, in turn, generates the control and sequencing signals for internal CPU elements . This is in contrast with horizontal microcode, in which the bit fields either directly produce the control and sequencing signals or are only minimally encoded. Consequently, vertical microcode requires smaller instruction lengths and less storage, but requires more time to decode, resulting in a slower CPU clock.
|
4,817
|
Some vertical microcode is just the assembly language of a simple conventional computer that is emulating a more complex computer. Some processors, such as DEC Alpha processors and the CMOS microprocessors on later IBM mainframes System/390 and z/Architecture, use machine code, running in a special mode that gives it access to special instructions, special registers, and other hardware resources unavailable to regular machine code, to implement some instructions and other functions, such as page table walks on Alpha processors. This is called PALcode on Alpha processors and millicode on IBM mainframe processors.
|
4,818
|
Another form of vertical microcode has two fields:
|
4,819
|
The field select selects which part of the CPU will be controlled by this word of the control store. The field value controls that part of the CPU. With this type of microcode, a designer explicitly chooses to make a slower CPU to save money by reducing the unused bits in the control store; however, the reduced complexity may increase the CPU's clock frequency, which lessens the effect of an increased number of cycles per instruction.
|
4,820
|
As transistors grew cheaper, horizontal microcode came to dominate the design of CPUs using microcode, with vertical microcode being used less often.
|
4,821
|
When both vertical and horizontal microcode are used, the horizontal microcode may be referred to as nanocode or picocode.
|
4,822
|
A few computers were built using writable microcode. In this design, rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a writable control store or WCS. Such a computer is sometimes called a writable instruction set computer .
|
4,823
|
Many experimental prototype computers use writable control stores; there are also commercial machines that use writable microcode, such as the Burroughs Small Systems, early Xerox workstations, the DEC VAX 8800 family, the Symbolics L- and G-machines, a number of IBM System/360 and System/370 implementations, some DEC PDP-10 machines, and the Data General Eclipse MV/8000.
|
4,824
|
The IBM System/370 includes a facility called Initial-Microprogram Load that can be invoked from the console, as part of power-on reset or from another processor in a tightly coupled multiprocessor complex.
|
4,825
|
Some commercial machines, for example IBM 360/85, have both a read-only storage and a writable control store for microcode.
|
4,826
|
WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs can provide. User-programmable WCS allows the user to optimize the machine for specific purposes.
|
4,827
|
Starting with the Pentium Pro in 1995, several x86 CPUs have writable Intel Microcode. This, for example, has allowed bugs in the Intel Core 2 and Intel Xeon microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced. A second prominent example is the set of microcode patches that Intel offered for some of their processor architectures of up to 10 years in age, in a bid to counter the security vulnerabilities discovered in their designs – Spectre and Meltdown – which went public at the start of 2018. A microcode update can be installed by Linux, FreeBSD, Microsoft Windows, or the motherboard BIOS.
|
4,828
|
Some machines offer user-programmable writable control stores as an option, including the HP 2100, DEC PDP-11/60, TI-990/12, and Varian Data Machines V-70 series minicomputers.
|
4,829
|
The design trend toward heavily microcoded processors with complex instructions began in the early 1960s and continued until roughly the mid-1980s. At that point the RISC design philosophy started becoming more prominent.
|
4,830
|
A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction. Some CISC processors include instructions that can take a very long time to execute. Such variations interfere with both interrupt latency and, what is far more important in modern systems, pipelining.
|
4,831
|
When designing a new processor, a hardwired control RISC has the following advantages over microcoded CISC:
|
4,832
|
There are counterpoints as well:
|
4,833
|
Many RISC and VLIW processors are designed to execute every instruction in a single cycle. This is very similar to the way CPUs with microcode execute one microinstruction per cycle. VLIW processors have instructions that behave similarly to very wide horizontal microcode, although typically without such fine-grained control over the hardware as provided by microcode. RISC instructions are sometimes similar to the narrow vertical microcode.
|
4,834
|
Microcode has been popular in application-specific processors such as network processors, digital signal processors, channel controllers, disk controllers, network interface controllers, flash memory controllers, graphics processing units, and in other hardware.
|
4,835
|
Modern CISC implementations, such as the x86 family, decode instructions into dynamically buffered micro-operations with an instruction encoding similar to RISC or traditional microcode. A hardwired instruction decode unit directly emits microoperations for common x86 instructions, but falls back to a more traditional microcode ROM containing microoperations for more complex or rarely used instructions.
|
4,836
|
For example, an x86 might look up microoperations from microcode to handle complex multistep operations such as loop or string instructions, floating-point unit transcendental functions or unusual values such as denormal numbers, and special-purpose instructions such as CPUID.
|
4,837
|
Usually the addresses are generated by some combination of a counter, a field from a microinstruction, and some subset of the instruction register. A counter is used for the typical case, that the next microinstruction is the one to execute. A field from the microinstruction is used for jumps, or other logic.
|
4,838
|
Since CPUs implement an instruction set, it's very useful to be able to decode the instruction's bits directly into the sequencer, to select a set of microinstructions to perform a CPU's instructions.
|
4,839
|
Most modern CISC processors use a combination of pipelined logic to process lower complexity opcodes which can be completed in one clock cycle, and microcode to implement ones that take multiple clock cycles to complete.
|
4,840
|
One of the first integrated microcoded processors was the IBM PALM Processor, which emulated all of the processor's instruction in microcode and was used on the IBM 5100, one of the first personal computers.
|
4,841
|
Recent examples of similar open-sourced microsequencer-based processors are the MicroCore Labs MCL86, MCL51 , and MCL65 cores which emulate the Intel 8086/8088, 8051 and MOS 6502 instruction sets entirely in microcode.
|
4,842
|
The Digital Scientific Corp. Meta 4 Series 16 computer system was a user-microprogrammable system first available in 1970. Branches in the microcode sequence occur in
one of three ways.
|
4,843
|
One more sequencing option allowed on a branch instruction is the execute option. When specified, the single instruction at the branch address is executed, but then execution continues after the original branch instruction. The IX option can be used with the XQ option.
|
4,844
|
The IBM System/360 was a series of compatible computers introduced in 1964, many of which were microprogrammed. The System/360 Model 40 is a good example of a microprogrammed machine with complex microsequencing.
|
4,845
|
The microstore consists of 4,096 56-bit microinstructions that operate in
a horizontal microprogramming style. The store is addressed by the 12-bit
read-only address register . Unlike most registers in the
S/360 architecture, bits in the ROAR are numbered from bit 0 on the right
to bit 11 on the left.
|
4,846
|
The model 40 performs no sequential execution of microinstructions and
therefore the microsequencer doesn't really branch in the conventional
sense. Instead, each microinstruction specifies the address of the next one
to be executed. Four fields in the microinstruction contribute to the new
address.
|
4,847
|
There are essentially three combinations or formats of these fields.
|
4,848
|
When the CB field contains 15, a functional branch occurs. The bits of
the new microstore address in the ROAR are determined as follows.
|
4,849
|
The CC field can specify various tests of the state of the machine. It can
also specify a constant 0 or 1 for an unconditional bit.
|
4,850
|
This format alters the flow of control to 1 of 16 instruction pairs
within the low 32 words of a 64-word block of microstore . The CC field then determines which instruction of the pair
receives control.
|
4,851
|
When the CD field is 0, 1, or 3, flow of control is directed to an
instruction within the current 64-word block. The bits of the new microstore
address are determined as follows.
|
4,852
|
The CA field selects 1 of 16 4-word groups within the current 64-word block.
The CB and CC fields then determine which instruction of the 4 receives
control.
|
4,853
|
When the CD field is 2, flow of control is directed in a nonobvious manner. The
bits of the new microstore address are determined as follows:
|
4,854
|
The next instruction is in the same 1K-word region as the current
instruction, because bits 11–10 remain the same. The CA field determines
the 64-word block within the region. The instruction is in the same 4-word
group within the new block as the current instruction is within the current
block, because bits 5–2 remain the same.
The CB and CC fields then determine which instruction of the 4 receives
control.
|
4,855
|
This description has been simplified. It ignores the following features.
|
4,856
|
Almost all computers, whether load/store architecture or not, load items of data from a larger memory into registers where they are used for arithmetic operations, bitwise operations, and other operations, and are manipulated or tested by machine instructions. Manipulated items are then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.
|
4,857
|
Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.
|
4,858
|
When a computer program accesses the same data repeatedly, this is called locality of reference. Holding frequently used values in registers can be critical to a program's performance. Register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.
|
4,859
|
Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register", "64-bit register", or even more. In some instruction sets, the registers can operate in various modes, breaking down their storage memory into smaller parts to which multiple data can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into a larger register. Processors that have the ability to execute single instructions on multiple data are called vector processors.
|
4,860
|
A processor often contains several kinds of registers, which can be classified according to the types of values they can store or the instructions that operate on them:
|
4,861
|
Hardware registers are similar, but occur outside CPUs.
|
4,862
|
In some architectures , the first or last register in the integer register file is a pseudo-register in that it is hardwired to always return zero when read , and it cannot be overwritten. In Alpha, this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.
|
4,863
|
The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors, the stack pointer is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.
|
4,864
|
Although all of the below-listed architectures are different, almost all are in a basic arrangement known as the von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.
|
4,865
|
The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.
|
4,866
|
The program counter , commonly called the instruction pointer in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register , the instruction counter, or just part of the instruction sequencer, is a processor register that indicates where a computer is in its program sequence.
|
4,867
|
Usually, the PC is incremented after fetching an instruction, and holds the memory address of the next instruction that would be executed.
|
4,868
|
Processors usually fetch instructions sequentially from memory, but control transfer instructions change the sequence by placing a new value in the PC. These include branches , subroutine calls, and returns. A transfer that is conditional on the truth of some assertion lets the computer follow a different sequence under different conditions.
|
4,869
|
A branch provides that the next instruction is fetched from elsewhere in memory. A subroutine call not only branches but saves the preceding contents of the PC somewhere. A return retrieves the saved contents of the PC and places it back in the PC, resuming sequential execution with the instruction following the subroutine call.
|
4,870
|
In a simple central processing unit , the PC is a digital counter that may be one of several hardware registers. The instruction cycle begins with a fetch, in which the CPU places the value of the PC on the address bus to send it to the memory. The memory responds by sending the contents of that memory location on the data bus. Following the fetch, the CPU proceeds to execution, taking some action based on the memory contents that it obtained. At some point in this cycle, the PC will be modified so that the next instruction executed is a different one .
|
4,871
|
Like other processor registers, the PC may be a bank of binary latches, each one representing one bit of the value of the PC. The number of bits relates to the processor architecture. For instance, a “32-bit” CPU may use 32 bits to be able to address 232 units of memory. On some processors, the width of program counter instead depends on the addressable memory; for example, some AVR microcontrollers have a PC which wraps around after 12 bits.
|
4,872
|
If the PC is a binary counter, it may increment when a pulse is applied to its COUNT UP input, or the CPU may compute some other value and load it into the PC by a pulse to its LOAD input.
|
4,873
|
To identify the current instruction, the PC may be combined with other registers that identify a segment or page. This approach permits a PC with fewer bits by assuming that most memory units of interest are within the current vicinity.
|
4,874
|
Use of a PC that normally increments assumes that what a computer does is execute a usually linear sequence of instructions. Such a PC is central to the von Neumann architecture. Thus programmers write a sequential control flow even for algorithms that do not have to be sequential. The resulting “von Neumann bottleneck” led to research into parallel computing, including non-von Neumann or dataflow models that did not use a PC; for example, rather than specifying sequential steps, the high-level programmer might specify desired function and the low-level programmer might specify this using combinatory logic.
|
4,875
|
This research also led to ways to making conventional, PC-based, CPUs run faster, including:
|
4,876
|
Modern high-level programming languages still follow the sequential-execution model and, indeed, a common way of identifying programming errors is with a “procedure execution” in which the programmer's finger identifies the point of execution as a PC would. The high-level language is essentially the machine language of a virtual machine, too complex to be built as hardware but instead emulated or interpreted by software.
|
4,877
|
However, new programming models transcend sequential-execution programming:
|
4,878
|
The design process involves choosing an instruction set and a certain execution paradigm and results in a microarchitecture, which might be described in e.g. VHDL or Verilog. For microprocessor design, this description is then manufactured employing some of the various semiconductor device fabrication processes, resulting in a die which is bonded onto a chip carrier. This chip carrier is then soldered onto, or inserted into a socket on, a printed circuit board .
|
4,879
|
The mode of operation of any processor is the execution of lists of instructions. Instructions typically include those to compute or manipulate data values using registers, change or retrieve values in read/write memory, perform relational tests between data values and to control program flow.
|
4,880
|
Processor designs are often tested and validated on one or several FPGAs before sending the design of the processor to a foundry for semiconductor fabrication.
|
4,881
|
CPU design is divided into multiple components. Information is transferred through datapaths . These datapaths are controlled through logic by control units. Memory components include register files and caches to retain information, or certain actions. Clock circuitry maintains internal rhythms and timing through clock drivers, PLLs, and clock distribution networks. Pad transceiver circuitry with allows signals to be received and sent and a logic gate cell library which is used to implement the logic.
|
4,882
|
CPUs designed for high-performance markets might require custom ) designs for each of these items to achieve frequency, power-dissipation, and chip-area goals whereas CPUs designed for lower performance markets might lessen the implementation burden by acquiring some of these items by purchasing them as intellectual property. Control logic implementation techniques can be used to implement datapaths, register files, and clocks. Common logic styles used in CPU design include unstructured random logic, finite-state machines, microprogramming , and Programmable logic arrays .
|
4,883
|
Device types used to implement the logic include:
|
4,884
|
A CPU design project generally has these major tasks:
|
4,885
|
Re-designing a CPU core to a smaller die area helps to shrink everything , resulting in the same number of transistors on a smaller die. It improves performance , reduces power and reduces cost . Releasing a CPU on the same size die, but with a smaller CPU core, keeps the cost about the same but allows higher levels of integration within one very-large-scale integration chip , improving performance and reducing overall system cost.
|
4,886
|
As with most complex electronic designs, the logic verification effort now dominates the project schedule of a CPU.
|
4,887
|
Key CPU architectural innovations include index register, cache, virtual memory, instruction pipelining, superscalar, CISC, RISC, virtual machine, emulators, microprogram, and stack.
|
4,888
|
A variety of new CPU design ideas have been proposed,
including reconfigurable logic, clockless CPUs, computational RAM, and optical computing.
|
4,889
|
Benchmarking is a way of testing CPU speed. Examples include SPECint and SPECfp, developed by Standard Performance Evaluation Corporation, and ConsumerMark developed by the Embedded Microprocessor Benchmark Consortium EEMBC.
|
4,890
|
Some of the commonly used metrics include:
|
4,891
|
There may be tradeoffs in optimizing some of these metrics. In particular, many design techniques that make a CPU run faster make the "performance per watt", "performance per dollar", and "deterministic response" much worse, and vice versa.
|
4,892
|
There are several different markets in which CPUs are used. Since each of these markets differ in their requirements for CPUs, the devices designed for one market are in most cases inappropriate for the other markets.
|
4,893
|
As of 2010, in the general-purpose computing market, that is, desktop, laptop, and server computers commonly used in businesses and homes, the Intel IA-32 and the 64-bit version x86-64 architecture dominate the market, with its rivals PowerPC and SPARC maintaining much smaller customer bases. Yearly, hundreds of millions of IA-32 architecture CPUs are used by this market. A growing percentage of these processors are for mobile implementations such as netbooks and laptops.
|
4,894
|
Since these devices are used to run countless different types of programs, these CPU designs are not specifically targeted at one type of application or one function. The demands of being able to run a wide range of programs efficiently has made these CPU designs among the more advanced technically, along with some disadvantages of being relatively costly, and having high power consumption.
|
4,895
|
In 1984, most high-performance CPUs required four to five years to develop.
|
4,896
|
Scientific computing is a much smaller niche market . It is used in government research labs and universities. Before 1990, CPU design was often done for this market, but mass market CPUs organized into large clusters have proven to be more affordable. The main remaining area of active hardware design and research for scientific computing is for high-speed data transmission systems to connect mass market CPUs.
|
4,897
|
As measured by units shipped, most CPUs are embedded in other machinery, such as telephones, clocks, appliances, vehicles, and infrastructure. Embedded processors sell in the volume of many billions of units per year, however, mostly at much lower price points than that of the general purpose processors.
|
4,898
|
These single-function devices differ from the more familiar general-purpose CPUs in several ways:
|
4,899
|
The embedded CPU family with the largest number of total units shipped is the 8051, averaging nearly a billion units per year. The 8051 is widely used because it is very inexpensive. The design time is now roughly zero, because it is widely available as commercial intellectual property. It is now often embedded as a small part of a larger system on a chip. The silicon cost of an 8051 is now as low as US$0.001, because some implementations use as few as 2,200 logic gates and take 0.4730 square millimeters of silicon.
|
4,900
|
As of 2009, more CPUs are produced using the ARM architecture family instruction sets than any other 32-bit instruction set.
The ARM architecture and the first ARM chip were designed in about one and a half years and 5 human years of work time.
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.