code string | repo_name string | path string | language string | license string | size int64 |
|---|---|---|---|---|---|
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package dao;
import java.util.List;
import myClass.Post;
import pojo.User;
/**
*
* @author 4pril
*/
public class PostDAO extends ObjectDAO{
public static List<Post> getListPost(User u_id){
... | 11hca1-java-web | trunk/src/java/dao/PostDAO.java | Java | gpl3 | 491 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package system;
/**
*
* @author 4pril
*/
public class System {
private static String login_url = "login";
private static String home_url = "index";
/**
* @return the login_url
*... | 11hca1-java-web | trunk/src/java/system/System.java | Java | gpl3 | 851 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package myClass;
import dao.ObjectTypeDAO;
/**
*
* @author 4pril
*/
public class Post extends pojo.Object{
public Post(){
this.setObjType( ObjectTypeDAO.getObjectTypeByName("post"));
... | 11hca1-java-web | trunk/src/java/myClass/Post.java | Java | gpl3 | 337 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import dao.MyQuery;
import dao.UserDAO;
import java.io.IOException;
import java.io.PrintWriter;
import java.net.URLDecoder;
import java.util.List;
import java.util.logging.Level;
import ... | 11hca1-java-web | trunk/src/java/controller/ajax_register.java | Java | gpl3 | 4,472 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import dao.MyQuery;
import dao.UserDAO;
import java.io.IOException;
import java.io.PrintWriter;
import java.util.List;
import javax.servlet.ServletException;
import javax.servlet.annotati... | 11hca1-java-web | trunk/src/java/controller/test.java | Java | gpl3 | 3,768 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import dao.MyQuery;
import dao.UserDAO;
import java.io.BufferedReader;
import java.io.IOException;
import java.io.OutputStreamWriter;
import java.io.PrintWriter;
import java.lang.reflect.... | 11hca1-java-web | trunk/src/java/controller/ajax_login.java | Java | gpl3 | 5,364 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import system.System;
import java.io.IOException;
import java.io.PrintWriter;
import javax.servlet.RequestDispatcher;
import javax.servlet.ServletException;
import javax.servlet.annotation... | 11hca1-java-web | trunk/src/java/controller/index.java | Java | gpl3 | 3,547 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import system.System;
import java.io.IOException;
import java.io.PrintWriter;
import javax.servlet.RequestDispatcher;
import javax.servlet.ServletException;
import javax.servlet.annotation... | 11hca1-java-web | trunk/src/java/controller/login.java | Java | gpl3 | 3,375 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package util;
import org.hibernate.cfg.AnnotationConfiguration;
import org.hibernate.SessionFactory;
/**
* Hibernate Utility class with a convenient method to get Session Factory
* object.
*
* @author ... | 11hca1-java-web | trunk/src/java/util/HibernateUtil.java | Java | gpl3 | 986 |
package controller;
import java.awt.Graphics2D;
import java.awt.image.BufferedImage;
import java.io.BufferedOutputStream;
import java.io.File;
import java.io.FileOutputStream;
import java.io.IOException;
import java.text.SimpleDateFormat;
import java.util.Calendar;
import java.util.HashMap;
import java.util... | 09130037-cnpm-pproject | DTCNPM/src/controller/FoodController.java | Java | asf20 | 4,876 |
<%@ page language="java" contentType="text/html; charset=ISO-8859-1"
pageEncoding="ISO-8859-1"%>
<%@ taglib uri="http://java.sun.com/jsp/jstl/core" prefix="c"%>
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<head>
<meta http-equiv="Content-Type" con... | 09130037-cnpm-pproject | DTCNPM/WebContent/WEB-INF/view/Upload.jsp | Java Server Pages | asf20 | 1,047 |
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="utf-8">
<title>Sign in · Twitter Bootstrap</title>
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<meta name="description" content="">
<meta name="author" content="">
<!-- Le styles -->
<link href="asset... | 069ka4-cms | trunk/signin.html | HTML | mit | 3,674 |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
<head>
<title>Ambition CMS</title>
<meta http-equiv="content-type" content="application/xhtml+xml; charset=UTF-8" />
<meta name="... | 069ka4-cms | trunk/main.html | HTML | mit | 11,023 |
.com { color: #93a1a1; }
.lit { color: #195f91; }
.pun, .opn, .clo { color: #93a1a1; }
.fun { color: #dc322f; }
.str, .atv { color: #D14; }
.kwd, .prettyprint .tag { color: #1e347b; }
.typ, .atn, .dec, .var { color: teal; }
.pln { color: #48484c; }
.prettyprint {
padding: 8px;
background-color: #f7f7f9;
border: ... | 069ka4-cms | trunk/assets/js/google-code-prettify/prettify.css | CSS | mit | 817 |
/*
Holder - 1.6 - client side image placeholders
(c) 2012 Ivan Malopinsky / http://imsky.co
Provided under the Apache 2.0 License: http://www.apache.org/licenses/LICENSE-2.0
Commercial use requires attribution.
*/
var Holder = Holder || {};
(function (app, win) {
var preempted = false,
fallback = false,
canvas = d... | 069ka4-cms | trunk/assets/js/holder/holder.js | JavaScript | mit | 10,517 |
// NOTICE!! DO NOT USE ANY OF THIS JAVASCRIPT
// IT'S ALL JUST JUNK FOR OUR DOCS!
// ++++++++++++++++++++++++++++++++++++++++++
!function ($) {
$(function(){
var $window = $(window)
// Disable certain links in docs
$('section [href^=#]').click(function (e) {
e.preventDefault()
})
// sid... | 069ka4-cms | trunk/assets/js/application.js | JavaScript | mit | 3,954 |
/* Add additional stylesheets below
-------------------------------------------------- */
/*
Bootstrap's documentation styles
Special styles for presenting Bootstrap's documentation and examples
*/
/* Body and structure
-------------------------------------------------- */
body {
position: relative;
padding... | 069ka4-cms | trunk/assets/css/docs.css | CSS | mit | 22,431 |
/* theme screen stylesheets */
/* import stylesheets and hide from ie/mac \*/
@import url("reset.css");
@import url("FreshPick.css");
/* end import/hide */ | 069ka4-cms | trunk/css/screen.css | CSS | mit | 161 |
/* ----------------------------------------------
Template Name : FreshPick
Template Code : S-0029
Version : 1.0
Author : Erwin Aligam
Author URI : http://www.styleshout.com/
Last Date Modified : April 24, 2009
------------------------------------------------ */
/* -----------------------------... | 069ka4-cms | trunk/css/FreshPick.css | CSS | mit | 14,763 |
/* http://meyerweb.com/eric/thoughts/2007/05/01/reset-reloaded/ */
html, body, div, span, applet, object, iframe, h1, h2, h3, h4, h5, h6, p, blockquote, pre,
a, abbr, acronym, address, big, cite, code, del, dfn, em, font, img, ins, kbd, q, s, samp,
small, strike, strong, sub, sup, tt, var,dl, dt, dd, ol, ul, li, field... | 069ka4-cms | trunk/css/reset.css | CSS | mit | 996 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class ContributorActivity extends Activity {
public void onCr... | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/ContributorActivity.java | Java | gpl3 | 2,356 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class AndDevActivity extends Activity {
@Override
public vo... | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/AndDevActivity.java | Java | gpl3 | 3,433 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class GroupActivity extends Activity {
public void onCreate... | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/GroupActivity.java | Java | gpl3 | 2,468 |
package info.tAIR.tAIRApp;
import android.app.TabActivity;
import android.content.Intent;
import android.content.res.Resources;
import android.os.Bundle;
import android.widget.TabHost;
public class tAIRTabWidget extends TabActivity {
/** Called when the activity is first created. */
@Override
public void ... | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/tAIRTabWidget.java | Java | gpl3 | 2,332 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
import android.widget.Toast;
public class CodeActivity extends Activity ... | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/CodeActivity.java | Java | gpl3 | 2,767 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class AIActivity extends Activity {
public void onCreat... | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/AIActivity.java | Java | gpl3 | 3,276 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class tAIRActivity extends Activity {
@Override
public void... | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/tAIRActivity.java | Java | gpl3 | 3,762 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity DECODER_TB is -- entity declaration
end DECODER_TB;
architecture TB of DECODER_TB is
signal T_I: std_logic_vector(1 downto 0):="00";
signal T_O: std_logic_vector(3 downto 0);
-- declare the component
component DECODER
port( I: in std_... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_demultiplexer.vhd | VHDL | lgpl | 1,782 |
-- some modifications made to the original version, which was provided by Alberto.
-- configuration at the bottom changed.
-- Rajesh
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal ... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_shiftreg-enable.vhd | VHDL | lgpl | 5,421 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity REG is
port(
D : in std_logic_vector(7 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(7 downto 0));
end entity REG;
architecture BEH_RE... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/REG.vhd | VHDL | lgpl | 557 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
clock: in std_logic;
clear: in std_logic;
Qc: out std_logic_vector(1 downto 0)
);
end counter;
architecture beh_counter of counter is
signal Pre_Q: std_logic_vector(1 downto 0);
begin
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/counter.vhd | VHDL | lgpl | 552 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY toplevel_shiftreg IS
PORT (
CLK : IN STD_LOGIC;
RSTx : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END toplevel_shiftreg;
ARCHITE... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/toplevel_shiftreg.vhd | VHDL | lgpl | 1,194 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG_ENABLE is
Port (
CLOCK : In std_logic;
RESET : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (31 ... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/SHIFTREG_enable.vhd | VHDL | lgpl | 1,531 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity MUX is
port (
Q0 : in std_logic_vector(7 downto 0);
Q1 : in std_logic_vector(7 downto 0);
enable: in std_logic;
Qmux : out std_logic_vector(7 downto 0)
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/MUX.vhd | VHDL | lgpl | 611 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal RESET : std_logic;
signal QK : std_logic_vector (7 downto 0);
signal Q : std_logic... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_shiftreg-gated2.vhd | VHDL | lgpl | 3,261 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter_TB is -- entity declaration
end counter_TB;
-----------------------------------------------------------------------
architecture TB of counter_TB is
component counter
port( clock: in std_... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_counter.vhd | VHDL | lgpl | 2,060 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut_enable.saif
run 41000 > run.out
quit | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/cmd_saif_enable.inc | PHP | lgpl | 108 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG_GATED is
Port ( CLK : In std_logic;
RESET : In std_logic;
QK : In std_logic_vector (7 downto 0);
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/SHIFTREG_GATED.vhd | VHDL | lgpl | 1,568 |
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;
architecture BEH_DECODER of DECODER is
begin
process (I)
begin
case I is
when "00" => O <= "1000";
when "01" => O <= "0100";
when "10" ... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/Decoder.vhd | VHDL | lgpl | 446 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
ENABLE : In std_logic;
QK : In std_lo... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/SHIFTREG.vhd | VHDL | lgpl | 962 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut_gated.saif
run 41000 > run.out
quit | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/cmd_saif_gated.inc | PHP | lgpl | 107 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal RESET : std_logic;
signal ENABLE : std_logic;
signal QK : std_logic_vector (7 downto 0... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_shiftreg.vhd | VHDL | lgpl | 3,328 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut.saif
run 41000 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/cmd_saif.inc | PHP | lgpl | 102 |
\documentclass[11pt,a4paper]{article}
\usepackage{url,,}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{multirow}
\usepackage{listings}
\usepackage{fullpage}
\usepackage{fancyhdr,a4w... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/report/dt07_lab2.tex | TeX | lgpl | 16,741 |
library IEEE;
use IEEE.std_logic_1164.all, IEEE.numeric_std.all;
entity NBitAdder is
port (A, B: in std_logic_vector(23 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector(23 downto 0);
Cout: out std_logic);
end entity NBitAdder;
architecture unsgned of NBitAdder is
sign... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/NBitAdder.vhdl | VHDL | lgpl | 665 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AdderNetlist is
port( A1 : in std_logic_vector(23 downto 0);
A2 : in std_logic_vector(23 downto 0);
Clock, Reset: in std_logic;
Z : out std_logic_vector( 23 downto 0));
end entity AdderNetlist;
architecture NetlistBehavior of Adder... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/addernetlist.vhdl | VHDL | lgpl | 1,057 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity reg is
port (D : in std_logic_vector(23 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(23 downto 0));
end entity reg;
architecture behavioural of reg is
begin
p0: process (Clock, Reset) is
begin
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/reg.vhdl | VHDL | lgpl | 499 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity TestNBitAdder is
end entity TestNBitAdder;
architecture TestBench_4 of TestNBitAdder is
signal A, B, Sumint : NATURAL;
signal Aslv, Bslv, Sum: std_logic_vector (23 downto 0);
signal Cin, Cout: std_logic;
signal error: BOOLEAN := FA... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/tbnadder.vhdl | VHDL | lgpl | 907 |
\documentclass[11pt,a4paper]{article}
\usepackage{url,,}
\usepackage{graphicx}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{multirow}
\usepackage{listings}
\usepackage{fullpage}
\usepackage{fancyhdr,a4wide}
\usepackage{makei... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/Report/dt07_lab1.tex | TeX | lgpl | 13,028 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal D : std_logic_vector (52 downto 0);
signal RESET : std_logic;
signal X : std_logi... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/tb_divr4_rec.vhd | VHDL | lgpl | 3,368 |
-- VHDL Model Created from SGE Symbol qds_table.sym -- Apr 21 16:34:54 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_TABLE is
Port ( D : In std_logic_vector (2 downto 0);
Y : In std_logic_vector (6 do... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/qds_table.vhd | VHDL | lgpl | 6,548 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_dualreg_ld is
GENERIC(n : integer);
Port ( AS : In std_logic_vector (n downto 0);
AC : In std_logic_vector (n downto 0);
RESET : In std_logic;
CLOCK : In std_logic;
LOAD :... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/gl_dualreg_ld.vhd | VHDL | lgpl | 978 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity divr4_rec is
Port ( CLOCK : In std_logic;
D : In std_logic_vector (52 downto 0);
RESET : In std_logic;
X : In std_logic_vector (... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/divr4_rec.vhd | VHDL | lgpl | 7,654 |
-- VHDL Model Created from SGE Symbol control.sym -- May 5 18:26:48 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity CONTROL is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
CL1 : Out std_lo... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/control.vhd | VHDL | lgpl | 1,523 |
-- VHDL Model Created from SGE Schematic qdsel.sch -- Apr 21 16:58:17 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDSEL is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto ... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/qdsel.vhd | VHDL | lgpl | 1,846 |
open run.out
logtime -e run.out
monitor -n Smon active *E/X'sig
monitor -n Smon active *E/D'sig
--monitor -n Smon active *E/Qj'sig
-- monitor -n Smon active *E/UUT/WS'sig
-- monitor -n Smon active *E/UUT/WC'sig
list > run.out
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/cmd.inc | C++ | lgpl | 266 |
-- VHDL Model Created from SGE Symbol mult.sym -- May 27 12:32:12 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MULT is
Port ( A : In std_logic_vector (54 downto 0);
M1 : In std_logic;
M2... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/mult.vhd | VHDL | lgpl | 1,093 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_divr4_rec is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_divr4_rec;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity CONTROL_DW01_inc_0 is
port( A : in std_logic_vector (4 downto 0); SU... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/divr4_rec_0.9ns.vhd | VHDL | lgpl | 155,432 |
library IEEE;
use IEEE.std_logic_1164.all;
entity csa32LSBs is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logi... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/csa32LSBs.vhd | VHDL | lgpl | 1,041 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_csa32 is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/gl_csa32.vhd | VHDL | lgpl | 977 |
-- VHDL Model Created from SGE Symbol qds_adder.sym -- Apr 21 16:44:47 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_ADDER is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 do... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/qds_adder.vhd | VHDL | lgpl | 2,330 |
-- VHDL Model Created from SGE Symbol mux.sym -- May 27 12:33:10 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MUX is
Port ( A : In std_logic_vector (56 downto 0);
B : In std_logic_vector (56 downto 0);
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/mux.vhd | VHDL | lgpl | 762 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut.saif
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/cmd_saif.inc | PHP | lgpl | 102 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal D : std_logic_vector (52 downto 0);
signal RESET : std_logic;
signal X : std_logi... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/tb_divr4_rec.vhd | VHDL | lgpl | 3,368 |
-- VHDL Model Created from SGE Symbol qds_table.sym -- Apr 21 16:34:54 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_TABLE is
Port ( D : In std_logic_vector (2 downto 0);
Y : In std_logic_vector (6 do... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/qds_table.vhd | VHDL | lgpl | 6,548 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_dualreg_ld is
GENERIC(n : integer);
Port ( AS : In std_logic_vector (n downto 0);
RESET : In std_logic;
CLOCK : In std_logic;
LOAD : In std_logic;
ZS : Out std_... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/gl_dualreg_ld.vhd | VHDL | lgpl | 835 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity divr4_rec is
Port ( CLOCK : In std_logic;
D : In std_logic_vector (52 downto 0);
RESET : In std_logic;
X : In std_logic_vector (... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/divr4_rec.vhd | VHDL | lgpl | 7,924 |
-- VHDL Model Created from SGE Symbol control.sym -- May 5 18:26:48 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity CONTROL is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
CL1 : Out std_lo... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/control.vhd | VHDL | lgpl | 1,523 |
-- VHDL Model Created from SGE Schematic qdsel.sch -- Apr 21 16:58:17 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDSEL is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto ... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/qdsel.vhd | VHDL | lgpl | 1,846 |
open run.out
logtime -e run.out
monitor -n Smon active *E/X'sig
monitor -n Smon active *E/D'sig
--monitor -n Smon active *E/Qj'sig
-- monitor -n Smon active *E/UUT/WS'sig
-- monitor -n Smon active *E/UUT/WC'sig
list > run.out
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/cmd.inc | C++ | lgpl | 266 |
-- VHDL Model Created from SGE Symbol mult.sym -- May 27 12:32:12 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MULT is
Port ( A : In std_logic_vector (54 downto 0);
M1 : In std_logic;
M2... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/mult.vhd | VHDL | lgpl | 1,093 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_divr4_rec is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_divr4_rec;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity CONTROL_DW01_inc_0 is
port( A : in std_logic_vector (4 downto 0); SU... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/divr4_rec_0.9ns.vhd | VHDL | lgpl | 155,462 |
library IEEE;
use IEEE.std_logic_1164.all;
entity csa32LSBs is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logi... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/csa32LSBs.vhd | VHDL | lgpl | 1,041 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_csa32 is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/gl_csa32.vhd | VHDL | lgpl | 977 |
-- VHDL Model Created from SGE Symbol qds_adder.sym -- Apr 21 16:44:47 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_ADDER is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 do... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/qds_adder.vhd | VHDL | lgpl | 2,330 |
-- VHDL Model Created from SGE Symbol mux.sym -- May 27 12:33:10 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MUX is
Port ( A : In std_logic_vector (56 downto 0);
B : In std_logic_vector (56 downto 0);
... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/mux.vhd | VHDL | lgpl | 762 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut.saif
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/cmd_saif.inc | PHP | lgpl | 102 |
\documentclass[11pt,a4paper]{article}
\usepackage{url,,}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{multirow}
\usepackage{listings}
\usepackage{fullpage}
\usepackage{fancyhdr,a4wide}
\usepackage{makeidx}
\usepackage{placeins}
%\usepackage[pro... | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/report/dt07_lab3.tex | TeX | lgpl | 17,427 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity MUX_4 is
port (
SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C: in STD_LOGIC_VECTOR(7 downto 0);
SIG: out STD_LOGIC_VECTOR(7 downto 0));
end MUX_4;
architecture BEH_MUX of MUX_4 is
begin
SEL_PROCESS: pro... | 02207-work-groupdt07 | trunk/Project/code/MUX_4.vhd | VHDL | lgpl | 581 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity TB_multiplier is
end TB_multiplier;
architecture TB of TB_multiplier is
component multiplier is
port( num1, num2: in std_logic_vector(7 downto 0);
product: out std_logic_vector(7 down... | 02207-work-groupdt07 | trunk/Project/code/tb_multiplier.vhd | VHDL | lgpl | 1,370 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- two 4-bit inputs and one 8-bit outputs
entity multiplier is
port( num1, num2: in std_logic_vector(7 downto 0);
product: out std_logic_vector(7 downto 0)
);
end multiplier;
architecture SCHEMATIC of multiplie... | 02207-work-groupdt07 | trunk/Project/code/Multiplier.vhd | VHDL | lgpl | 6,087 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity REG is
port(
D : in std_logic_vector(7 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(7 downto 0));
end entity REG;
architecture BEH_RE... | 02207-work-groupdt07 | trunk/Project/code/REG.vhd | VHDL | lgpl | 558 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity FSM_out_3 is
port (
clock: in std_logic;
reset: in std_logic;
read_address: out std_logic_vector(15 downto 0);
write_address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
sel: out s... | 02207-work-groupdt07 | trunk/Project/code/FSM_out.vhd | VHDL | lgpl | 9,373 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ADDER_2 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
Z : Out std_logic_vector (7 downto 0));
end ADDER_2;
architecture BEH_ADDER_2 of ADDER_2 is
signal sum_ou... | 02207-work-groupdt07 | trunk/Project/code/Adder_2.vhd | VHDL | lgpl | 1,258 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity fsm_out_tb is
end fsm_out_tb;
architecture FSM_TB of fsm_out_tb is
signal T_clock: std_logic;
signal T_reset: std_logic;
signal T_can_read: std_logic;
signal T_can_write: std... | 02207-work-groupdt07 | trunk/Project/code/TB_FSM_out.vhd | VHDL | lgpl | 1,809 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity MUX_2 is
port (
SEL: in STD_LOGIC;
A,B: in STD_LOGIC_VECTOR(15 downto 0);
SIG: out STD_LOGIC_VECTOR(15 downto 0));
end MUX_2;
architecture BEH_MUX_2 of MUX_2 is
begin
SEL_PROCESS: process (SEL,A,B)
... | 02207-work-groupdt07 | trunk/Project/code/MUX_2.vhd | VHDL | lgpl | 527 |
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_filter/uutp/clock
add wave -noupdate -format Logic /tb_filter/uutp/reset
add wave -noupdate -format Logic /tb_filter/uutp/read_in_mem
add wave -noupdate -format Logic /tb_filter/uutp/write_in_mem
add wave -noupdate -format Log... | 02207-work-groupdt07 | trunk/Project/code/wave_read&write_by_processor.do | Stata | lgpl | 2,505 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity Processor_3a is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
Read_In_Mem: Out std_logic;
Write_In_Mem : Out std_logic;
... | 02207-work-groupdt07 | trunk/Project/code/Processor_3_.vhd | VHDL | lgpl | 7,097 |
-----------------------------------------------------------------
-- test bench for FSM (ESD book figure 2.7)
-- by Weijun Zhang, 04/2001
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity... | 02207-work-groupdt07 | trunk/Project/code/TB_Sample_FSM.vhd | VHDL | lgpl | 2,174 |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity FSM_in_3 is
port (
clock: in std_logic;
reset: in std_logic;
address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
disable_cache: out std_logic
);
end FSM_in_3;
architecture BEH_FSM... | 02207-work-groupdt07 | trunk/Project/code/FSM_in.vhd | VHDL | lgpl | 5,782 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ADDER_3 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
C : In std_logic_vector (7 downto 0);
Z : Out std_logic_vector (7 downto 0));
end ADDER_3;
architecture BE... | 02207-work-groupdt07 | trunk/Project/code/Adder_3.vhd | VHDL | lgpl | 1,549 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CRA_8 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Y : Out std_logic_vector (7 downto 0) );
end CRA_8;
architectur... | 02207-work-groupdt07 | trunk/Project/code/CRA_8.vhd | VHDL | lgpl | 1,406 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
disable : In std_logic;
QK : In std_l... | 02207-work-groupdt07 | trunk/Project/code/SHIFTREG.vhd | VHDL | lgpl | 1,059 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity Processor is
Port ( CLOCK : In std_logic;
D : In std_logic_vector (2047 downto 0);
RESET : In std_logic;
Qj : Out std_log... | 02207-work-groupdt07 | trunk/Project/code/archive/proc.vhd | VHDL | lgpl | 5,589 |
------------------------------------------------------------------------
-- Project : 8404129 Hardware Description Languages
-- Group number : 32
-- Group : Markku Eerola 177065
-- markku.eerola@tut.fi
-- Vesa Salander 168075
-- vesa.salander@tut.fi
-- Date ... | 02207-work-groupdt07 | trunk/Project/code/archive/ctrl_fsm.vhdl | VHDL | lgpl | 4,159 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity Processor_3 is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
Read_In_Mem: Out std_logic;
Read_Out_Mem: Out std_logic;
... | 02207-work-groupdt07 | trunk/Project/code/archive/Processor_3_.vhd | VHDL | lgpl | 6,985 |
-- -----------------------------------------------------------------
-- Model for SRAM
-- use at your own risk
-- do not complain if it does not work properly
-- AN
--
-- ----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use... | 02207-work-groupdt07 | trunk/Project/code/archive/sram_1w1k.vhd | VHDL | lgpl | 2,684 |
library IEEE;
use IEEE.std_logic_1164.all;
entity csa32LSBs is
Port ( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
C : In std_logic_vector (7 downto 0);
Z : Out std_logic_vector (7 downto 0) );
end csa32LSBs;
architecture BEHAVIORAL of csa32LSBs is
begin
proces... | 02207-work-groupdt07 | trunk/Project/code/archive/csa32LSBs.vhd | VHDL | lgpl | 1,111 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADDER_TB is -- entity declaration
end ADDER_TB;
architecture TB of ADDER_TB is
component CRA is
port( A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
Cin: in std_log... | 02207-work-groupdt07 | trunk/Project/code/archive/tb_CRA.vhd | VHDL | lgpl | 2,234 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity csa8bit is
Port ( A : In std_logic_vector (15 downto 0);
B : In std_logic_vector (15 downto 0);
C : In std_logic_vector (15 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_... | 02207-work-groupdt07 | trunk/Project/code/archive/CSA_8bit.vhd | VHDL | lgpl | 1,080 |