_id stringlengths 2 7 | title stringlengths 1 88 | partition stringclasses 3
values | text stringlengths 75 19.8k | language stringclasses 1
value | meta_information dict |
|---|---|---|---|---|---|
q272100 | Cmd.do_help | test | def do_help(self, command):
"""Display this help message."""
if command:
doc = getattr(self, 'do_' + command).__doc__
print(cyan(doc.replace(' ' * 8, '')))
else:
print(magenta('Available commands:'))
print(magenta('Type "HELP <command>" to get more... | python | {
"resource": ""
} |
q272101 | Cmd.do_DBINFO | test | def do_DBINFO(self, *args):
"""Print some useful infos from Redis DB."""
info = DB.info()
keys = [
'keyspace_misses', 'keyspace_hits', 'used_memory_human',
'total_commands_processed', 'total_connections_received',
'connected_clients']
for key in keys:
... | python | {
"resource": ""
} |
q272102 | Cmd.do_DBKEY | test | def do_DBKEY(self, key):
"""Print raw content of a DB key.
DBKEY g|u09tyzfe"""
type_ = DB.type(key).decode()
if type_ == 'set':
out = DB.smembers(key)
elif type_ == 'string':
out = DB.get(key)
else:
out = 'Unsupported type {}'.format(ty... | python | {
"resource": ""
} |
q272103 | Cmd.do_GEOHASH | test | def do_GEOHASH(self, latlon):
"""Compute a geohash from latitude and longitude.
GEOHASH 48.1234 2.9876"""
try:
lat, lon = map(float, latlon.split())
except ValueError:
print(red('Invalid lat and lon {}'.format(latlon)))
else:
print(white(geohas... | python | {
"resource": ""
} |
q272104 | Cmd.do_GET | test | def do_GET(self, _id):
"""Get document from index with its id.
GET 772210180J"""
doc = doc_by_id(_id)
if not doc:
return self.error('id "{}" not found'.format(_id))
for key, value in doc.items():
if key == config.HOUSENUMBERS_FIELD:
continu... | python | {
"resource": ""
} |
q272105 | Cmd.do_INDEX | test | def do_INDEX(self, _id):
"""Get index details for a document by its id.
INDEX 772210180J"""
doc = doc_by_id(_id)
if not doc:
return self.error('id "{}" not found'.format(_id))
for field in config.FIELDS:
key = field['key']
if key in doc:
... | python | {
"resource": ""
} |
q272106 | Cmd.do_BESTSCORE | test | def do_BESTSCORE(self, word):
"""Return document linked to word with higher score.
BESTSCORE lilas"""
key = keys.token_key(indexed_string(word)[0])
for _id, score in DB.zrevrange(key, 0, 20, withscores=True):
result = Result(_id)
print(white(result), blue(score), ... | python | {
"resource": ""
} |
q272107 | Cmd.do_STRDISTANCE | test | def do_STRDISTANCE(self, s):
"""Print the distance score between two strings. Use | as separator.
STRDISTANCE rue des lilas|porte des lilas"""
s = s.split('|')
if not len(s) == 2:
print(red('Malformed string. Use | between the two strings.'))
return
one, t... | python | {
"resource": ""
} |
q272108 | send | test | def send(r, stream=False):
"""Just sends the request using its send method and returns its response. """
r.send(stream=stream)
return r.response | python | {
"resource": ""
} |
q272109 | map | test | def map(requests, stream=True, pool=None, size=1, exception_handler=None):
"""Concurrently converts a list of Requests to Responses.
:param requests: a collection of Request objects.
:param stream: If False, the content will not be downloaded immediately.
:param size: Specifies the number of workers to... | python | {
"resource": ""
} |
q272110 | getBits_from_array | test | def getBits_from_array(array, wordWidth, start, end,
reinterpretElmToType=None):
"""
Gets value of bits between selected range from memory
:param start: bit address of start of bit of bits
:param end: bit address of first bit behind bits
:return: instance of BitsVal (derived ... | python | {
"resource": ""
} |
q272111 | reinterptet_harray_to_bits | test | def reinterptet_harray_to_bits(typeFrom, sigOrVal, bitsT):
"""
Cast HArray signal or value to signal or value of type Bits
"""
size = int(typeFrom.size)
widthOfElm = typeFrom.elmType.bit_length()
w = bitsT.bit_length()
if size * widthOfElm != w:
raise TypeConversionErr(
"... | python | {
"resource": ""
} |
q272112 | slice_to_SLICE | test | def slice_to_SLICE(sliceVals, width):
"""convert python slice to value of SLICE hdl type"""
if sliceVals.step is not None:
raise NotImplementedError()
start = sliceVals.start
stop = sliceVals.stop
if sliceVals.start is None:
start = INT.fromPy(width)
else:
start = toHVa... | python | {
"resource": ""
} |
q272113 | find_files | test | def find_files(directory, pattern, recursive=True):
"""
Find files by pattern in directory
"""
if not os.path.isdir(directory):
if os.path.exists(directory):
raise IOError(directory + ' is not directory')
else:
raise IOError(directory + " does not exists")
if ... | python | {
"resource": ""
} |
q272114 | In | test | def In(sigOrVal, iterable):
"""
Hdl convertible in operator, check if any of items
in "iterable" equals "sigOrVal"
"""
res = None
for i in iterable:
i = toHVal(i)
if res is None:
res = sigOrVal._eq(i)
else:
res = res | sigOrVal._eq(i)
assert r... | python | {
"resource": ""
} |
q272115 | StaticForEach | test | def StaticForEach(parentUnit, items, bodyFn, name=""):
"""
Generate for loop for static items
:param parentUnit: unit where this code should be instantiated
:param items: items which this "for" itering on
:param bodyFn: function which fn(item, index) or fn(item)
returns (statementList, ack)... | python | {
"resource": ""
} |
q272116 | sll | test | def sll(sig, howMany) -> RtlSignalBase:
"Logical shift left"
width = sig._dtype.bit_length()
return sig[(width - howMany):]._concat(vec(0, howMany)) | python | {
"resource": ""
} |
q272117 | log2ceil | test | def log2ceil(x):
"""
Returns no of bits required to store x-1
for example x=8 returns 3
"""
if not isinstance(x, (int, float)):
x = int(x)
if x == 0 or x == 1:
res = 1
else:
res = math.ceil(math.log2(x))
return hInt(res) | python | {
"resource": ""
} |
q272118 | isPow2 | test | def isPow2(num) -> bool:
"""
Check if number or constant is power of two
"""
if not isinstance(num, int):
num = int(num)
return num != 0 and ((num & (num - 1)) == 0) | python | {
"resource": ""
} |
q272119 | Switch.Case | test | def Case(self, caseVal, *statements):
"c-like case of switch statement"
assert self.parentStm is None
caseVal = toHVal(caseVal, self.switchOn._dtype)
assert isinstance(caseVal, Value), caseVal
assert caseVal._isFullVld(), "Cmp with invalid value"
assert caseVal not in se... | python | {
"resource": ""
} |
q272120 | Switch.Default | test | def Default(self, *statements):
"""c-like default of switch statement
"""
assert self.parentStm is None
self.rank += 1
self.default = []
self._register_stements(statements, self.default)
return self | python | {
"resource": ""
} |
q272121 | VcdHdlSimConfig.vcdRegisterInterfaces | test | def vcdRegisterInterfaces(self, obj: Union[Interface, Unit],
parent: Optional[VcdVarWritingScope]):
"""
Register signals from interfaces for Interface or Unit instances
"""
if hasattr(obj, "_interfaces") and obj._interfaces:
name = obj._name
... | python | {
"resource": ""
} |
q272122 | VcdHdlSimConfig.beforeSim | test | def beforeSim(self, simulator, synthesisedUnit):
"""
This method is called before first step of simulation.
"""
vcd = self.vcdWriter
vcd.date(datetime.now())
vcd.timescale(1)
self.vcdRegisterInterfaces(synthesisedUnit, None)
self.vcdRegisterRemainingSigna... | python | {
"resource": ""
} |
q272123 | VcdHdlSimConfig.logChange | test | def logChange(self, nowTime, sig, nextVal):
"""
This method is called for every value change of any signal.
"""
try:
self.vcdWriter.logChange(nowTime, sig, nextVal)
except KeyError:
# not every signal has to be registered
pass | python | {
"resource": ""
} |
q272124 | SystemCSerializer_statements.HWProcess | test | def HWProcess(cls, proc, ctx):
"""
Serialize HWProcess instance
:param scope: name scope to prevent name collisions
"""
body = proc.statements
childCtx = ctx.withIndent()
statemets = [cls.asHdl(s, childCtx) for s in body]
proc.name = ctx.scope.checkedName... | python | {
"resource": ""
} |
q272125 | autoAddAgents | test | def autoAddAgents(unit):
"""
Walk all interfaces on unit and instantiate agent for every interface.
:return: all monitor/driver functions which should be added to simulation
as processes
"""
proc = []
for intf in unit._interfaces:
if not intf._isExtern:
continue
... | python | {
"resource": ""
} |
q272126 | InterfaceceImplDependentFns._getAssociatedClk | test | def _getAssociatedClk(self):
"""
If interface has associated clk return it otherwise
try to find clk on parent recursively
"""
a = self._associatedClk
if a is not None:
return a
p = self._parent
assert p is not None
if isinstance(p, ... | python | {
"resource": ""
} |
q272127 | distinctBy | test | def distinctBy(iterable, fn):
"""
uniq operation with key selector
"""
s = set()
for i in iterable:
r = fn(i)
if r not in s:
s.add(r)
yield i | python | {
"resource": ""
} |
q272128 | groupedby | test | def groupedby(collection, fn):
"""
same like itertools.groupby
:note: This function does not needs initial sorting like itertools.groupby
:attention: Order of pairs is not deterministic.
"""
d = {}
for item in collection:
k = fn(item)
try:
arr = d[k]
exc... | python | {
"resource": ""
} |
q272129 | flatten | test | def flatten(iterables, level=inf):
"""
Flatten nested lists, tuples, generators and maps
:param level: maximum depth of flattening
"""
if level >= 0 and isinstance(iterables, (list, tuple, GeneratorType,
map, zip)):
level -= 1
for i in it... | python | {
"resource": ""
} |
q272130 | IfContainer._merge_nested_if_from_else | test | def _merge_nested_if_from_else(self, ifStm: "IfContainer"):
"""
Merge nested IfContarner form else branch to this IfContainer
as elif and else branches
"""
self.elIfs.append((ifStm.cond, ifStm.ifTrue))
self.elIfs.extend(ifStm.elIfs)
self.ifFalse = ifStm.ifFalse | python | {
"resource": ""
} |
q272131 | removeUnconnectedSignals | test | def removeUnconnectedSignals(netlist):
"""
If signal is not driving anything remove it
"""
toDelete = set()
toSearch = netlist.signals
while toSearch:
_toSearch = set()
for sig in toSearch:
if not sig.endpoints:
try:
if sig._inte... | python | {
"resource": ""
} |
q272132 | checkIfIsTooSimple | test | def checkIfIsTooSimple(proc):
"""check if process is just unconditional assignments
and it is useless to merge them"""
try:
a, = proc.statements
if isinstance(a, Assignment):
return True
except ValueError:
pass
return False | python | {
"resource": ""
} |
q272133 | tryToMerge | test | def tryToMerge(procA: HWProcess, procB: HWProcess):
"""
Try merge procB into procA
:raise IncompatibleStructure: if merge is not possible
:attention: procA is now result if merge has succeed
:return: procA which is now result of merge
"""
if (checkIfIsTooSimple(procA) or
checkIf... | python | {
"resource": ""
} |
q272134 | reduceProcesses | test | def reduceProcesses(processes):
"""
Try to merge processes as much is possible
:param processes: list of processes instances
"""
# sort to make order of merging same deterministic
processes.sort(key=lambda x: (x.name, maxStmId(x)), reverse=True)
# now try to reduce processes with nearly sam... | python | {
"resource": ""
} |
q272135 | BramPort_withoutClkAgent.onWriteReq | test | def onWriteReq(self, sim, addr, data):
"""
on writeReqRecieved in monitor mode
"""
self.requests.append((WRITE, addr, data)) | python | {
"resource": ""
} |
q272136 | toRtl | test | def toRtl(unitOrCls: Unit, name: str=None,
serializer: GenericSerializer=VhdlSerializer,
targetPlatform=DummyPlatform(), saveTo: str=None):
"""
Convert unit to RTL using specified serializer
:param unitOrCls: unit instance or class, which should be converted
:param name: name overri... | python | {
"resource": ""
} |
q272137 | name_for_process_and_mark_outputs | test | def name_for_process_and_mark_outputs(statements: List[HdlStatement])\
-> str:
"""
Resolve name for process and mark outputs of statemens as not hidden
"""
out_names = []
for stm in statements:
for sig in stm._outputs:
if not sig.hasGenericName:
out_names.... | python | {
"resource": ""
} |
q272138 | cut_off_drivers_of | test | def cut_off_drivers_of(dstSignal, statements):
"""
Cut off drivers from statements
"""
separated = []
stm_filter = []
for stm in statements:
stm._clean_signal_meta()
d = stm._cut_off_drivers_of(dstSignal)
if d is not None:
separated.append(d)
f = d is... | python | {
"resource": ""
} |
q272139 | RtlNetlist.sig | test | def sig(self, name, dtype=BIT, clk=None, syncRst=None, defVal=None):
"""
Create new signal in this context
:param clk: clk signal, if specified signal is synthesized
as SyncSignal
:param syncRst: synchronous reset signal
"""
if isinstance(defVal, RtlSignal):
... | python | {
"resource": ""
} |
q272140 | RtlNetlist.synthesize | test | def synthesize(self, name, interfaces, targetPlatform):
"""
Build Entity and Architecture instance out of netlist representation
"""
ent = Entity(name)
ent._name = name + "_inst" # instance name
# create generics
for _, v in self.params.items():
ent.... | python | {
"resource": ""
} |
q272141 | getMaxStmIdForStm | test | def getMaxStmIdForStm(stm):
"""
Get maximum _instId from all assigments in statement
"""
maxId = 0
if isinstance(stm, Assignment):
return stm._instId
elif isinstance(stm, WaitStm):
return maxId
else:
for _stm in stm._iter_stms():
maxId = max(maxId, getMaxS... | python | {
"resource": ""
} |
q272142 | maxStmId | test | def maxStmId(proc):
"""
get max statement id,
used for sorting of processes in architecture
"""
maxId = 0
for stm in proc.statements:
maxId = max(maxId, getMaxStmIdForStm(stm))
return maxId | python | {
"resource": ""
} |
q272143 | RdSyncedAgent.doWrite | test | def doWrite(self, sim, data):
"""write data to interface"""
sim.write(data, self.intf.data) | python | {
"resource": ""
} |
q272144 | Interface._m | test | def _m(self):
"""
Note that this interface will be master
:return: self
"""
assert not hasattr(self, "_interfaces") or not self._interfaces, \
"Too late to change direction of interface"
self._direction = DIRECTION.asIntfDirection(DIRECTION.opposite(self._mas... | python | {
"resource": ""
} |
q272145 | Interface._loadDeclarations | test | def _loadDeclarations(self):
"""
load declaratoins from _declr method
This function is called first for parent and then for children
"""
if not hasattr(self, "_interfaces"):
self._interfaces = []
self._setAttrListener = self._declrCollector
self._declr... | python | {
"resource": ""
} |
q272146 | Interface._signalsForInterface | test | def _signalsForInterface(self, context, prefix='', typeTransform=None):
"""
generate _sig for each interface which has no subinterface
if already has _sig return it instead
:param context: instance of RtlNetlist where signals should be created
:param prefix: name prefix for crea... | python | {
"resource": ""
} |
q272147 | Interface._getPhysicalName | test | def _getPhysicalName(self):
"""Get name in HDL """
if hasattr(self, "_boundedEntityPort"):
return self._boundedEntityPort.name
else:
return self._getFullName().replace('.', self._NAME_SEPARATOR) | python | {
"resource": ""
} |
q272148 | Interface._bit_length | test | def _bit_length(self):
"""Sum of all width of interfaces in this interface"""
try:
interfaces = self._interfaces
except AttributeError:
interfaces = None
if interfaces is None:
# not loaded interface
_intf = self._clone()
_intf... | python | {
"resource": ""
} |
q272149 | sensitivityByOp | test | def sensitivityByOp(op):
"""
get sensitivity type for operator
"""
if op == AllOps.RISING_EDGE:
return SENSITIVITY.RISING
elif op == AllOps.FALLING_EDGE:
return SENSITIVITY.FALLING
else:
raise TypeError() | python | {
"resource": ""
} |
q272150 | OpDefinition.eval | test | def eval(self, operator, simulator=None):
"""Load all operands and process them by self._evalFn"""
def getVal(v):
while not isinstance(v, Value):
v = v._val
return v
operands = list(map(getVal, operator.operands))
if isEventDependentOp(operator.... | python | {
"resource": ""
} |
q272151 | convertBits | test | def convertBits(self, sigOrVal, toType):
"""
Cast signed-unsigned, to int or bool
"""
if isinstance(sigOrVal, Value):
return convertBits__val(self, sigOrVal, toType)
elif isinstance(toType, HBool):
if self.bit_length() == 1:
v = 0 if sigOrVal._dtype.negated else 1
... | python | {
"resource": ""
} |
q272152 | reinterpret_bits_to_hstruct | test | def reinterpret_bits_to_hstruct(sigOrVal, hStructT):
"""
Reinterpret signal of type Bits to signal of type HStruct
"""
container = hStructT.fromPy(None)
offset = 0
for f in hStructT.fields:
t = f.dtype
width = t.bit_length()
if f.name is not None:
s = sigOrVal... | python | {
"resource": ""
} |
q272153 | TransTmplWordIterator.fullWordCnt | test | def fullWordCnt(self, start: int, end: int):
"""Count of complete words between two addresses
"""
assert end >= start, (start, end)
gap = max(0, (end - start) - (start % self.wordWidth))
return gap // self.wordWidth | python | {
"resource": ""
} |
q272154 | TransTmplWordIterator.groupByWordIndex | test | def groupByWordIndex(self, transaction: 'TransTmpl', offset: int):
"""
Group transaction parts splited on words to words
:param transaction: TransTmpl instance which parts
should be grupped into words
:return: generator of tuples (wordIndex, list of transaction parts
... | python | {
"resource": ""
} |
q272155 | pprintInterface | test | def pprintInterface(intf, prefix="", indent=0, file=sys.stdout):
"""
Pretty print interface
"""
try:
s = intf._sig
except AttributeError:
s = ""
if s is not "":
s = " " + repr(s)
file.write("".join([getIndent(indent), prefix, repr(intf._getFullName()),
... | python | {
"resource": ""
} |
q272156 | FrameTmpl.framesFromTransTmpl | test | def framesFromTransTmpl(transaction: 'TransTmpl',
wordWidth: int,
maxFrameLen: Union[int, float]=inf,
maxPaddingWords: Union[int, float]=inf,
trimPaddingWordsOnStart: bool=False,
t... | python | {
"resource": ""
} |
q272157 | FrameTmpl.walkWords | test | def walkWords(self, showPadding: bool=False):
"""
Walk enumerated words in this frame
:attention: not all indexes has to be present, only words
with items will be generated when not showPadding
:param showPadding: padding TransParts are also present
:return: generato... | python | {
"resource": ""
} |
q272158 | FrameTmpl.packData | test | def packData(self, data):
"""
Pack data into list of BitsVal of specified dataWidth
:param data: dict of values for struct fields {fieldName: value}
:return: list of BitsVal which are representing values of words
"""
typeOfWord = simBitsT(self.wordWidth, None)
f... | python | {
"resource": ""
} |
q272159 | HdlStatement._clean_signal_meta | test | def _clean_signal_meta(self):
"""
Clean informations about enclosure for outputs and sensitivity
of this statement
"""
self._enclosed_for = None
self._sensitivity = None
for stm in self._iter_stms():
stm._clean_signal_meta() | python | {
"resource": ""
} |
q272160 | HdlStatement._discover_enclosure_for_statements | test | def _discover_enclosure_for_statements(statements: List['HdlStatement'],
outputs: List['HdlStatement']):
"""
Discover enclosure for list of statements
:param statements: list of statements in one code branch
:param outputs: list of outputs whic... | python | {
"resource": ""
} |
q272161 | HdlStatement._discover_sensitivity_seq | test | def _discover_sensitivity_seq(self,
signals: List[RtlSignalBase],
seen: set, ctx: SensitivityCtx)\
-> None:
"""
Discover sensitivity for list of signals
"""
casualSensitivity = set()
for s in signals... | python | {
"resource": ""
} |
q272162 | HdlStatement._get_rtl_context | test | def _get_rtl_context(self):
"""
get RtlNetlist context from signals
"""
for sig in chain(self._inputs, self._outputs):
if sig.ctx:
return sig.ctx
else:
# Param instances does not have context
continue
raise H... | python | {
"resource": ""
} |
q272163 | HdlStatement._on_reduce | test | def _on_reduce(self, self_reduced: bool, io_changed: bool,
result_statements: List["HdlStatement"]) -> None:
"""
Update signal IO after reuce atempt
:param self_reduced: if True this object was reduced
:param io_changed: if True IO of this object may changed
... | python | {
"resource": ""
} |
q272164 | HdlStatement._on_merge | test | def _on_merge(self, other):
"""
After merging statements update IO, sensitivity and context
:attention: rank is not updated
"""
self._inputs.extend(other._inputs)
self._outputs.extend(other._outputs)
if self._sensitivity is not None:
self._sensitivit... | python | {
"resource": ""
} |
q272165 | HdlStatement._is_mergable_statement_list | test | def _is_mergable_statement_list(cls, stmsA, stmsB):
"""
Walk statements and compare if they can be merged into one statement list
"""
if stmsA is None and stmsB is None:
return True
elif stmsA is None or stmsB is None:
return False
a_it = iter(st... | python | {
"resource": ""
} |
q272166 | HdlStatement._merge_statements | test | def _merge_statements(statements: List["HdlStatement"])\
-> Tuple[List["HdlStatement"], int]:
"""
Merge statements in list to remove duplicated if-then-else trees
:return: tuple (list of merged statements, rank decrease due merging)
:note: rank decrease is sum of ranks of re... | python | {
"resource": ""
} |
q272167 | HdlStatement._merge_statement_lists | test | def _merge_statement_lists(stmsA: List["HdlStatement"], stmsB: List["HdlStatement"])\
-> List["HdlStatement"]:
"""
Merge two lists of statements into one
:return: list of merged statements
"""
if stmsA is None and stmsB is None:
return None
tmp =... | python | {
"resource": ""
} |
q272168 | HdlStatement._try_reduce_list | test | def _try_reduce_list(statements: List["HdlStatement"]):
"""
Simplify statements in the list
"""
io_change = False
new_statements = []
for stm in statements:
reduced, _io_change = stm._try_reduce()
new_statements.extend(reduced)
io_chan... | python | {
"resource": ""
} |
q272169 | HdlStatement._on_parent_event_dependent | test | def _on_parent_event_dependent(self):
"""
After parrent statement become event dependent
propagate event dependency flag to child statements
"""
if not self._is_completly_event_dependent:
self._is_completly_event_dependent = True
for stm in self._iter_stms... | python | {
"resource": ""
} |
q272170 | HdlStatement._set_parent_stm | test | def _set_parent_stm(self, parentStm: "HdlStatement"):
"""
Assign parent statement and propagate dependency flags if necessary
"""
was_top = self.parentStm is None
self.parentStm = parentStm
if not self._now_is_event_dependent\
and parentStm._now_is_event_d... | python | {
"resource": ""
} |
q272171 | HdlStatement._register_stements | test | def _register_stements(self, statements: List["HdlStatement"],
target: List["HdlStatement"]):
"""
Append statements to this container under conditions specified
by condSet
"""
for stm in flatten(statements):
assert stm.parentStm is None, stm... | python | {
"resource": ""
} |
q272172 | HdlStatement._destroy | test | def _destroy(self):
"""
Disconnect this statement from signals and delete it from RtlNetlist context
:attention: signal endpoints/drivers will be altered
that means they can not be used for iteration
"""
ctx = self._get_rtl_context()
for i in self._inputs:
... | python | {
"resource": ""
} |
q272173 | UnitImplHelpers._reg | test | def _reg(self, name, dtype=BIT, defVal=None, clk=None, rst=None):
"""
Create register in this unit
:param defVal: default value of this register,
if this value is specified reset of this component is used
(unit has to have single interface of class Rst or Rst_n)
... | python | {
"resource": ""
} |
q272174 | UnitImplHelpers._sig | test | def _sig(self, name, dtype=BIT, defVal=None):
"""
Create signal in this unit
"""
if isinstance(dtype, HStruct):
if defVal is not None:
raise NotImplementedError()
container = dtype.fromPy(None)
for f in dtype.fields:
if ... | python | {
"resource": ""
} |
q272175 | UnitImplHelpers._cleanAsSubunit | test | def _cleanAsSubunit(self):
"""Disconnect internal signals so unit can be reused by parent unit"""
for pi in self._entity.ports:
pi.connectInternSig()
for i in chain(self._interfaces, self._private_interfaces):
i._clean() | python | {
"resource": ""
} |
q272176 | walkFlattenFields | test | def walkFlattenFields(sigOrVal, skipPadding=True):
"""
Walk all simple values in HStruct or HArray
"""
t = sigOrVal._dtype
if isinstance(t, Bits):
yield sigOrVal
elif isinstance(t, HUnion):
yield from walkFlattenFields(sigOrVal._val, skipPadding=skipPadding)
elif isinstance(t... | python | {
"resource": ""
} |
q272177 | HStruct_unpack | test | def HStruct_unpack(structT, data, getDataFn=None, dataWidth=None):
"""
opposite of packAxiSFrame
"""
if getDataFn is None:
assert dataWidth is not None
def _getDataFn(x):
return toHVal(x)._auto_cast(Bits(dataWidth))
getDataFn = _getDataFn
val = structT.fromPy(N... | python | {
"resource": ""
} |
q272178 | BitsVal._convSign | test | def _convSign(self, signed):
"""
Convert signum, no bit manipulation just data are represented
differently
:param signed: if True value will be signed,
if False value will be unsigned,
if None value will be vector without any sign specification
"""
... | python | {
"resource": ""
} |
q272179 | sensitivity | test | def sensitivity(proc: HWProcess, *sensitiveTo):
"""
register sensitivity for process
"""
for s in sensitiveTo:
if isinstance(s, tuple):
sen, s = s
if sen == SENSITIVITY.ANY:
s.simSensProcs.add(proc)
elif sen == SENSITIVITY.RISING:
... | python | {
"resource": ""
} |
q272180 | simEvalCond | test | def simEvalCond(simulator, *conds):
"""
Evaluate list of values as condition
"""
_cond = True
_vld = True
for v in conds:
val = bool(v.val)
fullVld = v.vldMask == 1
if fullVld:
if not val:
return False, True
else:
return Fal... | python | {
"resource": ""
} |
q272181 | connectSimPort | test | def connectSimPort(simUnit, subSimUnit, srcName, dstName, direction):
"""
Connect ports of simulation models by name
"""
if direction == DIRECTION.OUT:
origPort = getattr(subSimUnit, srcName)
newPort = getattr(simUnit, dstName)
setattr(subSimUnit, srcName, newPort)
else:
... | python | {
"resource": ""
} |
q272182 | mkUpdater | test | def mkUpdater(nextVal: Value, invalidate: bool):
"""
Create value updater for simulation
:param nextVal: instance of Value which will be asssiggned to signal
:param invalidate: flag which tells if value has been compromised
and if it should be invaidated
:return: function(value) -> tuple(va... | python | {
"resource": ""
} |
q272183 | mkArrayUpdater | test | def mkArrayUpdater(nextItemVal: Value, indexes: Tuple[Value],
invalidate: bool):
"""
Create value updater for simulation for value of array type
:param nextVal: instance of Value which will be asssiggned to signal
:param indexes: tuple on indexes where value should be updated
... | python | {
"resource": ""
} |
q272184 | vec | test | def vec(val, width, signed=None):
"""create hdl vector value"""
return Bits(width, signed, forceVector=True).fromPy(val) | python | {
"resource": ""
} |
q272185 | ResourceAnalyzer.HWProcess | test | def HWProcess(cls, proc: HWProcess, ctx: ResourceContext) -> None:
"""
Gues resource usage by HWProcess
"""
seen = ctx.seen
for stm in proc.statements:
encl = stm._enclosed_for
full_ev_dep = stm._is_completly_event_dependent
now_ev_dep = stm._n... | python | {
"resource": ""
} |
q272186 | evalParam | test | def evalParam(p):
"""
Get value of parameter
"""
while isinstance(p, Param):
p = p.get()
if isinstance(p, RtlSignalBase):
return p.staticEval()
# use rather param inheritance instead of param as param value
return toHVal(p) | python | {
"resource": ""
} |
q272187 | Param.set | test | def set(self, val):
"""
set value of this param
"""
assert not self.__isReadOnly, \
("This parameter(%s) was locked"
" and now it can not be changed" % self.name)
assert self.replacedWith is None, \
("This param was replaced with new one and t... | python | {
"resource": ""
} |
q272188 | HTypeFromIntfMap | test | def HTypeFromIntfMap(interfaceMap):
"""
Generate flattened register map for HStruct
:param interfaceMap: sequence of
tuple (type, name) or (will create standard struct field member)
interface or (will create a struct field from interface)
instance of hdl type (is used as padding)
... | python | {
"resource": ""
} |
q272189 | ResourceContext.finalize | test | def finalize(self):
"""
Resolve ports of discovered memories
"""
ff_to_remove = 0
res = self.resources
for m, addrDict in self.memories.items():
rwSyncPorts, rSyncPorts, wSyncPorts = 0, 0, 0
rwAsyncPorts, rAsyncPorts, wAsyncPorts = 0, 0, 0
... | python | {
"resource": ""
} |
q272190 | RtlSignalOps._getIndexCascade | test | def _getIndexCascade(self):
"""
Find out if this signal is something indexed
"""
try:
# now I am result of the index xxx[xx] <= source
# get index op
d = self.singleDriver()
try:
op = d.operator
except Attribute... | python | {
"resource": ""
} |
q272191 | HdlType.fromPy | test | def fromPy(self, v, vldMask=None):
"""
Construct value of this type.
Delegated on value class for this type
"""
return self.getValueCls().fromPy(v, self, vldMask=vldMask) | python | {
"resource": ""
} |
q272192 | HdlType.auto_cast | test | def auto_cast(self, sigOrVal, toType):
"""
Cast value or signal of this type to another compatible type.
:param sigOrVal: instance of signal or value to cast
:param toType: instance of HdlType to cast into
"""
if sigOrVal._dtype == toType:
return sigOrVal
... | python | {
"resource": ""
} |
q272193 | HdlType.reinterpret_cast | test | def reinterpret_cast(self, sigOrVal, toType):
"""
Cast value or signal of this type to another type of same size.
:param sigOrVal: instance of signal or value to cast
:param toType: instance of HdlType to cast into
"""
try:
return self.auto_cast(sigOrVal, toT... | python | {
"resource": ""
} |
q272194 | walkParams | test | def walkParams(intf, discovered):
"""
walk parameter instances on this interface
"""
for si in intf._interfaces:
yield from walkParams(si, discovered)
for p in intf._params:
if p not in discovered:
discovered.add(p)
yield p | python | {
"resource": ""
} |
q272195 | connectPacked | test | def connectPacked(srcPacked, dstInterface, exclude=None):
"""
Connect 1D vector signal to this structuralized interface
:param packedSrc: vector which should be connected
:param dstInterface: structuralized interface where should
packedSrc be connected to
:param exclude: sub interfaces of s... | python | {
"resource": ""
} |
q272196 | packIntf | test | def packIntf(intf, masterDirEqTo=DIRECTION.OUT, exclude=None):
"""
Concatenate all signals to one big signal, recursively
:param masterDirEqTo: only signals with this direction are packed
:param exclude: sequence of signals/interfaces to exclude
"""
if not intf._interfaces:
if intf._mas... | python | {
"resource": ""
} |
q272197 | VerilogSerializer.hardcodeRomIntoProcess | test | def hardcodeRomIntoProcess(cls, rom):
"""
Due to verilog restrictions it is not posible to use array constants
and rom memories has to be hardcoded as process
"""
processes = []
signals = []
for e in rom.endpoints:
assert isinstance(e, Operator) and e.... | python | {
"resource": ""
} |
q272198 | Unit._toRtl | test | def _toRtl(self, targetPlatform: DummyPlatform):
"""
synthesize all subunits, make connections between them,
build entity and component for this unit
"""
assert not self._wasSynthetised()
self._targetPlatform = targetPlatform
if not hasattr(self, "_name"):
... | python | {
"resource": ""
} |
q272199 | Unit._registerIntfInImpl | test | def _registerIntfInImpl(self, iName, intf):
"""
Register interface in implementation phase
"""
self._registerInterface(iName, intf, isPrivate=True)
self._loadInterface(intf, False)
intf._signalsForInterface(self._ctx) | python | {
"resource": ""
} |
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