Restructure dataset with extracted artifacts and manifest files

.gitattributes

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 # Video files - compressed
 *.mp4 filter=lfs diff=lfs merge=lfs -text
 *.webm filter=lfs diff=lfs merge=lfs -text
+paper/arXiv.pdf filter=lfs diff=lfs merge=lfs -text

CITATION.cff

@@ -0,0 +1,32 @@
+cff-version: 1.2.0
+message: "If you use this software or the accompanying reproducibility bundle, please cite it as below."
+title: "Wigner's Friend as a Circuit — Inter-Branch Communication Witness Benchmarks (Reproducibility Bundle)"
+type: software
+authors:
+  - family-names: Altman
+    given-names: Christopher
+    email: x@christopheraltman.com
+    website: "https://lab.christopheraltman.com"
+repository-code: "https://github.com/christopher-altman/ibm-qml-kernel"
+url: "https://github.com/christopher-altman/ibm-qml-kernel"
+license: MIT
+keywords:
+  - quantum computing
+  - quantum foundations
+  - Wigner's friend
+  - IBM Quantum
+  - reproducibility
+  - Qiskit
+  - noise models
+  - inter-branch communication
+version: "wigner-friend-v2b"
+date-released: "2026-01-21"
+preferred-citation:
+  type: article
+  authors:
+    - family-names: Altman
+      given-names: Christopher
+  title: "Wigner's Friend as a Circuit: Inter-Branch Communication Witness Benchmarks on Superconducting Quantum Hardware"
+  year: 2026
+  repository-code: "https://github.com/christopher-altman/ibm-qml-kernel"
+  notes: "arXiv preprint; reproducibility release tag: wigner-friend-v2b"

LICENSE

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+MIT License
+
+Copyright (c) 2026 Christopher Altman
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

README.md

@@ -0,0 +1,662 @@
+# Quantum Kernel Methods on IBM Quantum Hardware
+
+*Quantum kernel estimation for binary classification with realistic IBM Quantum hardware noise modeling and optional PSD (positive semidefinite) kernel projection for numerical stability.*
+
+<br>
+
+[![Python 3.10+](https://img.shields.io/badge/python-3.10+-blue.svg)](https://www.python.org/downloads/)
+[![License: MIT](https://img.shields.io/badge/License-MIT-yellow.svg)](https://opensource.org/licenses/MIT)
+[![Google Scholar](https://img.shields.io/badge/Google_Scholar-Profile-blue?logo=google-scholar)](https://scholar.google.com/citations?user=tvwpCcgAAAAJ)
+[![Hugging Face](https://img.shields.io/badge/huggingface-Coh%C3%A6rence-white)](https://huggingface.co/Cohaerence)
+
+[![CI](https://github.com/christopher-altman/ibm-qml-kernel/actions/workflows/ci.yml/badge.svg)](https://github.com/christopher-altman/ibm-qml-kernel/actions/workflows/ci.yml)
+[![X](https://img.shields.io/badge/X-@coherence-blue)](https://x.com/coherence)
+[![Website](https://img.shields.io/badge/website-christopheraltman.com-green)](https://www.christopheraltman.com)
+[![LinkedIn](https://img.shields.io/badge/LinkedIn-Altman-blue?logo=linkedin&logoColor=white)](https://www.linkedin.com/in/Altman)
+
+<br>
+
+<picture>
+  <source media="(prefers-color-scheme: dark)" srcset="assets/accuracy_comparison_dark.png">
+  <img src="assets/accuracy_comparison_light.png" alt="Accuracy comparison: Ideal vs Noisy quantum kernels on IBM hardware noise model">
+</picture>
+
+<br>
+
+> **TL;DR:** Realistic IBM Quantum noise (T1≈200 µs, T2≈135 µs, ECR error≈0.8%) degrades quantum kernel fidelity by 5–15% but classification capability persists. PSD projection ensures numerical stability under finite-shot noise with negligible impact on well-conditioned kernels.
+
+---
+
+## Table of Contents
+
+- [Background](#background)
+  - [Quantum Kernel Methods](#quantum-kernel-methods)
+  - [Hardware Noise Effects](#hardware-noise-effects)
+  - [PSD Kernel Projection](#psd-kernel-projection)
+- [Quickstart](#quickstart)
+- [Execution Modes](#execution-modes)
+- [Output Directory Semantics](#output-directory-semantics)
+- [CLI Reference](#cli-reference)
+- [Results Summary](#results-summary)
+- [Project Structure](#project-structure)
+- [Installation](#installation)
+- [RAW vs PSD Experiment](#raw-vs-psd-experiment)
+- [Interpreting Results](#interpreting-results)
+- [Branch-Transfer Experiment (Inter-Branch Communication) — Hardware Implementation](#branch-transfer-experiment-inter-branch-communication--hardware-implementation)
+  - [What Was Implemented](#what-was-implemented)
+  - [Why Visibility Alone Is Insufficient](#why-visibility-alone-is-insufficient)
+  - [Quickstart: Reproduce the Results](#quickstart-reproduce-the-results)
+  - [Latest Hardware Run (Provenance)](#latest-hardware-run-provenance)
+  - [Artifacts & Reproducibility](#artifacts--reproducibility)
+  - [Collapse / Nonunitary Channel Constraint Analysis](#collapse--nonunitary-channel-constraint-analysis)
+  - [Scaling Roadmap](#scaling-roadmap)
+- [Roadmap](#roadmap)
+- [References](#references)
+- [Citations](#citations)
+- [License](#license)
+- [Contact](#contact)
+
+---
+
+## Background
+
+### Quantum Kernel Methods
+
+Quantum kernel methods embed classical data into quantum Hilbert space via parameterized quantum circuits (feature maps), then compute kernel matrices from overlap fidelities between quantum states:
+
+$$
+K(x_i, x_j) = \bigl|\langle \phi(x_i) \mid \phi(x_j) \rangle\bigr|^2
+$$
+
+where the feature-mapped quantum state is $\lvert\phi(x)\rangle = U(x)\lvert 0\rangle^{\otimes n}$. This project uses the **ZZFeatureMap** from Qiskit, which encodes classical features through single-qubit rotations and ZZ entangling gates:
+
+$$
+U_{\mathrm{ZZ}}(\mathbf{x}) = \exp\Bigl(i \sum_{i < j} (\pi - x_i)(\pi - x_j)\, Z_i Z_j\Bigr) \prod_{k} R_z(x_k)\, H_k
+$$
+
+The resulting kernel matrix is used with a classical SVM for binary classification.
+
+### Hardware Noise Effects
+
+Real quantum hardware introduces several noise sources that degrade kernel fidelity:
+
+| Noise Source | IBM Brisbane (2026) | Effect on Kernel |
+|--------------|---------------------|------------------|
+| T1 relaxation | 200 µs | Energy decay during computation |
+| T2 dephasing | 135 µs | Phase coherence loss |
+| Single-qubit gate error | 0.15% | Rotation imprecision |
+| Two-qubit (ECR) gate error | 0.80% | Entanglement degradation |
+| Readout error | 2.5% | Measurement bit-flip noise |
+
+These parameters are extracted from IBM Quantum documentation and peer-reviewed literature (Journal of Supercomputing, April 2025).
+
+### PSD Kernel Projection
+
+Quantum kernel matrices may lose positive semidefiniteness due to:
+- Finite shot noise (statistical sampling)
+- Hardware gate/readout errors
+- Numerical precision limits
+
+This violates the mathematical requirements for valid kernel matrices in SVMs. The **PSD projection** algorithm restores validity:
+
+1. **Symmetrize**: $K \leftarrow (K + K^T)/2$
+2. **Eigen-decompose**: $K = V \Lambda V^T$
+3. **Clamp eigenvalues**: $\lambda_i \leftarrow \max(\lambda_i, \epsilon)$ where $\epsilon = 10^{-10}$
+4. **Reconstruct**: $K' = V \Lambda' V^T$
+5. **Preserve trace**: Scale to maintain $\text{tr}(K') = \text{tr}(K)$
+
+The projection is **off by default** and can be enabled via CLI flags.
+
+---
+
+## Quickstart
+
+```bash
+# Clone and setup
+git clone https://github.com/christopher-altman/ibm-qml-kernel.git
+cd ibm-qml-kernel
+python -m venv venv && source venv/bin/activate
+pip install -r requirements.txt
+
+# Run the full pipeline (ideal + noisy simulation)
+python src/qke_model.py      # Ideal quantum kernel estimation
+python src/qke_noisy.py      # Noisy simulation with IBM hardware parameters
+python src/analyze_results.py # Generate analysis report
+```
+
+**Expected runtime:** 2–3 minutes on CPU
+
+---
+
+## Execution Modes
+
+This project implements three quantum kernel estimation modes:
+
+| Mode | Script | Description | Runtime |
+|------|--------|-------------|---------|
+| **Ideal** | `qke_model.py` | Perfect quantum operations (statevector) | 30–60 s |
+| **Noisy** | `qke_noisy.py` | IBM hardware noise model (2026 calibration) | 1–2 min |
+| **Hardware** | `qke_full.py` | IBM Quantum Platform API integration | 5-30 min |
+
+### Hardware Access
+
+For IBM Quantum hardware execution:
+
+```bash
+export QISKIT_IBM_TOKEN='your-token-here'
+python src/qke_full.py
+```
+
+Get your token at [quantum.ibm.com](https://quantum.ibm.com) → Account → API Token.
+
+---
+
+## Output Directory Semantics
+
+The project uses a flexible output routing system via `--output-tag`:
+
+| Flag | Results Directory | Plots Directory | Analysis Report |
+|------|-------------------|-----------------|-----------------|
+| (none) | `results/` | `plots/` | `docs/analysis_report.md` |
+| `--output-tag raw` | `results_raw/` | `plots_raw/` | `docs/analysis_report_raw.md` |
+| `--output-tag psd` | `results_psd/` | `plots_psd/` | `docs/analysis_report_psd.md` |
+
+### Output Files
+
+Each execution generates:
+
+```
+results[_TAG]/
+├── train_kernel_{ideal,noisy,hardware}.npy   # Kernel matrices (N_train × N_train)
+├── test_kernel_{ideal,noisy,hardware}.npy    # Test kernels (N_test × N_train)
+├── metrics_{ideal,noisy,hardware}.json       # Accuracy, F1, noise params
+├── noise_impact_stats.json                   # Kernel degradation analysis
+└── comprehensive_analysis.json               # Full cross-implementation comparison
+
+plots[_TAG]/
+├── kernel_matrices_{ideal,noisy,hardware}.png
+├── accuracy_comparison.png
+├── kernel_error_heatmap.png
+└── noise_impact_comparison.png
+```
+
+---
+
+## CLI Reference
+
+All scripts support these common flags:
+
+| Flag | Description | Default |
+|------|-------------|---------|
+| `--output-tag TAG` | Route outputs to `results_TAG/`, `plots_TAG/` | None |
+| `--psd-project` | Enable PSD projection on training kernel | Disabled |
+| `--psd-epsilon FLOAT` | Minimum eigenvalue threshold for PSD | 1e-10 |
+
+**Examples:**
+
+```bash
+# Standard execution (default directories)
+python src/qke_model.py
+
+# RAW experiment (no PSD projection)
+python src/qke_model.py --output-tag raw
+
+# PSD experiment (projection enabled)
+python src/qke_model.py --output-tag psd --psd-project --psd-epsilon 1e-10
+```
+
+---
+
+## Results Summary
+
+Results from the RAW vs PSD experiment (100 samples, 70/30 train/test split):
+
+### Accuracy Comparison
+
+| Simulator | Metric | RAW | PSD | Delta |
+|-----------|--------|-----|-----|-------|
+| **Ideal** | Train | 82.9% | 84.3% | +1.4% |
+| **Ideal** | Test | 70.0% | 66.7% | -3.3% |
+| **Noisy** | Train | 84.3% | 85.7% | +1.4% |
+| **Noisy** | Test | 66.7% | 66.7% | 0.0% |
+
+### Noise Model Parameters
+
+| Parameter | Value | Source |
+|-----------|-------|--------|
+| T1 relaxation | 200 µs | IBM Brisbane (2026) |
+| T2 dephasing | 135 µs | IBM Brisbane (2026) |
+| Single-qubit error | 0.15% | Calibration data |
+| Two-qubit (ECR) error | 0.80% | Calibration data |
+| Readout error | 2.5% | Calibration data |
+| Shots | 1024 | Default |
+
+### Kernel Matrix Differences (RAW vs PSD)
+
+| Kernel | Frobenius Norm | Mean Δ | Max Δ |
+|--------|----------------|--------|-------|
+| Ideal Train | 0.878 | 0.97% | 4.8% |
+| Ideal Test | 0.799 | 1.3% | 7.5% |
+| Noisy Train | 1.209 | 1.3% | 6.8% |
+| Noisy Test | 0.796 | 1.3% | 7.1% |
+
+**Key Finding:** PSD projection has minimal impact on well-conditioned kernels (negative eigenvalues at the 1e-15 level are numerical noise, not physical). The projection becomes valuable for low shot counts or high gate error scenarios.
+
+---
+
+## Project Structure
+
+```
+ibm-qml-kernel/
+├── src/
+│   ├── qke_model.py           # Ideal quantum kernel estimation
+│   ├── qke_noisy.py           # Noise-modeled implementation
+│   ├── qke_full.py            # IBM Quantum API integration
+│   ├── analyze_results.py     # Comprehensive analysis suite
+│   ├── kernel_utils.py        # PSD projection utilities
+│   └─��� path_utils.py          # Output directory routing
+├── tools/
+│   └── compare_raw_vs_psd.py  # RAW vs PSD comparison script
+├── data/
+│   └── ibm_hardware_params_2026.json  # Hardware calibration parameters
+├── tests/
+│   └── test_basic.py          # Unit tests (11 tests, 4 PSD-specific)
+├── docs/
+│   ├── EXECUTION_GUIDE.md     # Detailed execution instructions
+│   ├── analysis_report.md     # Generated analysis report
+│   └── raw_vs_psd_report.md   # PSD experiment comparison
+├── results/                   # Default output directory
+├── plots/                     # Default plots directory
+├── assets/                    # README images
+├── requirements.txt
+├── pyproject.toml
+└── README.md
+```
+
+---
+
+## Installation
+
+### Prerequisites
+- Python 3.10 or higher
+- Virtual environment (recommended)
+
+### Steps
+
+```bash
+# 1. Create virtual environment
+python -m venv venv
+source venv/bin/activate  # Windows: venv\Scripts\activate
+
+# 2. Install dependencies
+pip install -r requirements.txt
+# Or: pip install -e .
+
+# 3. Verify installation
+python tests/test_basic.py
+```
+
+### Dependencies
+
+```
+qiskit>=1.0
+qiskit-aer>=0.14
+qiskit-machine-learning>=0.7
+qiskit-ibm-runtime>=0.20  # For hardware access
+scikit-learn>=1.3
+numpy>=1.24
+matplotlib>=3.7
+```
+
+---
+
+## RAW vs PSD Experiment
+
+Compare quantum kernel performance with and without PSD projection:
+
+```bash
+# 1. RAW pipeline (no PSD projection)
+python src/qke_model.py --output-tag raw
+python src/qke_noisy.py --output-tag raw
+python src/analyze_results.py --output-tag raw
+
+# 2. PSD pipeline (projection enabled)
+python src/qke_model.py --output-tag psd --psd-project --psd-epsilon 1e-10
+python src/qke_noisy.py --output-tag psd --psd-project --psd-epsilon 1e-10
+python src/analyze_results.py --output-tag psd
+
+# 3. Generate comparison report
+python tools/compare_raw_vs_psd.py
+```
+
+**Outputs:**
+- `docs/raw_vs_psd_report.md` — Markdown comparison
+- `docs/raw_vs_psd_comparison.json` — JSON data
+
+---
+
+## Interpreting Results
+
+### Kernel Matrices
+
+Kernel matrices represent quantum state overlap (similarity):
+- **Diagonal elements**: Self-similarity (should be ≈1.0)
+- **Off-diagonal elements**: Cross-similarity (affected by noise)
+- **Color intensity**: Higher values = more similar quantum states
+
+### Accuracy Metrics
+
+| Metric | Description | Typical Range |
+|--------|-------------|---------------|
+| Train Accuracy | Performance on training data | 80-100% (ideal), 75-95% (noisy) |
+| Test Accuracy | Generalization to unseen data | 70-95% (ideal), 65-90% (noisy) |
+| Degradation | Ideal − Noisy accuracy gap | 5-15% |
+
+### Kernel Alignment
+
+Measures similarity between two kernel matrices:
+- **1.0**: Perfect alignment (identical kernels)
+- **0.8-0.95**: Good noise tolerance
+- **<0.8**: Significant noise degradation
+
+---
+
+## Branch-Transfer Experiment (Inter-Branch Communication) — Hardware Implementation
+
+<picture>
+  <source media="(prefers-color-scheme: dark)" srcset="assets/branch_transfer_circuit_dark.png">
+  <img src="assets/branch_transfer_circuit_light.png"
+       alt="Branch-transfer (inter-branch communication) 5-qubit circuit primitive with protocol stages"
+       width="900">
+</picture>
+
+<p><em><strong>Figure:</strong> 5-qubit branch-transfer primitive executed on IBM hardware (ibm_fez). Shaded bands mark protocol stages (prep→corr→rec→msg→copy→erase→swap); final measurements feed visibility and coherence-witness diagnostics.</em></p>
+
+Motivated by the Violaris proposal for an inter-branch communication protocol in a Wigner's-friend-style setting ([arXiv:2601.08102](https://arxiv.org/abs/2601.08102)), this repository provides a hardware-executed implementation with coherence-witness diagnostics. The 5-qubit branch-transfer protocol was executed on superconducting quantum hardware (ibm_fez) and analyzed using coherence witness measurements.
+
+### What Was Implemented
+
+**Branch-transfer circuit primitive:**
+- 5-qubit protocol implementing branch-conditioned message transfer
+- Registers: Q (measured qubit), R (branch record), F (friend/observer), M (message buffer), P (paper/persistent record)
+- Visibility readout (V): Population-based metric V = P(P=1|R=0) - P(P=1|R=1)
+
+**Coherence-witness measurement suite:**
+- **W_X and W_Y**: Multi-qubit parity correlators on (Q,R,F,P) after basis rotations
+  - W_X = ⟨X_Q ⊗ X_R ⊗ X_F ⊗ X_P⟩ (measures coherence in X-basis)
+  - W_Y = ⟨Y_Q ⊗ Y_R ⊗ Y_F ⊗ Y_P⟩ (measures coherence in Y-basis)
+- **C_magnitude** = sqrt(W_X² + W_Y²): Phase-robust magnitude
+
+**Critical interpretation constraints:**
+- C_magnitude is **NOT** bounded by 1 and must not be described as a "coherence fraction" or probability. It is a correlation magnitude that can exceed 1. Since W_X, W_Y ∈ [-1,1], we have C_magnitude ≤ √2 for Pauli correlators.
+- W_Y_ideal = 0 in this dataset; therefore, normalized Y coherence (W̃_Y) is undefined. Raw W_Y is still reported and physically meaningful.
+
+**Related work:** See Violaris (2026, arXiv:2601.08102) for the conceptual framing of inter-branch communication protocols.
+
+### Why Visibility Alone Is Insufficient
+
+The visibility metric V is population-based and measures only diagonal elements in the Z-basis:
+- **V is insensitive to dephasing**: Dephasing in the computational basis preserves diagonal populations while destroying off-diagonal coherences
+- **Some decoherence placements do not change V**: Post-measurement dephasing or purely off-diagonal decoherence can be invisible to V
+- **Coherence witnesses probe off-diagonals**: W_X and W_Y measure superposition structure that V cannot detect, providing complementary information about quantum coherence
+
+### Quickstart: Reproduce the Results
+
+**Tier 1: Simulation Only (No Hardware Access Required)**
+
+```bash
+# Install dependencies
+pip install -e .[dev]
+
+# Run ideal simulation (statevector, no noise)
+python -m experiments.branch_transfer.run_sim --mode coherence_witness --include-y-basis --shots 20000
+
+# Run visibility protocol (ideal)
+python -m experiments.branch_transfer.run_sim --mode rp_z --mu 1 --shots 20000
+
+# Run backend-matched noisy simulation (uses IBM hardware noise model)
+python -m experiments.branch_transfer.run_sim --mode coherence_witness --include-y-basis --shots 20000 --noise-from-backend ibm_fez
+
+# Generate plots and analysis
+python -m experiments.branch_transfer.analyze --artifacts-dir artifacts/branch_transfer --figures-dir artifacts/branch_transfer/figures --plot-all
+```
+
+**Expected runtime:** 2-5 minutes on CPU
+
+**Tier 2: IBM Hardware (Requires IBM Quantum Access)**
+
+**Prerequisites:**
+- qiskit-ibm-runtime installed (included in requirements.txt)
+- IBM Quantum account saved via:
+  ```python
+  from qiskit_ibm_runtime import QiskitRuntimeService
+  QiskitRuntimeService.save_account(channel="ibm_quantum", token="YOUR_TOKEN")
+  ```
+- Get your token at [quantum.ibm.com](https://quantum.ibm.com) → Account → API Token
+
+**List available backends and select least busy:**
+```bash
+python -c "from qiskit_ibm_runtime import QiskitRuntimeService as S; s=S(); bs=s.backends(simulator=False, operational=True); print('Available:', [b.name for b in bs[:5]]); lb=s.least_busy(simulator=False, operational=True); print('Least busy:', lb.name)"
+```
+
+**Run on hardware:**
+```bash
+# Coherence witness measurement (X+Y basis)
+python -m experiments.branch_transfer.run_ibm --backend ibm_fez --mode coherence_witness --include-y-basis --shots 20000 --optimization-level 2
+
+# Visibility protocol
+python -m experiments.branch_transfer.run_ibm --backend ibm_fez --mode rp_z --mu 1 --shots 20000 --optimization-level 2
+```
+
+**Note:** The `--backend` flag is supported and allows you to specify any operational IBM Quantum backend (e.g., `--backend ibm_fez`). If omitted, the script selects the least busy backend automatically.
+
+**Expected runtime:** 5-30 minutes (queue time + execution)
+
+### Latest Hardware Run (Provenance)
+
+**Backend:** ibm_fez (156-qubit Heron processor, open plan)
+**Shots:** 20,000 per experiment
+**Optimization level:** 2 (hardware), 1 (simulator)
+**Date:** 2026-01-17
+
+**Job IDs:**
+- Coherence witness (X basis): d5lobdt9j2ac739k1a0g
+- Coherence witness (Y basis): d5locdhh2mqc739a2ubg
+- Visibility protocol (rp_z): d5locnd9j2ac739k1b80
+
+**Headline metrics:**
+
+| Metric | Hardware (ibm_fez) | Ideal Sim | Backend-Matched Noisy Sim |
+|--------|-------------------|-----------|---------------------------|
+| **V** (visibility) | 0.8771 ± 0.0034 | 1.0000 | 0.9381 |
+| **W_X** (X coherence) | 0.8398 ± 0.0038 | 1.0000 | 0.8984 |
+| **W_Y** (Y coherence) | -0.8107 ± 0.0041 | 0.0000* | -0.8972 |
+| **C_magnitude** | 1.1673 ± 0.0040 | 1.4142 | 1.2697 |
+
+*Although the theoretical ideal statevector gives W_Y = −1, the stored artifact field W_Y_ideal is recorded as 0 in this dataset due to how combined X/Y ideal baselines are merged, so Y-normalization is undefined and we report raw W_Y only.
+
+**Key finding:** Hardware visibility (V=0.877) closely matched backend-matched simulation (V=0.938), demonstrating robust protocol performance. The coherence magnitude C = 1.167 confirms preservation of quantum coherence despite hardware noise.
+
+### Artifacts & Reproducibility
+
+**Dataset Structure:**
+
+This dataset repository provides extracted experimental artifacts for programmatic access alongside the original archival bundle.
+
+```
+├── artifacts/
+│   └── branch_transfer/          # Primary experimental results
+│       ├── *.json                # 31 result files (hardware + simulation)
+│       ├── calibration/          # Backend calibration snapshots (3 files)
+│       │   └── ibm_fez_*_properties.json
+│       └── figures/              # Generated analysis plots (7 PNG + 7 PDF)
+│           ├── coherence_comparison.png
+│           ├── coherence_forecast_dephase_ideal_X.png
+│           ├── collapse_forecast_dephase_{ideal,noisy}.png
+│           ├── pr_distribution.png
+│           ├── visibility_comparison.png
+│           └── visibility_vs_opt_level.png
+├── manifest/
+│   ├── runs.csv                  # Tabular index (30 runs) for datasets library
+│   └── SHA256SUMS.txt            # File integrity checksums (55 entries)
+├── original/
+│   └── branch_transfer_arxiv_bundle_v2b.zip  # Archival parity ZIP (4.3 MB)
+├── paper/
+│   ├── arXiv.pdf                 # Manuscript (402 KB)
+│   ├── arXiv.tex                 # LaTeX source (31 KB)
+│   └── refs.bib                  # Bibliography (5.1 KB)
+├── README.md                      # This file
+├── LICENSE                        # MIT License
+└── CITATION.cff                   # Citation metadata
+
+Total: 60 files
+```
+
+**Primary Result Files (8 key experiments):**
+
+| File | Type | Backend | Shots | Job ID |
+|------|------|---------|-------|--------|
+| `hw_coherence_20260117_205321_..._opt-0.json` | Hardware | ibm_fez | 20,000 | d5lobdt9j2ac739k1a0g, d5locdhh2mqc739a2ubg |
+| `hw_20260117_205401_..._opt-2.json` | Hardware | ibm_fez | 20,000 | d5locnd9j2ac739k1b80 |
+| `coherence_*_statevector_*.json` (×2) | Ideal | statevector | 20,000 | - |
+| `coherence_*_noisy_ibm_fez_*.json` (×2) | Noisy | ibm_fez noise | 20,000 | - |
+| `sim_*_statevector_*.json` | Ideal | statevector | 20,000 | - |
+| `sim_*_noisy_ibm_fez_*.json` | Noisy | ibm_fez noise | 20,000 | - |
+
+**Programmatic Loading:**
+
+```python
+from datasets import load_dataset
+import pandas as pd
+
+# Load manifest
+ds = load_dataset("Cohaerence/ibm-qml-kernel", data_files="manifest/runs.csv")
+runs = pd.DataFrame(ds['train'])
+
+# Filter hardware runs
+hw_runs = runs[runs['run_type'] == 'hardware']
+print(hw_runs[['backend', 'mode', 'shots', 'job_id']])
+
+# Load specific result
+import json
+with open('artifacts/branch_transfer/hw_20260117_205401_ibm_fez_main_mu-1_shots-20000_opt-2.json') as f:
+    result = json.load(f)
+    print(f"Visibility: {result['visibility']:.4f} ± {result['visibility_error']:.4f}")
+```
+
+**Verify File Integrity:**
+```bash
+cd /path/to/dataset
+shasum -a 256 -c manifest/SHA256SUMS.txt
+# Expected: All files report "OK"
+```
+
+**Original Bundle:**
+The ZIP file at `original/branch_transfer_arxiv_bundle_v2b.zip` preserves byte-for-byte parity with the arXiv submission bundle for archival compliance.
+
+### Collapse / Nonunitary Channel Constraint Analysis
+
+**Method:**
+The protocol is used to constrain parameterized nonunitary channels (e.g., dephasing, amplitude damping) by:
+1. Implementing the full protocol on ideal and noisy simulators
+2. Comparing diagonal observables (visibility V) vs off-diagonal observables (coherence witnesses W_X, W_Y)
+3. Sweeping a parameterized collapse channel (gamma parameter) and forecasting detectability against device noise
+
+**Analysis:**
+- **Visibility (V) is insensitive to dephasing**: Post-measurement dephasing in the Z-basis preserves diagonal populations, leaving V unchanged across all gamma values
+- **Coherence witnesses (W_X, W_Y) detect dephasing**: At gamma=0.05, the coherence deviation exceeds shot noise uncertainty (2-sigma threshold), while V remains unaffected
+- **Detectability threshold**: gamma ≈ 0.05 for coherence-based detection with 20k shots
+
+**Interpretation:**
+This analysis constrains specific parameterized channels (e.g., continuous spontaneous localization-style dephasing) by demonstrating that coherence-based observables provide complementary sensitivity beyond population measurements. **This does not prove or disprove Many-Worlds or any specific unitary interpretation**—it operationally constrains collapse-model parameter space within the measurement precision of current hardware.
+
+**Run the analysis:**
+```bash
+# Coherence-based collapse model forecast (recommended for dephasing detection)
+python -m experiments.branch_transfer.collapse_models --mode coherence_witness --gamma-sweep --collapse-model dephase
+
+# Add backend-matched hardware noise
+python -m experiments.branch_transfer.collapse_models --mode coherence_witness --gamma-sweep --collapse-model dephase --add-hardware-noise
+```
+
+### Scaling Roadmap
+
+**Branch divergence scaling:**
+The protocol represents friend-0 and friend-1 measurement outcomes as orthogonal branches. To scale this:
+
+1. **Increase branching complexity**: Represent friend outcomes as longer bitstrings (e.g., 2-qubit friend → 4 branches, 3-qubit friend → 8 branches)
+2. **Swap complexity scaling**: The branch-swap operation (X-string on Q,R,F) generalizes to an X-string whose length scales with Hamming distance between branch labels
+3. **Witness degradation analysis**: Measure how coherence witness fidelity (W_X, W_Y, C_magnitude) degrades as a function of:
+   - Number of qubits in the swap operation
+   - Circuit depth increase from additional branching
+   - Hamming distance between swapped branches
+
+**Concrete example (implementable):**
+- Current: 1-qubit friend (2 branches), 3-qubit swap (X on Q,R,F)
+- Next: 2-qubit friend (4 branches), 4-5 qubit swap depending on branch pair
+- Analysis: Plot C_magnitude vs. (swap depth, Hamming distance, hardware noise level)
+
+This provides a concrete path to study how inter-branch communication degrades with system complexity and is directly implementable on current IBM hardware (up to ~10 qubits before depth/noise tradeoffs dominate).
+
+---
+
+## Roadmap
+
+- [ ] **Error mitigation**: Implement zero-noise extrapolation (ZNE) and probabilistic error cancellation (PEC)
+- [ ] **Scalability**: Extend to 4+ qubits with advanced feature maps
+- [ ] **Hardware runs**: Execute on IBM Brisbane/Kyoto with real queue submission
+- [ ] **Kernel alignment optimization**: Trainable feature map parameters
+- [ ] **Benchmarking**: Compare against classical kernels (RBF, polynomial) on standard datasets
+- [ ] **Branch-transfer scaling**: Implement multi-qubit friend register and measure witness degradation vs swap complexity
+
+---
+
+## References
+
+1. Havlíček, V., et al. (2019). Supervised learning with quantum-enhanced feature spaces. *Nature*, 567(7747), 209–212. [DOI: 10.1038/s41586-019-0980-2](https://doi.org/10.1038/s41586-019-0980-2)
+
+2. Schuld, M., & Killoran, N. (2019). Quantum machine learning in feature Hilbert spaces. *Physical Review Letters*, 122(4), 040504. [DOI: 10.1103/PhysRevLett.122.040504](https://doi.org/10.1103/PhysRevLett.122.040504)
+
+3. IBM Quantum Documentation (2026). Hardware specifications for Eagle r3 processors. [quantum.ibm.com/docs](https://quantum.ibm.com/docs)
+
+4. Temme, K., Bravyi, S., & Gambetta, J. M. (2017). Error mitigation for short-depth quantum circuits. *Physical Review Letters*, 119(18), 180509. [DOI: 10.1103/PhysRevLett.119.180509](https://doi.org/10.1103/PhysRevLett.119.180509)
+
+5. Abbas, A., et al. (2021). The power of quantum neural networks. *Nature Computational Science*, 1(6), 403–409. [DOI: 10.1038/s43588-021-00084-1](https://doi.org/10.1038/s43588-021-00084-1)
+
+6. Violaris, M. (2026). Quantum observers can communicate across multiverse branches. *arXiv:2601.08102*. [arXiv:2601.08102](https://arxiv.org/abs/2601.08102)
+
+---
+
+## Citations
+
+If you use this project in your research, please cite:
+
+```bibtex
+@software{altman2026ibmqmlkernel,
+  author       = {Altman, Christopher},
+  title        = {Quantum Kernel Methods on IBM Quantum Hardware},
+  year         = {2026},
+  url          = {https://github.com/christopher-altman/ibm-qml-kernel},
+  note         = {Quantum kernel estimation with IBM hardware noise modeling and PSD projection}
+}
+```
+
+---
+
+## License
+
+MIT License. See [LICENSE](LICENSE) for details.
+
+---
+
+## Contact
+
+- **Website:** [christopheraltman.com](https://christopheraltman.com)
+- **Research portfolio:** https://lab.christopheraltman.com/
+- **GitHub:** [github.com/christopher-altman](https://github.com/christopher-altman)
+- **Google Scholar:** [scholar.google.com/citations?user=tvwpCcgAAAAJ](https://scholar.google.com/citations?user=tvwpCcgAAAAJ)
+- **Email:** x@christopheraltman.com
+
+---
+
+*Christopher Altman (2026)*

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+  "backend": "aer_simulator_noisy_ibm_fez",
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+  "noise_source": "ibm_fez",
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artifacts/branch_transfer/coherence_sweep_20260117_161744_dephase_ideal_X.json

@@ -0,0 +1,984 @@
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artifacts/branch_transfer/coherence_sweep_20260117_161918_dephase_ideal_X.json

@@ -0,0 +1,1152 @@
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artifacts/branch_transfer/coherence_sweep_20260117_162148_dephase_ideal_X.json

@@ -0,0 +1,1136 @@
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artifacts/branch_transfer/collapse_sweep_20260117_155000_dephase_ideal.json

@@ -0,0 +1,811 @@
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artifacts/branch_transfer/collapse_sweep_20260117_155009_dephase_noisy.json

@@ -0,0 +1,895 @@
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+  ]
+}

artifacts/branch_transfer/comprehensive_analysis.json

@@ -0,0 +1,34 @@
+{
+  "timestamp": "2026-01-24T15:08:53.916029",
+  "artifacts_dir": "artifacts/branch_transfer",
+  "total_results": 31,
+  "ideal_summary": {
+    "count": 5,
+    "mean": 0.8,
+    "std": 0.4,
+    "min": 0.0,
+    "max": 1.0,
+    "mean_error": 0.0
+  },
+  "noisy_summary": {
+    "count": 8,
+    "mean": 0.7681544252625738,
+    "std": 0.29119438214526644,
+    "min": 0.00017642614139398022,
+    "max": 0.9381436161259128,
+    "mean_error": 0.003251119909366172
+  },
+  "hardware_summary": {
+    "count": 2,
+    "mean": 0.8772747136791494,
+    "std": 0.00017173849031870692,
+    "min": 0.8771029751888307,
+    "max": 0.8774464521694681,
+    "mean_error": 0.003400592665601571
+  },
+  "results_table": "| Backend | Mode | \u03bc | Shots | V | V_err | Depth | 2Q Gates |\n|---------|------|---|-------|---|-------|-------|----------|\n| noisy_simulator | - | 1 | 10000 | 0.0000 | 0.0000 | 8 | 5 |\n| ideal | - | 1 | 10000 | 0.0000 | 0.0000 | 9 | 5 |\n| noisy_simulator | - | 1 | 20000 | 0.0000 | 0.0000 | 9 | 5 |\n| ideal | - | 1 | 20000 | 0.0000 | 0.0000 | 10 | 5 |\n| ideal | - | 1 | 20000 | 0.0000 | 0.0000 | 9 | 5 |\n| noisy_simulator | - | 1 | 20000 | 0.0000 | 0.0000 | 21 | 5 |\n| ideal | - | 1 | 20000 | 0.0000 | 0.0000 | 10 | 5 |\n| noisy_simulator | - | 1 | 20000 | 0.0000 | 0.0000 | 20 | 5 |\n| unknown | - | - | - | 0.0000 | 0.0000 | - | - |\n| unknown | - | - | - | 0.0000 | 0.0000 | - | - |\n| unknown | - | - | - | 0.0000 | 0.0000 | - | - |\n| unknown | - | - | - | 0.0000 | 0.0000 | - | - |\n| unknown | - | - | - | 0.0000 | 0.0000 | - | - |\n| unknown | - | - | - | 0.0000 | 0.0000 | - | - |\n| hardware | main | 1 | 20000 | 0.8774 | 0.0034 | 16 | 5 |\n| hardware | main | 1 | 20000 | 0.8771 | 0.0034 | 16 | 5 |\n| hardware | coherence_witness_full | 1 | 20000 | 0.0000 | 0.0000 | - | - |\n| hardware | coherence_witness_full | 1 | 20000 | 0.0000 | 0.0000 | - | - |\n| noisy_simulator | main | 1 | 20000 | 0.8629 | 0.0036 | 8 | 5 |\n| noisy_simulator | main | 1 | 20000 | 0.8651 | 0.0035 | 8 | 5 |\n| noisy_simulator | main | 1 | 20000 | 0.8699 | 0.0035 | 8 | 5 |\n| noisy_simulator | main | 1 | 20000 | 0.8686 | 0.0035 | 8 | 5 |\n| ideal | main | 1 | 20000 | 1.0000 | 0.0000 | 8 | 5 |\n| noisy_simulator | control | 1 | 20000 | 0.8734 | 0.0034 | 7 | 4 |\n| noisy_simulator | main | 0 | 20000 | 0.0002 | 0.0025 | 7 | 4 |\n| ideal | control | 1 | 20000 | 1.0000 | 0.0000 | 7 | 4 |\n| ideal | main | 0 | 20000 | 0.0000 | 0.0000 | 7 | 4 |\n| ideal | main | 1 | 20000 | 1.0000 | 0.0000 | 8 | 5 |\n| noisy_simulator | main | 1 | 20000 | 0.8670 | 0.0035 | 8 | 5 |\n| ideal | main | 1 | 20000 | 1.0000 | 0.0000 | 8 | 5 |\n| noisy_simulator | main | 1 | 20000 | 0.9381 | 0.0024 | 40 | 5 |",
+  "visibility_degradation": {
+    "ideal_to_noisy": 0.03184557473742622,
+    "relative_loss": 0.039806968421782774
+  }
+}

artifacts/branch_transfer/hw_20260117_202107_ibm_fez_main_mu-1_shots-20000_opt-2.json

@@ -0,0 +1,64 @@
+{
+  "backend": "ibm_fez",
+  "backend_type": "hardware",
+  "backend_config": {
+    "backend_name": "ibm_fez",
+    "num_qubits": 156,
+    "processor_type": "Heron"
+  },
+  "job_id": "d5lnta59j2ac739k0t90",
+  "mode": "main",
+  "mu": 1,
+  "shots": 20000,
+  "actual_shots": 20000,
+  "counts": {
+    "11": 486,
+    "10": 8905,
+    "01": 9880,
+    "00": 729
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+  "probabilities": {
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+    "10": 0.44525,
+    "01": 0.494,
+    "00": 0.03645
+  },
+  "visibility": 0.8774464521694681,
+  "visibility_error": 0.003401602436805138,
+  "conditional_probabilities": {
+    "P(P=1|R=0)": 0.9243304961594353,
+    "P(P=1|R=1)": 0.0468840439899672,
+    "n_R0": 9634,
+    "n_R1": 10366
+  },
+  "expected_distribution": {
+    "01": 0.5,
+    "10": 0.5
+  },
+  "circuit_stats": {
+    "num_qubits": 5,
+    "num_clbits": 2,
+    "depth": 7,
+    "size": 11,
+    "gate_counts": {
+      "h": 1,
+      "cx": 5,
+      "x": 3
+    },
+    "two_qubit_gate_count": 5
+  },
+  "transpiled_depth": 16,
+  "transpiled_size": 35,
+  "transpiled_two_qubit_gates": 5,
+  "optimization_level": 2,
+  "physical_layout": {
+    "initial_layout": "Layout({\n2: <Qubit register=(5, \"q\"), index=0>,\n4: <Qubit register=(5, \"q\"), index=1>,\n3: <Qubit register=(5, \"q\"), index=2>,\n16: <Qubit register=(5, \"q\"), index=3>,\n23: <Qubit register=(5, \"q\"), index=4>,\n0: <Qubit register=(151, \"ancilla\"), index=0>,\n1: <Qubit register=(151, \"ancilla\"), index=1>,\n5: <Qubit register=(151, \"ancilla\"), index=2>,\n6: <Qubit register=(151, \"ancilla\"), index=3>,\n7: <Qubit register=(151, \"ancilla\"), index=4>,\n8: <Qubit register=(151, \"ancilla\"), index=5>,\n9: <Qubit register=(151, \"ancilla\"), index=6>,\n10: <Qubit register=(151, \"ancilla\"), index=7>,\n11: <Qubit register=(151, \"ancilla\"), index=8>,\n12: <Qubit register=(151, \"ancilla\"), index=9>,\n13: <Qubit register=(151, \"ancilla\"), index=10>,\n14: <Qubit register=(151, \"ancilla\"), index=11>,\n15: <Qubit register=(151, \"ancilla\"), index=12>,\n17: <Qubit register=(151, \"ancilla\"), index=13>,\n18: <Qubit register=(151, \"ancilla\"), index=14>,\n19: <Qubit register=(151, \"ancilla\"), index=15>,\n20: <Qubit register=(151, \"ancilla\"), index=16>,\n21: <Qubit register=(151, \"ancilla\"), index=17>,\n22: <Qubit register=(151, \"ancilla\"), index=18>,\n24: <Qubit register=(151, \"ancilla\"), index=19>,\n25: <Qubit register=(151, \"ancilla\"), index=20>,\n26: <Qubit register=(151, \"ancilla\"), index=21>,\n27: <Qubit register=(151, \"ancilla\"), index=22>,\n28: <Qubit register=(151, \"ancilla\"), index=23>,\n29: <Qubit register=(151, \"ancilla\"), index=24>,\n30: <Qubit register=(151, \"ancilla\"), index=25>,\n31: <Qubit register=(151, \"ancilla\"), index=26>,\n32: <Qubit register=(151, \"ancilla\"), index=27>,\n33: <Qubit register=(151, \"ancilla\"), index=28>,\n34: <Qubit register=(151, \"ancilla\"), index=29>,\n35: <Qubit register=(151, \"ancilla\"), index=30>,\n36: <Qubit register=(151, \"ancilla\"), index=31>,\n37: <Qubit register=(151, \"ancilla\"), index=32>,\n38: <Qubit register=(151, \"ancilla\"), index=33>,\n39: <Qubit register=(151, \"ancilla\"), index=34>,\n40: <Qubit register=(151, \"ancilla\"), index=35>,\n41: <Qubit register=(151, \"ancilla\"), index=36>,\n42: <Qubit register=(151, \"ancilla\"), index=37>,\n43: <Qubit register=(151, \"ancilla\"), index=38>,\n44: <Qubit register=(151, \"ancilla\"), index=39>,\n45: <Qubit register=(151, \"ancilla\"), index=40>,\n46: <Qubit register=(151, \"ancilla\"), index=41>,\n47: <Qubit register=(151, \"ancilla\"), index=42>,\n48: <Qubit register=(151, \"ancilla\"), index=43>,\n49: <Qubit register=(151, \"ancilla\"), index=44>,\n50: <Qubit register=(151, \"ancilla\"), index=45>,\n51: <Qubit register=(151, \"ancilla\"), index=46>,\n52: <Qubit register=(151, \"ancilla\"), index=47>,\n53: <Qubit register=(151, \"ancilla\"), index=48>,\n54: <Qubit register=(151, \"ancilla\"), index=49>,\n55: <Qubit register=(151, \"ancilla\"), index=50>,\n56: <Qubit register=(151, \"ancilla\"), index=51>,\n57: <Qubit register=(151, \"ancilla\"), index=52>,\n58: <Qubit register=(151, \"ancilla\"), index=53>,\n59: <Qubit register=(151, \"ancilla\"), index=54>,\n60: <Qubit register=(151, \"ancilla\"), index=55>,\n61: <Qubit register=(151, \"ancilla\"), index=56>,\n62: <Qubit register=(151, \"ancilla\"), index=57>,\n63: <Qubit register=(151, \"ancilla\"), index=58>,\n64: <Qubit register=(151, \"ancilla\"), index=59>,\n65: <Qubit register=(151, \"ancilla\"), index=60>,\n66: <Qubit register=(151, \"ancilla\"), index=61>,\n67: <Qubit register=(151, \"ancilla\"), index=62>,\n68: <Qubit register=(151, \"ancilla\"), index=63>,\n69: <Qubit register=(151, \"ancilla\"), index=64>,\n70: <Qubit register=(151, \"ancilla\"), index=65>,\n71: <Qubit register=(151, \"ancilla\"), index=66>,\n72: <Qubit register=(151, \"ancilla\"), index=67>,\n73: <Qubit register=(151, \"ancilla\"), index=68>,\n74: <Qubit register=(151, \"ancilla\"), index=69>,\n75: <Qubit register=(151, \"ancilla\"), index=70>,\n76: <Qubit register=(151, \"ancilla\"), index=71>,\n77: <Qubit register=(151, \"ancilla\"), index=72>,\n78: <Qubit register=(151, \"ancilla\"), index=73>,\n79: <Qubit register=(151, \"ancilla\"), index=74>,\n80: <Qubit register=(151, \"ancilla\"), index=75>,\n81: <Qubit register=(151, \"ancilla\"), index=76>,\n82: <Qubit register=(151, \"ancilla\"), index=77>,\n83: <Qubit register=(151, \"ancilla\"), index=78>,\n84: <Qubit register=(151, \"ancilla\"), index=79>,\n85: <Qubit register=(151, \"ancilla\"), index=80>,\n86: <Qubit register=(151, \"ancilla\"), index=81>,\n87: <Qubit register=(151, \"ancilla\"), index=82>,\n88: <Qubit register=(151, \"ancilla\"), index=83>,\n89: <Qubit register=(151, \"ancilla\"), index=84>,\n90: <Qubit register=(151, \"ancilla\"), index=85>,\n91: <Qubit register=(151, \"ancilla\"), index=86>,\n92: <Qubit register=(151, \"ancilla\"), index=87>,\n93: <Qubit register=(151, \"ancilla\"), index=88>,\n94: <Qubit register=(151, \"ancilla\"), index=89>,\n95: <Qubit register=(151, \"ancilla\"), index=90>,\n96: <Qubit register=(151, \"ancilla\"), index=91>,\n97: <Qubit register=(151, \"ancilla\"), index=92>,\n98: <Qubit register=(151, \"ancilla\"), index=93>,\n99: <Qubit register=(151, \"ancilla\"), index=94>,\n100: <Qubit register=(151, \"ancilla\"), index=95>,\n101: <Qubit register=(151, \"ancilla\"), index=96>,\n102: <Qubit register=(151, \"ancilla\"), index=97>,\n103: <Qubit register=(151, \"ancilla\"), index=98>,\n104: <Qubit register=(151, \"ancilla\"), index=99>,\n105: <Qubit register=(151, \"ancilla\"), index=100>,\n106: <Qubit register=(151, \"ancilla\"), index=101>,\n107: <Qubit register=(151, \"ancilla\"), index=102>,\n108: <Qubit register=(151, \"ancilla\"), index=103>,\n109: <Qubit register=(151, \"ancilla\"), index=104>,\n110: <Qubit register=(151, \"ancilla\"), index=105>,\n111: <Qubit register=(151, \"ancilla\"), index=106>,\n112: <Qubit register=(151, \"ancilla\"), index=107>,\n113: <Qubit register=(151, \"ancilla\"), index=108>,\n114: <Qubit register=(151, \"ancilla\"), index=109>,\n115: <Qubit register=(151, \"ancilla\"), index=110>,\n116: <Qubit register=(151, \"ancilla\"), index=111>,\n117: <Qubit register=(151, \"ancilla\"), index=112>,\n118: <Qubit register=(151, \"ancilla\"), index=113>,\n119: <Qubit register=(151, \"ancilla\"), index=114>,\n120: <Qubit register=(151, \"ancilla\"), index=115>,\n121: <Qubit register=(151, \"ancilla\"), index=116>,\n122: <Qubit register=(151, \"ancilla\"), index=117>,\n123: <Qubit register=(151, \"ancilla\"), index=118>,\n124: <Qubit register=(151, \"ancilla\"), index=119>,\n125: <Qubit register=(151, \"ancilla\"), index=120>,\n126: <Qubit register=(151, \"ancilla\"), index=121>,\n127: <Qubit register=(151, \"ancilla\"), index=122>,\n128: <Qubit register=(151, \"ancilla\"), index=123>,\n129: <Qubit register=(151, \"ancilla\"), index=124>,\n130: <Qubit register=(151, \"ancilla\"), index=125>,\n131: <Qubit register=(151, \"ancilla\"), index=126>,\n132: <Qubit register=(151, \"ancilla\"), index=127>,\n133: <Qubit register=(151, \"ancilla\"), index=128>,\n134: <Qubit register=(151, \"ancilla\"), index=129>,\n135: <Qubit register=(151, \"ancilla\"), index=130>,\n136: <Qubit register=(151, \"ancilla\"), index=131>,\n137: <Qubit register=(151, \"ancilla\"), index=132>,\n138: <Qubit register=(151, \"ancilla\"), index=133>,\n139: <Qubit register=(151, \"ancilla\"), index=134>,\n140: <Qubit register=(151, \"ancilla\"), index=135>,\n141: <Qubit register=(151, \"ancilla\"), index=136>,\n142: <Qubit register=(151, \"ancilla\"), index=137>,\n143: <Qubit register=(151, \"ancilla\"), index=138>,\n144: <Qubit register=(151, \"ancilla\"), index=139>,\n145: <Qubit register=(151, \"ancilla\"), index=140>,\n146: <Qubit register=(151, \"ancilla\"), index=141>,\n147: <Qubit register=(151, \"ancilla\"), index=142>,\n148: <Qubit register=(151, \"ancilla\"), index=143>,\n149: <Qubit register=(151, \"ancilla\"), index=144>,\n150: <Qubit register=(151, \"ancilla\"), index=145>,\n151: <Qubit register=(151, \"ancilla\"), index=146>,\n152: <Qubit register=(151, \"ancilla\"), index=147>,\n153: <Qubit register=(151, \"ancilla\"), index=148>,\n154: <Qubit register=(151, \"ancilla\"), index=149>,\n155: <Qubit register=(151, \"ancilla\"), index=150>\n})",
+    "final_layout": null
+  },
+  "timestamp": "20260117_202107",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2",
+    "qiskit_ibm_runtime": "0.45.0"
+  }
+}

artifacts/branch_transfer/hw_20260117_205401_ibm_fez_main_mu-1_shots-20000_opt-2.json

@@ -0,0 +1,64 @@
+{
+  "backend": "ibm_fez",
+  "backend_type": "hardware",
+  "backend_config": {
+    "backend_name": "ibm_fez",
+    "num_qubits": 156,
+    "processor_type": "Heron"
+  },
+  "job_id": "d5locnd9j2ac739k1b80",
+  "mode": "main",
+  "mu": 1,
+  "shots": 20000,
+  "actual_shots": 20000,
+  "counts": {
+    "10": 9045,
+    "01": 9732,
+    "00": 731,
+    "11": 492
+  },
+  "probabilities": {
+    "10": 0.45225,
+    "01": 0.4866,
+    "00": 0.03655,
+    "11": 0.0246
+  },
+  "visibility": 0.8771029751888307,
+  "visibility_error": 0.0033995828943980035,
+  "conditional_probabilities": {
+    "P(P=1|R=0)": 0.9252250409165302,
+    "P(P=1|R=1)": 0.04812206572769953,
+    "n_R0": 9776,
+    "n_R1": 10224
+  },
+  "expected_distribution": {
+    "01": 0.5,
+    "10": 0.5
+  },
+  "circuit_stats": {
+    "num_qubits": 5,
+    "num_clbits": 2,
+    "depth": 7,
+    "size": 11,
+    "gate_counts": {
+      "h": 1,
+      "cx": 5,
+      "x": 3
+    },
+    "two_qubit_gate_count": 5
+  },
+  "transpiled_depth": 16,
+  "transpiled_size": 35,
+  "transpiled_two_qubit_gates": 5,
+  "optimization_level": 2,
+  "physical_layout": {
+    "initial_layout": "Layout({\n2: <Qubit register=(5, \"q\"), index=0>,\n4: <Qubit register=(5, \"q\"), index=1>,\n3: <Qubit register=(5, \"q\"), index=2>,\n16: <Qubit register=(5, \"q\"), index=3>,\n23: <Qubit register=(5, \"q\"), index=4>,\n0: <Qubit register=(151, \"ancilla\"), index=0>,\n1: <Qubit register=(151, \"ancilla\"), index=1>,\n5: <Qubit register=(151, \"ancilla\"), index=2>,\n6: <Qubit register=(151, \"ancilla\"), index=3>,\n7: <Qubit register=(151, \"ancilla\"), index=4>,\n8: <Qubit register=(151, \"ancilla\"), index=5>,\n9: <Qubit register=(151, \"ancilla\"), index=6>,\n10: <Qubit register=(151, \"ancilla\"), index=7>,\n11: <Qubit register=(151, \"ancilla\"), index=8>,\n12: <Qubit register=(151, \"ancilla\"), index=9>,\n13: <Qubit register=(151, \"ancilla\"), index=10>,\n14: <Qubit register=(151, \"ancilla\"), index=11>,\n15: <Qubit register=(151, \"ancilla\"), index=12>,\n17: <Qubit register=(151, \"ancilla\"), index=13>,\n18: <Qubit register=(151, \"ancilla\"), index=14>,\n19: <Qubit register=(151, \"ancilla\"), index=15>,\n20: <Qubit register=(151, \"ancilla\"), index=16>,\n21: <Qubit register=(151, \"ancilla\"), index=17>,\n22: <Qubit register=(151, \"ancilla\"), index=18>,\n24: <Qubit register=(151, \"ancilla\"), index=19>,\n25: <Qubit register=(151, \"ancilla\"), index=20>,\n26: <Qubit register=(151, \"ancilla\"), index=21>,\n27: <Qubit register=(151, \"ancilla\"), index=22>,\n28: <Qubit register=(151, \"ancilla\"), index=23>,\n29: <Qubit register=(151, \"ancilla\"), index=24>,\n30: <Qubit register=(151, \"ancilla\"), index=25>,\n31: <Qubit register=(151, \"ancilla\"), index=26>,\n32: <Qubit register=(151, \"ancilla\"), index=27>,\n33: <Qubit register=(151, \"ancilla\"), index=28>,\n34: <Qubit register=(151, \"ancilla\"), index=29>,\n35: <Qubit register=(151, \"ancilla\"), index=30>,\n36: <Qubit register=(151, \"ancilla\"), index=31>,\n37: <Qubit register=(151, \"ancilla\"), index=32>,\n38: <Qubit register=(151, \"ancilla\"), index=33>,\n39: <Qubit register=(151, \"ancilla\"), index=34>,\n40: <Qubit register=(151, \"ancilla\"), index=35>,\n41: <Qubit register=(151, \"ancilla\"), index=36>,\n42: <Qubit register=(151, \"ancilla\"), index=37>,\n43: <Qubit register=(151, \"ancilla\"), index=38>,\n44: <Qubit register=(151, \"ancilla\"), index=39>,\n45: <Qubit register=(151, \"ancilla\"), index=40>,\n46: <Qubit register=(151, \"ancilla\"), index=41>,\n47: <Qubit register=(151, \"ancilla\"), index=42>,\n48: <Qubit register=(151, \"ancilla\"), index=43>,\n49: <Qubit register=(151, \"ancilla\"), index=44>,\n50: <Qubit register=(151, \"ancilla\"), index=45>,\n51: <Qubit register=(151, \"ancilla\"), index=46>,\n52: <Qubit register=(151, \"ancilla\"), index=47>,\n53: <Qubit register=(151, \"ancilla\"), index=48>,\n54: <Qubit register=(151, \"ancilla\"), index=49>,\n55: <Qubit register=(151, \"ancilla\"), index=50>,\n56: <Qubit register=(151, \"ancilla\"), index=51>,\n57: <Qubit register=(151, \"ancilla\"), index=52>,\n58: <Qubit register=(151, \"ancilla\"), index=53>,\n59: <Qubit register=(151, \"ancilla\"), index=54>,\n60: <Qubit register=(151, \"ancilla\"), index=55>,\n61: <Qubit register=(151, \"ancilla\"), index=56>,\n62: <Qubit register=(151, \"ancilla\"), index=57>,\n63: <Qubit register=(151, \"ancilla\"), index=58>,\n64: <Qubit register=(151, \"ancilla\"), index=59>,\n65: <Qubit register=(151, \"ancilla\"), index=60>,\n66: <Qubit register=(151, \"ancilla\"), index=61>,\n67: <Qubit register=(151, \"ancilla\"), index=62>,\n68: <Qubit register=(151, \"ancilla\"), index=63>,\n69: <Qubit register=(151, \"ancilla\"), index=64>,\n70: <Qubit register=(151, \"ancilla\"), index=65>,\n71: <Qubit register=(151, \"ancilla\"), index=66>,\n72: <Qubit register=(151, \"ancilla\"), index=67>,\n73: <Qubit register=(151, \"ancilla\"), index=68>,\n74: <Qubit register=(151, \"ancilla\"), index=69>,\n75: <Qubit register=(151, \"ancilla\"), index=70>,\n76: <Qubit register=(151, \"ancilla\"), index=71>,\n77: <Qubit register=(151, \"ancilla\"), index=72>,\n78: <Qubit register=(151, \"ancilla\"), index=73>,\n79: <Qubit register=(151, \"ancilla\"), index=74>,\n80: <Qubit register=(151, \"ancilla\"), index=75>,\n81: <Qubit register=(151, \"ancilla\"), index=76>,\n82: <Qubit register=(151, \"ancilla\"), index=77>,\n83: <Qubit register=(151, \"ancilla\"), index=78>,\n84: <Qubit register=(151, \"ancilla\"), index=79>,\n85: <Qubit register=(151, \"ancilla\"), index=80>,\n86: <Qubit register=(151, \"ancilla\"), index=81>,\n87: <Qubit register=(151, \"ancilla\"), index=82>,\n88: <Qubit register=(151, \"ancilla\"), index=83>,\n89: <Qubit register=(151, \"ancilla\"), index=84>,\n90: <Qubit register=(151, \"ancilla\"), index=85>,\n91: <Qubit register=(151, \"ancilla\"), index=86>,\n92: <Qubit register=(151, \"ancilla\"), index=87>,\n93: <Qubit register=(151, \"ancilla\"), index=88>,\n94: <Qubit register=(151, \"ancilla\"), index=89>,\n95: <Qubit register=(151, \"ancilla\"), index=90>,\n96: <Qubit register=(151, \"ancilla\"), index=91>,\n97: <Qubit register=(151, \"ancilla\"), index=92>,\n98: <Qubit register=(151, \"ancilla\"), index=93>,\n99: <Qubit register=(151, \"ancilla\"), index=94>,\n100: <Qubit register=(151, \"ancilla\"), index=95>,\n101: <Qubit register=(151, \"ancilla\"), index=96>,\n102: <Qubit register=(151, \"ancilla\"), index=97>,\n103: <Qubit register=(151, \"ancilla\"), index=98>,\n104: <Qubit register=(151, \"ancilla\"), index=99>,\n105: <Qubit register=(151, \"ancilla\"), index=100>,\n106: <Qubit register=(151, \"ancilla\"), index=101>,\n107: <Qubit register=(151, \"ancilla\"), index=102>,\n108: <Qubit register=(151, \"ancilla\"), index=103>,\n109: <Qubit register=(151, \"ancilla\"), index=104>,\n110: <Qubit register=(151, \"ancilla\"), index=105>,\n111: <Qubit register=(151, \"ancilla\"), index=106>,\n112: <Qubit register=(151, \"ancilla\"), index=107>,\n113: <Qubit register=(151, \"ancilla\"), index=108>,\n114: <Qubit register=(151, \"ancilla\"), index=109>,\n115: <Qubit register=(151, \"ancilla\"), index=110>,\n116: <Qubit register=(151, \"ancilla\"), index=111>,\n117: <Qubit register=(151, \"ancilla\"), index=112>,\n118: <Qubit register=(151, \"ancilla\"), index=113>,\n119: <Qubit register=(151, \"ancilla\"), index=114>,\n120: <Qubit register=(151, \"ancilla\"), index=115>,\n121: <Qubit register=(151, \"ancilla\"), index=116>,\n122: <Qubit register=(151, \"ancilla\"), index=117>,\n123: <Qubit register=(151, \"ancilla\"), index=118>,\n124: <Qubit register=(151, \"ancilla\"), index=119>,\n125: <Qubit register=(151, \"ancilla\"), index=120>,\n126: <Qubit register=(151, \"ancilla\"), index=121>,\n127: <Qubit register=(151, \"ancilla\"), index=122>,\n128: <Qubit register=(151, \"ancilla\"), index=123>,\n129: <Qubit register=(151, \"ancilla\"), index=124>,\n130: <Qubit register=(151, \"ancilla\"), index=125>,\n131: <Qubit register=(151, \"ancilla\"), index=126>,\n132: <Qubit register=(151, \"ancilla\"), index=127>,\n133: <Qubit register=(151, \"ancilla\"), index=128>,\n134: <Qubit register=(151, \"ancilla\"), index=129>,\n135: <Qubit register=(151, \"ancilla\"), index=130>,\n136: <Qubit register=(151, \"ancilla\"), index=131>,\n137: <Qubit register=(151, \"ancilla\"), index=132>,\n138: <Qubit register=(151, \"ancilla\"), index=133>,\n139: <Qubit register=(151, \"ancilla\"), index=134>,\n140: <Qubit register=(151, \"ancilla\"), index=135>,\n141: <Qubit register=(151, \"ancilla\"), index=136>,\n142: <Qubit register=(151, \"ancilla\"), index=137>,\n143: <Qubit register=(151, \"ancilla\"), index=138>,\n144: <Qubit register=(151, \"ancilla\"), index=139>,\n145: <Qubit register=(151, \"ancilla\"), index=140>,\n146: <Qubit register=(151, \"ancilla\"), index=141>,\n147: <Qubit register=(151, \"ancilla\"), index=142>,\n148: <Qubit register=(151, \"ancilla\"), index=143>,\n149: <Qubit register=(151, \"ancilla\"), index=144>,\n150: <Qubit register=(151, \"ancilla\"), index=145>,\n151: <Qubit register=(151, \"ancilla\"), index=146>,\n152: <Qubit register=(151, \"ancilla\"), index=147>,\n153: <Qubit register=(151, \"ancilla\"), index=148>,\n154: <Qubit register=(151, \"ancilla\"), index=149>,\n155: <Qubit register=(151, \"ancilla\"), index=150>\n})",
+    "final_layout": null
+  },
+  "timestamp": "20260117_205401",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2",
+    "qiskit_ibm_runtime": "0.45.0"
+  }
+}

artifacts/branch_transfer/hw_coherence_20260117_202030_ibm_fez_coherence_witness_full_mu-1_shots-20000_opt-0.json

@@ -0,0 +1,154 @@
+{
+  "backend": "ibm_fez",
+  "backend_type": "hardware",
+  "mode": "coherence_witness_full",
+  "mu": 1,
+  "shots": 20000,
+  "W_X": 0.8369,
+  "W_X_error": 0.0038703900966181692,
+  "W_X_ideal": 1.0,
+  "W_X_tilde": 0.8369,
+  "W_X_tilde_error": 0.0038703900966181692,
+  "x_basis_result": {
+    "backend": "ibm_fez",
+    "backend_type": "hardware",
+    "backend_config": {
+      "backend_name": "ibm_fez",
+      "num_qubits": 156,
+      "processor_type": "Heron"
+    },
+    "job_id": "d5lnss48d8hc73cfq3qg",
+    "mode": "coherence_witness",
+    "measurement_basis": "X",
+    "mu": 1,
+    "shots": 20000,
+    "actual_shots": 20000,
+    "counts": {
+      "1010": 2267,
+      "1001": 2285,
+      "0010": 271,
+      "0000": 2503,
+      "0110": 2265,
+      "0101": 2333,
+      "0011": 2234,
+      "1111": 2097,
+      "0100": 236,
+      "1100": 2385,
+      "1000": 243,
+      "1101": 138,
+      "1011": 193,
+      "0001": 265,
+      "1110": 153,
+      "0111": 132
+    },
+    "W_X": 0.8369,
+    "W_X_error": 0.0038703900966181692,
+    "W_X_ideal": 1.0,
+    "W_X_tilde": 0.8369,
+    "W_X_tilde_error": 0.0038703900966181692,
+    "parity_counts": {
+      "n_even": 18369,
+      "n_odd": 1631,
+      "p_even": 0.91845,
+      "p_odd": 0.08155
+    },
+    "circuit_stats": {
+      "num_qubits": 5,
+      "num_clbits": 4,
+      "depth": 8,
+      "size": 17,
+      "gate_counts": {
+        "h": 5,
+        "cx": 5,
+        "x": 3
+      },
+      "two_qubit_gate_count": 5
+    },
+    "transpiled_depth": 17,
+    "transpiled_size": 40,
+    "transpiled_two_qubit_gates": 5,
+    "optimization_level": 2,
+    "physical_layout": {
+      "initial_layout": "Layout({\n16: <Qubit register=(5, \"q\"), index=0>,\n24: <Qubit register=(5, \"q\"), index=1>,\n23: <Qubit register=(5, \"q\"), index=2>,\n22: <Qubit register=(5, \"q\"), index=3>,\n21: <Qubit register=(5, \"q\"), index=4>,\n0: <Qubit register=(151, \"ancilla\"), index=0>,\n1: <Qubit register=(151, \"ancilla\"), index=1>,\n2: <Qubit register=(151, \"ancilla\"), index=2>,\n3: <Qubit register=(151, \"ancilla\"), index=3>,\n4: <Qubit register=(151, \"ancilla\"), index=4>,\n5: <Qubit register=(151, \"ancilla\"), index=5>,\n6: <Qubit register=(151, \"ancilla\"), index=6>,\n7: <Qubit register=(151, \"ancilla\"), index=7>,\n8: <Qubit register=(151, \"ancilla\"), index=8>,\n9: <Qubit register=(151, \"ancilla\"), index=9>,\n10: <Qubit register=(151, \"ancilla\"), index=10>,\n11: <Qubit register=(151, \"ancilla\"), index=11>,\n12: <Qubit register=(151, \"ancilla\"), index=12>,\n13: <Qubit register=(151, \"ancilla\"), index=13>,\n14: <Qubit register=(151, \"ancilla\"), index=14>,\n15: <Qubit register=(151, \"ancilla\"), index=15>,\n17: <Qubit register=(151, \"ancilla\"), index=16>,\n18: <Qubit register=(151, \"ancilla\"), index=17>,\n19: <Qubit register=(151, \"ancilla\"), index=18>,\n20: <Qubit register=(151, \"ancilla\"), index=19>,\n25: <Qubit register=(151, \"ancilla\"), index=20>,\n26: <Qubit register=(151, \"ancilla\"), index=21>,\n27: <Qubit register=(151, \"ancilla\"), index=22>,\n28: <Qubit register=(151, \"ancilla\"), index=23>,\n29: <Qubit register=(151, \"ancilla\"), index=24>,\n30: <Qubit register=(151, \"ancilla\"), index=25>,\n31: <Qubit register=(151, \"ancilla\"), index=26>,\n32: <Qubit register=(151, \"ancilla\"), index=27>,\n33: <Qubit register=(151, \"ancilla\"), index=28>,\n34: <Qubit register=(151, \"ancilla\"), index=29>,\n35: <Qubit register=(151, \"ancilla\"), index=30>,\n36: <Qubit register=(151, \"ancilla\"), index=31>,\n37: <Qubit register=(151, \"ancilla\"), index=32>,\n38: <Qubit register=(151, \"ancilla\"), index=33>,\n39: <Qubit register=(151, \"ancilla\"), index=34>,\n40: <Qubit register=(151, \"ancilla\"), index=35>,\n41: <Qubit register=(151, \"ancilla\"), index=36>,\n42: <Qubit register=(151, \"ancilla\"), index=37>,\n43: <Qubit register=(151, \"ancilla\"), index=38>,\n44: <Qubit register=(151, \"ancilla\"), index=39>,\n45: <Qubit register=(151, \"ancilla\"), index=40>,\n46: <Qubit register=(151, \"ancilla\"), index=41>,\n47: <Qubit register=(151, \"ancilla\"), index=42>,\n48: <Qubit register=(151, \"ancilla\"), index=43>,\n49: <Qubit register=(151, \"ancilla\"), index=44>,\n50: <Qubit register=(151, \"ancilla\"), index=45>,\n51: <Qubit register=(151, \"ancilla\"), index=46>,\n52: <Qubit register=(151, \"ancilla\"), index=47>,\n53: <Qubit register=(151, \"ancilla\"), index=48>,\n54: <Qubit register=(151, \"ancilla\"), index=49>,\n55: <Qubit register=(151, \"ancilla\"), index=50>,\n56: <Qubit register=(151, \"ancilla\"), index=51>,\n57: <Qubit register=(151, \"ancilla\"), index=52>,\n58: <Qubit register=(151, \"ancilla\"), index=53>,\n59: <Qubit register=(151, \"ancilla\"), index=54>,\n60: <Qubit register=(151, \"ancilla\"), index=55>,\n61: <Qubit register=(151, \"ancilla\"), index=56>,\n62: <Qubit register=(151, \"ancilla\"), index=57>,\n63: <Qubit register=(151, \"ancilla\"), index=58>,\n64: <Qubit register=(151, \"ancilla\"), index=59>,\n65: <Qubit register=(151, \"ancilla\"), index=60>,\n66: <Qubit register=(151, \"ancilla\"), index=61>,\n67: <Qubit register=(151, \"ancilla\"), index=62>,\n68: <Qubit register=(151, \"ancilla\"), index=63>,\n69: <Qubit register=(151, \"ancilla\"), index=64>,\n70: <Qubit register=(151, \"ancilla\"), index=65>,\n71: <Qubit register=(151, \"ancilla\"), index=66>,\n72: <Qubit register=(151, \"ancilla\"), index=67>,\n73: <Qubit register=(151, \"ancilla\"), index=68>,\n74: <Qubit register=(151, \"ancilla\"), index=69>,\n75: <Qubit register=(151, \"ancilla\"), index=70>,\n76: <Qubit register=(151, \"ancilla\"), index=71>,\n77: <Qubit register=(151, \"ancilla\"), index=72>,\n78: <Qubit register=(151, \"ancilla\"), index=73>,\n79: <Qubit register=(151, \"ancilla\"), index=74>,\n80: <Qubit register=(151, \"ancilla\"), index=75>,\n81: <Qubit register=(151, \"ancilla\"), index=76>,\n82: <Qubit register=(151, \"ancilla\"), index=77>,\n83: <Qubit register=(151, \"ancilla\"), index=78>,\n84: <Qubit register=(151, \"ancilla\"), index=79>,\n85: <Qubit register=(151, \"ancilla\"), index=80>,\n86: <Qubit register=(151, \"ancilla\"), index=81>,\n87: <Qubit register=(151, \"ancilla\"), index=82>,\n88: <Qubit register=(151, \"ancilla\"), index=83>,\n89: <Qubit register=(151, \"ancilla\"), index=84>,\n90: <Qubit register=(151, \"ancilla\"), index=85>,\n91: <Qubit register=(151, \"ancilla\"), index=86>,\n92: <Qubit register=(151, \"ancilla\"), index=87>,\n93: <Qubit register=(151, \"ancilla\"), index=88>,\n94: <Qubit register=(151, \"ancilla\"), index=89>,\n95: <Qubit register=(151, \"ancilla\"), index=90>,\n96: <Qubit register=(151, \"ancilla\"), index=91>,\n97: <Qubit register=(151, \"ancilla\"), index=92>,\n98: <Qubit register=(151, \"ancilla\"), index=93>,\n99: <Qubit register=(151, \"ancilla\"), index=94>,\n100: <Qubit register=(151, \"ancilla\"), index=95>,\n101: <Qubit register=(151, \"ancilla\"), index=96>,\n102: <Qubit register=(151, \"ancilla\"), index=97>,\n103: <Qubit register=(151, \"ancilla\"), index=98>,\n104: <Qubit register=(151, \"ancilla\"), index=99>,\n105: <Qubit register=(151, \"ancilla\"), index=100>,\n106: <Qubit register=(151, \"ancilla\"), index=101>,\n107: <Qubit register=(151, \"ancilla\"), index=102>,\n108: <Qubit register=(151, \"ancilla\"), index=103>,\n109: <Qubit register=(151, \"ancilla\"), index=104>,\n110: <Qubit register=(151, \"ancilla\"), index=105>,\n111: <Qubit register=(151, \"ancilla\"), index=106>,\n112: <Qubit register=(151, \"ancilla\"), index=107>,\n113: <Qubit register=(151, \"ancilla\"), index=108>,\n114: <Qubit register=(151, \"ancilla\"), index=109>,\n115: <Qubit register=(151, \"ancilla\"), index=110>,\n116: <Qubit register=(151, \"ancilla\"), index=111>,\n117: <Qubit register=(151, \"ancilla\"), index=112>,\n118: <Qubit register=(151, \"ancilla\"), index=113>,\n119: <Qubit register=(151, \"ancilla\"), index=114>,\n120: <Qubit register=(151, \"ancilla\"), index=115>,\n121: <Qubit register=(151, \"ancilla\"), index=116>,\n122: <Qubit register=(151, \"ancilla\"), index=117>,\n123: <Qubit register=(151, \"ancilla\"), index=118>,\n124: <Qubit register=(151, \"ancilla\"), index=119>,\n125: <Qubit register=(151, \"ancilla\"), index=120>,\n126: <Qubit register=(151, \"ancilla\"), index=121>,\n127: <Qubit register=(151, \"ancilla\"), index=122>,\n128: <Qubit register=(151, \"ancilla\"), index=123>,\n129: <Qubit register=(151, \"ancilla\"), index=124>,\n130: <Qubit register=(151, \"ancilla\"), index=125>,\n131: <Qubit register=(151, \"ancilla\"), index=126>,\n132: <Qubit register=(151, \"ancilla\"), index=127>,\n133: <Qubit register=(151, \"ancilla\"), index=128>,\n134: <Qubit register=(151, \"ancilla\"), index=129>,\n135: <Qubit register=(151, \"ancilla\"), index=130>,\n136: <Qubit register=(151, \"ancilla\"), index=131>,\n137: <Qubit register=(151, \"ancilla\"), index=132>,\n138: <Qubit register=(151, \"ancilla\"), index=133>,\n139: <Qubit register=(151, \"ancilla\"), index=134>,\n140: <Qubit register=(151, \"ancilla\"), index=135>,\n141: <Qubit register=(151, \"ancilla\"), index=136>,\n142: <Qubit register=(151, \"ancilla\"), index=137>,\n143: <Qubit register=(151, \"ancilla\"), index=138>,\n144: <Qubit register=(151, \"ancilla\"), index=139>,\n145: <Qubit register=(151, \"ancilla\"), index=140>,\n146: <Qubit register=(151, \"ancilla\"), index=141>,\n147: <Qubit register=(151, \"ancilla\"), index=142>,\n148: <Qubit register=(151, \"ancilla\"), index=143>,\n149: <Qubit register=(151, \"ancilla\"), index=144>,\n150: <Qubit register=(151, \"ancilla\"), index=145>,\n151: <Qubit register=(151, \"ancilla\"), index=146>,\n152: <Qubit register=(151, \"ancilla\"), index=147>,\n153: <Qubit register=(151, \"ancilla\"), index=148>,\n154: <Qubit register=(151, \"ancilla\"), index=149>,\n155: <Qubit register=(151, \"ancilla\"), index=150>\n})",
+      "final_layout": null
+    }
+  },
+  "W_Y": -0.802,
+  "W_Y_error": 0.004223718740636029,
+  "W_Y_ideal": 0.0,
+  "W_Y_tilde": 0.0,
+  "W_Y_tilde_error": 0.0,
+  "y_basis_result": {
+    "backend": "ibm_fez",
+    "backend_type": "hardware",
+    "backend_config": {
+      "backend_name": "ibm_fez",
+      "num_qubits": 156,
+      "processor_type": "Heron"
+    },
+    "job_id": "d5lnt148d8hc73cfq3vg",
+    "mode": "coherence_witness",
+    "measurement_basis": "Y",
+    "mu": 1,
+    "shots": 20000,
+    "actual_shots": 20000,
+    "counts": {
+      "1101": 2163,
+      "0000": 349,
+      "0100": 2380,
+      "0111": 2099,
+      "1011": 2156,
+      "0010": 2264,
+      "0001": 2387,
+      "1000": 2420,
+      "1001": 288,
+      "1111": 171,
+      "0110": 205,
+      "1110": 2151,
+      "1100": 233,
+      "0101": 213,
+      "1010": 260,
+      "0011": 261
+    },
+    "W_Y": -0.802,
+    "W_Y_error": 0.004223718740636029,
+    "W_Y_ideal": 0.0,
+    "W_Y_tilde": 0.0,
+    "W_Y_tilde_error": 0.0,
+    "parity_counts": {
+      "n_even": 1980,
+      "n_odd": 18020,
+      "p_even": 0.099,
+      "p_odd": 0.901
+    },
+    "circuit_stats": {
+      "num_qubits": 5,
+      "num_clbits": 4,
+      "depth": 9,
+      "size": 21,
+      "gate_counts": {
+        "h": 5,
+        "cx": 5,
+        "x": 3,
+        "sdg": 4
+      },
+      "two_qubit_gate_count": 5
+    },
+    "transpiled_depth": 17,
+    "transpiled_size": 42,
+    "transpiled_two_qubit_gates": 5,
+    "optimization_level": 2,
+    "physical_layout": {
+      "initial_layout": "Layout({\n16: <Qubit register=(5, \"q\"), index=0>,\n24: <Qubit register=(5, \"q\"), index=1>,\n23: <Qubit register=(5, \"q\"), index=2>,\n22: <Qubit register=(5, \"q\"), index=3>,\n21: <Qubit register=(5, \"q\"), index=4>,\n0: <Qubit register=(151, \"ancilla\"), index=0>,\n1: <Qubit register=(151, \"ancilla\"), index=1>,\n2: <Qubit register=(151, \"ancilla\"), index=2>,\n3: <Qubit register=(151, \"ancilla\"), index=3>,\n4: <Qubit register=(151, \"ancilla\"), index=4>,\n5: <Qubit register=(151, \"ancilla\"), index=5>,\n6: <Qubit register=(151, \"ancilla\"), index=6>,\n7: <Qubit register=(151, \"ancilla\"), index=7>,\n8: <Qubit register=(151, \"ancilla\"), index=8>,\n9: <Qubit register=(151, \"ancilla\"), index=9>,\n10: <Qubit register=(151, \"ancilla\"), index=10>,\n11: <Qubit register=(151, \"ancilla\"), index=11>,\n12: <Qubit register=(151, \"ancilla\"), index=12>,\n13: <Qubit register=(151, \"ancilla\"), index=13>,\n14: <Qubit register=(151, \"ancilla\"), index=14>,\n15: <Qubit register=(151, \"ancilla\"), index=15>,\n17: <Qubit register=(151, \"ancilla\"), index=16>,\n18: <Qubit register=(151, \"ancilla\"), index=17>,\n19: <Qubit register=(151, \"ancilla\"), index=18>,\n20: <Qubit register=(151, \"ancilla\"), index=19>,\n25: <Qubit register=(151, \"ancilla\"), index=20>,\n26: <Qubit register=(151, \"ancilla\"), index=21>,\n27: <Qubit register=(151, \"ancilla\"), index=22>,\n28: <Qubit register=(151, \"ancilla\"), index=23>,\n29: <Qubit register=(151, \"ancilla\"), index=24>,\n30: <Qubit register=(151, \"ancilla\"), index=25>,\n31: <Qubit register=(151, \"ancilla\"), index=26>,\n32: <Qubit register=(151, \"ancilla\"), index=27>,\n33: <Qubit register=(151, \"ancilla\"), index=28>,\n34: <Qubit register=(151, \"ancilla\"), index=29>,\n35: <Qubit register=(151, \"ancilla\"), index=30>,\n36: <Qubit register=(151, \"ancilla\"), index=31>,\n37: <Qubit register=(151, \"ancilla\"), index=32>,\n38: <Qubit register=(151, \"ancilla\"), index=33>,\n39: <Qubit register=(151, \"ancilla\"), index=34>,\n40: <Qubit register=(151, \"ancilla\"), index=35>,\n41: <Qubit register=(151, \"ancilla\"), index=36>,\n42: <Qubit register=(151, \"ancilla\"), index=37>,\n43: <Qubit register=(151, \"ancilla\"), index=38>,\n44: <Qubit register=(151, \"ancilla\"), index=39>,\n45: <Qubit register=(151, \"ancilla\"), index=40>,\n46: <Qubit register=(151, \"ancilla\"), index=41>,\n47: <Qubit register=(151, \"ancilla\"), index=42>,\n48: <Qubit register=(151, \"ancilla\"), index=43>,\n49: <Qubit register=(151, \"ancilla\"), index=44>,\n50: <Qubit register=(151, \"ancilla\"), index=45>,\n51: <Qubit register=(151, \"ancilla\"), index=46>,\n52: <Qubit register=(151, \"ancilla\"), index=47>,\n53: <Qubit register=(151, \"ancilla\"), index=48>,\n54: <Qubit register=(151, \"ancilla\"), index=49>,\n55: <Qubit register=(151, \"ancilla\"), index=50>,\n56: <Qubit register=(151, \"ancilla\"), index=51>,\n57: <Qubit register=(151, \"ancilla\"), index=52>,\n58: <Qubit register=(151, \"ancilla\"), index=53>,\n59: <Qubit register=(151, \"ancilla\"), index=54>,\n60: <Qubit register=(151, \"ancilla\"), index=55>,\n61: <Qubit register=(151, \"ancilla\"), index=56>,\n62: <Qubit register=(151, \"ancilla\"), index=57>,\n63: <Qubit register=(151, \"ancilla\"), index=58>,\n64: <Qubit register=(151, \"ancilla\"), index=59>,\n65: <Qubit register=(151, \"ancilla\"), index=60>,\n66: <Qubit register=(151, \"ancilla\"), index=61>,\n67: <Qubit register=(151, \"ancilla\"), index=62>,\n68: <Qubit register=(151, \"ancilla\"), index=63>,\n69: <Qubit register=(151, \"ancilla\"), index=64>,\n70: <Qubit register=(151, \"ancilla\"), index=65>,\n71: <Qubit register=(151, \"ancilla\"), index=66>,\n72: <Qubit register=(151, \"ancilla\"), index=67>,\n73: <Qubit register=(151, \"ancilla\"), index=68>,\n74: <Qubit register=(151, \"ancilla\"), index=69>,\n75: <Qubit register=(151, \"ancilla\"), index=70>,\n76: <Qubit register=(151, \"ancilla\"), index=71>,\n77: <Qubit register=(151, \"ancilla\"), index=72>,\n78: <Qubit register=(151, \"ancilla\"), index=73>,\n79: <Qubit register=(151, \"ancilla\"), index=74>,\n80: <Qubit register=(151, \"ancilla\"), index=75>,\n81: <Qubit register=(151, \"ancilla\"), index=76>,\n82: <Qubit register=(151, \"ancilla\"), index=77>,\n83: <Qubit register=(151, \"ancilla\"), index=78>,\n84: <Qubit register=(151, \"ancilla\"), index=79>,\n85: <Qubit register=(151, \"ancilla\"), index=80>,\n86: <Qubit register=(151, \"ancilla\"), index=81>,\n87: <Qubit register=(151, \"ancilla\"), index=82>,\n88: <Qubit register=(151, \"ancilla\"), index=83>,\n89: <Qubit register=(151, \"ancilla\"), index=84>,\n90: <Qubit register=(151, \"ancilla\"), index=85>,\n91: <Qubit register=(151, \"ancilla\"), index=86>,\n92: <Qubit register=(151, \"ancilla\"), index=87>,\n93: <Qubit register=(151, \"ancilla\"), index=88>,\n94: <Qubit register=(151, \"ancilla\"), index=89>,\n95: <Qubit register=(151, \"ancilla\"), index=90>,\n96: <Qubit register=(151, \"ancilla\"), index=91>,\n97: <Qubit register=(151, \"ancilla\"), index=92>,\n98: <Qubit register=(151, \"ancilla\"), index=93>,\n99: <Qubit register=(151, \"ancilla\"), index=94>,\n100: <Qubit register=(151, \"ancilla\"), index=95>,\n101: <Qubit register=(151, \"ancilla\"), index=96>,\n102: <Qubit register=(151, \"ancilla\"), index=97>,\n103: <Qubit register=(151, \"ancilla\"), index=98>,\n104: <Qubit register=(151, \"ancilla\"), index=99>,\n105: <Qubit register=(151, \"ancilla\"), index=100>,\n106: <Qubit register=(151, \"ancilla\"), index=101>,\n107: <Qubit register=(151, \"ancilla\"), index=102>,\n108: <Qubit register=(151, \"ancilla\"), index=103>,\n109: <Qubit register=(151, \"ancilla\"), index=104>,\n110: <Qubit register=(151, \"ancilla\"), index=105>,\n111: <Qubit register=(151, \"ancilla\"), index=106>,\n112: <Qubit register=(151, \"ancilla\"), index=107>,\n113: <Qubit register=(151, \"ancilla\"), index=108>,\n114: <Qubit register=(151, \"ancilla\"), index=109>,\n115: <Qubit register=(151, \"ancilla\"), index=110>,\n116: <Qubit register=(151, \"ancilla\"), index=111>,\n117: <Qubit register=(151, \"ancilla\"), index=112>,\n118: <Qubit register=(151, \"ancilla\"), index=113>,\n119: <Qubit register=(151, \"ancilla\"), index=114>,\n120: <Qubit register=(151, \"ancilla\"), index=115>,\n121: <Qubit register=(151, \"ancilla\"), index=116>,\n122: <Qubit register=(151, \"ancilla\"), index=117>,\n123: <Qubit register=(151, \"ancilla\"), index=118>,\n124: <Qubit register=(151, \"ancilla\"), index=119>,\n125: <Qubit register=(151, \"ancilla\"), index=120>,\n126: <Qubit register=(151, \"ancilla\"), index=121>,\n127: <Qubit register=(151, \"ancilla\"), index=122>,\n128: <Qubit register=(151, \"ancilla\"), index=123>,\n129: <Qubit register=(151, \"ancilla\"), index=124>,\n130: <Qubit register=(151, \"ancilla\"), index=125>,\n131: <Qubit register=(151, \"ancilla\"), index=126>,\n132: <Qubit register=(151, \"ancilla\"), index=127>,\n133: <Qubit register=(151, \"ancilla\"), index=128>,\n134: <Qubit register=(151, \"ancilla\"), index=129>,\n135: <Qubit register=(151, \"ancilla\"), index=130>,\n136: <Qubit register=(151, \"ancilla\"), index=131>,\n137: <Qubit register=(151, \"ancilla\"), index=132>,\n138: <Qubit register=(151, \"ancilla\"), index=133>,\n139: <Qubit register=(151, \"ancilla\"), index=134>,\n140: <Qubit register=(151, \"ancilla\"), index=135>,\n141: <Qubit register=(151, \"ancilla\"), index=136>,\n142: <Qubit register=(151, \"ancilla\"), index=137>,\n143: <Qubit register=(151, \"ancilla\"), index=138>,\n144: <Qubit register=(151, \"ancilla\"), index=139>,\n145: <Qubit register=(151, \"ancilla\"), index=140>,\n146: <Qubit register=(151, \"ancilla\"), index=141>,\n147: <Qubit register=(151, \"ancilla\"), index=142>,\n148: <Qubit register=(151, \"ancilla\"), index=143>,\n149: <Qubit register=(151, \"ancilla\"), index=144>,\n150: <Qubit register=(151, \"ancilla\"), index=145>,\n151: <Qubit register=(151, \"ancilla\"), index=146>,\n152: <Qubit register=(151, \"ancilla\"), index=147>,\n153: <Qubit register=(151, \"ancilla\"), index=148>,\n154: <Qubit register=(151, \"ancilla\"), index=149>,\n155: <Qubit register=(151, \"ancilla\"), index=150>\n})",
+      "final_layout": null
+    }
+  },
+  "C_magnitude": 1.159140030367341,
+  "C_magnitude_error": 0.004043388041465454,
+  "timestamp": "20260117_202030",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2",
+    "qiskit_ibm_runtime": "0.45.0"
+  }
+}

artifacts/branch_transfer/hw_coherence_20260117_205321_ibm_fez_coherence_witness_full_mu-1_shots-20000_opt-0.json

@@ -0,0 +1,154 @@
+{
+  "backend": "ibm_fez",
+  "backend_type": "hardware",
+  "mode": "coherence_witness_full",
+  "mu": 1,
+  "shots": 20000,
+  "W_X": 0.8398000000000001,
+  "W_X_error": 0.003838853735166267,
+  "W_X_ideal": 1.0,
+  "W_X_tilde": 0.8398000000000001,
+  "W_X_tilde_error": 0.003838853735166267,
+  "x_basis_result": {
+    "backend": "ibm_fez",
+    "backend_type": "hardware",
+    "backend_config": {
+      "backend_name": "ibm_fez",
+      "num_qubits": 156,
+      "processor_type": "Heron"
+    },
+    "job_id": "d5lobdt9j2ac739k1a0g",
+    "mode": "coherence_witness",
+    "measurement_basis": "X",
+    "mu": 1,
+    "shots": 20000,
+    "actual_shots": 20000,
+    "counts": {
+      "1100": 2281,
+      "0011": 2225,
+      "1010": 2309,
+      "0110": 2325,
+      "0100": 240,
+      "0101": 2388,
+      "1001": 2233,
+      "1111": 2140,
+      "0000": 2497,
+      "1110": 126,
+      "1011": 188,
+      "0010": 245,
+      "0001": 270,
+      "1101": 150,
+      "1000": 237,
+      "0111": 146
+    },
+    "W_X": 0.8398000000000001,
+    "W_X_error": 0.003838853735166267,
+    "W_X_ideal": 1.0,
+    "W_X_tilde": 0.8398000000000001,
+    "W_X_tilde_error": 0.003838853735166267,
+    "parity_counts": {
+      "n_even": 18398,
+      "n_odd": 1602,
+      "p_even": 0.9199,
+      "p_odd": 0.0801
+    },
+    "circuit_stats": {
+      "num_qubits": 5,
+      "num_clbits": 4,
+      "depth": 8,
+      "size": 17,
+      "gate_counts": {
+        "h": 5,
+        "cx": 5,
+        "x": 3
+      },
+      "two_qubit_gate_count": 5
+    },
+    "transpiled_depth": 17,
+    "transpiled_size": 40,
+    "transpiled_two_qubit_gates": 5,
+    "optimization_level": 2,
+    "physical_layout": {
+      "initial_layout": "Layout({\n16: <Qubit register=(5, \"q\"), index=0>,\n24: <Qubit register=(5, \"q\"), index=1>,\n23: <Qubit register=(5, \"q\"), index=2>,\n22: <Qubit register=(5, \"q\"), index=3>,\n21: <Qubit register=(5, \"q\"), index=4>,\n0: <Qubit register=(151, \"ancilla\"), index=0>,\n1: <Qubit register=(151, \"ancilla\"), index=1>,\n2: <Qubit register=(151, \"ancilla\"), index=2>,\n3: <Qubit register=(151, \"ancilla\"), index=3>,\n4: <Qubit register=(151, \"ancilla\"), index=4>,\n5: <Qubit register=(151, \"ancilla\"), index=5>,\n6: <Qubit register=(151, \"ancilla\"), index=6>,\n7: <Qubit register=(151, \"ancilla\"), index=7>,\n8: <Qubit register=(151, \"ancilla\"), index=8>,\n9: <Qubit register=(151, \"ancilla\"), index=9>,\n10: <Qubit register=(151, \"ancilla\"), index=10>,\n11: <Qubit register=(151, \"ancilla\"), index=11>,\n12: <Qubit register=(151, \"ancilla\"), index=12>,\n13: <Qubit register=(151, \"ancilla\"), index=13>,\n14: <Qubit register=(151, \"ancilla\"), index=14>,\n15: <Qubit register=(151, \"ancilla\"), index=15>,\n17: <Qubit register=(151, \"ancilla\"), index=16>,\n18: <Qubit register=(151, \"ancilla\"), index=17>,\n19: <Qubit register=(151, \"ancilla\"), index=18>,\n20: <Qubit register=(151, \"ancilla\"), index=19>,\n25: <Qubit register=(151, \"ancilla\"), index=20>,\n26: <Qubit register=(151, \"ancilla\"), index=21>,\n27: <Qubit register=(151, \"ancilla\"), index=22>,\n28: <Qubit register=(151, \"ancilla\"), index=23>,\n29: <Qubit register=(151, \"ancilla\"), index=24>,\n30: <Qubit register=(151, \"ancilla\"), index=25>,\n31: <Qubit register=(151, \"ancilla\"), index=26>,\n32: <Qubit register=(151, \"ancilla\"), index=27>,\n33: <Qubit register=(151, \"ancilla\"), index=28>,\n34: <Qubit register=(151, \"ancilla\"), index=29>,\n35: <Qubit register=(151, \"ancilla\"), index=30>,\n36: <Qubit register=(151, \"ancilla\"), index=31>,\n37: <Qubit register=(151, \"ancilla\"), index=32>,\n38: <Qubit register=(151, \"ancilla\"), index=33>,\n39: <Qubit register=(151, \"ancilla\"), index=34>,\n40: <Qubit register=(151, \"ancilla\"), index=35>,\n41: <Qubit register=(151, \"ancilla\"), index=36>,\n42: <Qubit register=(151, \"ancilla\"), index=37>,\n43: <Qubit register=(151, \"ancilla\"), index=38>,\n44: <Qubit register=(151, \"ancilla\"), index=39>,\n45: <Qubit register=(151, \"ancilla\"), index=40>,\n46: <Qubit register=(151, \"ancilla\"), index=41>,\n47: <Qubit register=(151, \"ancilla\"), index=42>,\n48: <Qubit register=(151, \"ancilla\"), index=43>,\n49: <Qubit register=(151, \"ancilla\"), index=44>,\n50: <Qubit register=(151, \"ancilla\"), index=45>,\n51: <Qubit register=(151, \"ancilla\"), index=46>,\n52: <Qubit register=(151, \"ancilla\"), index=47>,\n53: <Qubit register=(151, \"ancilla\"), index=48>,\n54: <Qubit register=(151, \"ancilla\"), index=49>,\n55: <Qubit register=(151, \"ancilla\"), index=50>,\n56: <Qubit register=(151, \"ancilla\"), index=51>,\n57: <Qubit register=(151, \"ancilla\"), index=52>,\n58: <Qubit register=(151, \"ancilla\"), index=53>,\n59: <Qubit register=(151, \"ancilla\"), index=54>,\n60: <Qubit register=(151, \"ancilla\"), index=55>,\n61: <Qubit register=(151, \"ancilla\"), index=56>,\n62: <Qubit register=(151, \"ancilla\"), index=57>,\n63: <Qubit register=(151, \"ancilla\"), index=58>,\n64: <Qubit register=(151, \"ancilla\"), index=59>,\n65: <Qubit register=(151, \"ancilla\"), index=60>,\n66: <Qubit register=(151, \"ancilla\"), index=61>,\n67: <Qubit register=(151, \"ancilla\"), index=62>,\n68: <Qubit register=(151, \"ancilla\"), index=63>,\n69: <Qubit register=(151, \"ancilla\"), index=64>,\n70: <Qubit register=(151, \"ancilla\"), index=65>,\n71: <Qubit register=(151, \"ancilla\"), index=66>,\n72: <Qubit register=(151, \"ancilla\"), index=67>,\n73: <Qubit register=(151, \"ancilla\"), index=68>,\n74: <Qubit register=(151, \"ancilla\"), index=69>,\n75: <Qubit register=(151, \"ancilla\"), index=70>,\n76: <Qubit register=(151, \"ancilla\"), index=71>,\n77: <Qubit register=(151, \"ancilla\"), index=72>,\n78: <Qubit register=(151, \"ancilla\"), index=73>,\n79: <Qubit register=(151, \"ancilla\"), index=74>,\n80: <Qubit register=(151, \"ancilla\"), index=75>,\n81: <Qubit register=(151, \"ancilla\"), index=76>,\n82: <Qubit register=(151, \"ancilla\"), index=77>,\n83: <Qubit register=(151, \"ancilla\"), index=78>,\n84: <Qubit register=(151, \"ancilla\"), index=79>,\n85: <Qubit register=(151, \"ancilla\"), index=80>,\n86: <Qubit register=(151, \"ancilla\"), index=81>,\n87: <Qubit register=(151, \"ancilla\"), index=82>,\n88: <Qubit register=(151, \"ancilla\"), index=83>,\n89: <Qubit register=(151, \"ancilla\"), index=84>,\n90: <Qubit register=(151, \"ancilla\"), index=85>,\n91: <Qubit register=(151, \"ancilla\"), index=86>,\n92: <Qubit register=(151, \"ancilla\"), index=87>,\n93: <Qubit register=(151, \"ancilla\"), index=88>,\n94: <Qubit register=(151, \"ancilla\"), index=89>,\n95: <Qubit register=(151, \"ancilla\"), index=90>,\n96: <Qubit register=(151, \"ancilla\"), index=91>,\n97: <Qubit register=(151, \"ancilla\"), index=92>,\n98: <Qubit register=(151, \"ancilla\"), index=93>,\n99: <Qubit register=(151, \"ancilla\"), index=94>,\n100: <Qubit register=(151, \"ancilla\"), index=95>,\n101: <Qubit register=(151, \"ancilla\"), index=96>,\n102: <Qubit register=(151, \"ancilla\"), index=97>,\n103: <Qubit register=(151, \"ancilla\"), index=98>,\n104: <Qubit register=(151, \"ancilla\"), index=99>,\n105: <Qubit register=(151, \"ancilla\"), index=100>,\n106: <Qubit register=(151, \"ancilla\"), index=101>,\n107: <Qubit register=(151, \"ancilla\"), index=102>,\n108: <Qubit register=(151, \"ancilla\"), index=103>,\n109: <Qubit register=(151, \"ancilla\"), index=104>,\n110: <Qubit register=(151, \"ancilla\"), index=105>,\n111: <Qubit register=(151, \"ancilla\"), index=106>,\n112: <Qubit register=(151, \"ancilla\"), index=107>,\n113: <Qubit register=(151, \"ancilla\"), index=108>,\n114: <Qubit register=(151, \"ancilla\"), index=109>,\n115: <Qubit register=(151, \"ancilla\"), index=110>,\n116: <Qubit register=(151, \"ancilla\"), index=111>,\n117: <Qubit register=(151, \"ancilla\"), index=112>,\n118: <Qubit register=(151, \"ancilla\"), index=113>,\n119: <Qubit register=(151, \"ancilla\"), index=114>,\n120: <Qubit register=(151, \"ancilla\"), index=115>,\n121: <Qubit register=(151, \"ancilla\"), index=116>,\n122: <Qubit register=(151, \"ancilla\"), index=117>,\n123: <Qubit register=(151, \"ancilla\"), index=118>,\n124: <Qubit register=(151, \"ancilla\"), index=119>,\n125: <Qubit register=(151, \"ancilla\"), index=120>,\n126: <Qubit register=(151, \"ancilla\"), index=121>,\n127: <Qubit register=(151, \"ancilla\"), index=122>,\n128: <Qubit register=(151, \"ancilla\"), index=123>,\n129: <Qubit register=(151, \"ancilla\"), index=124>,\n130: <Qubit register=(151, \"ancilla\"), index=125>,\n131: <Qubit register=(151, \"ancilla\"), index=126>,\n132: <Qubit register=(151, \"ancilla\"), index=127>,\n133: <Qubit register=(151, \"ancilla\"), index=128>,\n134: <Qubit register=(151, \"ancilla\"), index=129>,\n135: <Qubit register=(151, \"ancilla\"), index=130>,\n136: <Qubit register=(151, \"ancilla\"), index=131>,\n137: <Qubit register=(151, \"ancilla\"), index=132>,\n138: <Qubit register=(151, \"ancilla\"), index=133>,\n139: <Qubit register=(151, \"ancilla\"), index=134>,\n140: <Qubit register=(151, \"ancilla\"), index=135>,\n141: <Qubit register=(151, \"ancilla\"), index=136>,\n142: <Qubit register=(151, \"ancilla\"), index=137>,\n143: <Qubit register=(151, \"ancilla\"), index=138>,\n144: <Qubit register=(151, \"ancilla\"), index=139>,\n145: <Qubit register=(151, \"ancilla\"), index=140>,\n146: <Qubit register=(151, \"ancilla\"), index=141>,\n147: <Qubit register=(151, \"ancilla\"), index=142>,\n148: <Qubit register=(151, \"ancilla\"), index=143>,\n149: <Qubit register=(151, \"ancilla\"), index=144>,\n150: <Qubit register=(151, \"ancilla\"), index=145>,\n151: <Qubit register=(151, \"ancilla\"), index=146>,\n152: <Qubit register=(151, \"ancilla\"), index=147>,\n153: <Qubit register=(151, \"ancilla\"), index=148>,\n154: <Qubit register=(151, \"ancilla\"), index=149>,\n155: <Qubit register=(151, \"ancilla\"), index=150>\n})",
+      "final_layout": null
+    }
+  },
+  "W_Y": -0.8107,
+  "W_Y_error": 0.004139840033141377,
+  "W_Y_ideal": 0.0,
+  "W_Y_tilde": 0.0,
+  "W_Y_tilde_error": 0.0,
+  "y_basis_result": {
+    "backend": "ibm_fez",
+    "backend_type": "hardware",
+    "backend_config": {
+      "backend_name": "ibm_fez",
+      "num_qubits": 156,
+      "processor_type": "Heron"
+    },
+    "job_id": "d5locdhh2mqc739a2ubg",
+    "mode": "coherence_witness",
+    "measurement_basis": "Y",
+    "mu": 1,
+    "shots": 20000,
+    "actual_shots": 20000,
+    "counts": {
+      "1100": 202,
+      "1000": 2405,
+      "0100": 2348,
+      "1011": 2134,
+      "0001": 2364,
+      "0111": 2124,
+      "0011": 219,
+      "1110": 2199,
+      "1101": 2272,
+      "0010": 2261,
+      "1001": 293,
+      "0110": 197,
+      "0000": 311,
+      "1111": 190,
+      "1010": 280,
+      "0101": 201
+    },
+    "W_Y": -0.8107,
+    "W_Y_error": 0.004139840033141377,
+    "W_Y_ideal": 0.0,
+    "W_Y_tilde": 0.0,
+    "W_Y_tilde_error": 0.0,
+    "parity_counts": {
+      "n_even": 1893,
+      "n_odd": 18107,
+      "p_even": 0.09465,
+      "p_odd": 0.90535
+    },
+    "circuit_stats": {
+      "num_qubits": 5,
+      "num_clbits": 4,
+      "depth": 9,
+      "size": 21,
+      "gate_counts": {
+        "h": 5,
+        "cx": 5,
+        "x": 3,
+        "sdg": 4
+      },
+      "two_qubit_gate_count": 5
+    },
+    "transpiled_depth": 17,
+    "transpiled_size": 42,
+    "transpiled_two_qubit_gates": 5,
+    "optimization_level": 2,
+    "physical_layout": {
+      "initial_layout": "Layout({\n16: <Qubit register=(5, \"q\"), index=0>,\n24: <Qubit register=(5, \"q\"), index=1>,\n23: <Qubit register=(5, \"q\"), index=2>,\n22: <Qubit register=(5, \"q\"), index=3>,\n21: <Qubit register=(5, \"q\"), index=4>,\n0: <Qubit register=(151, \"ancilla\"), index=0>,\n1: <Qubit register=(151, \"ancilla\"), index=1>,\n2: <Qubit register=(151, \"ancilla\"), index=2>,\n3: <Qubit register=(151, \"ancilla\"), index=3>,\n4: <Qubit register=(151, \"ancilla\"), index=4>,\n5: <Qubit register=(151, \"ancilla\"), index=5>,\n6: <Qubit register=(151, \"ancilla\"), index=6>,\n7: <Qubit register=(151, \"ancilla\"), index=7>,\n8: <Qubit register=(151, \"ancilla\"), index=8>,\n9: <Qubit register=(151, \"ancilla\"), index=9>,\n10: <Qubit register=(151, \"ancilla\"), index=10>,\n11: <Qubit register=(151, \"ancilla\"), index=11>,\n12: <Qubit register=(151, \"ancilla\"), index=12>,\n13: <Qubit register=(151, \"ancilla\"), index=13>,\n14: <Qubit register=(151, \"ancilla\"), index=14>,\n15: <Qubit register=(151, \"ancilla\"), index=15>,\n17: <Qubit register=(151, \"ancilla\"), index=16>,\n18: <Qubit register=(151, \"ancilla\"), index=17>,\n19: <Qubit register=(151, \"ancilla\"), index=18>,\n20: <Qubit register=(151, \"ancilla\"), index=19>,\n25: <Qubit register=(151, \"ancilla\"), index=20>,\n26: <Qubit register=(151, \"ancilla\"), index=21>,\n27: <Qubit register=(151, \"ancilla\"), index=22>,\n28: <Qubit register=(151, \"ancilla\"), index=23>,\n29: <Qubit register=(151, \"ancilla\"), index=24>,\n30: <Qubit register=(151, \"ancilla\"), index=25>,\n31: <Qubit register=(151, \"ancilla\"), index=26>,\n32: <Qubit register=(151, \"ancilla\"), index=27>,\n33: <Qubit register=(151, \"ancilla\"), index=28>,\n34: <Qubit register=(151, \"ancilla\"), index=29>,\n35: <Qubit register=(151, \"ancilla\"), index=30>,\n36: <Qubit register=(151, \"ancilla\"), index=31>,\n37: <Qubit register=(151, \"ancilla\"), index=32>,\n38: <Qubit register=(151, \"ancilla\"), index=33>,\n39: <Qubit register=(151, \"ancilla\"), index=34>,\n40: <Qubit register=(151, \"ancilla\"), index=35>,\n41: <Qubit register=(151, \"ancilla\"), index=36>,\n42: <Qubit register=(151, \"ancilla\"), index=37>,\n43: <Qubit register=(151, \"ancilla\"), index=38>,\n44: <Qubit register=(151, \"ancilla\"), index=39>,\n45: <Qubit register=(151, \"ancilla\"), index=40>,\n46: <Qubit register=(151, \"ancilla\"), index=41>,\n47: <Qubit register=(151, \"ancilla\"), index=42>,\n48: <Qubit register=(151, \"ancilla\"), index=43>,\n49: <Qubit register=(151, \"ancilla\"), index=44>,\n50: <Qubit register=(151, \"ancilla\"), index=45>,\n51: <Qubit register=(151, \"ancilla\"), index=46>,\n52: <Qubit register=(151, \"ancilla\"), index=47>,\n53: <Qubit register=(151, \"ancilla\"), index=48>,\n54: <Qubit register=(151, \"ancilla\"), index=49>,\n55: <Qubit register=(151, \"ancilla\"), index=50>,\n56: <Qubit register=(151, \"ancilla\"), index=51>,\n57: <Qubit register=(151, \"ancilla\"), index=52>,\n58: <Qubit register=(151, \"ancilla\"), index=53>,\n59: <Qubit register=(151, \"ancilla\"), index=54>,\n60: <Qubit register=(151, \"ancilla\"), index=55>,\n61: <Qubit register=(151, \"ancilla\"), index=56>,\n62: <Qubit register=(151, \"ancilla\"), index=57>,\n63: <Qubit register=(151, \"ancilla\"), index=58>,\n64: <Qubit register=(151, \"ancilla\"), index=59>,\n65: <Qubit register=(151, \"ancilla\"), index=60>,\n66: <Qubit register=(151, \"ancilla\"), index=61>,\n67: <Qubit register=(151, \"ancilla\"), index=62>,\n68: <Qubit register=(151, \"ancilla\"), index=63>,\n69: <Qubit register=(151, \"ancilla\"), index=64>,\n70: <Qubit register=(151, \"ancilla\"), index=65>,\n71: <Qubit register=(151, \"ancilla\"), index=66>,\n72: <Qubit register=(151, \"ancilla\"), index=67>,\n73: <Qubit register=(151, \"ancilla\"), index=68>,\n74: <Qubit register=(151, \"ancilla\"), index=69>,\n75: <Qubit register=(151, \"ancilla\"), index=70>,\n76: <Qubit register=(151, \"ancilla\"), index=71>,\n77: <Qubit register=(151, \"ancilla\"), index=72>,\n78: <Qubit register=(151, \"ancilla\"), index=73>,\n79: <Qubit register=(151, \"ancilla\"), index=74>,\n80: <Qubit register=(151, \"ancilla\"), index=75>,\n81: <Qubit register=(151, \"ancilla\"), index=76>,\n82: <Qubit register=(151, \"ancilla\"), index=77>,\n83: <Qubit register=(151, \"ancilla\"), index=78>,\n84: <Qubit register=(151, \"ancilla\"), index=79>,\n85: <Qubit register=(151, \"ancilla\"), index=80>,\n86: <Qubit register=(151, \"ancilla\"), index=81>,\n87: <Qubit register=(151, \"ancilla\"), index=82>,\n88: <Qubit register=(151, \"ancilla\"), index=83>,\n89: <Qubit register=(151, \"ancilla\"), index=84>,\n90: <Qubit register=(151, \"ancilla\"), index=85>,\n91: <Qubit register=(151, \"ancilla\"), index=86>,\n92: <Qubit register=(151, \"ancilla\"), index=87>,\n93: <Qubit register=(151, \"ancilla\"), index=88>,\n94: <Qubit register=(151, \"ancilla\"), index=89>,\n95: <Qubit register=(151, \"ancilla\"), index=90>,\n96: <Qubit register=(151, \"ancilla\"), index=91>,\n97: <Qubit register=(151, \"ancilla\"), index=92>,\n98: <Qubit register=(151, \"ancilla\"), index=93>,\n99: <Qubit register=(151, \"ancilla\"), index=94>,\n100: <Qubit register=(151, \"ancilla\"), index=95>,\n101: <Qubit register=(151, \"ancilla\"), index=96>,\n102: <Qubit register=(151, \"ancilla\"), index=97>,\n103: <Qubit register=(151, \"ancilla\"), index=98>,\n104: <Qubit register=(151, \"ancilla\"), index=99>,\n105: <Qubit register=(151, \"ancilla\"), index=100>,\n106: <Qubit register=(151, \"ancilla\"), index=101>,\n107: <Qubit register=(151, \"ancilla\"), index=102>,\n108: <Qubit register=(151, \"ancilla\"), index=103>,\n109: <Qubit register=(151, \"ancilla\"), index=104>,\n110: <Qubit register=(151, \"ancilla\"), index=105>,\n111: <Qubit register=(151, \"ancilla\"), index=106>,\n112: <Qubit register=(151, \"ancilla\"), index=107>,\n113: <Qubit register=(151, \"ancilla\"), index=108>,\n114: <Qubit register=(151, \"ancilla\"), index=109>,\n115: <Qubit register=(151, \"ancilla\"), index=110>,\n116: <Qubit register=(151, \"ancilla\"), index=111>,\n117: <Qubit register=(151, \"ancilla\"), index=112>,\n118: <Qubit register=(151, \"ancilla\"), index=113>,\n119: <Qubit register=(151, \"ancilla\"), index=114>,\n120: <Qubit register=(151, \"ancilla\"), index=115>,\n121: <Qubit register=(151, \"ancilla\"), index=116>,\n122: <Qubit register=(151, \"ancilla\"), index=117>,\n123: <Qubit register=(151, \"ancilla\"), index=118>,\n124: <Qubit register=(151, \"ancilla\"), index=119>,\n125: <Qubit register=(151, \"ancilla\"), index=120>,\n126: <Qubit register=(151, \"ancilla\"), index=121>,\n127: <Qubit register=(151, \"ancilla\"), index=122>,\n128: <Qubit register=(151, \"ancilla\"), index=123>,\n129: <Qubit register=(151, \"ancilla\"), index=124>,\n130: <Qubit register=(151, \"ancilla\"), index=125>,\n131: <Qubit register=(151, \"ancilla\"), index=126>,\n132: <Qubit register=(151, \"ancilla\"), index=127>,\n133: <Qubit register=(151, \"ancilla\"), index=128>,\n134: <Qubit register=(151, \"ancilla\"), index=129>,\n135: <Qubit register=(151, \"ancilla\"), index=130>,\n136: <Qubit register=(151, \"ancilla\"), index=131>,\n137: <Qubit register=(151, \"ancilla\"), index=132>,\n138: <Qubit register=(151, \"ancilla\"), index=133>,\n139: <Qubit register=(151, \"ancilla\"), index=134>,\n140: <Qubit register=(151, \"ancilla\"), index=135>,\n141: <Qubit register=(151, \"ancilla\"), index=136>,\n142: <Qubit register=(151, \"ancilla\"), index=137>,\n143: <Qubit register=(151, \"ancilla\"), index=138>,\n144: <Qubit register=(151, \"ancilla\"), index=139>,\n145: <Qubit register=(151, \"ancilla\"), index=140>,\n146: <Qubit register=(151, \"ancilla\"), index=141>,\n147: <Qubit register=(151, \"ancilla\"), index=142>,\n148: <Qubit register=(151, \"ancilla\"), index=143>,\n149: <Qubit register=(151, \"ancilla\"), index=144>,\n150: <Qubit register=(151, \"ancilla\"), index=145>,\n151: <Qubit register=(151, \"ancilla\"), index=146>,\n152: <Qubit register=(151, \"ancilla\"), index=147>,\n153: <Qubit register=(151, \"ancilla\"), index=148>,\n154: <Qubit register=(151, \"ancilla\"), index=149>,\n155: <Qubit register=(151, \"ancilla\"), index=150>\n})",
+      "final_layout": null
+    }
+  },
+  "C_magnitude": 1.1672611233138883,
+  "C_magnitude_error": 0.003986879658025441,
+  "timestamp": "20260117_205321",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2",
+    "qiskit_ibm_runtime": "0.45.0"
+  }
+}

artifacts/branch_transfer/noise_snapshots/ibm_fez_20260117_205750_properties.json

@@ -0,0 +1,18 @@
+{
+  "backend_name": "ibm_fez",
+  "timestamp": "20260117_205750",
+  "num_qubits": 156,
+  "version": "2",
+  "basis_gates": [
+    "measure",
+    "rz",
+    "reset",
+    "cz",
+    "delay",
+    "if_else",
+    "id",
+    "x",
+    "sx"
+  ],
+  "properties_timestamp": "2026-01-17 19:50:28+08:00"
+}

artifacts/branch_transfer/noise_snapshots/ibm_fez_20260117_205802_properties.json

@@ -0,0 +1,18 @@
+{
+  "backend_name": "ibm_fez",
+  "timestamp": "20260117_205802",
+  "num_qubits": 156,
+  "version": "2",
+  "basis_gates": [
+    "measure",
+    "rz",
+    "reset",
+    "cz",
+    "delay",
+    "if_else",
+    "id",
+    "x",
+    "sx"
+  ],
+  "properties_timestamp": "2026-01-17 19:50:28+08:00"
+}

artifacts/branch_transfer/noise_snapshots/ibm_fez_20260117_205833_properties.json

@@ -0,0 +1,18 @@
+{
+  "backend_name": "ibm_fez",
+  "timestamp": "20260117_205833",
+  "num_qubits": 156,
+  "version": "2",
+  "basis_gates": [
+    "cz",
+    "id",
+    "rz",
+    "if_else",
+    "x",
+    "sx",
+    "delay",
+    "reset",
+    "measure"
+  ],
+  "properties_timestamp": "2026-01-17 19:50:28+08:00"
+}

artifacts/branch_transfer/sim_20260117_154945_aer_simulator_noisy_ibm_brisbane_main_mu-1_shots-20000_opt-0.json

@@ -0,0 +1,59 @@
+{
+  "backend": "aer_simulator_noisy_ibm_brisbane",
+  "backend_type": "noisy_simulator",
+  "noise_source": "ibm_brisbane",
+  "mode": "main",
+  "mu": 1,
+  "shots": 20000,
+  "counts": {
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+    "11": 636,
+    "10": 9437,
+    "01": 9191
+  },
+  "probabilities": {
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+    "10": 0.47185,
+    "01": 0.45955
+  },
+  "visibility": 0.8629319769113698,
+  "visibility_error": 0.0035716858211577215,
+  "conditional_probabilities": {
+    "P(P=1|R=0)": 0.9276516268554016,
+    "P(P=1|R=1)": 0.06471964994403175,
+    "n_R0": 10173,
+    "n_R1": 9827
+  },
+  "expected_distribution": {
+    "01": 0.5,
+    "10": 0.5
+  },
+  "circuit_stats": {
+    "num_qubits": 5,
+    "num_clbits": 2,
+    "depth": 8,
+    "size": 11,
+    "gate_counts": {
+      "h": 1,
+      "cx": 5,
+      "x": 3
+    },
+    "two_qubit_gate_count": 5
+  },
+  "transpiled_depth": 8,
+  "transpiled_size": 11,
+  "optimization_level": 0,
+  "noise_params": {
+    "T1_us": 200,
+    "T2_us": 135,
+    "single_qubit_error_pct": 0.15,
+    "two_qubit_error_pct": 0.8,
+    "readout_error_pct": 2.5
+  },
+  "timestamp": "20260117_154945",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2"
+  }
+}

artifacts/branch_transfer/sim_20260117_154945_aer_simulator_noisy_ibm_brisbane_main_mu-1_shots-20000_opt-1.json

@@ -0,0 +1,59 @@
+{
+  "backend": "aer_simulator_noisy_ibm_brisbane",
+  "backend_type": "noisy_simulator",
+  "noise_source": "ibm_brisbane",
+  "mode": "main",
+  "mu": 1,
+  "shots": 20000,
+  "counts": {
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+    "11": 644,
+    "10": 9241,
+    "01": 9410
+  },
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+    "11": 0.0322,
+    "10": 0.46205,
+    "01": 0.4705
+  },
+  "visibility": 0.865063125240732,
+  "visibility_error": 0.0035474659691202967,
+  "conditional_probabilities": {
+    "P(P=1|R=0)": 0.929117233058516,
+    "P(P=1|R=1)": 0.06405410781778396,
+    "n_R0": 9946,
+    "n_R1": 10054
+  },
+  "expected_distribution": {
+    "01": 0.5,
+    "10": 0.5
+  },
+  "circuit_stats": {
+    "num_qubits": 5,
+    "num_clbits": 2,
+    "depth": 8,
+    "size": 11,
+    "gate_counts": {
+      "h": 1,
+      "cx": 5,
+      "x": 3
+    },
+    "two_qubit_gate_count": 5
+  },
+  "transpiled_depth": 8,
+  "transpiled_size": 11,
+  "optimization_level": 1,
+  "noise_params": {
+    "T1_us": 200,
+    "T2_us": 135,
+    "single_qubit_error_pct": 0.15,
+    "two_qubit_error_pct": 0.8,
+    "readout_error_pct": 2.5
+  },
+  "timestamp": "20260117_154945",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2"
+  }
+}

artifacts/branch_transfer/sim_20260117_154945_aer_simulator_noisy_ibm_brisbane_main_mu-1_shots-20000_opt-2.json

@@ -0,0 +1,59 @@
+{
+  "backend": "aer_simulator_noisy_ibm_brisbane",
+  "backend_type": "noisy_simulator",
+  "noise_source": "ibm_brisbane",
+  "mode": "main",
+  "mu": 1,
+  "shots": 20000,
+  "counts": {
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+    "00": 680,
+    "10": 9262,
+    "01": 9437
+  },
+  "probabilities": {
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+    "00": 0.034,
+    "10": 0.4631,
+    "01": 0.47185
+  },
+  "visibility": 0.8698614021375679,
+  "visibility_error": 0.00348835341729255,
+  "conditional_probabilities": {
+    "P(P=1|R=0)": 0.9316032991349829,
+    "P(P=1|R=1)": 0.061741896997414995,
+    "n_R0": 9942,
+    "n_R1": 10058
+  },
+  "expected_distribution": {
+    "01": 0.5,
+    "10": 0.5
+  },
+  "circuit_stats": {
+    "num_qubits": 5,
+    "num_clbits": 2,
+    "depth": 8,
+    "size": 11,
+    "gate_counts": {
+      "h": 1,
+      "cx": 5,
+      "x": 3
+    },
+    "two_qubit_gate_count": 5
+  },
+  "transpiled_depth": 8,
+  "transpiled_size": 11,
+  "optimization_level": 2,
+  "noise_params": {
+    "T1_us": 200,
+    "T2_us": 135,
+    "single_qubit_error_pct": 0.15,
+    "two_qubit_error_pct": 0.8,
+    "readout_error_pct": 2.5
+  },
+  "timestamp": "20260117_154945",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2"
+  }
+}

artifacts/branch_transfer/sim_20260117_154945_aer_simulator_noisy_ibm_brisbane_main_mu-1_shots-20000_opt-3.json

@@ -0,0 +1,59 @@
+{
+  "backend": "aer_simulator_noisy_ibm_brisbane",
+  "backend_type": "noisy_simulator",
+  "noise_source": "ibm_brisbane",
+  "mode": "main",
+  "mu": 1,
+  "shots": 20000,
+  "counts": {
+    "01": 9341,
+    "11": 581,
+    "00": 734,
+    "10": 9344
+  },
+  "probabilities": {
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+    "11": 0.02905,
+    "00": 0.0367,
+    "10": 0.4672
+  },
+  "visibility": 0.8686113463143097,
+  "visibility_error": 0.0035009429380310855,
+  "conditional_probabilities": {
+    "P(P=1|R=0)": 0.927168088906529,
+    "P(P=1|R=1)": 0.05855674259221931,
+    "n_R0": 10078,
+    "n_R1": 9922
+  },
+  "expected_distribution": {
+    "01": 0.5,
+    "10": 0.5
+  },
+  "circuit_stats": {
+    "num_qubits": 5,
+    "num_clbits": 2,
+    "depth": 8,
+    "size": 11,
+    "gate_counts": {
+      "h": 1,
+      "cx": 5,
+      "x": 3
+    },
+    "two_qubit_gate_count": 5
+  },
+  "transpiled_depth": 8,
+  "transpiled_size": 11,
+  "optimization_level": 3,
+  "noise_params": {
+    "T1_us": 200,
+    "T2_us": 135,
+    "single_qubit_error_pct": 0.15,
+    "two_qubit_error_pct": 0.8,
+    "readout_error_pct": 2.5
+  },
+  "timestamp": "20260117_154945",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2"
+  }
+}

artifacts/branch_transfer/sim_20260117_154945_aer_simulator_statevector_main_mu-1_shots-20000_opt-0.json

@@ -0,0 +1,47 @@
+{
+  "backend": "aer_simulator_statevector",
+  "backend_type": "ideal",
+  "mode": "main",
+  "mu": 1,
+  "shots": 20000,
+  "counts": {
+    "10": 10023,
+    "01": 9977
+  },
+  "probabilities": {
+    "10": 0.50115,
+    "01": 0.49885
+  },
+  "visibility": 1.0,
+  "visibility_error": 0.0,
+  "conditional_probabilities": {
+    "P(P=1|R=0)": 1.0,
+    "P(P=1|R=1)": 0.0,
+    "n_R0": 10023,
+    "n_R1": 9977
+  },
+  "expected_distribution": {
+    "01": 0.5,
+    "10": 0.5
+  },
+  "circuit_stats": {
+    "num_qubits": 5,
+    "num_clbits": 2,
+    "depth": 8,
+    "size": 11,
+    "gate_counts": {
+      "h": 1,
+      "cx": 5,
+      "x": 3
+    },
+    "two_qubit_gate_count": 5
+  },
+  "transpiled_depth": 8,
+  "transpiled_size": 11,
+  "optimization_level": 0,
+  "timestamp": "20260117_154945",
+  "qiskit_version": {
+    "qiskit": "2.3.0",
+    "qiskit_aer": "0.17.2"
+  }
+}