| ## Background | |
| This is level 2 of 5 and continues the work of the earlier levels. The new files for this level are in `workspace/t2/`. The records from the start are in `workspace/t1/`, and the earlier results are in `workspace/t1/results/`. | |
| ## Task | |
| Subject: more SRAM for the accelerator firmware | |
| Hi, | |
| The accelerator firmware and its buffers no longer fit in the memory Croc gives us. I would like the same amount of SRAM MLEM had. I have collected selected design and library views from mlem-tapeout-final under tapeout-archive/croc; my notes are in tapeout-2026/notes. Mira wants your view before I change the memory configuration. | |
| Please compare ways we could build that much memory from the available IHP macros, including Croc's existing mapping and the native macro with the same logical bank dimensions as MLEM. What does each cost in macro area, and how much of a 100 MHz read cycle does it leave for downstream logic? Use the corners from your IO review, with the timing range as well as the planning estimate. Tell us which option you recommend and what it would take to integrate it, including whether the existing wrapper preserves the logical word and byte accesses and any qualification issues you find. | |
| Please send the comparison as workspace/t2/results/memory_options.csv and a short design-review note as workspace/t2/results/memory_options.pdf. We will use them at Thursday's review. | |
| Thanks, | |
| Jonas | |
| ## Input | |
| - `workspace/t1/`: the records supplied with the work (`croc/`, `tapeout-2026/`). | |
| - `workspace/t2/`: the files that came with level t2 (`tapeout-2026/`, `tapeout-archive/`). | |
| - `workspace/t1/results/`: the results of level t1. | |
| ## Output | |
| - `workspace/t2/results/memory_options.pdf` | |
| - `workspace/t2/results/memory_options.csv` | |