HDTenEightyP/CompuServe · Datasets at Hugging Face

text stringlengths 0 99.6k
of the 256 possible banks your code is located in.

The Data Bank Register is used in conjunction with either of the index
registers X or Y to denote a high order 8 bit offset. It is not used
with the Accumulator.

The Processor sees the Stack only in Zero Bank (i.e.,) the highest 8 bits
of the 24 address lines are zeroed out when the Stack is accessed).

The Direct Page Register is used for adjusting where Zero Page will be
found in the given 64K Bank. The Effective Address is arrived at by adding
the argument of the opcode to D and then zeroing out the high order bits
16 through 23. That way no matter what value is in Direct Page Register,
the resulting Effective Address will remain in the same Bank that you
started with; that is, there's no wrapping over Bank Boundaries.


* Processor Status Register *

Bit Significance Flag The Easy Way of Checking
0 Carry C (test by BCC or BCS)
1 Zero/Equality Z (test by BNE or BEQ)
2 Interrupt I PHP PLA AND #$02 (test by BNE or BEQ)
3 Decimal D PHP PLA AND #$04 (test by BNE or BEQ)
4 Index Width X PHP PLA AND #$08 (test by BNE or BEQ)
5 Accum Width M PHP PLA AND #$10 (test by BNE or BEQ)
6 Overflow V PHP PLA BIT #$40 (test by BNE, BEQ, BVC, BVS)
7 Minus/Negation N (test by BPL or BMI)
8 Emulation Flag E XCE (then test by BCC or BCS)


* 8 Bit Mode *

By adjusting certain bits of the processor status register you can toggle
A, X, or Y from 8 bit mode to 16 bit mode.

When Bit M = 1 the Accumulator will behave in truncated 8 Bit Mode and the
high byte of the Accumulator (called "Accumulator B") will remain untouched
by Accumulator operations.

When Bit M = 0 the Accumulator will behave in "long" 16 bit mode. Additions,
subtractions, shifts, and rotates will involve both low and high bytes.

In either case, the low and high bytes of Accumulator may be swapped by
employing the XBA instruction. There do not seem to be any instructions
for loading, storing, or otherwise independently manipulating Accumulator
"B" save by swapping it down to the low byte position.

When Bit X = 1 both of the index Registers X and Y will behave in short 8
Bit Mode. The High Bytes will remain untouched and unaltered.

When Bit X = 0 both of the index Registers X and Y will behave in long 16
Bit Mode. That is, instructions like INX or DEX will involve both bytes
of the index registers.


* Emulation Mode *

The main purpose for the Emulation bit of the 65C816 mpu is for providing
an enhanced degree of compatibility with the old NMOS 6502. That is,
instruction timings are identical to that of the 6502. System interrupts
are driven by the old regular 6502 hardware vectors that we have all come
to love and hate. It is interesting that one of the tricks of playing with
the 65C816 would be to avoid COP and ABORT interrupts by going into
Emulation (E=1) mode.

Apparently there is no reduction in the 65C816 instruction set when toggling
the Emulation Bit; all the regular instructions remain available- It is
only in the timing of the cycles, and the processing of interrupts, that
things will differ.


* Incompatibilities *

The 65C816 does not contain the 65C02 instructions SMB (Set Memory Bit),
RMB (Clear or Reset Memory Bit), BBR (Branch on Bit Reset), or BBS
(Branch on Bit Set).

The BRK software interrupt will use either vector $FFFE or $FFF6 depending
on whether Emulation Bit is Clear or Set, respectively.

The 65C816 will write (i.e., corrupt) a series of bytes on system RESET
by saving PBR, PC high, PC low, Processor Status on Stack somewhere in
Bank Zero. The 6502 does not save any information on stack at RESET.
Since the high byte of stack pointer is cleared to one on RESET, we might
assume that the data is written to an unpredictable range in page one(?)..
On the other hand, we might further expect RESET (with E=1) to behave
properly and refrain from saving registers on stack.

JMP Indirect on a page boundary works properly, unlike 6502.

Unimplemented 6502 opcodes behave as the Implemented 65816 opcodes.

Logical Flags are valid even in Decimal Mode. [Hmmmm. Gonna have to try
that one out!]

Extra Memory Read on page boundary fetches last byte read, not spurious
byte. This relates to data latching, and is of concern when writing to
I/O peripherals that are sensitive to read's and write's... Since I'm
not much of a hardware hacker, I won't dwell on this point. Apparently

of the 256 possible banks your code is located in.

The Data Bank Register is used in conjunction with either of the index

registers X or Y to denote a high order 8 bit offset. It is not used

with the Accumulator.

The Processor sees the Stack only in Zero Bank (i.e.,) the highest 8 bits

of the 24 address lines are zeroed out when the Stack is accessed).

The Direct Page Register is used for adjusting where Zero Page will be

found in the given 64K Bank. The Effective Address is arrived at by adding

the argument of the opcode to D and then zeroing out the high order bits

16 through 23. That way no matter what value is in Direct Page Register,

the resulting Effective Address will remain in the same Bank that you

started with; that is, there's no wrapping over Bank Boundaries.

*** Processor Status Register ***

Bit Significance Flag The Easy Way of Checking

0 Carry C (test by BCC or BCS)

1 Zero/Equality Z (test by BNE or BEQ)

2 Interrupt I PHP PLA AND #$02 (test by BNE or BEQ)

3 Decimal D PHP PLA AND #$04 (test by BNE or BEQ)

4 Index Width X PHP PLA AND #$08 (test by BNE or BEQ)

5 Accum Width M PHP PLA AND #$10 (test by BNE or BEQ)

6 Overflow V PHP PLA BIT #$40 (test by BNE, BEQ, BVC, BVS)

7 Minus/Negation N (test by BPL or BMI)

8 Emulation Flag E XCE (then test by BCC or BCS)

*** 8 Bit Mode ***

By adjusting certain bits of the processor status register you can toggle

A, X, or Y from 8 bit mode to 16 bit mode.

When Bit M = 1 the Accumulator will behave in truncated 8 Bit Mode and the

high byte of the Accumulator (called "Accumulator B") will remain untouched

by Accumulator operations.

When Bit M = 0 the Accumulator will behave in "long" 16 bit mode. Additions,

subtractions, shifts, and rotates will involve both low and high bytes.

In either case, the low and high bytes of Accumulator may be swapped by

employing the XBA instruction. There do not seem to be any instructions

for loading, storing, or otherwise independently manipulating Accumulator

"B" save by swapping it down to the low byte position.

When Bit X = 1 both of the index Registers X and Y will behave in short 8

Bit Mode. The High Bytes will remain untouched and unaltered.

When Bit X = 0 both of the index Registers X and Y will behave in long 16

Bit Mode. That is, instructions like INX or DEX will involve both bytes

of the index registers.

*** Emulation Mode ***

The main purpose for the Emulation bit of the 65C816 mpu is for providing

an enhanced degree of compatibility with the old NMOS 6502. That is,

instruction timings are identical to that of the 6502. System interrupts

are driven by the old regular 6502 hardware vectors that we have all come

to love and hate. It is interesting that one of the tricks of playing with

the 65C816 would be to avoid COP and ABORT interrupts by going into

Emulation (E=1) mode.

Apparently there is no reduction in the 65C816 instruction set when toggling

the Emulation Bit; all the regular instructions remain available- It is

only in the timing of the cycles, and the processing of interrupts, that

things will differ.

*** Incompatibilities ***

The 65C816 does not contain the 65C02 instructions SMB (Set Memory Bit),

RMB (Clear or Reset Memory Bit), BBR (Branch on Bit Reset), or BBS

(Branch on Bit Set).

The BRK software interrupt will use either vector $FFFE or $FFF6 depending

on whether Emulation Bit is Clear or Set, respectively.

The 65C816 will write (i.e., corrupt) a series of bytes on system RESET

by saving PBR, PC high, PC low, Processor Status on Stack somewhere in

Bank Zero. The 6502 does not save any information on stack at RESET.

Since the high byte of stack pointer is cleared to one on RESET, we might

assume that the data is written to an unpredictable range in page one(?)..

On the other hand, we might further expect RESET (with E=1) to behave

properly and refrain from saving registers on stack.

JMP Indirect on a page boundary works properly, unlike 6502.

Unimplemented 6502 opcodes behave as the Implemented 65816 opcodes.

Logical Flags are valid even in Decimal Mode. [Hmmmm. Gonna have to try

that one out!]

Extra Memory Read on page boundary fetches last byte read, not spurious

byte. This relates to data latching, and is of concern when writing to

I/O peripherals that are sensitive to read's and write's... Since I'm

not much of a hardware hacker, I won't dwell on this point. Apparently