task_id stringlengths 16 24 | shuttle_name stringclasses 7
values | project_name stringlengths 12 79 | task_name stringlengths 7 59 | top_module_name stringlengths 9 54 | system_message stringclasses 1
value | prompt stringlengths 724 368k | golden_module stringlengths 66 320k |
|---|---|---|---|---|---|---|---|
tt06-finale_0001 | tt06-finale | CEJMU-tt06_tinyrv1 | task_alu | tt_um_cejmu_riscv | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fet... | module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire... |
tt06-finale_0002 | tt06-finale | CEJMU-tt06_tinyrv1 | task_control | tt_um_cejmu_riscv | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_... | module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _01... |
tt06-finale_0003 | tt06-finale | CEJMU-tt06_tinyrv1 | task_cpu | tt_um_cejmu_riscv | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_... | module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [... |
tt06-finale_0004 | tt06-finale | CEJMU-tt06_tinyrv1 | task_instructioncounter | tt_um_cejmu_riscv | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_... | module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
out... |
tt06-finale_0005 | tt06-finale | CEJMU-tt06_tinyrv1 | task_regs | tt_um_cejmu_riscv | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_... | module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0]... |
tt06-finale_0006 | tt06-finale | CEJMU-tt06_tinyrv1 | task_spi_master | tt_um_cejmu_riscv | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_... | module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire ... |
tt06-finale_0007 | tt06-finale | CEJMU-tt06_tinyrv1 | task_tt_um_cejmu_riscv | tt_um_cejmu_riscv | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_... | module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wi... |
tt06-finale_0008 | tt06-finale | CKPope-tt06-verilog-template | task_Compx1 | tt_um_CKPope_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTI... | module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
always @(*)
begin
aeqb = (a & b) | ((!(a)) & (!(b)));
agtb = a & (!(b));
altb = (!(a)) & b ;
end
endmodule |
tt06-finale_0009 | tt06-finale | CKPope-tt06-verilog-template | task_Compx4 | tt_um_CKPope_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTI... | module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
wire [3:0] aeqb;
wire [3:0] agtb;
wire [3:0] altb;
// connections to single bit comparators
Compx1 Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3])... |
tt06-finale_0010 | tt06-finale | CKPope-tt06-verilog-template | task_Mealy_SM | tt_um_CKPope_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTI... | module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
outp... |
tt06-finale_0011 | tt06-finale | CKPope-tt06-verilog-template | task_input_synch | tt_um_CKPope_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTI... | module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
reg [1:0] chain0, chain1;
always @ (posedge clk)
begin
chain0[1:0] <= {chain0[0], reset};
chain1[1:0] <= {chain1[0], sync_in};
end
assign sync_reset = (chain0[1]);
assign sync_ou... |
tt06-finale_0012 | tt06-finale | CKPope-tt06-verilog-template | task_target_reg | tt_um_CKPope_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTI... | module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
target_reg <= 4'b0000;
else if (load)
target_reg <= data ;
e... |
tt06-finale_0013 | tt06-finale | CKPope-tt06-verilog-template | task_ud_counter | tt_um_CKPope_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTI... | module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else if ((count_en & count_up1_dwn0) & (coun... |
tt06-finale_0014 | tt06-finale | EduHolg-FDC_chip | task_chip | tt_um_fdc_chip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
... |
tt06-finale_0015 | tt06-finale | EduHolg-FDC_chip | task_counter | tt_um_fdc_chip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule |
tt06-finale_0016 | tt06-finale | EduHolg-FDC_chip | task_demux | tt_um_fdc_chip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule |
tt06-finale_0017 | tt06-finale | EduHolg-FDC_chip | task_fdc_sincronico | tt_um_fdc_chip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
... |
tt06-finale_0018 | tt06-finale | EduHolg-FDC_chip | task_ff_d_fdc | tt_um_fdc_chip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule |
tt06-finale_0019 | tt06-finale | EduHolg-FDC_chip | task_register | tt_um_fdc_chip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule |
tt06-finale_0020 | tt06-finale | EduHolg-FDC_chip | task_tt_um_fdc_chip | tt_um_fdc_chip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt06-finale_0021 | tt06-finale | Fountaincoder-multimac | task_DMADD | tt_um_fountaincoder_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jonny Edwards
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_fountaincoder_top (
input wire clk, // clock
input wire ena, // will go high when the design is enabled
input wire [7:0] ui_in, // Dedicated inputs
ou... | module DMADD(
input wire clk,
input wire rst_n, // reset_n - low to reset
input wire [3:0] index,
input wire [3:0] data,
input wire [1:0] insn,
input wire load,
input wire run,
output [7:0] out,
output [3:0] out_top
);
reg [4:0] j; //j=0 ;
reg [3:0] i; // i = 4'b1111;
reg signed ... |
tt06-finale_0022 | tt06-finale | Fountaincoder-multimac | task_tt_um_fountaincoder_top | tt_um_fountaincoder_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jonny Edwards
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_fountaincoder_top (
input wire clk, // clock
input wire ena, // will go high when the design is enabled
input wire [7:0] ui_in, // Dedicated inputs
ou... | module tt_um_fountaincoder_top (
input wire clk, // clock
input wire ena, // will go high when the design is enabled
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire... |
tt06-finale_0023 | tt06-finale | JoseKaisen-ALU_3bits | task_ALU | tt_um_ALU | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // I... | module ALU (input [2:0] ctrl, input [2:0] A,B, output [5:0] Leds);
wire [5:0] Y3_MULT;
wire [3:0] Y1_ADD;
wire [2:0] Y2_MIN,Y4_DIV, Y5_MOD;
reg [5:0] aux;
arithmetic_operators U2 (.A(A), .B(B), .Y1_ADD(Y1_ADD),
.Y2_MIN(Y2_MIN), .Y3_MULT(Y3_MULT), .Y4_DIV(Y4_DIV), .Y5_MOD(Y5_MOD));
assign Leds= aux;
always... |
tt06-finale_0024 | tt06-finale | JoseKaisen-ALU_3bits | task_arithmetic_operators | tt_um_ALU | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // I... | module arithmetic_operators (input [2:0]A,B, output reg [3:0]Y1_ADD, output reg[5:0]Y3_MULT,
output reg[2:0]Y2_MIN, Y4_DIV, Y5_MOD);
always@(A,B)
begin
Y1_ADD = A + B;
Y2_MIN = A - B;
Y3_MULT = A * B;
Y4_DIV = A / B;
Y5_MOD = A % B;
end
endmodule |
tt06-finale_0025 | tt06-finale | JoseKaisen-ALU_3bits | task_tt_um_ALU | tt_um_ALU | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // I... | module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
inpu... |
tt06-finale_0026 | tt06-finale | Lefteris-B-i_tree | task_IsolationTreeStateMachine | tt_um_i_tree_batzolislefteris | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [... | module IsolationTreeStateMachine(
input wire clk,
input wire reset,
input wire [7:0] data_input,
input wire data_valid,
output reg anomaly_detected,
output reg data_processed
);
// Define state constants
localparam [1:0] IDLE = 2'b00,
CHECK_ANOMALY = 2'b01,
PRO... |
tt06-finale_0027 | tt06-finale | Lefteris-B-i_tree | task_i_tree | tt_um_i_tree_batzolislefteris | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [... | module i_tree(
input wire clk,
input wire reset,
input wire sensor_data, // Incoming sensor data bit
output wire anomaly_detected // Output indicating if an anomaly was detected
);
// Internal signal declarations
wire [7:0] data_from_buffer;
wire data_ready;
wire data_processed;
// Instantiate the Inp... |
tt06-finale_0028 | tt06-finale | Lefteris-B-i_tree | task_tt_um_i_tree_batzolislefteris | tt_um_i_tree_batzolislefteris | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [... | module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input,... |
tt06-finale_0029 | tt06-finale | OnSachinSharma-tt06-verilog-PWM | task_DFF_PWM | tt_um_shivam | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_shivam (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, /... | module DFF_PWM(clk,en,D,Q);
input clk,en,D;
output reg Q;
always @(posedge clk)
begin
if(en==1) // slow clock enable signal
Q <= D;
end
endmodule |
tt06-finale_0030 | tt06-finale | OnSachinSharma-tt06-verilog-PWM | task_tt_um_shivam | tt_um_shivam | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_shivam (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, /... | module tt_um_shivam (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
i... |
tt06-finale_0031 | tt06-finale | SteffenReith-TT06_ASG | task_ASG | tt_um_SteffenReith_ASGTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire... | module ASG (
input wire [1:0] loadIt,
input wire load,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire R1_enable;
wire R2_enable;
wire R3_enable;
wire R1_... |
tt06-finale_0032 | tt06-finale | SteffenReith-TT06_ASG | task_LSFR | tt_um_SteffenReith_ASGTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire... | module LSFR (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [30:0] fsRegN;
reg [30:0] fsReg;
wire taps_0;
wire taps_1;
re... |
tt06-finale_0033 | tt06-finale | SteffenReith-TT06_ASG | task_LSFR_1 | tt_um_SteffenReith_ASGTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire... | module LSFR_1 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [62:0] fsRegN;
reg [62:0] fsReg;
wire taps_0;
wire taps_1;
... |
tt06-finale_0034 | tt06-finale | SteffenReith-TT06_ASG | task_LSFR_2 | tt_um_SteffenReith_ASGTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire... | module LSFR_2 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [88:0] fsRegN;
reg [88:0] fsReg;
wire taps_0;
wire taps_1;
... |
tt06-finale_0035 | tt06-finale | SteffenReith-TT06_ASG | task_tt_um_SteffenReith_ASGTop | tt_um_SteffenReith_ASGTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire... | module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=... |
tt06-finale_0036 | tt06-finale | SteffenReith-TT06_PiMac | task_PiMAC | tt_um_SteffenReith_PiMACTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : PiMAC
// Git hash : 82e1b4b4426cb20a6f387f1686876bda014c9247
`timescale 1ns/1ps
module PiMAC (
input wire [3:0] a,
input wire [3:0] b,
input wire [3:0] c,
output wire [7:0] result,
input w... | module PiMAC (
input wire [3:0] a,
input wire [3:0] b,
input wire [3:0] c,
output wire [7:0] result,
input wire clk,
input wire reset
);
wire [4:0] _zz_nodes_1_ACC_1;
wire [5:0] _zz_nodes_2_ACC_2;
wire [6:0] _zz_nodes_3_ACC_3;
reg ... |
tt06-finale_0037 | tt06-finale | SteffenReith-TT06_PiMac | task_tt_um_SteffenReith_PiMACTop | tt_um_SteffenReith_PiMACTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : PiMAC
// Git hash : 82e1b4b4426cb20a6f387f1686876bda014c9247
`timescale 1ns/1ps
module PiMAC (
input wire [3:0] a,
input wire [3:0] b,
input wire [3:0] c,
output wire [7:0] result,
input w... | module tt_um_SteffenReith_PiMACTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... |
tt06-finale_0038 | tt06-finale | ThorKn-TT06_AudioChip_V2 | task_PWMaudio | tt_um_thorkn_audiochip_v2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module PWMaudio (
output io_pwm_1,
output io_pwm_2,
input [11:0] io_frequency,
input io_adsr_switch,
input [2:0] io_adsr_choice,
input clk,
input reset
);
localparam fsm_adsr_enumDef_BOOT = 3'd0;
localparam fsm_adsr_enu... |
tt06-finale_0039 | tt06-finale | ThorKn-TT06_AudioChip_V2 | task_PWMctrl | tt_um_thorkn_audiochip_v2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module PWMctrl (
input [11:0] io_freq,
input [7:0] io_level,
output io_pwm_1,
output io_pwm_2,
input clk,
input reset
);
wire pwmdriver_1_1_io_pwm;
wire pwmdriver_2_io_pwm;
wire [11:0] _zz_freq_... |
tt06-finale_0040 | tt06-finale | ThorKn-TT06_AudioChip_V2 | task_PWMdriver | tt_um_thorkn_audiochip_v2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module PWMdriver (
input [7:0] io_dutyCycle,
output io_pwm,
input clk,
input reset
);
wire [7:0] _zz_counter_valueNext;
wire [0:0] _zz_counter_valueNext_1;
reg counter_willIncrement;
wire counter_willClear... |
tt06-finale_0041 | tt06-finale | ThorKn-TT06_AudioChip_V2 | task_tt_um_thorkn_audiochip_v2 | tt_um_thorkn_audiochip_v2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=... |
tt06-finale_0042 | tt06-finale | adennen-tt06-arond-project | task_clock_divider | tt_um_7seg_animated | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module clock_divider (
// Inputs
input wire clk,
input wire reset,
// Outputs
output wire clkPwm,
output wire clk60
);
reg [5:0] count; // 6-bit counter for 12.5 MHz -> 122,400 Hz signal (51 counts per transition)
reg [9:0] count2; // 10-bit counter for 122,400 Hz -> 60 Hz signal (1020 counts per tr... |
tt06-finale_0043 | tt06-finale | adennen-tt06-arond-project | task_pwm | tt_um_7seg_animated | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module pwm (
// Inputs
input wire enable,
input wire clk,
input wire reset,
input wire [7:0] pwmValue,
// Outputs
output wire pwmOut
);
reg [7:0] pwmCount;
reg out;
assign pwmOut = out;
always @(posedge clk) begin
if (enable) begin
if (reset) begin
pwmCount <= 0;
... |
tt06-finale_0044 | tt06-finale | adennen-tt06-arond-project | task_segment_animator | tt_um_7seg_animated | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module segment_animator (
// Inputs
input wire reset,
input wire enable,
input wire clk,
input wire clk60, // 60Hz clock input for timing
input wire charAvailable, // A character is available to be read
input wire [6:0] charInput, // The next character to read
// Outputs
output wire [6:0] out // 7-s... |
tt06-finale_0045 | tt06-finale | adennen-tt06-arond-project | task_tt_um_7seg_animated | tt_um_7seg_animated | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output... |
tt06-finale_0046 | tt06-finale | aiju-tt06-aiju-8080 | task_bus_if | tt_um_aiju_8080 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IO... | module bus_if(
input wire clk,
input wire rst_n,
input wire bus_handshake_ack,
output reg bus_handshake_req,
output reg [1:0] bus_state,
input wire [7:0] bus_data_in,
output reg [7:0] bus_data_out,
output reg bus_output_enable,
output wire bus_io,
input wire memory_read,
input wire memory... |
tt06-finale_0047 | tt06-finale | aiju-tt06-aiju-8080 | task_cpu | tt_um_aiju_8080 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IO... | module cpu(
input wire clk,
input wire rst_n,
output reg memory_read,
output reg memory_write,
output reg [15:0] memory_addr,
output reg memory_io,
output reg [7:0] memory_wdata,
input wire [7:0] memory_rdata,
input wire memory_done,
input wire debug_req,
input wire int_req... |
tt06-finale_0048 | tt06-finale | aiju-tt06-aiju-8080 | task_sync | tt_um_aiju_8080 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IO... | module sync(
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
(* keep *) reg a;
(* keep *) reg b;
assign out = b;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a <= 1'b0;
b <= 1'b0;
end else begin
a <= in;
b <= a;
end
end
endmodule |
tt06-finale_0049 | tt06-finale | aiju-tt06-aiju-8080 | task_tt_um_aiju_8080 | tt_um_aiju_8080 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IO... | module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt06-finale_0050 | tt06-finale | andrewtron3000-tt06-verilog-template | task_Counter | tt_um_andrewtron3000 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;... |
tt06-finale_0051 | tt06-finale | andrewtron3000-tt06-verilog-template | task_FIFO1 | tt_um_andrewtron3000 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1'b1;
input CLK;
input RST;
input [width -... |
tt06-finale_0052 | tt06-finale | andrewtron3000-tt06-verilog-template | task_SizedFIFO | tt_um_andrewtron3000 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter ... |
tt06-finale_0053 | tt06-finale | andrewtron3000-tt06-verilog-template | task_mkRule30 | tt_um_andrewtron3000 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
input CLK;
input RST_N;
// action method start
input [7 : 0] start_a;
input EN_start;
output RDY_start;
// actionvalue method getResult
input EN_getResult;
output [7 : 0] getResult... |
tt06-finale_0054 | tt06-finale | andrewtron3000-tt06-verilog-template | task_mkRule30Driver | tt_um_andrewtron3000 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
input CLK;
input RST_N;
// action method operation_mode
input [... |
tt06-finale_0055 | tt06-finale | andrewtron3000-tt06-verilog-template | task_tt_um_andrewtron3000 | tt_um_andrewtron3000 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=outpu... |
tt06-finale_0056 | tt06-finale | couchand-tt06-cora16 | task_alu | tt_um_couchand_cora16 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module alu (
input wire [15:0] accum,
input wire [15:0] rhs,
output wire [15:0] result,
output wire zero,
output wire neg,
output wire carry,
output wire is_alu_inst,
input wire inst_add,
input wire inst_sub,
input wire inst_t... |
tt06-finale_0057 | tt06-finale | couchand-tt06-cora16 | task_cpu | tt_um_couchand_cora16 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module cpu (
input wire clk,
input wire rst_n,
output wire spi_mosi,
output wire spi_select,
output wire spi_clk,
input wire spi_miso,
input wire step,
output wire busy,
output wire halt,
output wire trap,
inp... |
tt06-finale_0058 | tt06-finale | couchand-tt06-cora16 | task_decoder | tt_um_couchand_cora16 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module decoder (
input wire en,
input wire [15:0] inst,
input wire [15:0] accum,
input wire [7:0] data,
output wire [15:0] rhs,
output wire [1:0] bytes,
output wire inst_nop,
output wire inst_halt,
output wire inst_trap,
output wire inst_l... |
tt06-finale_0059 | tt06-finale | couchand-tt06-cora16 | task_tt_um_couchand_cora16 | tt_um_couchand_cora16 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=outp... |
tt06-finale_0060 | tt06-finale | drburke3-SADdiff_v1 | task_black_cell | tt_um_drburke3_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module black_cell(G6_8,P6_8,G7_10,P7_10,G6_10,P6_10);
input G6_8,P6_8,G7_10,P7_10;
output G6_10,P6_10;
wire signal;
assign signal = P6_8 & G7_10;
assign G6_10=signal | G6_8;
assign P6_10=P6_8 & P7_10;
endmodule |
tt06-finale_0061 | tt06-finale | drburke3-SADdiff_v1 | task_generate_propagate | tt_um_drburke3_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module generate_propagate(A,B,G,P);
input A,B;
output G,P;
assign G = A&B;
assign P = A^B;
endmodule |
tt06-finale_0062 | tt06-finale | drburke3-SADdiff_v1 | task_gray_cell | tt_um_drburke3_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module gray_cell(G4_3,P4_3,G2_2,G4_2);
input G4_3,P4_3,G2_2;
output G4_2;
wire signal;
assign signal = P4_3 & G2_2;
assign G4_2=signal | G4_3;
endmodule |
tt06-finale_0063 | tt06-finale | drburke3-SADdiff_v1 | task_sklansky_adder_8bit | tt_um_drburke3_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module sklansky_adder_8bit(a,b,sum,enable,clock,reset_n);
input [7:0] a;
input [7:0] b;
output reg [7:0] sum;
input enable;
input clock;
input reset_n;
// declare array wires
wire [8:0] g [8:0];
wire [8:0] p [8:0];
assign g[0][0]=1'b0;
assign p[0][0]=1'b0;
generate_propagate GeneratePropagate_00(a[0],b[0],g[1][... |
tt06-finale_0064 | tt06-finale | existential-ai-izhekevich_neuron | task_signed_mult | tt_um_exai_izhikevich_neuron | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Dmitri Lyalikov
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
/**
| Behavior | A | B | C | D |
| --------------------------- | --- | ---- | --- | --- |
0| RS (Regular Spiking) | .02 | .02 | -65 | 8 |
1| IB (Intri... | module signed_mult (out, a, b);
output [17:0] out;
input signed [17:0] a;
input signed [17:0] b;
wire signed [17:0] out;
/* verilator lint_off UNUSEDSIGNAL */
wire signed [35:0] mult_out;
// Remove linter warning of unused bits
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out =... |
tt06-finale_0065 | tt06-finale | existential-ai-izhekevich_neuron | task_tt_um_exai_izhikevich_neuron | tt_um_exai_izhikevich_neuron | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Dmitri Lyalikov
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
/**
| Behavior | A | B | C | D |
| --------------------------- | --- | ---- | --- | --- |
0| RS (Regular Spiking) | .02 | .02 | -65 | 8 |
1| IB (Intri... | module tt_um_exai_izhikevich_neuron (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input,... |
tt06-finale_0066 | tt06-finale | ignaciosim-tt06-triple-watchdog | task_tt_um_triple_watchdog | tt_um_triple_watchdog | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
`timescale 1ns/1ns
module tt_um_triple_watchdog (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs:... | module tt_um_triple_watchdog (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=outp... |
tt06-finale_0067 | tt06-finale | ignaciosim-tt06-triple-watchdog | task_watchdog | tt_um_triple_watchdog | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
`timescale 1ns/1ns
module tt_um_triple_watchdog (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs:... | module watchdog (
input wire clk, // Clock input
input wire rst_n, // Reset input
input wire [7:0] ui_in, // Dedicated inputs
output wire watchdog_expired // Watchdog expiration signal
);
// Parameters
parameter TIMEOUT_VALUE = 100000; // Timeout value (in clock cycles)
// Internal si... |
tt06-finale_0068 | tt06-finale | jferrer08-latinpractice | task_RS232_TX | tt_um_topTDC | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module RS232_TX(D, reset, clk, EOT, STT, TX);
parameter BaudRate=9600;
parameter reloj=50000000;
parameter conta=reloj/BaudRate;
input clk,reset,STT;
input [7:0] D;
output reg TX, EOT;
reg B,enable; //Pulso Buad Rate emisor
reg [12:0] k;
reg [3:0] estado, nex_estado,M;
reg [7:0] Dreg;
wire P;
always @(estado... |
tt06-finale_0069 | tt06-finale | jferrer08-latinpractice | task_contadorTDC | tt_um_topTDC | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module contadorTDC(start, clk, cuenta);
input start;
input clk;
output reg [7:0] cuenta;
reg [7:0] q;
always @(posedge clk, negedge start)
begin
if (start == 0)
q <= 0;
else
q <= q + 1'b1;
end
always @(posedge clk)
begin
cuenta <= q;
end
endmodule |
tt06-finale_0070 | tt06-finale | jferrer08-latinpractice | task_topTDC | tt_um_topTDC | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module topTDC(clk, stop, reset, tx, eot);
input clk;
input stop;
input reset;
//output [7:0] dato;
output tx,eot;
//estados
reg [2:0] estado, edo_futuro;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
reg stc; //start de cuen... |
tt06-finale_0071 | tt06-finale | jferrer08-latinpractice | task_tt_um_topTDC | tt_um_topTDC | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
i... |
tt06-finale_0072 | tt06-finale | mattvenn-tt06-ian-keypad-controller | task_decoder | tt_um_ian_keypad_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7... | module decoder(
input [3:0] key, // inputs
output reg [6:0] segments // outputs
);
always @(*) begin
case(key)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b100... |
tt06-finale_0073 | tt06-finale | mattvenn-tt06-ian-keypad-controller | task_keypad | tt_um_ian_keypad_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7... | module keypad(
input wire clk,
input wire reset,
input [3:0] rows, // inputs
output reg [3:0] cols, // outputs
output reg [1:0] counter_cols,
output reg [3:0] key
);
// Debounced Rows
// Instantiate the debounce module for each row
wire [3:0] debounced_rows; // Debounced signals for each row
... |
tt06-finale_0074 | tt06-finale | mattvenn-tt06-ian-keypad-controller | task_tt_um_ian_keypad_controller | tt_um_ian_keypad_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7... | module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... |
tt06-finale_0075 | tt06-finale | mattvenn-tt06-rgb-mixer | task_rgb_mixer | tt_um_mattvenn_rgb_mixer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mattvenn_rgb_mixer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0]... | module rgb_mixer (
input wire clk,
input wire reset,
input wire enc0_a,
input wire enc0_b,
input wire enc1_a,
input wire enc1_b,
input wire enc2_a,
input wire enc2_b,
output wire pwm0_out,
output wire pwm1_out,
output wire pwm2_out,
output wire [7:0] enc0,
output wire... |
tt06-finale_0076 | tt06-finale | mattvenn-tt06-rgb-mixer | task_tt_um_mattvenn_rgb_mixer | tt_um_mattvenn_rgb_mixer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mattvenn_rgb_mixer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0]... | module tt_um_mattvenn_rgb_mixer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=o... |
tt06-finale_0077 | tt06-finale | matztron-tt06-PAL | task_tt_um_MATTHIAS_M_PAL_TOP_WRAPPER | tt_um_MATTHIAS_M_PAL_TOP_WRAPPER | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_MATTHIAS_M_PAL_TOP_WRAPPER (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wi... | module tt_um_MATTHIAS_M_PAL_TOP_WRAPPER (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=in... |
tt06-finale_0078 | tt06-finale | mitsece-tt06-verilog-mitssdd | task_co_processor | tt_um_mitssdd | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module co_processor (
input [7:0] r0, // 8-bit input
input [1:0] check, // sensor checking
input reset,
input clk, // clock input
output reg Q // output Q
);
reg [7:0] proc; // processing register
reg [7:0] r1= 8'b0;
reg [7:0] r2= 8'b0;
reg [7:0] r3= 8'b0;
reg [7:0] r4= 8'b0;
reg [7:0] res;
alway... |
tt06-finale_0079 | tt06-finale | mitsece-tt06-verilog-mitssdd | task_fault_pro | tt_um_mitssdd | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module fault_pro(
input [7:0] r0,
input [1:0] check,
input reset,
input clk,
output reg [2:0] out,
output reg [1:0] out1
);
reg [9:0] proc;
reg [2:0] counter1 = 3'b0;
reg [2:0] counter2 = 3'b0;
reg [2:0] counter3 = 3'b0;
reg [2:0] counter4 = 3'b0;
reg maincount = 1'b0;
reg fin = 1'b0;
reg ... |
tt06-finale_0080 | tt06-finale | mitsece-tt06-verilog-mitssdd | task_tt_um_mitssdd | tt_um_mitssdd | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt06-finale_0081 | tt06-finale | noritsuna-tt06-tt_um_i4004 | task_alu | tt_um_noritsuna_i4004 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@op... | module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
... |
tt06-finale_0082 | tt06-finale | noritsuna-tt06-tt_um_i4004 | task_counter | tt_um_noritsuna_i4004 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@op... | module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule |
tt06-finale_0083 | tt06-finale | noritsuna-tt06-tt_um_i4004 | task_instruction_decode | tt_um_noritsuna_i4004 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@op... | module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clea... |
tt06-finale_0084 | tt06-finale | noritsuna-tt06-tt_um_i4004 | task_instruction_pointer | tt_um_noritsuna_i4004 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@op... | module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,... |
tt06-finale_0085 | tt06-finale | noritsuna-tt06-tt_um_i4004 | task_scratchpad | tt_um_noritsuna_i4004 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@op... | module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input ... |
tt06-finale_0086 | tt06-finale | noritsuna-tt06-tt_um_i4004 | task_timing_io | tt_um_noritsuna_i4004 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@op... | module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output ... |
tt06-finale_0087 | tt06-finale | noritsuna-tt06-tt_um_i4004 | task_tt_um_noritsuna_i4004 | tt_um_noritsuna_i4004 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@op... | module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=outp... |
tt06-finale_0088 | tt06-finale | pcky-tt06-wokwi | task_number_init | tt_um_pckys_game | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module number_init(
input clk,
input rst,
output [7:0] out
);
reg [7:0] counter;
assign out = counter;
always @(posedge clk )
begin
counter <= 0;
if (rst) begin
counter <= counter + 1;
end else begin
end
end
endmodule |
tt06-finale_0089 | tt06-finale | pcky-tt06-wokwi | task_timer | tt_um_pckys_game | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module timer(input clk, output reg [11:0] counter = 12'h0 + 12'd512, output reg [2:0] counter2 = 0);
reg flag1 = 0;
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter[9]) begin
if(counter2 == 6)
counter2 <= 0;
if(flag1) begin
flag1 <=... |
tt06-finale_0090 | tt06-finale | pcky-tt06-wokwi | task_tt_um_pckys_game | tt_um_pckys_game | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt06-finale_0091 | tt06-finale | pyamnihc-tt06_um_ks_pyamnihc | task_prbs15 | tt_um_ks_pyamnihc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out... | module prbs15 (
input clk_i,
input rst_ni,
input [14:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [14:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS15 = x^15 + x^14 + 1
reg [14:0] lfs... |
tt06-finale_0092 | tt06-finale | pyamnihc-tt06_um_ks_pyamnihc | task_prbs7 | tt_um_ks_pyamnihc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out... | module prbs7 (
input clk_i,
input rst_ni,
input [6:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [6:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS7 = x^7 + x^6 + 1
reg [6:0] lfsr_reg;
... |
tt06-finale_0093 | tt06-finale | pyamnihc-tt06_um_ks_pyamnihc | task_tt_um_ks_pyamnihc | tt_um_ks_pyamnihc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out... | module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out, // IOs: Bidirectiona... |
tt06-finale_0094 | tt06-finale | tommythorn-tt06-tommythorn-4b-cpu | task_tt_um_tommythorn_4b_cpu_v2 | tt_um_tommythorn_4b_cpu_v2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Tommy Thorn
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
`default_nettype none
// Instructions
`define Load 0
`define Store 1
`define Add 2
`define Bz 3
// Commands
`define Reset 0
`define LoadCode 1
`define LoadData 2
`define Run 3
module tt_um_tommythorn_4b_cpu_... | module tt_um_tommythorn_4b_cpu_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1... |
tt06-finale_0095 | tt06-finale | wmk7fe-tt06-otp-encryptor | task_LFSR_PRNG | tt_um_otp_encryptor | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
`default_nettype none
module tt_um_otp_encryptor (
input [7:0] ui_in, // Dedicated inputs
output [7:0] uo_out, // Dedicated outputs
/* verilator lint_off UNUSEDSIGNAL */
input [7:0] uio_in, // IOs: Input path
/* verilator lint_on UNUSEDSIGNAL */
output [7:0] uio_out, // IOs: Output path
... | module LFSR_PRNG (
clk,
rst,
prn);
input clk;
input rst;
output [7:0] prn;
reg [31:0] D32 = 32'hbdca2c92; //NEVER 000000
assign prn[0] = D32[23];
assign prn[1] = D32[17];
assign prn[2] = D32[13];
assign prn[3] = D32[11];
assign prn[4] = D32[7];
assign prn[5] = D32[5];
... |
tt06-finale_0096 | tt06-finale | wmk7fe-tt06-otp-encryptor | task_tt_um_otp_encryptor | tt_um_otp_encryptor | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
`default_nettype none
module tt_um_otp_encryptor (
input [7:0] ui_in, // Dedicated inputs
output [7:0] uo_out, // Dedicated outputs
/* verilator lint_off UNUSEDSIGNAL */
input [7:0] uio_in, // IOs: Input path
/* verilator lint_on UNUSEDSIGNAL */
output [7:0] uio_out, // IOs: Output path
... | module tt_um_otp_encryptor (
input [7:0] ui_in, // Dedicated inputs
output [7:0] uo_out, // Dedicated outputs
/* verilator lint_off UNUSEDSIGNAL */
input [7:0] uio_in, // IOs: Input path
/* verilator lint_on UNUSEDSIGNAL */
output [7:0] uio_out, // IOs: Output path
output [7:0] uio_oe,... |
tt06-finale_0097 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_demo_rom_64B | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module demo_rom_64B(
//Input Addr
input wire [5:0] address,
//Output Data
output reg [7:0] data_out
);
always @(address)
case(address)
6'h00: data_out = _NOP; //First istr is a NOP
6'h01: data_out = _LDA_IMM; //Make sure A is zero
6'h02: d... |
tt06-finale_0098 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_drive_enable_fanout | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module drive_enable_fanout(
//Drive enable input signal
input wire drive_en,
//Output drive signals
output reg [7:0] drive
);
//Main Procedural Block
//--------------------------
always @(*) begin
if(drive_en == 0)
drive = 0;
else
drive = 8'hff... |
tt06-finale_0099 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_alu | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_alu (
//ALU Inputs
input wire signed [7:0] a_in,
input wire signed [7:0] b_in,
input wire [3:0] alu_op_in,
//ALU Outputs
output reg signed [7:0] res_out,
output reg [1:0] flags_zn_out
);
//Main Procedural Block
//--------------------------
always @... |
tt06-finale_0100 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_cpu | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_cpu (
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//Memory and IO Inputs
input wire [7:0] data_in,
//DFT Testmode Inputs
input wire [2:0] tm_control,
//Memory and IO Outputs
output wire [7:0] addr_out,
output wire [7:0]... |
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