LLMs for Chip Design
Collection
Benchmarks, datasets and other resources related with LLM models tuned for chip design.
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tt06-finale_0001
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tt06-finale
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CEJMU-tt06_tinyrv1
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task_alu
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tt_um_cejmu_riscv
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You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
|
tt06-finale_0002
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_control
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
|
tt06-finale_0003
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_cpu
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
|
tt06-finale_0004
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_instructioncounter
|
tt_um_cejmu_riscv
| "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)
| "/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)
| "module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);\n wire [15:0] _0(...TRUNCATED)
|
tt06-finale_0005
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_regs
|
tt_um_cejmu_riscv
| "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)
| "/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)
| "module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);\n wire [31:0] _000_;\n(...TRUNCATED)
|
tt06-finale_0006
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_spi_master
|
tt_um_cejmu_riscv
| "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)
| "/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)
| "module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_vali(...TRUNCATED)
|
tt06-finale_0007
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_tt_um_cejmu_riscv
|
tt_um_cejmu_riscv
| "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)
| "/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)
| "module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);\n wire _0_;\n (...TRUNCATED)
|
tt06-finale_0008
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_Compx1
|
tt_um_CKPope_top
| "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)
| "module tt_um_CKPope_top \n(\n input wire [7:0] ui_in, // Dedicated inputs for X and Y Target(...TRUNCATED)
| "module Compx1\n(\n input a,\n\tinput b,\n \toutput reg aeqb,\t\t\n\toutput reg agtb,\t\t\n\toutpu(...TRUNCATED)
|
tt06-finale_0009
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_Compx4
|
tt_um_CKPope_top
| "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)
| "module tt_um_CKPope_top \n(\n input wire [7:0] ui_in, // Dedicated inputs for X and Y Target(...TRUNCATED)
| "module Compx4\n(\n input [3:0] a_hex,\n\tinput [3:0] b_hex,\n \toutput reg a_eq_b,\t\t\n\toutput (...TRUNCATED)
|
tt06-finale_0010
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_Mealy_SM
|
tt_um_CKPope_top
| "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)
| "module tt_um_CKPope_top \n(\n input wire [7:0] ui_in, // Dedicated inputs for X and Y Target(...TRUNCATED)
| "module Mealy_SM\n(\n input clk,\n input reset,\t \n input motion,\n input x_comp_eq,\n inp(...TRUNCATED)
|
End of preview. Expand
in Data Studio
NotSoTiny: A Large, Living Benchmark for RTL Code Generation
Summary
NotSoTiny is a large, structurally rich, and "living" benchmark designed to assess Large Language Models (LLMs) on the generation of context-aware RTL (Register-Transfer Level) code. Built from hundreds of real hardware designs produced by the Tiny Tapeout community, this benchmark overcomes the limitations of prior static datasets by periodically incorporating new designs, making it resilient to data contamination.
Unlike previous benchmarks which rely on standalone modules or explicit specifications, NotSoTiny focuses on contextual module completion. In this setup, models are presented with a full design context, where one module is masked. The LLM must infer the missing module's functionality and interface solely from the surrounding implementation, mirroring real-world development scenarios where new components must integrate into existing systems.
This dataset includes the 25-12 release, with 1,114 deduplicated and curated tasks derived from real, taped-out hardware designs, making it significantly larger and more complex than existing RTL benchmarks.
Supported Tasks and Leaderboards
- Task:
module-completion(Hardware (Verilog) Code Completion). - Leaderboard: Solutions are evaluated using syntex checks and functional correctness through Formal Equivalence Checking (via Yosys). A leaderboard tracking model performance is available in the TuRTLe Leaderboard.
Languages
The dataset contains:
- Verilog (for hardware designs, prompts, and golden modules).
- English (for system messages and metadata).
Dataset Structure
Data Instances
Each row in the dataset represents a single module completion task. The model is given a system_message and a prompt (containing the context file task.v), and is expected to generate the missing Verilog code that matches the functionality of the golden_module.
Data Fields
task_id(string): A unique identifier for the task, formatted as<shuttle_name>_<incremental_number>.shuttle_name(string): The identifier of the Tiny Tapeout shuttle from which the design originated (e.g., TT06, TT08).project_name(string): The name of the original Tiny Tapeout project containing the task.task_name(string): The name of the task directory, corresponding to the specific design module being tested.system_message(string): A unified system prompt (same for all tasks) used to instruct the LLM.prompt(string): The content oftask.v. This contains the surrounding design context with the target module missing, serving as the input for the LLM.golden_module(string): The content oforiginal_module.v. This is the ground truth implementation of the maked module, used for formal verification.
Data Splits
The 25-12 release consists of a single split containing 1,114 validated tasks. These tasks are derived from multiple Tiny Tapeout shuttles (TT06, TT07, TT08, TT09, TT10 IHP-02, TT10 IHP-25a, and TTsky25a).
Dataset Creation
Curation Rationale
Current RTL benchmarks suffer from insufficient scale, shallow verification protocols, and a high risk of training data contamination. NotSoTiny was created to address these issues by:
- Scale & Complexity: Providing tasks with deeper hierarchies and complex control/datapath interactions typical of real hardware.
- Living Nature: Utilizing the continuous release schedule of Tiny Tapeout shuttles to constantly refresh the benchmark, keeping it ahead of LLM training data.
- Rigorous Verification: Using formal equivalence checking to ensure functional correctness, as simulation testbenches were found to have low coverage.
Source Data
The designs are sourced from the Tiny Tapeout project repositories on GitHub. These are open-source digital, mixed-signal, and analog circuits submitted by researchers and engineers for fabrication.
Data Processing
The dataset construction pipeline follows these steps:
- Filtering: Projects are filtered to ensure they contain valid
src/andtest/directories, aMakefile, and a validinfo.yaml. - Module Aggregation: The
vppreproctool is used to merge project files into a single self-contained Verilog file, preserving internal hierarchies. - Task Building: Each aggregated design is decomposed into multiple tasks. For each task, the body of one module is removed (to be generated), while the remaining modules serve as context.
- Temporal Deduplication: To prevent data leakage and redundancy, designs are deduplicated across shuttles using MinHash and Locality-Sensitive Hashing (LSH). If duplicates exist, only the version from the oldest shuttle is retained.
- Self-Verification: A final validation step ensures compatibility by verifying the golden solution against itself using the general Yosys formal verification script. Only tasks that pass this check are included.
Considerations for Using the Data
To use this dataset for benchmarking, it is highly recommended to integrate with the TuRTLe framework. TuRTLe is a unified evaluation framework designed to automate the entire benchmarking pipeline for RTL generation.
Specifically, the framework handles:
- Model Serving: It manages model interactions and generation requests.
- Processing & Verification: It executes all necessary processing steps, from initial syntax validation to rigorous Formal Equivalence Checking (using Yosys) against the
golden_module. - Final Reporting: It calculates and outputs the final performance results hsing standardized metrics.
Additional Information
License
The dataset is released under the Apache License 2.0.
Citation Information
@misc{ghorab2025notsotinylargelivingbenchmark,
title={NotSoTiny: A Large, Living Benchmark for RTL Code Generation},
author={Razine Moundir Ghorab and Emanuele Parisi and Cristian Gutierrez-Gomez and Miquel Albert\'i-Binimelis and Miquel Moreto and Dario Garcia-Gasulla and Gokcen Kestor},
year={2025},
eprint={2512.20823},
archivePrefix={arXiv},
primaryClass={cs.AR},
url={[https://arxiv.org/abs/2512.20823](https://arxiv.org/abs/2512.20823)},
}
Acknowledgements
The HPAI team behind NotSoTiny would like to thank the Tiny Tapeout community for the open source efforts, which made possible this contribution. Special thanks to Matt Venn for his support.
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